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raw | patch | inline | side by side (parent: b8bbea6)
raw | patch | inline | side by side (parent: b8bbea6)
author | Lokesh Vutla <lokeshvutla@ti.com> | |
Mon, 8 Jul 2013 10:34:39 +0000 (16:04 +0530) | ||
committer | Somnath Mukherjee <somnath@ti.com> | |
Wed, 14 Aug 2013 16:02:00 +0000 (21:32 +0530) |
Locking DPLL_GMAC
[mugunthanvnm@ti.com:Configure only if CPSW is selected]
Change-Id: I5b3cffa699f83cf88ee98086ba2dc9a8586a1074
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Added change-id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
[mugunthanvnm@ti.com:Configure only if CPSW is selected]
Change-Id: I5b3cffa699f83cf88ee98086ba2dc9a8586a1074
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Added change-id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 88d93926cb00f58320a7d461e3ca95d8ec3107cd..4e0907c1db00c26b004664b3893159ffea68881c 100644 (file)
return &dpll_data->ddr[sysclk_ind];
}
+#ifdef CONFIG_DRIVER_TI_CPSW
+static const struct dpll_params *get_gmac_dpll_params
+ (struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+
+ if (!dpll_data->gmac)
+ return NULL;
+ return &dpll_data->gmac[sysclk_ind];
+}
+#endif
+
static void do_setup_dpll(u32 const base, const struct dpll_params *params,
u8 lock, char *dpll)
{
params = get_ddr_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
params, DPLL_LOCK, "ddr");
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+ params = get_gmac_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
+ DPLL_LOCK, "gmac");
+#endif
}
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
index 79c42f125d41feff8ffe947263a91e02fa882a5b..d5f6c1d789e952d385bf6da61c65b4615903730d 100644 (file)
{665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
};
+static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
+ {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+};
+
struct dplls omap5_dplls_es1 = {
.mpu = mpu_dpll_params_800mhz,
.core = core_dpll_params_2128mhz_ddr532,
.iva = iva_dpll_params_2330mhz_dra7xx,
.usb = usb_dpll_params_1920mhz,
.ddr = ddr_dpll_params_2128mhz,
+ .gmac = gmac_dpll_params_2000mhz,
};
struct pmic_data palmas = {
index debc56bb6454b15a6be326a4c93f0e6d31db129d..7838f430bc4f103199bdd485c075f82af581918c 100644 (file)
.cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c,
.cm_clkmode_dpll_dsp = 0x4a005234,
.cm_shadow_freq_config1 = 0x4a005260,
+ .cm_clkmode_dpll_gmac = 0x4a0052a8,
/* cm1.mpu */
.cm_mpu_mpu_clkctrl = 0x4a005320,
index c8d4619d7c0f3cf8a6cc4896e1af385266261635..9c1a154125e405ce6e27017cbf4f09bb4dbd1367 100644 (file)
u32 cm_ssc_deltamstep_dpll_ddrphy;
u32 cm_clkmode_dpll_dsp;
u32 cm_shadow_freq_config1;
+ u32 cm_clkmode_dpll_gmac;
u32 cm_mpu_mpu_clkctrl;
/* cm1.dsp */
const struct dpll_params *iva;
const struct dpll_params *usb;
const struct dpll_params *ddr;
+ const struct dpll_params *gmac;
};
struct pmic_data {