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raw | patch | inline | side by side (from parent 1: 3951f98)
raw | patch | inline | side by side (from parent 1: 3951f98)
author | Mugunthan V N <mugunthanvnm@ti.com> | |
Mon, 8 Jul 2013 10:34:40 +0000 (16:04 +0530) | ||
committer | Somnath Mukherjee <somnath@ti.com> | |
Wed, 14 Aug 2013 16:02:05 +0000 (21:32 +0530) |
Enabling CPSW module by enabling GMAC clock control
Change-Id: I6b48ee2ba5dd400b3f9e1744933e7dbc09e4a13e
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Resolved merge conflicts and added change id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
Change-Id: I6b48ee2ba5dd400b3f9e1744933e7dbc09e4a13e
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Resolved merge conflicts and added change id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
arch/arm/cpu/armv7/omap5/hw_data.c | patch | blob | history | |
arch/arm/cpu/armv7/omap5/prcm-regs.c | patch | blob | history | |
arch/arm/include/asm/omap_common.h | patch | blob | history |
index d5f6c1d789e952d385bf6da61c65b4615903730d..8d379b3884d3c568e2a4377c534c5dee0ce45159 100644 (file)
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
(*prcm)->cm_l3init_clkstctrl,
(*prcm)->cm_memif_clkstctrl,
(*prcm)->cm_l4cfg_clkstctrl,
+#ifdef CONFIG_DRIVER_TI_CPSW
+ (*prcm)->cm_gmac_clkstctrl,
+#endif
0
};
0
};
#ifdef CONFIG_TI_QSPI
(*prcm)->cm_l4per_qspi_clkctrl,
#endif
#ifdef CONFIG_TI_QSPI
(*prcm)->cm_l4per_qspi_clkctrl,
#endif
+#ifdef CONFIG_DRIVER_TI_CPSW
+ (*prcm)->cm_gmac_gmac_clkctrl,
+#endif
0
};
0
};
(*prcm)->cm_l3init_fsusb_clkctrl,
0
};
(*prcm)->cm_l3init_fsusb_clkctrl,
0
};
-
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
do_enable_clocks(clk_domains_essential,
clk_modules_hw_auto_essential,
clk_modules_explicit_en_essential,
index 7838f430bc4f103199bdd485c075f82af581918c..091338397e8f878a5e355a8861ae8901e5b2781f 100644 (file)
.cm_l3init_hsusbhost_clkctrl = 0x4a009340,
.cm_l3init_hsusbotg_clkctrl = 0x4a009348,
.cm_l3init_hsusbtll_clkctrl = 0x4a009350,
.cm_l3init_hsusbhost_clkctrl = 0x4a009340,
.cm_l3init_hsusbotg_clkctrl = 0x4a009348,
.cm_l3init_hsusbtll_clkctrl = 0x4a009350,
+ .cm_gmac_clkstctrl = 0x4a0093c0,
+ .cm_gmac_gmac_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
/* cm2.l4per */
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
/* cm2.l4per */
index 9c1a154125e405ce6e27017cbf4f09bb4dbd1367..d9f9c33118bb927c33d3580713ab65493c7cafba 100644 (file)
u32 cm_l3init_usbphy_clkctrl;
u32 cm_l4per_mcbsp4_clkctrl;
u32 prm_vc_cfg_channel;
u32 cm_l3init_usbphy_clkctrl;
u32 cm_l4per_mcbsp4_clkctrl;
u32 prm_vc_cfg_channel;
+
+ /* GMAC Clk Ctrl */
+ u32 cm_gmac_gmac_clkctrl;
+ u32 cm_gmac_clkstctrl;
};
struct omap_sys_ctrl_regs {
};
struct omap_sys_ctrl_regs {