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raw | patch | inline | side by side (parent: de5bf02)
raw | patch | inline | side by side (parent: de5bf02)
author | Fabio Estevam <fabio.estevam@freescale.com> | |
Thu, 15 Nov 2012 11:23:24 +0000 (11:23 +0000) | ||
committer | Stefano Babic <sbabic@denx.de> | |
Mon, 19 Nov 2012 07:49:00 +0000 (08:49 +0100) |
Measuring the spi clock line on a scope shows a 'glitch' during the reset of the
spi.
Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes
always stable.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
spi.
Fix this by toggling only the MXC_CSPICTRL_EN bit, so that the clock line becomes
always stable.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
drivers/spi/mxc_spi.c | patch | blob | history |
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index b6bad989527b75b6e94d1f1184e929a66203e9e1..859c43fee2790de7c80335bb58a71b20934c49f9 100644 (file)
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
reg_ctrl = reg_read(®s->ctrl);
/* Reset spi */
- reg_write(®s->ctrl, 0);
- reg_write(®s->ctrl, (reg_ctrl | 0x1));
+ reg_write(®s->ctrl, (reg_ctrl & ~MXC_CSPICTRL_EN));
+ reg_write(®s->ctrl, (reg_ctrl | MXC_CSPICTRL_EN));
/*
* The following computation is taken directly from Freescale's code.