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raw | patch | inline | side by side (parent: 3840f3c)
raw | patch | inline | side by side (parent: 3840f3c)
author | Matt Porter <matt.porter@linaro.org> | |
Wed, 7 Aug 2013 12:38:28 +0000 (18:08 +0530) | ||
committer | Somnath Mukherjee <somnath@ti.com> | |
Thu, 8 Aug 2013 12:58:52 +0000 (18:28 +0530) |
Add QSPI definitions and clock configuration support.
Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
index 9374c6a82e196e7d57d47adb38901ebb71540e83..b29d97ab3d0f948cb0ff04d56a571d6a0ebe76de 100644 (file)
(*prcm)->cm_wkup_wdtimer2_clkctrl,
(*prcm)->cm_l4per_uart3_clkctrl,
(*prcm)->cm_l4per_i2c1_clkctrl,
+ #ifdef CONFIG_TI_QSPI
+ (*prcm)->cm_l4per_qspi_clkctrl,
+ #endif
0
};
clk_modules_explicit_en_essential,
1);
+#ifdef CONFIG_TI_QSPI
+ setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
+#endif
+
/* Enable SCRM OPT clocks for PER and CORE dpll */
setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
OPTFCLKEN_SCRM_PER_MASK);
index 331117c35c8244fdf7143d4a8a33a8db71f8ac7a..debc56bb6454b15a6be326a4c93f0e6d31db129d 100644 (file)
.cm_l4per_gpio8_clkctrl = 0x4a009818,
.cm_l4per_mmcsd3_clkctrl = 0x4a009820,
.cm_l4per_mmcsd4_clkctrl = 0x4a009828,
+ .cm_l4per_qspi_clkctrl = 0x4a009838,
.cm_l4per_uart1_clkctrl = 0x4a009840,
.cm_l4per_uart2_clkctrl = 0x4a009848,
.cm_l4per_uart3_clkctrl = 0x4a009850,
index e7d79fc3c410d01dcf7ab498293a66ad1a43cd37..d2c493011d1680b4f9bc9d65675492fab698f3c9 100644 (file)
/* GPMC */
#define OMAP54XX_GPMC_BASE 0x50000000
+/* QSPI */
+#define QSPI_BASE 0x4B300000
+
/*
* Hardware Register Details
*/
index d4d353c80b95f1a874bb1d67ce6e225c7e249003..8905cb89999c20d5fa1d4796acd026fa2377bf76 100644 (file)
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
+#define BOOT_DEVICE_SPI 10
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
index fa2835846a8ee331a28c772b579872f72b3670dd..c8d4619d7c0f3cf8a6cc4896e1af385266261635 100644 (file)
u32 cm_l4per_mmcsd4_clkctrl;
u32 cm_l4per_msprohg_clkctrl;
u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_qspi_clkctrl;
u32 cm_l4per_uart1_clkctrl;
u32 cm_l4per_uart2_clkctrl;
u32 cm_l4per_uart3_clkctrl;