Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 8 Jan 2013 13:59:37 +0000 (14:59 +0100)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 8 Jan 2013 13:59:37 +0000 (14:59 +0100)
257 files changed:
Makefile
README
arch/arm/cpu/arm1136/cpu.c
arch/arm/cpu/arm1176/s3c64xx/Makefile
arch/arm/cpu/arm1176/s3c64xx/init.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/davinci/reset.c
arch/arm/cpu/arm926ejs/mxs/clock.c
arch/arm/cpu/armv7/am33xx/Makefile
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock.c
arch/arm/cpu/armv7/am33xx/elm.c [new file with mode: 0644]
arch/arm/cpu/armv7/am33xx/mem.c [new file with mode: 0644]
arch/arm/cpu/armv7/cache_v7.c
arch/arm/cpu/armv7/exynos/clock.c
arch/arm/cpu/armv7/exynos/pinmux.c
arch/arm/cpu/armv7/omap-common/Makefile
arch/arm/cpu/armv7/omap-common/boot-common.c
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap3/board.c
arch/arm/cpu/armv7/omap3/mem.c
arch/arm/cpu/armv7/omap3/sdrc.c
arch/arm/cpu/armv7/omap4/clocks.c
arch/arm/cpu/armv7/omap4/hwinit.c
arch/arm/cpu/armv7/s5p-common/Makefile
arch/arm/cpu/armv7/tegra20/Makefile
arch/arm/cpu/armv7/tegra20/display.c [new file with mode: 0644]
arch/arm/cpu/armv7/tegra20/pwm.c [new file with mode: 0644]
arch/arm/cpu/tegra20-common/funcmux.c
arch/arm/cpu/tegra20-common/pinmux.c
arch/arm/dts/tegra20.dtsi
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/elm.h [new file with mode: 0644]
arch/arm/include/asm/arch-am33xx/hardware.h
arch/arm/include/asm/arch-am33xx/mem.h [new file with mode: 0644]
arch/arm/include/asm/arch-am33xx/omap_gpmc.h [new file with mode: 0644]
arch/arm/include/asm/arch-am33xx/sys_proto.h
arch/arm/include/asm/arch-exynos/clk.h
arch/arm/include/asm/arch-exynos/clock.h
arch/arm/include/asm/arch-exynos/cpu.h
arch/arm/include/asm/arch-exynos/gpio.h
arch/arm/include/asm/arch-exynos/i2s-regs.h [new file with mode: 0644]
arch/arm/include/asm/arch-exynos/periph.h
arch/arm/include/asm/arch-exynos/sound.h [new file with mode: 0644]
arch/arm/include/asm/arch-exynos/spi.h [new file with mode: 0644]
arch/arm/include/asm/arch-mxs/clock.h
arch/arm/include/asm/arch-omap3/sys_proto.h
arch/arm/include/asm/arch-s5pc1xx/gpio.h
arch/arm/include/asm/arch-tegra20/dc.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra20/display.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra20/pinmux.h
arch/arm/include/asm/arch-tegra20/pwm.h [new file with mode: 0644]
arch/arm/include/asm/omap_gpio.h
arch/arm/include/asm/system.h
arch/arm/lib/board.c
arch/arm/lib/cache-cp15.c
arch/m68k/include/asm/string.h
arch/m68k/lib/board.c
arch/microblaze/lib/board.c
arch/mips/cpu/mips64/start.S
arch/mips/include/asm/bitops.h
arch/mips/lib/board.c
arch/powerpc/cpu/mpc85xx/mp.c
arch/powerpc/include/asm/string.h
arch/powerpc/lib/board.c
arch/sparc/include/asm/string.h
arch/sparc/lib/board.c
board/Marvell/db64360/db64360.c
board/Marvell/db64460/db64460.c
board/compal/paz00/paz00.c
board/compulab/dts/tegra20-trimslice.dts
board/compulab/trimslice/trimslice.c
board/corscience/tricorder/tricorder.c
board/esd/cpci750/cpci750.c
board/esd/pmc440/cmd_pmc440.c
board/gw8260/gw8260.c
board/isee/igep0020/igep0020.c
board/isee/igep0030/igep0030.c
board/nvidia/common/board.c
board/nvidia/dts/tegra20-seaboard.dts
board/nvidia/harmony/harmony.c
board/nvidia/seaboard/seaboard.c
board/overo/overo.c
board/prodrive/p3mx/p3mx.c
board/samsung/smdk5250/Makefile
board/samsung/smdk5250/smdk5250.c
board/samsung/smdk5250/spl_boot.c [moved from board/samsung/smdk5250/mmc_boot.c with 66% similarity]
board/samsung/trats/trats.c
board/samsung/universal_c210/Makefile
board/samsung/universal_c210/lowlevel_init.S [deleted file]
board/samsung/universal_c210/universal.c
board/technexion/twister/twister.c
board/teejet/mt_ventoux/mt_ventoux.c
board/ti/am335x/board.c
board/ti/am335x/mux.c
board/ti/beagle/beagle.c
board/ti/evm/evm.c
board/timll/devkit8000/devkit8000.c
common/Makefile
common/cmd_bootm.c
common/cmd_gettime.c [new file with mode: 0644]
common/cmd_gpt.c [new file with mode: 0644]
common/cmd_hash.c [new file with mode: 0644]
common/cmd_i2c.c
common/cmd_io.c [new file with mode: 0644]
common/cmd_nvedit.c
common/cmd_read.c [new file with mode: 0644]
common/cmd_sha1sum.c
common/cmd_sound.c [new file with mode: 0644]
common/cmd_spl.c
common/cmd_tpm.c
common/console.c
common/edid.c [new file with mode: 0644]
common/env_attr.c [new file with mode: 0644]
common/env_callback.c [new file with mode: 0644]
common/env_common.c
common/env_dataflash.c
common/env_eeprom.c
common/env_fat.c
common/env_flags.c [new file with mode: 0644]
common/env_flash.c
common/env_mmc.c
common/env_nand.c
common/env_nvram.c
common/env_onenand.c
common/env_sf.c
common/fdt_support.c
common/hash.c [new file with mode: 0644]
common/image.c
common/lcd.c
common/main.c
common/stdio.c
disk/part_efi.c
doc/README.gpt [new file with mode: 0644]
doc/README.silent
doc/device-tree-bindings/pwm/tegra20-pwm.txt [new file with mode: 0644]
doc/device-tree-bindings/video/displaymode.txt [new file with mode: 0644]
doc/device-tree-bindings/video/tegra20-dc.txt [new file with mode: 0644]
drivers/gpio/omap_gpio.c
drivers/gpio/s5p_gpio.c
drivers/i2c/designware_i2c.c
drivers/i2c/designware_i2c.h
drivers/i2c/mxc_i2c.c
drivers/i2c/mxs_i2c.c
drivers/i2c/omap24xx_i2c.c
drivers/i2c/s3c24x0_i2c.c
drivers/i2c/soft_i2c.c
drivers/input/tegra-kbc.c
drivers/mmc/tegra_mmc.c
drivers/mtd/nand/Makefile
drivers/mtd/nand/am335x_spl_bch.c [new file with mode: 0644]
drivers/mtd/nand/mxs_nand.c
drivers/mtd/nand/omap_gpmc.c
drivers/net/cpsw.c
drivers/net/e1000.c
drivers/net/e1000.h
drivers/net/phy/marvell.c
drivers/net/sh_eth.c
drivers/net/sh_eth.h
drivers/power/pmic/Makefile
drivers/power/pmic/pmic_max77686.c [new file with mode: 0644]
drivers/power/twl6035.c
drivers/serial/s3c64xx.c
drivers/serial/serial.c
drivers/sound/Makefile [new file with mode: 0644]
drivers/sound/samsung-i2s.c [new file with mode: 0644]
drivers/sound/sound.c [new file with mode: 0644]
drivers/sound/wm8994.c [new file with mode: 0644]
drivers/sound/wm8994.h [new file with mode: 0644]
drivers/sound/wm8994_registers.h [new file with mode: 0644]
drivers/spi/Makefile
drivers/spi/exynos_spi.c [new file with mode: 0644]
drivers/spi/omap3_spi.c
drivers/spi/omap3_spi.h
drivers/video/Makefile
drivers/video/exynos_fb.c
drivers/video/ld9040.c [new file with mode: 0644]
drivers/video/tegra.c [new file with mode: 0644]
drivers/watchdog/Makefile
drivers/watchdog/s5p_wdt.c [moved from arch/arm/cpu/armv7/s5p-common/wdt.c with 100% similarity]
include/asm-generic/gpio.h
include/command.h
include/common.h
include/config_cmd_all.h
include/configs/CRAYL1.h
include/configs/GEN860T.h
include/configs/TOP860.h
include/configs/am335x_evm.h
include/configs/cm_t35.h
include/configs/dig297.h
include/configs/ep8260.h
include/configs/harmony.h
include/configs/igep00x0.h
include/configs/m28evk.h
include/configs/mcx.h
include/configs/mx28evk.h
include/configs/omap3_beagle.h
include/configs/omap3_evm.h
include/configs/omap3_mvblx.h
include/configs/omap3_pandora.h
include/configs/omap3_sdp3430.h
include/configs/omap3_zoom1.h
include/configs/omap3_zoom2.h
include/configs/palmld.h
include/configs/palmtc.h
include/configs/paz00.h
include/configs/s5pc210_universal.h
include/configs/seaboard.h
include/configs/smdk5250.h
include/configs/tam3517-common.h
include/configs/tec.h
include/configs/tegra-common-post.h
include/configs/tegra20-common.h
include/configs/trats.h
include/configs/tricorder.h
include/configs/trimslice.h
include/configs/utx8245.h
include/configs/ventana.h
include/configs/whistler.h
include/configs/zipitz2.h
include/edid.h [new file with mode: 0644]
include/env_attr.h [new file with mode: 0644]
include/env_callback.h [new file with mode: 0644]
include/env_default.h
include/env_flags.h [new file with mode: 0644]
include/environment.h
include/exports.h
include/fdtdec.h
include/hash.h [new file with mode: 0644]
include/i2s.h [new file with mode: 0644]
include/image.h
include/lcd.h
include/ld9040.h [new file with mode: 0644]
include/linux/linux_string.h [new file with mode: 0644]
include/linux/string.h
include/part.h
include/part_efi.h [moved from disk/part_efi.h with 66% similarity]
include/power/max77686_pmic.h [new file with mode: 0644]
include/power/max8998_pmic.h
include/search.h
include/sha1.h
include/sha256.h
include/sound.h [new file with mode: 0644]
include/twl6035.h
lib/Makefile
lib/fdtdec.c
lib/hashtable.c
lib/linux_string.c [new file with mode: 0644]
lib/sha1.c
lib/sha256.c
lib/string.c
lib/vsprintf.c
net/link_local.c
net/net.c
net/tftp.c
tools/env/Makefile
tools/env/fw_env.c
tools/fit_image.c

index d3766b901744b3a855c3e2d03a32e108bb810da3..a7b6cd1cbad361ecfa6f71faff567ebae86c449d 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -24,7 +24,7 @@
 VERSION = 2013
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -316,6 +316,7 @@ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
 endif
 LIBS-y += drivers/rtc/librtc.o
 LIBS-y += drivers/serial/libserial.o
+LIBS-y += drivers/sound/libsound.o
 LIBS-$(CONFIG_GENERIC_LPC_TPM) += drivers/tpm/libtpm.o
 LIBS-y += drivers/twserial/libtws.o
 LIBS-y += drivers/usb/eth/libusb_eth.o
diff --git a/README b/README
index 5a86ae9c5f9188dd53a8b54ce3eb9554f2485f41..653ef6aa4a55d57686165e56eeec847dcd40b3f1 100644 (file)
--- a/README
+++ b/README
@@ -815,6 +815,8 @@ The following options need to be configured:
                CONFIG_CMD_EDITENV        edit env variable
                CONFIG_CMD_EEPROM       * EEPROM read/write support
                CONFIG_CMD_ELF          * bootelf, bootvx
+               CONFIG_CMD_ENV_CALLBACK * display details about env callbacks
+               CONFIG_CMD_ENV_FLAGS    * display details about env flags
                CONFIG_CMD_EXPORTENV    * export the environment
                CONFIG_CMD_EXT2         * ext2 command support
                CONFIG_CMD_EXT4         * ext4 command support
@@ -824,8 +826,10 @@ The following options need to be configured:
                CONFIG_CMD_FDOS         * Dos diskette Support
                CONFIG_CMD_FLASH          flinfo, erase, protect
                CONFIG_CMD_FPGA           FPGA device initialization support
+               CONFIG_CMD_GETTIME      * Get time since boot
                CONFIG_CMD_GO           * the 'go' command (exec code)
                CONFIG_CMD_GREPENV      * search environment
+               CONFIG_CMD_HASH         * calculate hash / digest
                CONFIG_CMD_HWFLOW       * RTS/CTS hw flow control
                CONFIG_CMD_I2C          * I2C serial bus support
                CONFIG_CMD_IDE          * IDE harddisk support
@@ -860,6 +864,7 @@ The following options need to be configured:
                CONFIG_CMD_PING         * send ICMP ECHO_REQUEST to network
                                          host
                CONFIG_CMD_PORTIO       * Port I/O
+               CONFIG_CMD_READ         * Read raw data from partition
                CONFIG_CMD_REGINFO      * Register dump
                CONFIG_CMD_RUN            run command in env variable
                CONFIG_CMD_SAVES        * save S record dump
@@ -1481,10 +1486,29 @@ CBFS (Coreboot Filesystem) support
                Normally display is black on white background; define
                CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
 
+               CONFIG_LCD_ALIGNMENT
+
+               Normally the LCD is page-aligned (tyically 4KB). If this is
+               defined then the LCD will be aligned to this value instead.
+               For ARM it is sometimes useful to use MMU_SECTION_SIZE
+               here, since it is cheaper to change data cache settings on
+               a per-section basis.
+
+               CONFIG_CONSOLE_SCROLL_LINES
+
+               When the console need to be scrolled, this is the number of
+               lines to scroll by. It defaults to 1. Increasing this makes
+               the console jump but can help speed up operation when scrolling
+               is slow.
+
                CONFIG_LCD_BMP_RLE8
 
                Support drawing of RLE8-compressed bitmaps on the LCD.
 
+               CONFIG_I2C_EDID
+
+               Enables an 'i2c edid' command which can read EDID
+               information over I2C from an attached LCD display.
 
 - Splash Screen Support: CONFIG_SPLASH_SCREEN
 
@@ -2179,6 +2203,11 @@ CBFS (Coreboot Filesystem) support
                serial# is unaffected by this, i. e. it remains
                read-only.]
 
+               The same can be accomplished in a more flexible way
+               for any variable by configuring the type of access
+               to allow for those variables in the ".flags" variable
+               or define CONFIG_ENV_FLAGS_LIST_STATIC.
+
 - Protected RAM:
                CONFIG_PRAM
 
@@ -2409,6 +2438,23 @@ CBFS (Coreboot Filesystem) support
                A better solution is to properly configure the firewall,
                but sometimes that is not allowed.
 
+- Hashing support:
+               CONFIG_CMD_HASH
+
+               This enables a generic 'hash' command which can produce
+               hashes / digests from a few algorithms (e.g. SHA1, SHA256).
+
+               CONFIG_HASH_VERIFY
+
+               Enable the hash verify command (hash -v). This adds to code
+               size a little.
+
+               CONFIG_SHA1 - support SHA1 hashing
+               CONFIG_SHA256 - support SHA256 hashing
+
+               Note: There is also a sha1sum command, which should perhaps
+               be deprecated in favour of 'hash sha1'.
+
 - Show boot progress:
                CONFIG_SHOW_BOOT_PROGRESS
 
@@ -2943,9 +2989,6 @@ Configuration Settings:
                non page size aligned address and this could cause major
                problems.
 
-- CONFIG_SYS_TFTP_LOADADDR:
-               Default load address for network file downloads
-
 - CONFIG_SYS_LOADS_BAUD_CHANGE:
                Enable temporary baudrate change while serial download
 
@@ -3087,6 +3130,49 @@ Configuration Settings:
        cases. This setting can be used to tune behaviour; see
        lib/hashtable.c for details.
 
+- CONFIG_ENV_FLAGS_LIST_DEFAULT
+- CONFIG_ENV_FLAGS_LIST_STATIC
+       Enable validation of the values given to enviroment variables when
+       calling env set.  Variables can be restricted to only decimal,
+       hexadecimal, or boolean.  If CONFIG_CMD_NET is also defined,
+       the variables can also be restricted to IP address or MAC address.
+
+       The format of the list is:
+               type_attribute = [s|d|x|b|i|m]
+               access_atribute = [a|r|o|c]
+               attributes = type_attribute[access_atribute]
+               entry = variable_name[:attributes]
+               list = entry[,list]
+
+       The type attributes are:
+               s - String (default)
+               d - Decimal
+               x - Hexadecimal
+               b - Boolean ([1yYtT|0nNfF])
+               i - IP address
+               m - MAC address
+
+       The access attributes are:
+               a - Any (default)
+               r - Read-only
+               o - Write-once
+               c - Change-default
+
+       - CONFIG_ENV_FLAGS_LIST_DEFAULT
+               Define this to a list (string) to define the ".flags"
+               envirnoment variable in the default or embedded environment.
+
+       - CONFIG_ENV_FLAGS_LIST_STATIC
+               Define this to a list (string) to define validation that
+               should be done if an entry is not found in the ".flags"
+               environment variable.  To override a setting in the static
+               list, simply add an entry for the same variable name to the
+               ".flags" variable.
+
+- CONFIG_ENV_ACCESS_IGNORE_FORCE
+       If defined, don't allow the -f switch to env set override variable
+       access flags.
+
 The following definitions that deal with the placement and management
 of environment data (variable area); in general, we support the
 following configurations:
@@ -4188,6 +4274,36 @@ Please note that changes to some configuration parameters may take
 only effect after the next boot (yes, that's just like Windoze :-).
 
 
+Callback functions for environment variables:
+---------------------------------------------
+
+For some environment variables, the behavior of u-boot needs to change
+when their values are changed.  This functionailty allows functions to
+be associated with arbitrary variables.  On creation, overwrite, or
+deletion, the callback will provide the opportunity for some side
+effect to happen or for the change to be rejected.
+
+The callbacks are named and associated with a function using the
+U_BOOT_ENV_CALLBACK macro in your board or driver code.
+
+These callbacks are associated with variables in one of two ways.  The
+static list can be added to by defining CONFIG_ENV_CALLBACK_LIST_STATIC
+in the board configuration to a string that defines a list of
+associations.  The list must be in the following format:
+
+       entry = variable_name[:callback_name]
+       list = entry[,list]
+
+If the callback name is not specified, then the callback is deleted.
+Spaces are also allowed anywhere in the list.
+
+Callbacks can also be associated by defining the ".callbacks" variable
+with the same list format above.  Any association in ".callbacks" will
+override any association in the static list. You can define
+CONFIG_ENV_CALLBACK_LIST_DEFAULT to a list (string) to define the
+".callbacks" envirnoment variable in the default or embedded environment.
+
+
 Command Line Parsing:
 =====================
 
index b98e3d9face97006d5588901eecb152b2d799701..32a4c244c5748a231f0c33bb9509998aeba6ccb9 100644 (file)
@@ -141,16 +141,6 @@ void flush_cache(unsigned long start, unsigned long size)
        flush_dcache_range(start, start + size);
 }
 
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
-       icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-       dcache_enable();
-#endif
-}
-
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
@@ -172,3 +162,15 @@ void flush_cache(unsigned long start, unsigned long size)
 {
 }
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+       icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+       dcache_enable();
+#endif
+}
+#endif
index 0785b194c50cd4894f6031ba03d98a67af0f9870..266a0739ce8840afafa5f500e36c035f4d665abd 100644 (file)
@@ -31,7 +31,7 @@ LIB   = $(obj)lib$(SOC).o
 SOBJS  = reset.o
 
 COBJS-$(CONFIG_S3C6400)        += cpu_init.o speed.o
-COBJS-y        += timer.o
+COBJS-y        += timer.o init.o
 
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
 
diff --git a/arch/arm/cpu/arm1176/s3c64xx/init.c b/arch/arm/cpu/arm1176/s3c64xx/init.c
new file mode 100644 (file)
index 0000000..f113d8e
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2012 Ashok Kumar Reddy Kourla
+ * ashokkourla2000@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include<common.h>
+
+int arch_cpu_init(void)
+{
+       icache_enable();
+
+       return 0;
+}
index 968fb035c89f9cada737f6eaaed0eef26cb2561d..80f1ce9d31815e637e54214097f7749d2715a8b0 100644 (file)
@@ -16,7 +16,7 @@
 void reset_cpu(unsigned long a)
 {
        struct davinci_timer *const wdttimer =
-               (struct davinci_timer *)DAVINCI_TIMER1_BASE;
+               (struct davinci_timer *)DAVINCI_WDOG_BASE;
        writel(0x08, &wdttimer->tgcr);
        writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
        writel(0, &wdttimer->tim12);
index bfea6abeb0714e38dc02351bb32fd6ec7031fef2..4ff19c37efe91ac7247f2b48c0d78097de9fd9e1 100644 (file)
@@ -333,6 +333,8 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
                return mx28_get_sspclk(MXC_SSPCLK2);
        case MXC_SSP3_CLK:
                return mx28_get_sspclk(MXC_SSPCLK3);
+       case MXC_XTAL_CLK:
+               return XTAL_FREQ_KHZ * 1000;
        }
 
        return 0;
index 74875b32558c2957415ee177320fcb1daa9dad77..70c443edbbb0a4ebd53f741cc0e53a3de15129e2 100644 (file)
@@ -18,10 +18,12 @@ LIB = $(obj)lib$(SOC).o
 
 COBJS  += clock.o
 COBJS  += sys_info.o
+COBJS  += mem.o
 COBJS  += ddr.o
 COBJS  += emif4.o
 COBJS  += board.o
 COBJS  += mux.o
+COBJS-$(CONFIG_NAND_OMAP_GPMC) += elm.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
index da5bc731852c428078fe76fa484240096f62c6a0..ab313265d0c43553cc89b507570b05e3c0acfadb 100644 (file)
@@ -25,6 +25,7 @@
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
index 0b4cb4e529e6c5301c7809890355e41d68fd5ece..d7d98d1111e0ed5495caa98045bbc5ab8bb897fc 100644 (file)
@@ -151,6 +151,16 @@ static void enable_per_clocks(void)
                ;
 #endif /* CONFIG_SERIAL6 */
 
+       /* GPMC */
+       writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
+       while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
+               ;
+
+       /* ELM */
+       writel(PRCM_MOD_EN, &cmper->elmclkctrl);
+       while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
+               ;
+
        /* MMC0*/
        writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
        while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c
new file mode 100644 (file)
index 0000000..9eed23d
--- /dev/null
@@ -0,0 +1,212 @@
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * BCH Error Location Module (ELM) support.
+ *
+ * NOTE:
+ * 1. Supports only continuous mode. Dont see need for page mode in uboot
+ * 2. Supports only syndrome polynomial 0. i.e. poly local variable is
+ *    always set to ELM_DEFAULT_POLY. Dont see need for other polynomial
+ *    sets in uboot
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap_gpmc.h>
+#include <asm/arch/elm.h>
+
+#define ELM_DEFAULT_POLY (0)
+
+struct elm *elm_cfg;
+
+/**
+ * elm_load_syndromes - Load BCH syndromes based on nibble selection
+ * @syndrome: BCH syndrome
+ * @nibbles:
+ * @poly: Syndrome Polynomial set to use
+ *
+ * Load BCH syndromes based on nibble selection
+ */
+static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
+{
+       u32 *ptr;
+       u32 val;
+
+       /* reg 0 */
+       ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0];
+       val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) |
+                               (syndrome[3] << 24);
+       writel(val, ptr);
+       /* reg 1 */
+       ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1];
+       val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) |
+                               (syndrome[7] << 24);
+       writel(val, ptr);
+
+       /* BCH 8-bit with 26 nibbles (4*8=32) */
+       if (nibbles > 13) {
+               /* reg 2 */
+               ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
+               val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
+                               (syndrome[11] << 24);
+               writel(val, ptr);
+               /* reg 3 */
+               ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3];
+               val = syndrome[12] | (syndrome[13] << 8) |
+                       (syndrome[14] << 16) | (syndrome[15] << 24);
+               writel(val, ptr);
+       }
+
+       /* BCH 16-bit with 52 nibbles (7*8=56) */
+       if (nibbles > 26) {
+               /* reg 4 */
+               ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
+               val = syndrome[16] | (syndrome[17] << 8) |
+                       (syndrome[18] << 16) | (syndrome[19] << 24);
+               writel(val, ptr);
+
+               /* reg 5 */
+               ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5];
+               val = syndrome[20] | (syndrome[21] << 8) |
+                       (syndrome[22] << 16) | (syndrome[23] << 24);
+               writel(val, ptr);
+
+               /* reg 6 */
+               ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6];
+               val = syndrome[24] | (syndrome[25] << 8) |
+                       (syndrome[26] << 16) | (syndrome[27] << 24);
+               writel(val, ptr);
+       }
+}
+
+/**
+ * elm_check_errors - Check for BCH errors and return error locations
+ * @syndrome: BCH syndrome
+ * @nibbles:
+ * @error_count: Returns number of errrors in the syndrome
+ * @error_locations: Returns error locations (in decimal) in this array
+ *
+ * Check the provided syndrome for BCH errors and return error count
+ * and locations in the array passed. Returns -1 if error is not correctable,
+ * else returns 0
+ */
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+               u32 *error_locations)
+{
+       u8 poly = ELM_DEFAULT_POLY;
+       s8 i;
+       u32 location_status;
+
+       elm_load_syndromes(syndrome, nibbles, poly);
+
+       /* start processing */
+       writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
+                               | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID),
+               &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]);
+
+       /* wait for processing to complete */
+       while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1)
+               ;
+       /* clear status */
+       writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)),
+                       &elm_cfg->irqstatus);
+
+       /* check if correctable */
+       location_status = readl(&elm_cfg->error_location[poly].location_status);
+       if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK))
+               return -1;
+
+       /* get error count */
+       *error_count = readl(&elm_cfg->error_location[poly].location_status) &
+                                       ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK;
+
+       for (i = 0; i < *error_count; i++) {
+               error_locations[i] =
+                       readl(&elm_cfg->error_location[poly].error_location_x[i]);
+       }
+
+       return 0;
+}
+
+
+/**
+ * elm_config - Configure ELM module
+ * @level: 4 / 8 / 16 bit BCH
+ *
+ * Configure ELM module based on BCH level.
+ * Set mode as continuous mode.
+ * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used.
+ * Also, the mode is set only for syndrome 0
+ */
+int elm_config(enum bch_level level)
+{
+       u32 val;
+       u8 poly = ELM_DEFAULT_POLY;
+       u32 buffer_size = 0x7FF;
+
+       /* config size and level */
+       val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK;
+       val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) &
+                               ELM_LOCATION_CONFIG_ECC_SIZE_MASK);
+       writel(val, &elm_cfg->location_config);
+
+       /* config continous mode */
+       /* enable interrupt generation for syndrome polynomial set */
+       writel((readl(&elm_cfg->irqenable) | (0x1 << poly)),
+                       &elm_cfg->irqenable);
+       /* set continuous mode for the syndrome polynomial set */
+       writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)),
+                       &elm_cfg->page_ctrl);
+
+       return 0;
+}
+
+/**
+ * elm_reset - Do a soft reset of ELM
+ *
+ * Perform a soft reset of ELM and return after reset is done.
+ */
+void elm_reset(void)
+{
+       /* initiate reset */
+       writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET),
+                               &elm_cfg->sysconfig);
+
+       /* wait for reset complete and normal operation */
+       while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) !=
+               ELM_SYSSTATUS_RESETDONE)
+               ;
+}
+
+/**
+ * elm_init - Initialize ELM module
+ *
+ * Initialize ELM support. Currently it does only base address init
+ * and ELM reset.
+ */
+void elm_init(void)
+{
+       elm_cfg = (struct elm *)ELM_BASE;
+       elm_reset();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
new file mode 100644 (file)
index 0000000..b8f54ab
--- /dev/null
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *     Manikandan Pillai <mani.pillai@ti.com>
+ *     Richard Woodruff <r-woodruff2@ti.com>
+ *     Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <command.h>
+
+struct gpmc *gpmc_cfg;
+
+#if defined(CONFIG_CMD_NAND)
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
+       M_NAND_GPMC_CONFIG1,
+       M_NAND_GPMC_CONFIG2,
+       M_NAND_GPMC_CONFIG3,
+       M_NAND_GPMC_CONFIG4,
+       M_NAND_GPMC_CONFIG5,
+       M_NAND_GPMC_CONFIG6, 0
+};
+#endif
+
+
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+                       u32 size)
+{
+       writel(0, &cs->config7);
+       sdelay(1000);
+       /* Delay for settling */
+       writel(gpmc_config[0], &cs->config1);
+       writel(gpmc_config[1], &cs->config2);
+       writel(gpmc_config[2], &cs->config3);
+       writel(gpmc_config[3], &cs->config4);
+       writel(gpmc_config[4], &cs->config5);
+       writel(gpmc_config[5], &cs->config6);
+       /* Enable the config */
+       writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+               (1 << 6)), &cs->config7);
+       sdelay(2000);
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+       /* putting a blanket check on GPMC based on ZeBu for now */
+       gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+#ifdef CONFIG_CMD_NAND
+       const u32 *gpmc_config = NULL;
+       u32 base = 0;
+       u32 size = 0;
+#endif
+       /* global settings */
+       writel(0x00000008, &gpmc_cfg->sysconfig);
+       writel(0x00000100, &gpmc_cfg->irqstatus);
+       writel(0x00000200, &gpmc_cfg->irqenable);
+       writel(0x00000012, &gpmc_cfg->config);
+       /*
+        * Disable the GPMC0 config set by ROM code
+        */
+       writel(0, &gpmc_cfg->cs[0].config7);
+       sdelay(1000);
+
+#ifdef CONFIG_CMD_NAND
+       gpmc_config = gpmc_m_nand;
+
+       base = PISMO1_NAND_BASE;
+       size = PISMO1_NAND_SIZE;
+       enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
+#endif
+}
index 1b4e808a79c74ff91f955bf24ec2007e27250828..5f6d0396f3af877c5cbc7abf4eef9f16c28a9699 100644 (file)
@@ -297,6 +297,12 @@ void arm_init_before_mmu(void)
        v7_inval_tlb();
 }
 
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+       flush_dcache_range(start, stop);
+       v7_inval_tlb();
+}
+
 /*
  * Flush range from all levels of d-cache/unified-cache used:
  * Affects the range [start, start + size - 1]
@@ -329,6 +335,11 @@ void arm_init_before_mmu(void)
 void  flush_cache(unsigned long start, unsigned long size)
 {
 }
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+}
+
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 #ifndef CONFIG_SYS_ICACHE_OFF
index 4f3b451be9955cc6e09047b5daedbe39ea2c412f..74599798c435ff84ee4e05117c13936e57351ed7 100644 (file)
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
-
-/* exynos4: return pll clock frequency */
-static unsigned long exynos4_get_pll_clk(int pllreg)
+#include <asm/arch/periph.h>
+
+/* Epll Clock division values to achive different frequency output */
+static struct set_epll_con_val exynos5_epll_div[] = {
+       { 192000000, 0, 48, 3, 1, 0 },
+       { 180000000, 0, 45, 3, 1, 0 },
+       {  73728000, 1, 73, 3, 3, 47710 },
+       {  67737600, 1, 90, 4, 3, 20762 },
+       {  49152000, 0, 49, 3, 3, 9961 },
+       {  45158400, 0, 45, 3, 3, 10381 },
+       { 180633600, 0, 45, 3, 1, 10381 }
+};
+
+/* exynos: return pll clock frequency */
+static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 {
-       struct exynos4_clock *clk =
-               (struct exynos4_clock *)samsung_get_base_clock();
-       unsigned long r, m, p, s, k = 0, mask, fout;
+       unsigned long m, p, s = 0, mask, fout;
        unsigned int freq;
-
-       switch (pllreg) {
-       case APLL:
-               r = readl(&clk->apll_con0);
-               break;
-       case MPLL:
-               r = readl(&clk->mpll_con0);
-               break;
-       case EPLL:
-               r = readl(&clk->epll_con0);
-               k = readl(&clk->epll_con1);
-               break;
-       case VPLL:
-               r = readl(&clk->vpll_con0);
-               k = readl(&clk->vpll_con1);
-               break;
-       default:
-               printf("Unsupported PLL (%d)\n", pllreg);
-               return 0;
-       }
-
        /*
         * APLL_CON: MIDV [25:16]
         * MPLL_CON: MIDV [25:16]
         * EPLL_CON: MIDV [24:16]
         * VPLL_CON: MIDV [24:16]
+        * BPLL_CON: MIDV [25:16]: Exynos5
         */
-       if (pllreg == APLL || pllreg == MPLL)
+       if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
                mask = 0x3ff;
        else
                mask = 0x1ff;
@@ -92,13 +82,43 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
        return fout;
 }
 
+/* exynos4: return pll clock frequency */
+static unsigned long exynos4_get_pll_clk(int pllreg)
+{
+       struct exynos4_clock *clk =
+               (struct exynos4_clock *)samsung_get_base_clock();
+       unsigned long r, k = 0;
+
+       switch (pllreg) {
+       case APLL:
+               r = readl(&clk->apll_con0);
+               break;
+       case MPLL:
+               r = readl(&clk->mpll_con0);
+               break;
+       case EPLL:
+               r = readl(&clk->epll_con0);
+               k = readl(&clk->epll_con1);
+               break;
+       case VPLL:
+               r = readl(&clk->vpll_con0);
+               k = readl(&clk->vpll_con1);
+               break;
+       default:
+               printf("Unsupported PLL (%d)\n", pllreg);
+               return 0;
+       }
+
+       return exynos_get_pll_clk(pllreg, r, k);
+}
+
 /* exynos5: return pll clock frequency */
 static unsigned long exynos5_get_pll_clk(int pllreg)
 {
        struct exynos5_clock *clk =
                (struct exynos5_clock *)samsung_get_base_clock();
-       unsigned long r, m, p, s, k = 0, mask, fout;
-       unsigned int freq, pll_div2_sel, fout_sel;
+       unsigned long r, k = 0, fout;
+       unsigned int pll_div2_sel, fout_sel;
 
        switch (pllreg) {
        case APLL:
@@ -123,41 +143,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
                return 0;
        }
 
-       /*
-        * APLL_CON: MIDV [25:16]
-        * MPLL_CON: MIDV [25:16]
-        * EPLL_CON: MIDV [24:16]
-        * VPLL_CON: MIDV [24:16]
-        * BPLL_CON: MIDV [25:16]
-        */
-       if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
-               mask = 0x3ff;
-       else
-               mask = 0x1ff;
-
-       m = (r >> 16) & mask;
-
-       /* PDIV [13:8] */
-       p = (r >> 8) & 0x3f;
-       /* SDIV [2:0] */
-       s = r & 0x7;
-
-       freq = CONFIG_SYS_CLK_FREQ;
-
-       if (pllreg == EPLL) {
-               k = k & 0xffff;
-               /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
-               fout = (m + k / 65536) * (freq / (p * (1 << s)));
-       } else if (pllreg == VPLL) {
-               k = k & 0xfff;
-               /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
-               fout = (m + k / 1024) * (freq / (p * (1 << s)));
-       } else {
-               if (s < 1)
-                       s = 1;
-               /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
-               fout = m * (freq / (p * (1 << (s - 1))));
-       }
+       fout = exynos_get_pll_clk(pllreg, r, k);
 
        /* According to the user manual, in EVT1 MPLL and BPLL always gives
         * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
@@ -732,6 +718,224 @@ static unsigned long exynos5_get_i2c_clk(void)
        return aclk_66;
 }
 
+int exynos5_set_epll_clk(unsigned long rate)
+{
+       unsigned int epll_con, epll_con_k;
+       unsigned int i;
+       unsigned int lockcnt;
+       unsigned int start;
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+
+       epll_con = readl(&clk->epll_con0);
+       epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
+                       EPLL_CON0_LOCK_DET_EN_SHIFT) |
+               EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
+               EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
+               EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
+
+       for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
+               if (exynos5_epll_div[i].freq_out == rate)
+                       break;
+       }
+
+       if (i == ARRAY_SIZE(exynos5_epll_div))
+               return -1;
+
+       epll_con_k = exynos5_epll_div[i].k_dsm << 0;
+       epll_con |= exynos5_epll_div[i].en_lock_det <<
+                               EPLL_CON0_LOCK_DET_EN_SHIFT;
+       epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
+       epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
+       epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
+
+       /*
+        * Required period ( in cycles) to genarate a stable clock output.
+        * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
+        * frequency input (as per spec)
+        */
+       lockcnt = 3000 * exynos5_epll_div[i].p_div;
+
+       writel(lockcnt, &clk->epll_lock);
+       writel(epll_con, &clk->epll_con0);
+       writel(epll_con_k, &clk->epll_con1);
+
+       start = get_timer(0);
+
+        while (!(readl(&clk->epll_con0) &
+                       (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
+               if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
+                       debug("%s: Timeout waiting for EPLL lock\n", __func__);
+                       return -1;
+               }
+       }
+       return 0;
+}
+
+void exynos5_set_i2s_clk_source(void)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+
+       clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
+                       (CLK_SRC_SCLK_EPLL));
+}
+
+int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
+                                       unsigned int dst_frq)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       unsigned int div;
+
+       if ((dst_frq == 0) || (src_frq == 0)) {
+               debug("%s: Invalid requency input for prescaler\n", __func__);
+               debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+               return -1;
+       }
+
+       div = (src_frq / dst_frq);
+       if (div > AUDIO_1_RATIO_MASK) {
+               debug("%s: Frequency ratio is out of range\n", __func__);
+               debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+               return -1;
+       }
+       clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
+                               (div & AUDIO_1_RATIO_MASK));
+       return 0;
+}
+
+/**
+ * Linearly searches for the most accurate main and fine stage clock scalars
+ * (divisors) for a specified target frequency and scalar bit sizes by checking
+ * all multiples of main_scalar_bits values. Will always return scalars up to or
+ * slower than target.
+ *
+ * @param main_scalar_bits     Number of main scalar bits, must be > 0 and < 32
+ * @param fine_scalar_bits     Number of fine scalar bits, must be > 0 and < 32
+ * @param input_freq           Clock frequency to be scaled in Hz
+ * @param target_freq          Desired clock frequency in Hz
+ * @param best_fine_scalar     Pointer to store the fine stage divisor
+ *
+ * @return best_main_scalar    Main scalar for desired frequency or -1 if none
+ * found
+ */
+static int clock_calc_best_scalar(unsigned int main_scaler_bits,
+       unsigned int fine_scalar_bits, unsigned int input_rate,
+       unsigned int target_rate, unsigned int *best_fine_scalar)
+{
+       int i;
+       int best_main_scalar = -1;
+       unsigned int best_error = target_rate;
+       const unsigned int cap = (1 << fine_scalar_bits) - 1;
+       const unsigned int loops = 1 << main_scaler_bits;
+
+       debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
+                       target_rate, cap);
+
+       assert(best_fine_scalar != NULL);
+       assert(main_scaler_bits <= fine_scalar_bits);
+
+       *best_fine_scalar = 1;
+
+       if (input_rate == 0 || target_rate == 0)
+               return -1;
+
+       if (target_rate >= input_rate)
+               return 1;
+
+       for (i = 1; i <= loops; i++) {
+               const unsigned int effective_div = max(min(input_rate / i /
+                                                       target_rate, cap), 1);
+               const unsigned int effective_rate = input_rate / i /
+                                                       effective_div;
+               const int error = target_rate - effective_rate;
+
+               debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
+                               effective_rate, error);
+
+               if (error >= 0 && error <= best_error) {
+                       best_error = error;
+                       best_main_scalar = i;
+                       *best_fine_scalar = effective_div;
+               }
+       }
+
+       return best_main_scalar;
+}
+
+static int exynos5_set_spi_clk(enum periph_id periph_id,
+                                       unsigned int rate)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       int main;
+       unsigned int fine;
+       unsigned shift, pre_shift;
+       unsigned mask = 0xff;
+       u32 *reg;
+
+       main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+       if (main < 0) {
+               debug("%s: Cannot set clock rate for periph %d",
+                               __func__, periph_id);
+               return -1;
+       }
+       main = main - 1;
+       fine = fine - 1;
+
+       switch (periph_id) {
+       case PERIPH_ID_SPI0:
+               reg = &clk->div_peric1;
+               shift = 0;
+               pre_shift = 8;
+               break;
+       case PERIPH_ID_SPI1:
+               reg = &clk->div_peric1;
+               shift = 16;
+               pre_shift = 24;
+               break;
+       case PERIPH_ID_SPI2:
+               reg = &clk->div_peric2;
+               shift = 0;
+               pre_shift = 8;
+               break;
+       case PERIPH_ID_SPI3:
+               reg = &clk->sclk_div_isp;
+               shift = 0;
+               pre_shift = 4;
+               break;
+       case PERIPH_ID_SPI4:
+               reg = &clk->sclk_div_isp;
+               shift = 12;
+               pre_shift = 16;
+               break;
+       default:
+               debug("%s: Unsupported peripheral ID %d\n", __func__,
+                     periph_id);
+               return -1;
+       }
+       clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
+       clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
+
+       return 0;
+}
+
+static unsigned long exynos4_get_i2c_clk(void)
+{
+       struct exynos4_clock *clk =
+               (struct exynos4_clock *)samsung_get_base_clock();
+       unsigned long sclk, aclk_100;
+       unsigned int ratio;
+
+       sclk = get_pll_clk(APLL);
+
+       ratio = (readl(&clk->div_top)) >> 4;
+       ratio &= 0xf;
+       aclk_100 = sclk / (ratio + 1);
+       return aclk_100;
+}
+
 unsigned long get_pll_clk(int pllreg)
 {
        if (cpu_is_exynos5())
@@ -752,6 +956,8 @@ unsigned long get_i2c_clk(void)
 {
        if (cpu_is_exynos5()) {
                return exynos5_get_i2c_clk();
+       } else if (cpu_is_exynos4()) {
+               return exynos4_get_i2c_clk();
        } else {
                debug("I2C clock is not set for this CPU\n");
                return 0;
@@ -803,3 +1009,34 @@ void set_mipi_clk(void)
        if (cpu_is_exynos4())
                exynos4_set_mipi_clk();
 }
+
+int set_spi_clk(int periph_id, unsigned int rate)
+{
+       if (cpu_is_exynos5())
+               return exynos5_set_spi_clk(periph_id, rate);
+       else
+               return 0;
+}
+
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
+{
+
+       if (cpu_is_exynos5())
+               return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq);
+       else
+               return 0;
+}
+
+void set_i2s_clk_source(void)
+{
+       if (cpu_is_exynos5())
+               exynos5_set_i2s_clk_source();
+}
+
+int set_epll_clk(unsigned long rate)
+{
+       if (cpu_is_exynos5())
+               return exynos5_set_epll_clk(rate);
+       else
+               return 0;
+}
index 7776add9db3de7fb3212c43e959d6603534c1c2d..20a4b8414a9f5aff3d6a93844f1f8e2f6045706e 100644 (file)
@@ -112,6 +112,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
                s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
                s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
        }
+
        return 0;
 }
 
@@ -230,6 +231,59 @@ static void exynos5_i2c_config(int peripheral, int flags)
        }
 }
 
+static void exynos5_i2s_config(int peripheral)
+{
+       int i;
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+       for (i = 0; i < 5; i++)
+               s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+}
+
+void exynos5_spi_config(int peripheral)
+{
+       int cfg = 0, pin = 0, i;
+       struct s5p_gpio_bank *bank = NULL;
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+       struct exynos5_gpio_part2 *gpio2 =
+               (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
+
+       switch (peripheral) {
+       case PERIPH_ID_SPI0:
+               bank = &gpio1->a2;
+               cfg = GPIO_FUNC(0x2);
+               pin = 0;
+               break;
+       case PERIPH_ID_SPI1:
+               bank = &gpio1->a2;
+               cfg = GPIO_FUNC(0x2);
+               pin = 4;
+               break;
+       case PERIPH_ID_SPI2:
+               bank = &gpio1->b1;
+               cfg = GPIO_FUNC(0x5);
+               pin = 1;
+               break;
+       case PERIPH_ID_SPI3:
+               bank = &gpio2->f1;
+               cfg = GPIO_FUNC(0x2);
+               pin = 0;
+               break;
+       case PERIPH_ID_SPI4:
+               for (i = 0; i < 2; i++) {
+                       s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
+                       s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+               }
+               break;
+       }
+       if (peripheral != PERIPH_ID_SPI4) {
+               for (i = pin; i < pin + 4; i++)
+                       s5p_gpio_cfg_pin(bank, i, cfg);
+       }
+}
+
 static int exynos5_pinmux_config(int peripheral, int flags)
 {
        switch (peripheral) {
@@ -257,6 +311,78 @@ static int exynos5_pinmux_config(int peripheral, int flags)
        case PERIPH_ID_I2C7:
                exynos5_i2c_config(peripheral, flags);
                break;
+       case PERIPH_ID_I2S1:
+               exynos5_i2s_config(peripheral);
+               break;
+       case PERIPH_ID_SPI0:
+       case PERIPH_ID_SPI1:
+       case PERIPH_ID_SPI2:
+       case PERIPH_ID_SPI3:
+       case PERIPH_ID_SPI4:
+               exynos5_spi_config(peripheral);
+               break;
+       default:
+               debug("%s: invalid peripheral %d", __func__, peripheral);
+               return -1;
+       }
+
+       return 0;
+}
+
+static void exynos4_i2c_config(int peripheral, int flags)
+{
+       struct exynos4_gpio_part1 *gpio1 =
+               (struct exynos4_gpio_part1 *) samsung_get_base_gpio_part1();
+
+       switch (peripheral) {
+       case PERIPH_ID_I2C0:
+               s5p_gpio_cfg_pin(&gpio1->d1, 0, GPIO_FUNC(0x2));
+               s5p_gpio_cfg_pin(&gpio1->d1, 1, GPIO_FUNC(0x2));
+               break;
+       case PERIPH_ID_I2C1:
+               s5p_gpio_cfg_pin(&gpio1->d1, 2, GPIO_FUNC(0x2));
+               s5p_gpio_cfg_pin(&gpio1->d1, 3, GPIO_FUNC(0x2));
+               break;
+       case PERIPH_ID_I2C2:
+               s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+               s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+               break;
+       case PERIPH_ID_I2C3:
+               s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+               s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+               break;
+       case PERIPH_ID_I2C4:
+               s5p_gpio_cfg_pin(&gpio1->b, 2, GPIO_FUNC(0x3));
+               s5p_gpio_cfg_pin(&gpio1->b, 3, GPIO_FUNC(0x3));
+               break;
+       case PERIPH_ID_I2C5:
+               s5p_gpio_cfg_pin(&gpio1->b, 6, GPIO_FUNC(0x3));
+               s5p_gpio_cfg_pin(&gpio1->b, 7, GPIO_FUNC(0x3));
+               break;
+       case PERIPH_ID_I2C6:
+               s5p_gpio_cfg_pin(&gpio1->c1, 3, GPIO_FUNC(0x4));
+               s5p_gpio_cfg_pin(&gpio1->c1, 4, GPIO_FUNC(0x4));
+               break;
+       case PERIPH_ID_I2C7:
+               s5p_gpio_cfg_pin(&gpio1->d0, 2, GPIO_FUNC(0x3));
+               s5p_gpio_cfg_pin(&gpio1->d0, 3, GPIO_FUNC(0x3));
+               break;
+       }
+}
+
+static int exynos4_pinmux_config(int peripheral, int flags)
+{
+       switch (peripheral) {
+       case PERIPH_ID_I2C0:
+       case PERIPH_ID_I2C1:
+       case PERIPH_ID_I2C2:
+       case PERIPH_ID_I2C3:
+       case PERIPH_ID_I2C4:
+       case PERIPH_ID_I2C5:
+       case PERIPH_ID_I2C6:
+       case PERIPH_ID_I2C7:
+               exynos4_i2c_config(peripheral, flags);
+               break;
        default:
                debug("%s: invalid peripheral %d", __func__, peripheral);
                return -1;
@@ -269,6 +395,8 @@ int exynos_pinmux_config(int peripheral, int flags)
 {
        if (cpu_is_exynos5())
                return exynos5_pinmux_config(peripheral, flags);
+       else if (cpu_is_exynos4())
+               return exynos4_pinmux_config(peripheral, flags);
        else {
                debug("pinmux functionality not supported\n");
                return -1;
index 1f2fa027c8f84198ab90e2afeb3ff9aa1e5d494b..0efc80ddeb486e5e154091304225ae042d3f1f16 100644 (file)
@@ -25,9 +25,8 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)libomap-common.o
 
-SOBJS  := reset.o
-
-COBJS  := timer.o
+COBJS  := reset.o
+COBJS  += timer.o
 COBJS  += utils.o
 
 ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
index 0f19141cc23ab362c5c66f5ff4d907cd2bb29067..2b584e0a53755ec0164a0412a9449a57760af13f 100644 (file)
@@ -21,6 +21,7 @@
 #include <asm/omap_common.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
 
 /*
  * This is used to verify if the configuration header
index 30dcf1b0b04ec1112a8dead33762c289c8915001..88253cf8ce3e5bf1128d70f08d22bacdfddb09b4 100644 (file)
@@ -33,6 +33,8 @@
 #include <asm/utils.h>
 #include <linux/compiler.h>
 
+static int emif1_enabled = -1, emif2_enabled = -1;
+
 void set_lpmode_selfrefresh(u32 base)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@@ -1109,6 +1111,7 @@ void emif_post_init_config(u32 base)
 void dmm_init(u32 base)
 {
        const struct dmm_lisa_map_regs *lisa_map_regs;
+       u32 i, section, valid;
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
        emif_get_dmm_regs(&lisa_map_regs);
@@ -1216,6 +1219,29 @@ void dmm_init(u32 base)
                writel(lisa_map_regs->dmm_lisa_map_0,
                        &hw_lisa_map_regs->dmm_lisa_map_0);
        }
+
+       /*
+        * EMIF should be configured only when
+        * memory is mapped on it. Using emif1_enabled
+        * and emif2_enabled variables for this.
+        */
+       emif1_enabled = 0;
+       emif2_enabled = 0;
+       for (i = 0; i < 4; i++) {
+               section = __raw_readl(DMM_BASE + i*4);
+               valid = (section & EMIF_SDRC_MAP_MASK) >>
+                       (EMIF_SDRC_MAP_SHIFT);
+               if (valid == 3) {
+                       emif1_enabled = 1;
+                       emif2_enabled = 1;
+                       break;
+               } else if (valid == 1) {
+                       emif1_enabled = 1;
+               } else if (valid == 2) {
+                       emif2_enabled = 1;
+               }
+       }
+
 }
 
 /*
@@ -1255,15 +1281,20 @@ void sdram_init(void)
                        writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
        }
 
-       do_sdram_init(EMIF1_BASE);
-       do_sdram_init(EMIF2_BASE);
-
        if (!in_sdram)
                dmm_init(DMM_BASE);
 
+       if (emif1_enabled)
+               do_sdram_init(EMIF1_BASE);
+
+       if (emif2_enabled)
+               do_sdram_init(EMIF2_BASE);
+
        if (!(in_sdram || warm_reset())) {
-               emif_post_init_config(EMIF1_BASE);
-               emif_post_init_config(EMIF2_BASE);
+               if (emif1_enabled)
+                       emif_post_init_config(EMIF1_BASE);
+               if (emif2_enabled)
+                       emif_post_init_config(EMIF2_BASE);
        }
 
        /* for the shadow registers to take effect */
index f3cd81ad98879b05b55bab3017b22f71b4bffe4b..89c587e3108aca523f71a3f3823a2e220fb43c6a 100644 (file)
@@ -478,7 +478,7 @@ void omap3_outer_cache_disable(void)
         */
        omap3_update_aux_cr(0, 0x2);
 }
-#endif
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
@@ -486,4 +486,4 @@ void enable_caches(void)
        /* Enable D-cache. I-cache is already enabled in start.S */
        dcache_enable();
 }
-#endif
+#endif /* !CONFIG_SYS_DCACHE_OFF */
index 2fe5ac7c3946d4a8f4b09d7dcc85ce441c47bfce..d04a5a10d75e887b2d19516ee6d7ed19de70aa57 100644 (file)
@@ -42,14 +42,7 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
        M_NAND_GPMC_CONFIG5,
        M_NAND_GPMC_CONFIG6, 0
 };
-
-#if defined(CONFIG_ENV_IS_IN_NAND)
-#define GPMC_CS 0
-#else
-#define GPMC_CS 1
-#endif
-
-#endif
+#endif /* CONFIG_CMD_NAND */
 
 #if defined(CONFIG_CMD_ONENAND)
 static const u32 gpmc_onenand[GPMC_MAX_REG] = {
@@ -60,14 +53,7 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = {
        ONENAND_GPMC_CONFIG5,
        ONENAND_GPMC_CONFIG6, 0
 };
-
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
-#define GPMC_CS 0
-#else
-#define GPMC_CS 1
-#endif
-
-#endif
+#endif /* CONFIG_CMD_ONENAND */
 
 /********************************************************
  *  mem_ok() - test used to see if timings are correct
index f6d9b97bb4dcb6df17380c675ecaf96d3afe08ae..e32bf118b182ca9b893dce64597c9d54d70b06ea 100644 (file)
@@ -113,18 +113,18 @@ u32 get_sdr_cs_offset(u32 cs)
  *  - Test CS to make sure it's OK for use
  */
 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
-               u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
+                       struct board_sdrc_timings *timings)
 {
        /* Setup timings we got from the board. */
-       writel(mcfg, &sdrc_base->cs[cs].mcfg);
-       writel(ctrla, &sdrc_actim_base->ctrla);
-       writel(ctrlb, &sdrc_actim_base->ctrlb);
-       writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
+       writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
+       writel(timings->ctrla, &sdrc_actim_base->ctrla);
+       writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
+       writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
        writel(CMD_NOP, &sdrc_base->cs[cs].manual);
        writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
        writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
        writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-       writel(mr, &sdrc_base->cs[cs].mr);
+       writel(timings->mr, &sdrc_base->cs[cs].mr);
 
        /*
         * Test ram in this bank
@@ -143,7 +143,7 @@ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
 void do_sdrc_init(u32 cs, u32 early)
 {
        struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
-       u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr;
+       struct board_sdrc_timings timings;
 
        sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
        sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
@@ -158,7 +158,7 @@ void do_sdrc_init(u32 cs, u32 early)
         * setup CS1.
         */
 #ifdef CONFIG_SPL_BUILD
-       get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
+       get_board_mem_timings(&timings);
 #endif
        if (early) {
                /* reset sdrc controller */
@@ -177,11 +177,9 @@ void do_sdrc_init(u32 cs, u32 early)
                writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
                sdelay(0x20000);
 #ifdef CONFIG_SPL_BUILD
-               write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
-                               rfr_ctrl, mr);
+               write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
                make_cs1_contiguous();
-               write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb,
-                               rfr_ctrl, mr);
+               write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
 #endif
 
        }
@@ -193,14 +191,12 @@ void do_sdrc_init(u32 cs, u32 early)
         * so we may be asked now to setup CS1.
         */
        if (cs == CS1) {
-               mcfg = readl(&sdrc_base->cs[CS0].mcfg),
-               rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
-               ctrla = readl(&sdrc_actim_base0->ctrla),
-               ctrlb = readl(&sdrc_actim_base0->ctrlb);
-               mr = readl(&sdrc_base->cs[CS0].mr);
-               write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb,
-                               rfr_ctrl, mr);
-
+               timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
+               timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
+               timings.ctrla = readl(&sdrc_actim_base0->ctrla);
+               timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
+               timings.mr = readl(&sdrc_base->cs[CS0].mr);
+               write_sdrc_timings(cs, sdrc_actim_base1, &timings);
        }
 }
 
index 5bd0a88fdeb2b730a096602ca01702f63d7afe96..12c58033d2600371c78ab8ae8de40216c1e83c55 100644 (file)
@@ -44,7 +44,7 @@
  */
 #define printf(fmt, args...)
 #define puts(s)
-#endif
+#endif /* !CONFIG_SPL_BUILD */
 
 struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
 
index 2c34e48f42854ae8227b29adf2dc5f39459fd8c4..f4123aaffca6a8b0bc5564b904d60b8d998f901d 100644 (file)
@@ -116,7 +116,7 @@ void do_io_settings(void)
        if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2))
                writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
 }
-#endif
+#endif /* CONFIG_SPL_BUILD */
 
 /* dummy fuction for omap4 */
 void config_data_eye_leveling_samples(u32 emif_base)
@@ -182,4 +182,4 @@ void v7_outer_cache_disable(void)
 {
        set_pl310_ctrl_reg(0);
 }
-#endif
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
index f975f3f06c9fbca7f1fe904eae34d5f57f2dde4a..17053995bd61aa21e26ee20b8917528b09400c41 100644 (file)
@@ -28,7 +28,6 @@ LIB   = $(obj)libs5p-common.o
 COBJS-y                += cpu_info.o
 COBJS-y                += timer.o
 COBJS-y                += sromc.o
-COBJS-y                += wdt.o
 COBJS-$(CONFIG_PWM)    += pwm.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
index 09a0314d0d9e664b799e4d131871a49b83c3c72e..54ed8c48b40814a6436a7fb0918ea3e1504a02a1 100644 (file)
@@ -28,6 +28,8 @@ include $(TOPDIR)/config.mk
 LIB    =  $(obj)lib$(SOC).o
 
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
+COBJS-$(CONFIG_PWM_TEGRA) += pwm.o
+COBJS-$(CONFIG_VIDEO_TEGRA) += display.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c
new file mode 100644 (file)
index 0000000..031f9a8
--- /dev/null
@@ -0,0 +1,409 @@
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/display.h>
+#include <asm/arch/dc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+
+static struct fdt_disp_config config;
+
+static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
+{
+       unsigned h_dda, v_dda;
+       unsigned long val;
+
+       val = readl(&dc->cmd.disp_win_header);
+       val |= WINDOW_A_SELECT;
+       writel(val, &dc->cmd.disp_win_header);
+
+       writel(win->fmt, &dc->win.color_depth);
+
+       clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
+                       BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
+
+       val = win->out_x << H_POSITION_SHIFT;
+       val |= win->out_y << V_POSITION_SHIFT;
+       writel(val, &dc->win.pos);
+
+       val = win->out_w << H_SIZE_SHIFT;
+       val |= win->out_h << V_SIZE_SHIFT;
+       writel(val, &dc->win.size);
+
+       val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
+       val |= win->h << V_PRESCALED_SIZE_SHIFT;
+       writel(val, &dc->win.prescaled_size);
+
+       writel(0, &dc->win.h_initial_dda);
+       writel(0, &dc->win.v_initial_dda);
+
+       h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1);
+       v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1);
+
+       val = h_dda << H_DDA_INC_SHIFT;
+       val |= v_dda << V_DDA_INC_SHIFT;
+       writel(val, &dc->win.dda_increment);
+
+       writel(win->stride, &dc->win.line_stride);
+       writel(0, &dc->win.buf_stride);
+
+       val = WIN_ENABLE;
+       if (win->bpp < 24)
+               val |= COLOR_EXPAND;
+       writel(val, &dc->win.win_opt);
+
+       writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
+       writel(win->x, &dc->winbuf.addr_h_offset);
+       writel(win->y, &dc->winbuf.addr_v_offset);
+
+       writel(0xff00, &dc->win.blend_nokey);
+       writel(0xff00, &dc->win.blend_1win);
+
+       val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
+       val |= GENERAL_UPDATE | WIN_A_UPDATE;
+       writel(val, &dc->cmd.state_ctrl);
+}
+
+static void write_pair(struct fdt_disp_config *config, int item, u32 *reg)
+{
+       writel(config->horiz_timing[item] |
+                       (config->vert_timing[item] << 16), reg);
+}
+
+static int update_display_mode(struct dc_disp_reg *disp,
+               struct fdt_disp_config *config)
+{
+       unsigned long val;
+       unsigned long rate;
+       unsigned long div;
+
+       writel(0x0, &disp->disp_timing_opt);
+       write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
+       write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
+       write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
+       write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
+
+       writel(config->width | (config->height << 16), &disp->disp_active);
+
+       val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
+       val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
+       writel(val, &disp->data_enable_opt);
+
+       val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
+       val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
+       val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
+       writel(val, &disp->disp_interface_ctrl);
+
+       /*
+        * The pixel clock divider is in 7.1 format (where the bottom bit
+        * represents 0.5). Here we calculate the divider needed to get from
+        * the display clock (typically 600MHz) to the pixel clock. We round
+        * up or down as requried.
+        */
+       rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
+       div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
+       debug("Display clock %lu, divider %lu\n", rate, div);
+
+       writel(0x00010001, &disp->shift_clk_opt);
+
+       val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
+       val |= div << SHIFT_CLK_DIVIDER_SHIFT;
+       writel(val, &disp->disp_clk_ctrl);
+
+       return 0;
+}
+
+/* Start up the display and turn on power to PWMs */
+static void basic_init(struct dc_cmd_reg *cmd)
+{
+       u32 val;
+
+       writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
+       writel(0x0000011a, &cmd->cont_syncpt_vsync);
+       writel(0x00000000, &cmd->int_type);
+       writel(0x00000000, &cmd->int_polarity);
+       writel(0x00000000, &cmd->int_mask);
+       writel(0x00000000, &cmd->int_enb);
+
+       val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
+       val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
+       val |= PM1_ENABLE;
+       writel(val, &cmd->disp_pow_ctrl);
+
+       val = readl(&cmd->disp_cmd);
+       val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
+       writel(val, &cmd->disp_cmd);
+}
+
+static void basic_init_timer(struct dc_disp_reg *disp)
+{
+       writel(0x00000020, &disp->mem_high_pri);
+       writel(0x00000001, &disp->mem_high_pri_timer);
+}
+
+static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+};
+
+static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
+       0x00000000,
+       0x01000000,
+       0x00000000,
+       0x00000000,
+};
+
+static const u32 rgb_data_tab[PIN_REG_COUNT] = {
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+};
+
+static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00210222,
+       0x00002200,
+       0x00020000,
+};
+
+static void rgb_enable(struct dc_com_reg *com)
+{
+       int i;
+
+       for (i = 0; i < PIN_REG_COUNT; i++) {
+               writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
+               writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
+               writel(rgb_data_tab[i], &com->pin_output_data[i]);
+       }
+
+       for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
+               writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
+}
+
+int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config)
+{
+       win->x = 0;
+       win->y = 0;
+       win->w = config->width;
+       win->h = config->height;
+       win->out_x = 0;
+       win->out_y = 0;
+       win->out_w = config->width;
+       win->out_h = config->height;
+       win->phys_addr = config->frame_buffer;
+       win->stride = config->width * (1 << config->log2_bpp) / 8;
+       debug("%s: depth = %d\n", __func__, config->log2_bpp);
+       switch (config->log2_bpp) {
+       case 5:
+       case 24:
+               win->fmt = COLOR_DEPTH_R8G8B8A8;
+               win->bpp = 32;
+               break;
+       case 4:
+               win->fmt = COLOR_DEPTH_B5G6R5;
+               win->bpp = 16;
+               break;
+
+       default:
+               debug("Unsupported LCD bit depth");
+               return -1;
+       }
+
+       return 0;
+}
+
+struct fdt_disp_config *tegra_display_get_config(void)
+{
+       return config.valid ? &config : NULL;
+}
+
+static void debug_timing(const char *name, unsigned int timing[])
+{
+#ifdef DEBUG
+       int i;
+
+       debug("%s timing: ", name);
+       for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
+               debug("%d ", timing[i]);
+       debug("\n");
+#endif
+}
+
+/**
+ * Decode panel information from the fdt, according to a standard binding
+ *
+ * @param blob         fdt blob
+ * @param node         offset of fdt node to read from
+ * @param config       structure to store fdt config into
+ * @return 0 if ok, -ve on error
+ */
+static int tegra_decode_panel(const void *blob, int node,
+                             struct fdt_disp_config *config)
+{
+       int front, back, ref;
+
+       config->width = fdtdec_get_int(blob, node, "xres", -1);
+       config->height = fdtdec_get_int(blob, node, "yres", -1);
+       config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0);
+       if (!config->pixel_clock || config->width == -1 ||
+                       config->height == -1) {
+               debug("%s: Pixel parameters missing\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       back = fdtdec_get_int(blob, node, "left-margin", -1);
+       front = fdtdec_get_int(blob, node, "right-margin", -1);
+       ref = fdtdec_get_int(blob, node, "hsync-len", -1);
+       if ((back | front | ref) == -1) {
+               debug("%s: Horizontal parameters missing\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       /* Use a ref-to-sync of 1 always, and take this from the front porch */
+       config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
+       config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
+       config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
+       config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
+               config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
+       debug_timing("horiz", config->horiz_timing);
+
+       back = fdtdec_get_int(blob, node, "upper-margin", -1);
+       front = fdtdec_get_int(blob, node, "lower-margin", -1);
+       ref = fdtdec_get_int(blob, node, "vsync-len", -1);
+       if ((back | front | ref) == -1) {
+               debug("%s: Vertical parameters missing\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
+       config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
+       config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
+       config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
+               config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
+       debug_timing("vert", config->vert_timing);
+
+       return 0;
+}
+
+/**
+ * Decode the display controller information from the fdt.
+ *
+ * @param blob         fdt blob
+ * @param config       structure to store fdt config into
+ * @return 0 if ok, -ve on error
+ */
+static int tegra_display_decode_config(const void *blob,
+                                      struct fdt_disp_config *config)
+{
+       int node, rgb;
+       int bpp, bit;
+
+       /* TODO: Support multiple controllers */
+       node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC);
+       if (node < 0) {
+               debug("%s: Cannot find display controller node in fdt\n",
+                     __func__);
+               return node;
+       }
+       config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
+       if (!config->disp) {
+               debug("%s: No display controller address\n", __func__);
+               return -1;
+       }
+
+       rgb = fdt_subnode_offset(blob, node, "rgb");
+
+       config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
+       if (!config->panel_node < 0) {
+               debug("%s: Cannot find panel information\n", __func__);
+               return -1;
+       }
+
+       if (tegra_decode_panel(blob, config->panel_node, config)) {
+               debug("%s: Failed to decode panel information\n", __func__);
+               return -1;
+       }
+
+       bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel",
+                            -1);
+       bit = ffs(bpp) - 1;
+       if (bpp == (1 << bit))
+               config->log2_bpp = bit;
+       else
+               config->log2_bpp = bpp;
+       if (bpp == -1) {
+               debug("%s: Pixel bpp parameters missing\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+       config->bpp = bpp;
+
+       config->valid = 1;      /* we have a valid configuration */
+
+       return 0;
+}
+
+int tegra_display_probe(const void *blob, void *default_lcd_base)
+{
+       struct disp_ctl_win window;
+       struct dc_ctlr *dc;
+
+       if (tegra_display_decode_config(blob, &config))
+               return -1;
+
+       config.frame_buffer = (u32)default_lcd_base;
+
+       dc = (struct dc_ctlr *)config.disp;
+
+       /*
+        * A header file for clock constants was NAKed upstream.
+        * TODO: Put this into the FDT and fdt_lcd struct when we have clock
+        * support there
+        */
+       clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
+                              144 * 1000000);
+       clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
+                              600 * 1000000);
+       basic_init(&dc->cmd);
+       basic_init_timer(&dc->disp);
+       rgb_enable(&dc->com);
+
+       if (config.pixel_clock)
+               update_display_mode(&dc->disp, &config);
+
+       if (setup_window(&window, &config))
+               return -1;
+
+       update_window(dc, &window);
+
+       return 0;
+}
diff --git a/arch/arm/cpu/armv7/tegra20/pwm.c b/arch/arm/cpu/armv7/tegra20/pwm.c
new file mode 100644 (file)
index 0000000..b655c5c
--- /dev/null
@@ -0,0 +1,101 @@
+/*
+ * Tegra2 pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pwm.h>
+
+struct pwm_info {
+       struct pwm_ctlr *pwm;           /* Registers for our pwm controller */
+       int pwm_node;                   /* PWM device tree node */
+} local;
+
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
+{
+       u32 reg;
+
+       assert(channel < PWM_NUM_CHANNELS);
+
+       /* TODO: Can we use clock_adjust_periph_pll_div() here? */
+       clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
+
+       reg = PWM_ENABLE_MASK;
+       reg |= pulse_width << PWM_WIDTH_SHIFT;
+       reg |= freq_divider << PWM_DIVIDER_SHIFT;
+       writel(reg, &local.pwm[channel].control);
+       debug("%s: channel=%d, rate=%d\n", __func__, channel, rate);
+}
+
+int pwm_request(const void *blob, int node, const char *prop_name)
+{
+       int pwm_node;
+       u32 data[3];
+
+       if (fdtdec_get_int_array(blob, node, prop_name, data,
+                       ARRAY_SIZE(data))) {
+               debug("%s: Cannot decode PWM property '%s'\n", __func__,
+                     prop_name);
+               return -1;
+       }
+
+       pwm_node = fdt_node_offset_by_phandle(blob, data[0]);
+       if (pwm_node != local.pwm_node) {
+               debug("%s: PWM property '%s' phandle %d not recognised"
+                     "- expecting %d\n", __func__, prop_name, data[0],
+                     local.pwm_node);
+               return -1;
+       }
+       if (data[1] >= PWM_NUM_CHANNELS) {
+               debug("%s: PWM property '%s': invalid channel %u\n", __func__,
+                     prop_name, data[1]);
+               return -1;
+       }
+
+       /*
+        * TODO: We could maintain a list of requests, but it might not be
+        * worth it for U-Boot.
+        */
+       return data[1];
+}
+
+int pwm_init(const void *blob)
+{
+       local.pwm_node = fdtdec_next_compatible(blob, 0,
+                                               COMPAT_NVIDIA_TEGRA20_PWM);
+       if (local.pwm_node < 0) {
+               debug("%s: Cannot find device tree node\n", __func__);
+               return -1;
+       }
+
+       local.pwm = (struct pwm_ctlr *)fdtdec_get_addr(blob, local.pwm_node,
+                                                      "reg");
+       if (local.pwm == (struct pwm_ctlr *)FDT_ADDR_T_NONE) {
+               debug("%s: Cannot find pwm reg address\n", __func__);
+               return -1;
+       }
+       debug("Tegra PWM at %p, node %d\n", local.pwm, local.pwm_node);
+
+       return 0;
+}
index 00b8029ebad252be08d43916ba37592ac9f87897..ece7ad9ec954333a9bc9a85769adc97d82b2fe08 100644 (file)
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 
+/*
+ * The PINMUX macro is used to set up pinmux tables.
+ */
+#define PINMUX(grp, mux, pupd, tri)                   \
+       {PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
+
+static const struct pingroup_config disp1_default[] = {
+       PINMUX(LDI,   DISPA,      NORMAL,    NORMAL),
+       PINMUX(LHP0,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LHP1,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LHP2,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LHS,   DISPA,      NORMAL,    NORMAL),
+       PINMUX(LM0,   RSVD4,      NORMAL,    NORMAL),
+       PINMUX(LPP,   DISPA,      NORMAL,    NORMAL),
+       PINMUX(LPW0,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LPW2,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LSC0,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LSPI,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LVP1,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LVS,   DISPA,      NORMAL,    NORMAL),
+       PINMUX(SLXD,  SPDIF,      NORMAL,    NORMAL),
+};
+
+
 int funcmux_select(enum periph_id id, int config)
 {
        int bad_config = config != FUNCMUX_DEFAULT;
@@ -257,6 +281,19 @@ int funcmux_select(enum periph_id id, int config)
                        break;
                }
                break;
+       case PERIPH_ID_DISP1:
+               if (config == FUNCMUX_DEFAULT) {
+                       int i;
+
+                       for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) {
+                               pinmux_set_func(i, PMUX_FUNC_DISPA);
+                               pinmux_tristate_disable(i);
+                               pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
+                       }
+                       pinmux_config_table(disp1_default,
+                                           ARRAY_SIZE(disp1_default));
+               }
+               break;
 
        default:
                debug("%s: invalid periph_id %d", __func__, id);
index 08b83055dbb74b4e660c3865e4930a04f41049c8..a2a09169e54bc46acbdc0b2bc5f89478a775b2be 100644 (file)
@@ -554,7 +554,7 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
        writel(reg, muxctl);
 }
 
-void pinmux_config_pingroup(struct pingroup_config *config)
+void pinmux_config_pingroup(const struct pingroup_config *config)
 {
        enum pmux_pingrp pin = config->pingroup;
 
@@ -563,7 +563,7 @@ void pinmux_config_pingroup(struct pingroup_config *config)
        pinmux_set_tristate(pin, config->tristate);
 }
 
-void pinmux_config_table(struct pingroup_config *config, int len)
+void pinmux_config_table(const struct pingroup_config *config, int len)
 {
        int i;
 
index d936b1e7e6a1d32ff1aa8728cf550b6c44d69b5b..636ec2c1fe7da999c29542bee5b0089f5e6081ba 100644 (file)
                compatible = "nvidia,tegra20-nand";
                reg = <0x70008000 0x100>;
        };
+
+       pwm: pwm@7000a000 {
+               compatible = "nvidia,tegra20-pwm";
+               reg = <0x7000a000 0x100>;
+               #pwm-cells = <2>;
+       };
+
+       host1x {
+               compatible = "nvidia,tegra20-host1x", "simple-bus";
+               reg = <0x50000000 0x00024000>;
+               interrupts = <0 65 0x04   /* mpcore syncpt */
+                             0 67 0x04>; /* mpcore general */
+               status = "disabled";
+
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               ranges = <0x54000000 0x54000000 0x04000000>;
+
+               /* video-encoding/decoding */
+               mpe {
+                       reg = <0x54040000 0x00040000>;
+                       interrupts = <0 68 0x04>;
+                       status = "disabled";
+               };
+
+               /* video input */
+               vi {
+                       reg = <0x54080000 0x00040000>;
+                       interrupts = <0 69 0x04>;
+                       status = "disabled";
+               };
+
+               /* EPP */
+               epp {
+                       reg = <0x540c0000 0x00040000>;
+                       interrupts = <0 70 0x04>;
+                       status = "disabled";
+               };
+
+               /* ISP */
+               isp {
+                       reg = <0x54100000 0x00040000>;
+                       interrupts = <0 71 0x04>;
+                       status = "disabled";
+               };
+
+               /* 2D engine */
+               gr2d {
+                       reg = <0x54140000 0x00040000>;
+                       interrupts = <0 72 0x04>;
+                       status = "disabled";
+               };
+
+               /* 3D engine */
+               gr3d {
+                       reg = <0x54180000 0x00040000>;
+                       status = "disabled";
+               };
+
+               /* display controllers */
+               dc@54200000 {
+                       compatible = "nvidia,tegra20-dc";
+                       reg = <0x54200000 0x00040000>;
+                       interrupts = <0 73 0x04>;
+                       status = "disabled";
+
+                       rgb {
+                               status = "disabled";
+                       };
+               };
+
+               dc@54240000 {
+                       compatible = "nvidia,tegra20-dc";
+                       reg = <0x54240000 0x00040000>;
+                       interrupts = <0 74 0x04>;
+                       status = "disabled";
+
+                       rgb {
+                               status = "disabled";
+                       };
+               };
+
+               /* outputs */
+               hdmi {
+                       compatible = "nvidia,tegra20-hdmi";
+                       reg = <0x54280000 0x00040000>;
+                       interrupts = <0 75 0x04>;
+                       status = "disabled";
+               };
+
+               tvo {
+                       compatible = "nvidia,tegra20-tvo";
+                       reg = <0x542c0000 0x00040000>;
+                       interrupts = <0 76 0x04>;
+                       status = "disabled";
+               };
+
+               dsi {
+                       compatible = "nvidia,tegra20-dsi";
+                       reg = <0x54300000 0x00040000>;
+                       status = "disabled";
+               };
+       };
+
 };
index d6c038e3aec225a46dd13af6ded8e59c1ed621e9..16e8a80700a497936f8c14cd4f023892b7a4c6b7 100644 (file)
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+struct gpmc_cs {
+       u32 config1;            /* 0x00 */
+       u32 config2;            /* 0x04 */
+       u32 config3;            /* 0x08 */
+       u32 config4;            /* 0x0C */
+       u32 config5;            /* 0x10 */
+       u32 config6;            /* 0x14 */
+       u32 config7;            /* 0x18 */
+       u32 nand_cmd;           /* 0x1C */
+       u32 nand_adr;           /* 0x20 */
+       u32 nand_dat;           /* 0x24 */
+       u8 res[8];              /* blow up to 0x30 byte */
+};
+
+struct bch_res_0_3 {
+       u32 bch_result_x[4];
+};
+
+struct gpmc {
+       u8 res1[0x10];
+       u32 sysconfig;          /* 0x10 */
+       u8 res2[0x4];
+       u32 irqstatus;          /* 0x18 */
+       u32 irqenable;          /* 0x1C */
+       u8 res3[0x20];
+       u32 timeout_control;    /* 0x40 */
+       u8 res4[0xC];
+       u32 config;             /* 0x50 */
+       u32 status;             /* 0x54 */
+       u8 res5[0x8];           /* 0x58 */
+       struct gpmc_cs cs[8];   /* 0x60, 0x90, .. */
+       u8 res6[0x14];          /* 0x1E0 */
+       u32 ecc_config;         /* 0x1F4 */
+       u32 ecc_control;        /* 0x1F8 */
+       u32 ecc_size_config;    /* 0x1FC */
+       u32 ecc1_result;        /* 0x200 */
+       u32 ecc2_result;        /* 0x204 */
+       u32 ecc3_result;        /* 0x208 */
+       u32 ecc4_result;        /* 0x20C */
+       u32 ecc5_result;        /* 0x210 */
+       u32 ecc6_result;        /* 0x214 */
+       u32 ecc7_result;        /* 0x218 */
+       u32 ecc8_result;        /* 0x21C */
+       u32 ecc9_result;        /* 0x220 */
+       u8 res7[12];            /* 0x224 */
+       u32 testmomde_ctrl;     /* 0x230 */
+       u8 res8[12];            /* 0x234 */
+       struct bch_res_0_3 bch_result_0_3[2];   /* 0x240 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
 /* Encapsulating core pll registers */
 struct cm_wkuppll {
        unsigned int wkclkstctrl;       /* offset 0x00 */
diff --git a/arch/arm/include/asm/arch-am33xx/elm.h b/arch/arm/include/asm/arch-am33xx/elm.h
new file mode 100644 (file)
index 0000000..e80f7d4
--- /dev/null
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2010-2011 Texas Instruments, <www.ti.com>
+ * Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Derived from work done by Rohit Choraria <rohitkc@ti.com> for omap3
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_ELM_H
+#define __ASM_ARCH_ELM_H
+/*
+ * ELM Module Registers
+ */
+
+/* ELM registers bit fields */
+#define ELM_SYSCONFIG_SOFTRESET_MASK                   (0x2)
+#define ELM_SYSCONFIG_SOFTRESET                        (0x2)
+#define ELM_SYSSTATUS_RESETDONE_MASK                   (0x1)
+#define ELM_SYSSTATUS_RESETDONE                        (0x1)
+#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK         (0x3)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK              (0x7FF0000)
+#define ELM_LOCATION_CONFIG_ECC_SIZE_POS               (16)
+#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID         (0x00010000)
+#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK       (0x100)
+#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK         (0x1F)
+
+#ifndef __ASSEMBLY__
+
+enum bch_level {
+       BCH_4_BIT = 0,
+       BCH_8_BIT,
+       BCH_16_BIT
+};
+
+
+/* BCH syndrome registers */
+struct syndrome {
+       u32 syndrome_fragment_x[7];     /* 0x400, 0x404.... 0x418 */
+       u8 res1[36];                    /* 0x41c */
+};
+
+/* BCH error status & location register */
+struct location {
+       u32 location_status;            /* 0x800 */
+       u8 res1[124];                   /* 0x804 */
+       u32 error_location_x[16];       /* 0x880.... */
+       u8 res2[64];                    /* 0x8c0 */
+};
+
+/* BCH ELM register map - do not try to allocate memmory for this structure.
+ * We have used plenty of reserved variables to fill the slots in the ELM
+ * register memory map.
+ * Directly initialize the struct pointer to ELM base address.
+ */
+struct elm {
+       u32 rev;                                /* 0x000 */
+       u8 res1[12];                            /* 0x004 */
+       u32 sysconfig;                          /* 0x010 */
+       u32 sysstatus;                          /* 0x014 */
+       u32 irqstatus;                          /* 0x018 */
+       u32 irqenable;                          /* 0x01c */
+       u32 location_config;                    /* 0x020 */
+       u8 res2[92];                            /* 0x024 */
+       u32 page_ctrl;                          /* 0x080 */
+       u8 res3[892];                           /* 0x084 */
+       struct  syndrome syndrome_fragments[8]; /* 0x400 */
+       u8 res4[512];                           /* 0x600 */
+       struct location  error_location[8];     /* 0x800 */
+};
+
+int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
+               u32 *error_locations);
+int elm_config(enum bch_level level);
+void elm_reset(void);
+void elm_init(void);
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_ELM_H */
index 24ab365ea31ebdfa6faeb4a07defd197e59a40f9..6dd3296907acce5671364bc09b8b6b65824108f0 100644 (file)
@@ -80,6 +80,9 @@
 #define DDRPHY_0_CONFIG_BASE           (CTRL_BASE + 0x1400)
 #define DDRPHY_CONFIG_BASE             DDRPHY_0_CONFIG_BASE
 
+/* GPMC Base address */
+#define GPMC_BASE                      0x50000000
+
 /* CPSW Config space */
 #define AM335X_CPSW_BASE               0x4A100000
 #define AM335X_CPSW_MDIO_BASE          0x4A101000
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
new file mode 100644 (file)
index 0000000..c3bf74e
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ *             Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *             Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * M_NAND - Micron NAND
+ */
+#define GPMC_SIZE_256M         0x0
+#define GPMC_SIZE_128M         0x8
+#define GPMC_SIZE_64M          0xC
+#define GPMC_SIZE_32M          0xE
+#define GPMC_SIZE_16M          0xF
+
+#define M_NAND_GPMC_CONFIG1    0x00000800
+#define M_NAND_GPMC_CONFIG2    0x001e1e00
+#define M_NAND_GPMC_CONFIG3    0x001e1e00
+#define M_NAND_GPMC_CONFIG4    0x16051807
+#define M_NAND_GPMC_CONFIG5    0x00151e1e
+#define M_NAND_GPMC_CONFIG6    0x16000f80
+#define M_NAND_GPMC_CONFIG7    0x00000008
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS            8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG           7
+
+#define PISMO1_NOR             1
+#define PISMO1_NAND            2
+#define PISMO2_CS0             3
+#define PISMO2_CS1             4
+#define PISMO1_ONENAND         5
+#define DBG_MPDB               6
+#define PISMO2_NAND_CS0                7
+#define PISMO2_NAND_CS1                8
+
+/* make it readable for the gpmc_init */
+#define PISMO1_NOR_BASE        FLASH_BASE
+#define PISMO1_NAND_BASE       CONFIG_SYS_NAND_BASE
+#define PISMO1_NAND_SIZE       GPMC_SIZE_256M
+
+#endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h
new file mode 100644 (file)
index 0000000..572f9d0
--- /dev/null
@@ -0,0 +1,120 @@
+/*
+ * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
+ * Rohit Choraria <rohitkc@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_OMAP_GPMC_H
+#define __ASM_ARCH_OMAP_GPMC_H
+
+#define GPMC_BUF_EMPTY 0
+#define GPMC_BUF_FULL  1
+
+#define ECCCLEAR       (0x1 << 8)
+#define ECCRESULTREG1  (0x1 << 0)
+#define ECCSIZE512BYTE 0xFF
+#define ECCSIZE1       (ECCSIZE512BYTE << 22)
+#define ECCSIZE0       (ECCSIZE512BYTE << 12)
+#define ECCSIZE0SEL    (0x000 << 0)
+
+/* Generic ECC Layouts */
+/* Large Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+       .eccbytes = 12,\
+       .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
+               9, 10, 11, 12},\
+       .oobfree = {\
+               {.offset = 13,\
+                .length = 51 } } \
+}
+#endif
+
+/* Large Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+       .eccbytes = 12,\
+       .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
+               10, 11, 12, 13},\
+       .oobfree = {\
+               {.offset = 14,\
+                .length = 50 } } \
+}
+#endif
+
+/* Small Page x8 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+       .eccbytes = 3,\
+       .eccpos = {1, 2, 3},\
+       .oobfree = {\
+               {.offset = 4,\
+                .length = 12 } } \
+}
+#endif
+
+/* Small Page x16 NAND device Layout */
+#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
+#define GPMC_NAND_HW_ECC_LAYOUT {\
+       .eccbytes = 3,\
+       .eccpos = {2, 3, 4},\
+       .oobfree = {\
+               {.offset = 5,\
+                .length = 11 } } \
+}
+#endif
+
+#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
+       .eccbytes = 32,\
+       .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+                               16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+                               28, 29, 30, 31, 32, 33},\
+       .oobfree = {\
+               {.offset = 34,\
+                .length = 30 } } \
+}
+
+#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
+       .eccbytes = 56,\
+       .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+                               16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+                               28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+                               40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+                               52, 53, 54, 55, 56, 57},\
+       .oobfree = {\
+               {.offset = 58,\
+                .length = 6 } } \
+}
+
+#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
+       .eccbytes = 104,\
+       .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
+                               16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
+                               28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
+                               40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
+                               52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
+                               64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
+                               76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
+                               88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
+                               100, 101, 102, 103, 104, 105},\
+       .oobfree = {\
+               {.offset = 106,\
+                .length = 8 } } \
+}
+#endif /* __ASM_ARCH_OMAP_GPMC_H */
index 9cf35e0257838bb5cfca49cc885b86e25fed1cd8..588d8de82fbf2b0e75db5c6fa8bef29eb5486673 100644 (file)
@@ -33,4 +33,7 @@ u32 get_device_type(void);
 void setup_clocks_for_console(void);
 void ddr_pll_config(unsigned int ddrpll_M);
 
+void sdelay(unsigned long);
+void gpmc_init(void);
+void omap_nand_switch_ecc(int);
 #endif
index 552902573ff3536b895a6ad5b9e6a543a4395ee7..cd12323509a844c26c5de4c539b46bc854856d91 100644 (file)
@@ -38,5 +38,9 @@ void set_mmc_clk(int dev_index, unsigned int div);
 unsigned long get_lcd_clk(void);
 void set_lcd_clk(void);
 void set_mipi_clk(void);
+void set_i2s_clk_source(void);
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
+int set_epll_clk(unsigned long rate);
+int set_spi_clk(int periph_id, unsigned int rate);
 
 #endif
index fce38efbb259892d9511a12b893e41197061792c..ff6781aae45a41e616f81e5d5816f32a66e57ec2 100644 (file)
@@ -595,9 +595,38 @@ struct exynos5_clock {
        unsigned int    pll_div2_sel;
        unsigned char   res123[0xf5d8];
 };
+
+/* structure for epll configuration used in audio clock configuration */
+struct set_epll_con_val {
+       unsigned int freq_out;          /* frequency out */
+       unsigned int en_lock_det;       /* enable lock detect */
+       unsigned int m_div;             /* m divider value */
+       unsigned int p_div;             /* p divider value */
+       unsigned int s_div;             /* s divider value */
+       unsigned int k_dsm;             /* k value of delta signal modulator */
+};
 #endif
 
 #define MPLL_FOUT_SEL_SHIFT    4
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT  29  /* EPLL Locked bit position*/
+#define TIMEOUT_EPLL_LOCK              1000
+
+#define AUDIO_0_RATIO_MASK             0x0f
+#define AUDIO_1_RATIO_MASK             0x0f
+
+#define AUDIO1_SEL_MASK                        0xf
+#define CLK_SRC_SCLK_EPLL              0x7
+
+/* CON0 bit-fields */
+#define EPLL_CON0_MDIV_MASK            0x1ff
+#define EPLL_CON0_PDIV_MASK            0x3f
+#define EPLL_CON0_SDIV_MASK            0x7
+#define EPLL_CON0_MDIV_SHIFT           16
+#define EPLL_CON0_PDIV_SHIFT           8
+#define EPLL_CON0_SDIV_SHIFT           0
+#define EPLL_CON0_LOCK_DET_EN_SHIFT    28
+#define EPLL_CON0_LOCK_DET_EN_MASK     1
+
 #define MPLL_FOUT_SEL_MASK     0x1
 #define BPLL_FOUT_SEL_SHIFT    0
 #define BPLL_FOUT_SEL_MASK     0x1
index 2cd4ae152624bd5e7a213fd9a66a0768f33a1da1..f06af2eb8592597944aa3b7393396545b9c45541 100644 (file)
@@ -28,6 +28,8 @@
 #define EXYNOS4_ADDR_BASE              0x10000000
 
 /* EXYNOS4 */
+#define EXYNOS4_I2C_SPACING            0x10000
+
 #define EXYNOS4_GPIO_PART3_BASE                0x03860000
 #define EXYNOS4_PRO_ID                 0x10000000
 #define EXYNOS4_SYSREG_BASE            0x10010000
 #define EXYNOS4_UART_BASE              0x13800000
 #define EXYNOS4_I2C_BASE               0x13860000
 #define EXYNOS4_ADC_BASE               0x13910000
+#define EXYNOS4_SPI_BASE               0x13920000
 #define EXYNOS4_PWMTIMER_BASE          0x139D0000
 #define EXYNOS4_MODEM_BASE             0x13A00000
 #define EXYNOS4_USBPHY_CONTROL         0x10020704
+#define EXYNOS4_I2S_BASE               0xE2100000
 
 #define EXYNOS4_GPIO_PART4_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DP_BASE                        DEVICE_NOT_AVAILABLE
+#define EXYNOS4_SPI_ISP_BASE           DEVICE_NOT_AVAILABLE
 
 /* EXYNOS5 */
 #define EXYNOS5_I2C_SPACING            0x10000
 #define EXYNOS5_SROMC_BASE             0x12250000
 #define EXYNOS5_UART_BASE              0x12C00000
 #define EXYNOS5_I2C_BASE               0x12C60000
+#define EXYNOS5_SPI_BASE               0x12D20000
+#define EXYNOS5_I2S_BASE               0x12D60000
 #define EXYNOS5_PWMTIMER_BASE          0x12DD0000
+#define EXYNOS5_SPI_ISP_BASE           0x131A0000
 #define EXYNOS5_GPIO_PART2_BASE                0x13400000
 #define EXYNOS5_FIMD_BASE              0x14400000
 #define EXYNOS5_DP_BASE                        0x145B0000
@@ -139,6 +147,15 @@ static inline int cpu_is_##type(void)                      \
 IS_SAMSUNG_TYPE(exynos4, 0x4)
 IS_SAMSUNG_TYPE(exynos5, 0x5)
 
+#define IS_EXYNOS_TYPE(type, id)                       \
+static inline int proid_is_##type(void)                        \
+{                                                      \
+       return s5p_cpu_id == id;                        \
+}
+
+IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos5250, 0x5250)
+
 #define SAMSUNG_BASE(device, base)                             \
 static inline unsigned int samsung_get_base_##device(void)     \
 {                                                              \
@@ -156,6 +173,7 @@ SAMSUNG_BASE(dp, DP_BASE)
 SAMSUNG_BASE(sysreg, SYSREG_BASE)
 SAMSUNG_BASE(fimd, FIMD_BASE)
 SAMSUNG_BASE(i2c, I2C_BASE)
+SAMSUNG_BASE(i2s, I2S_BASE)
 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
@@ -173,6 +191,8 @@ SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
+SAMSUNG_BASE(spi, SPI_BASE)
+SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
 #endif
 
 #endif /* _EXYNOS4_CPU_H */
index 97be4eac052d122573bbd750e0081a2bda611420..4db8fd640e0f78006d040f5abe53c1100585269f 100644 (file)
@@ -207,6 +207,25 @@ static inline unsigned int s5p_gpio_base(int nr)
        return 0;
 }
 
+static inline unsigned int s5p_gpio_part_max(int nr)
+{
+       if (cpu_is_exynos5()) {
+               if (nr < EXYNOS5_GPIO_PART1_MAX)
+                       return 0;
+               else if (nr < EXYNOS5_GPIO_PART2_MAX)
+                       return EXYNOS5_GPIO_PART1_MAX;
+               else
+                       return EXYNOS5_GPIO_PART2_MAX;
+
+       } else if (cpu_is_exynos4()) {
+               if (nr < EXYNOS4_GPIO_PART1_MAX)
+                       return 0;
+               else
+                       return EXYNOS4_GPIO_PART1_MAX;
+       }
+
+       return 0;
+}
 #endif
 
 /* Pin configurations */
diff --git a/arch/arm/include/asm/arch-exynos/i2s-regs.h b/arch/arm/include/asm/arch-exynos/i2s-regs.h
new file mode 100644 (file)
index 0000000..2326ca0
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __I2S_REGS_H__
+#define __I2S_REGS_H__
+
+#define CON_TXFIFO_FULL                (1 << 8)
+#define CON_TXCH_PAUSE         (1 << 4)
+#define CON_ACTIVE             (1 << 0)
+
+#define MOD_BLCP_SHIFT         24
+#define MOD_BLCP_16BIT         (0 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_8BIT          (1 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_24BIT         (2 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_MASK          (3 << MOD_BLCP_SHIFT)
+
+#define MOD_BLC_16BIT          (0 << 13)
+#define MOD_BLC_8BIT           (1 << 13)
+#define MOD_BLC_24BIT          (2 << 13)
+#define MOD_BLC_MASK           (3 << 13)
+
+#define MOD_SLAVE              (1 << 11)
+#define MOD_MASK               (3 << 8)
+#define MOD_LR_LLOW            (0 << 7)
+#define MOD_LR_RLOW            (1 << 7)
+#define MOD_SDF_IIS            (0 << 5)
+#define MOD_SDF_MSB            (1 << 5)
+#define MOD_SDF_LSB            (2 << 5)
+#define MOD_SDF_MASK           (3 << 5)
+#define MOD_RCLK_256FS         (0 << 3)
+#define MOD_RCLK_512FS         (1 << 3)
+#define MOD_RCLK_384FS         (2 << 3)
+#define MOD_RCLK_768FS         (3 << 3)
+#define MOD_RCLK_MASK          (3 << 3)
+#define MOD_BCLK_32FS          (0 << 1)
+#define MOD_BCLK_48FS          (1 << 1)
+#define MOD_BCLK_16FS          (2 << 1)
+#define MOD_BCLK_24FS          (3 << 1)
+#define MOD_BCLK_MASK          (3 << 1)
+
+#define MOD_CDCLKCON           (1 << 12)
+
+#define FIC_TXFLUSH            (1 << 15)
+#define FIC_RXFLUSH            (1 << 7)
+
+#endif /* __I2S_REGS_H__ */
index b861d7d58425060a3a90d545e42efaa27f82177d..13abd2d703a58d7dacb42dd533aff3b4a6c0a8bf 100644 (file)
@@ -38,11 +38,18 @@ enum periph_id {
        PERIPH_ID_I2C5,
        PERIPH_ID_I2C6,
        PERIPH_ID_I2C7,
+       PERIPH_ID_I2S1,
        PERIPH_ID_SDMMC0,
        PERIPH_ID_SDMMC1,
        PERIPH_ID_SDMMC2,
        PERIPH_ID_SDMMC3,
+       PERIPH_ID_SDMMC4,
        PERIPH_ID_SROMC,
+       PERIPH_ID_SPI0,
+       PERIPH_ID_SPI1,
+       PERIPH_ID_SPI2,
+       PERIPH_ID_SPI3,
+       PERIPH_ID_SPI4,
        PERIPH_ID_UART0,
        PERIPH_ID_UART1,
        PERIPH_ID_UART2,
diff --git a/arch/arm/include/asm/arch-exynos/sound.h b/arch/arm/include/asm/arch-exynos/sound.h
new file mode 100644 (file)
index 0000000..d1bd2f6
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __SOUND_ARCH_H__
+#define __SOUND_ARCH_H__
+
+/* I2S values */
+#define I2S_PLL_CLK            192000000
+#define I2S_SAMPLING_RATE      48000
+#define I2S_BITS_PER_SAMPLE    16
+#define I2S_CHANNELS           2
+#define I2S_RFS                        256
+#define I2S_BFS                        32
+
+/* I2C values */
+#define AUDIO_I2C_BUS          1
+#define AUDIO_I2C_REG          0x1a
+
+/* Audio Codec */
+#define AUDIO_CODEC            "wm8994"
+
+#define AUDIO_COMPAT           1
+#endif
diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h
new file mode 100644 (file)
index 0000000..7cab1e9
--- /dev/null
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Padmavathi Venna <padma.v@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+
+#ifndef __ASSEMBLY__
+
+/* SPI peripheral register map; padded to 64KB */
+struct exynos_spi {
+       unsigned int            ch_cfg;         /* 0x00 */
+       unsigned char           reserved0[4];
+       unsigned int            mode_cfg;       /* 0x08 */
+       unsigned int            cs_reg;         /* 0x0c */
+       unsigned char           reserved1[4];
+       unsigned int            spi_sts;        /* 0x14 */
+       unsigned int            tx_data;        /* 0x18 */
+       unsigned int            rx_data;        /* 0x1c */
+       unsigned int            pkt_cnt;        /* 0x20 */
+       unsigned char           reserved2[4];
+       unsigned char           reserved3[4];
+       unsigned int            fb_clk;         /* 0x2c */
+       unsigned char           padding[0xffd0];
+};
+
+#define EXYNOS_SPI_MAX_FREQ    50000000
+
+#define SPI_TIMEOUT_MS         10
+
+/* SPI_CHCFG */
+#define SPI_CH_HS_EN           (1 << 6)
+#define SPI_CH_RST             (1 << 5)
+#define SPI_SLAVE_MODE         (1 << 4)
+#define SPI_CH_CPOL_L          (1 << 3)
+#define SPI_CH_CPHA_B          (1 << 2)
+#define SPI_RX_CH_ON           (1 << 1)
+#define SPI_TX_CH_ON           (1 << 0)
+
+/* SPI_MODECFG */
+#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
+#define SPI_MODE_BUS_WIDTH_WORD        (0x2 << 17)
+
+/* SPI_CSREG */
+#define SPI_SLAVE_SIG_INACT    (1 << 0)
+
+/* SPI_STS */
+#define SPI_ST_TX_DONE         (1 << 25)
+#define SPI_FIFO_LVL_MASK      0x1ff
+#define SPI_TX_LVL_OFFSET      6
+#define SPI_RX_LVL_OFFSET      15
+
+/* Feedback Delay */
+#define SPI_CLK_BYPASS         (0 << 0)
+#define SPI_FB_DELAY_90                (1 << 0)
+#define SPI_FB_DELAY_180       (2 << 0)
+#define SPI_FB_DELAY_270       (3 << 0)
+
+/* Packet Count */
+#define SPI_PACKET_CNT_EN      (1 << 16)
+
+#endif /* __ASSEMBLY__ */
+#endif
index 1700fe39155f7a8fd982a38237f72b2eeb0e2a4e..3d39ef235d611ce17c3f466db61ce667e734bc99 100644 (file)
@@ -35,6 +35,7 @@ enum mxc_clock {
        MXC_SSP1_CLK,
        MXC_SSP2_CLK,
        MXC_SSP3_CLK,
+       MXC_XTAL_CLK,
 };
 
 enum mxs_ioclock {
index 9e52b12aa291ac3145a0a779909642919f553f82..d60f2addb2aa166c52301e24fc4f1e469d0d653b 100644 (file)
@@ -32,6 +32,15 @@ struct emu_hal_params {
        u32 param1;
 };
 
+/* Board SDRC timing values */
+struct board_sdrc_timings {
+       u32 mcfg;
+       u32 ctrla;
+       u32 ctrlb;
+       u32 rfr_ctrl;
+       u32 mr;
+};
+
 void prcm_init(void);
 void per_clocks_enable(void);
 void ehci_clocks_enable(void);
@@ -39,8 +48,8 @@ void ehci_clocks_enable(void);
 void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr);
+
+void get_board_mem_timings(struct board_sdrc_timings *timings);
 void identify_nand_chip(int *mfr, int *id);
 void emif4_init(void);
 void gpmc_init(void);
index 76b901b3977bbc5110f45ad47546400e479775ed..00e498d834b3dea2164cbdfc0dcdec40999fa16f 100644 (file)
@@ -143,7 +143,12 @@ static inline unsigned int s5p_gpio_base(int nr)
        return S5PC110_GPIO_BASE;
 }
 
-#define s5pc110_gpio_get_nr(bank, pin) \
+static inline unsigned int s5p_gpio_part_max(int nr)
+{
+       return 0;
+}
+
+#define s5pc110_gpio_get_nr(bank, pin)   \
        ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
            - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
          * GPIO_PER_BANK) + pin)
diff --git a/arch/arm/include/asm/arch-tegra20/dc.h b/arch/arm/include/asm/arch-tegra20/dc.h
new file mode 100644 (file)
index 0000000..37934e1
--- /dev/null
@@ -0,0 +1,545 @@
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DC_H
+#define __ASM_ARCH_TEGRA_DC_H
+
+/* Register definitions for the Tegra display controller */
+
+/* CMD register 0x000 ~ 0x43 */
+struct dc_cmd_reg {
+       /* Address 0x000 ~ 0x002 */
+       uint gen_incr_syncpt;           /* _CMD_GENERAL_INCR_SYNCPT_0 */
+       uint gen_incr_syncpt_ctrl;      /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
+       uint gen_incr_syncpt_err;       /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
+
+       uint reserved0[5];              /* reserved_0[5] */
+
+       /* Address 0x008 ~ 0x00a */
+       uint win_a_incr_syncpt;         /* _CMD_WIN_A_INCR_SYNCPT_0 */
+       uint win_a_incr_syncpt_ctrl;    /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
+       uint win_a_incr_syncpt_err;     /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
+
+       uint reserved1[5];              /* reserved_1[5] */
+
+       /* Address 0x010 ~ 0x012 */
+       uint win_b_incr_syncpt;         /* _CMD_WIN_B_INCR_SYNCPT_0 */
+       uint win_b_incr_syncpt_ctrl;    /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
+       uint win_b_incr_syncpt_err;     /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */
+
+       uint reserved2[5];              /* reserved_2[5] */
+
+       /* Address 0x018 ~ 0x01a */
+       uint win_c_incr_syncpt;         /* _CMD_WIN_C_INCR_SYNCPT_0 */
+       uint win_c_incr_syncpt_ctrl;    /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */
+       uint win_c_incr_syncpt_err;     /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */
+
+       uint reserved3[13];             /* reserved_3[13] */
+
+       /* Address 0x028 */
+       uint cont_syncpt_vsync;         /* _CMD_CONT_SYNCPT_VSYNC_0 */
+
+       uint reserved4[7];              /* reserved_4[7] */
+
+       /* Address 0x030 ~ 0x033 */
+       uint ctxsw;                     /* _CMD_CTXSW_0 */
+       uint disp_cmd_opt0;             /* _CMD_DISPLAY_COMMAND_OPTION0_0 */
+       uint disp_cmd;                  /* _CMD_DISPLAY_COMMAND_0 */
+       uint sig_raise;                 /* _CMD_SIGNAL_RAISE_0 */
+
+       uint reserved5[2];              /* reserved_0[2] */
+
+       /* Address 0x036 ~ 0x03e */
+       uint disp_pow_ctrl;             /* _CMD_DISPLAY_POWER_CONTROL_0 */
+       uint int_stat;                  /* _CMD_INT_STATUS_0 */
+       uint int_mask;                  /* _CMD_INT_MASK_0 */
+       uint int_enb;                   /* _CMD_INT_ENABLE_0 */
+       uint int_type;                  /* _CMD_INT_TYPE_0 */
+       uint int_polarity;              /* _CMD_INT_POLARITY_0 */
+       uint sig_raise1;                /* _CMD_SIGNAL_RAISE1_0 */
+       uint sig_raise2;                /* _CMD_SIGNAL_RAISE2_0 */
+       uint sig_raise3;                /* _CMD_SIGNAL_RAISE3_0 */
+
+       uint reserved6;                 /* reserved_6 */
+
+       /* Address 0x040 ~ 0x043 */
+       uint state_access;              /* _CMD_STATE_ACCESS_0 */
+       uint state_ctrl;                /* _CMD_STATE_CONTROL_0 */
+       uint disp_win_header;           /* _CMD_DISPLAY_WINDOW_HEADER_0 */
+       uint reg_act_ctrl;              /* _CMD_REG_ACT_CONTROL_0 */
+};
+
+enum {
+       PIN_REG_COUNT           = 4,
+       PIN_OUTPUT_SEL_COUNT    = 7,
+};
+
+/* COM register 0x300 ~ 0x329 */
+struct dc_com_reg {
+       /* Address 0x300 ~ 0x301 */
+       uint crc_ctrl;                  /* _COM_CRC_CONTROL_0 */
+       uint crc_checksum;              /* _COM_CRC_CHECKSUM_0 */
+
+       /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */
+       uint pin_output_enb[PIN_REG_COUNT];
+
+       /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */
+       uint pin_output_polarity[PIN_REG_COUNT];
+
+       /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */
+       uint pin_output_data[PIN_REG_COUNT];
+
+       /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */
+       uint pin_input_enb[PIN_REG_COUNT];
+
+       /* Address 0x312 ~ 0x313 */
+       uint pin_input_data0;           /* _COM_PIN_INPUT_DATA0_0 */
+       uint pin_input_data1;           /* _COM_PIN_INPUT_DATA1_0 */
+
+       /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */
+       uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
+
+       /* Address 0x31b ~ 0x329 */
+       uint pin_misc_ctrl;             /* _COM_PIN_MISC_CONTROL_0 */
+       uint pm0_ctrl;                  /* _COM_PM0_CONTROL_0 */
+       uint pm0_duty_cycle;            /* _COM_PM0_DUTY_CYCLE_0 */
+       uint pm1_ctrl;                  /* _COM_PM1_CONTROL_0 */
+       uint pm1_duty_cycle;            /* _COM_PM1_DUTY_CYCLE_0 */
+       uint spi_ctrl;                  /* _COM_SPI_CONTROL_0 */
+       uint spi_start_byte;            /* _COM_SPI_START_BYTE_0 */
+       uint hspi_wr_data_ab;           /* _COM_HSPI_WRITE_DATA_AB_0 */
+       uint hspi_wr_data_cd;           /* _COM_HSPI_WRITE_DATA_CD */
+       uint hspi_cs_dc;                /* _COM_HSPI_CS_DC_0 */
+       uint scratch_reg_a;             /* _COM_SCRATCH_REGISTER_A_0 */
+       uint scratch_reg_b;             /* _COM_SCRATCH_REGISTER_B_0 */
+       uint gpio_ctrl;                 /* _COM_GPIO_CTRL_0 */
+       uint gpio_debounce_cnt;         /* _COM_GPIO_DEBOUNCE_COUNTER_0 */
+       uint crc_checksum_latched;      /* _COM_CRC_CHECKSUM_LATCHED_0 */
+};
+
+enum dc_disp_h_pulse_pos {
+       H_PULSE0_POSITION_A,
+       H_PULSE0_POSITION_B,
+       H_PULSE0_POSITION_C,
+       H_PULSE0_POSITION_D,
+       H_PULSE0_POSITION_COUNT,
+};
+
+struct _disp_h_pulse {
+       /* _DISP_H_PULSE0/1/2_CONTROL_0 */
+       uint h_pulse_ctrl;
+       /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */
+       uint h_pulse_pos[H_PULSE0_POSITION_COUNT];
+};
+
+enum dc_disp_v_pulse_pos {
+       V_PULSE0_POSITION_A,
+       V_PULSE0_POSITION_B,
+       V_PULSE0_POSITION_C,
+       V_PULSE0_POSITION_COUNT,
+};
+
+struct _disp_v_pulse0 {
+       /* _DISP_H_PULSE0/1_CONTROL_0 */
+       uint v_pulse_ctrl;
+       /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */
+       uint v_pulse_pos[V_PULSE0_POSITION_COUNT];
+};
+
+struct _disp_v_pulse2 {
+       /* _DISP_H_PULSE2/3_CONTROL_0 */
+       uint v_pulse_ctrl;
+       /* _DISP_H_PULSE2/3_POSITION_A_0 */
+       uint v_pulse_pos_a;
+};
+
+enum dc_disp_h_pulse_reg {
+       H_PULSE0,
+       H_PULSE1,
+       H_PULSE2,
+       H_PULSE_COUNT,
+};
+
+enum dc_disp_pp_select {
+       PP_SELECT_A,
+       PP_SELECT_B,
+       PP_SELECT_C,
+       PP_SELECT_D,
+       PP_SELECT_COUNT,
+};
+
+/* DISP register 0x400 ~ 0x4c1 */
+struct dc_disp_reg {
+       /* Address 0x400 ~ 0x40a */
+       uint disp_signal_opt0;          /* _DISP_DISP_SIGNAL_OPTIONS0_0 */
+       uint disp_signal_opt1;          /* _DISP_DISP_SIGNAL_OPTIONS1_0 */
+       uint disp_win_opt;              /* _DISP_DISP_WIN_OPTIONS_0 */
+       uint mem_high_pri;              /* _DISP_MEM_HIGH_PRIORITY_0 */
+       uint mem_high_pri_timer;        /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */
+       uint disp_timing_opt;           /* _DISP_DISP_TIMING_OPTIONS_0 */
+       uint ref_to_sync;               /* _DISP_REF_TO_SYNC_0 */
+       uint sync_width;                /* _DISP_SYNC_WIDTH_0 */
+       uint back_porch;                /* _DISP_BACK_PORCH_0 */
+       uint disp_active;               /* _DISP_DISP_ACTIVE_0 */
+       uint front_porch;               /* _DISP_FRONT_PORCH_0 */
+
+       /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_  */
+       struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
+
+       /* Address 0x41a ~ 0x421 */
+       struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */
+       struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */
+
+       /* Address 0x422 ~ 0x425 */
+       struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */
+       struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */
+
+       /* Address 0x426 ~ 0x429 */
+       uint m0_ctrl;                   /* _DISP_M0_CONTROL_0 */
+       uint m1_ctrl;                   /* _DISP_M1_CONTROL_0 */
+       uint di_ctrl;                   /* _DISP_DI_CONTROL_0 */
+       uint pp_ctrl;                   /* _DISP_PP_CONTROL_0 */
+
+       /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */
+       uint pp_select[PP_SELECT_COUNT];
+
+       /* Address 0x42e ~ 0x435 */
+       uint disp_clk_ctrl;             /* _DISP_DISP_CLOCK_CONTROL_0 */
+       uint disp_interface_ctrl;       /* _DISP_DISP_INTERFACE_CONTROL_0 */
+       uint disp_color_ctrl;           /* _DISP_DISP_COLOR_CONTROL_0 */
+       uint shift_clk_opt;             /* _DISP_SHIFT_CLOCK_OPTIONS_0 */
+       uint data_enable_opt;           /* _DISP_DATA_ENABLE_OPTIONS_0 */
+       uint serial_interface_opt;      /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */
+       uint lcd_spi_opt;               /* _DISP_LCD_SPI_OPTIONS_0 */
+       uint border_color;              /* _DISP_BORDER_COLOR_0 */
+
+       /* Address 0x436 ~ 0x439 */
+       uint color_key0_lower;          /* _DISP_COLOR_KEY0_LOWER_0 */
+       uint color_key0_upper;          /* _DISP_COLOR_KEY0_UPPER_0 */
+       uint color_key1_lower;          /* _DISP_COLOR_KEY1_LOWER_0 */
+       uint color_key1_upper;          /* _DISP_COLOR_KEY1_UPPER_0 */
+
+       uint reserved0[2];              /* reserved_0[2] */
+
+       /* Address 0x43c ~ 0x442 */
+       uint cursor_foreground;         /* _DISP_CURSOR_FOREGROUND_0 */
+       uint cursor_background;         /* _DISP_CURSOR_BACKGROUND_0 */
+       uint cursor_start_addr;         /* _DISP_CURSOR_START_ADDR_0 */
+       uint cursor_start_addr_ns;      /* _DISP_CURSOR_START_ADDR_NS_0 */
+       uint cursor_pos;                /* _DISP_CURSOR_POSITION_0 */
+       uint cursor_pos_ns;             /* _DISP_CURSOR_POSITION_NS_0 */
+       uint seq_ctrl;                  /* _DISP_INIT_SEQ_CONTROL_0 */
+
+       /* Address 0x442 ~ 0x446 */
+       uint spi_init_seq_data_a;       /* _DISP_SPI_INIT_SEQ_DATA_A_0 */
+       uint spi_init_seq_data_b;       /* _DISP_SPI_INIT_SEQ_DATA_B_0 */
+       uint spi_init_seq_data_c;       /* _DISP_SPI_INIT_SEQ_DATA_C_0 */
+       uint spi_init_seq_data_d;       /* _DISP_SPI_INIT_SEQ_DATA_D_0 */
+
+       uint reserved1[0x39];           /* reserved1[0x39], */
+
+       /* Address 0x480 ~ 0x484 */
+       uint dc_mccif_fifoctrl;         /* _DISP_DC_MCCIF_FIFOCTRL_0 */
+       uint mccif_disp0a_hyst;         /* _DISP_MCCIF_DISPLAY0A_HYST_0 */
+       uint mccif_disp0b_hyst;         /* _DISP_MCCIF_DISPLAY0B_HYST_0 */
+       uint mccif_disp0c_hyst;         /* _DISP_MCCIF_DISPLAY0C_HYST_0 */
+       uint mccif_disp1b_hyst;         /* _DISP_MCCIF_DISPLAY1B_HYST_0 */
+
+       uint reserved2[0x3b];           /* reserved2[0x3b] */
+
+       /* Address 0x4c0 ~ 0x4c1 */
+       uint dac_crt_ctrl;              /* _DISP_DAC_CRT_CTRL_0 */
+       uint disp_misc_ctrl;            /* _DISP_DISP_MISC_CONTROL_0 */
+};
+
+enum dc_winc_filter_p {
+       WINC_FILTER_COUNT       = 0x10,
+};
+
+/* Window A/B/C register 0x500 ~ 0x628 */
+struct dc_winc_reg {
+
+       /* Address 0x500 */
+       uint color_palette;             /* _WINC_COLOR_PALETTE_0 */
+
+       uint reserved0[0xff];           /* reserved_0[0xff] */
+
+       /* Address 0x600 */
+       uint palette_color_ext;         /* _WINC_PALETTE_COLOR_EXT_0 */
+
+       /* _WINC_H_FILTER_P00~0F_0 */
+       /* Address 0x601 ~ 0x610 */
+       uint h_filter_p[WINC_FILTER_COUNT];
+
+       /* Address 0x611 ~ 0x618 */
+       uint csc_yof;                   /* _WINC_CSC_YOF_0 */
+       uint csc_kyrgb;                 /* _WINC_CSC_KYRGB_0 */
+       uint csc_kur;                   /* _WINC_CSC_KUR_0 */
+       uint csc_kvr;                   /* _WINC_CSC_KVR_0 */
+       uint csc_kug;                   /* _WINC_CSC_KUG_0 */
+       uint csc_kvg;                   /* _WINC_CSC_KVG_0 */
+       uint csc_kub;                   /* _WINC_CSC_KUB_0 */
+       uint csc_kvb;                   /* _WINC_CSC_KVB_0 */
+
+       /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
+       uint v_filter_p[WINC_FILTER_COUNT];
+};
+
+/* WIN A/B/C Register 0x700 ~ 0x714*/
+struct dc_win_reg {
+       /* Address 0x700 ~ 0x714 */
+       uint win_opt;                   /* _WIN_WIN_OPTIONS_0 */
+       uint byte_swap;                 /* _WIN_BYTE_SWAP_0 */
+       uint buffer_ctrl;               /* _WIN_BUFFER_CONTROL_0 */
+       uint color_depth;               /* _WIN_COLOR_DEPTH_0 */
+       uint pos;                       /* _WIN_POSITION_0 */
+       uint size;                      /* _WIN_SIZE_0 */
+       uint prescaled_size;            /* _WIN_PRESCALED_SIZE_0 */
+       uint h_initial_dda;             /* _WIN_H_INITIAL_DDA_0 */
+       uint v_initial_dda;             /* _WIN_V_INITIAL_DDA_0 */
+       uint dda_increment;             /* _WIN_DDA_INCREMENT_0 */
+       uint line_stride;               /* _WIN_LINE_STRIDE_0 */
+       uint buf_stride;                /* _WIN_BUF_STRIDE_0 */
+       uint uv_buf_stride;             /* _WIN_UV_BUF_STRIDE_0 */
+       uint buffer_addr_mode;          /* _WIN_BUFFER_ADDR_MODE_0 */
+       uint dv_ctrl;                   /* _WIN_DV_CONTROL_0 */
+       uint blend_nokey;               /* _WIN_BLEND_NOKEY_0 */
+       uint blend_1win;                /* _WIN_BLEND_1WIN_0 */
+       uint blend_2win_x;              /* _WIN_BLEND_2WIN_X_0 */
+       uint blend_2win_y;              /* _WIN_BLEND_2WIN_Y_0 */
+       uint blend_3win_xy;             /* _WIN_BLEND_3WIN_XY_0 */
+       uint hp_fetch_ctrl;             /* _WIN_HP_FETCH_CONTROL_0 */
+};
+
+/* WINBUF A/B/C Register 0x800 ~ 0x80a */
+struct dc_winbuf_reg {
+       /* Address 0x800 ~ 0x80a */
+       uint start_addr;                /* _WINBUF_START_ADDR_0 */
+       uint start_addr_ns;             /* _WINBUF_START_ADDR_NS_0 */
+       uint start_addr_u;              /* _WINBUF_START_ADDR_U_0 */
+       uint start_addr_u_ns;           /* _WINBUF_START_ADDR_U_NS_0 */
+       uint start_addr_v;              /* _WINBUF_START_ADDR_V_0 */
+       uint start_addr_v_ns;           /* _WINBUF_START_ADDR_V_NS_0 */
+       uint addr_h_offset;             /* _WINBUF_ADDR_H_OFFSET_0 */
+       uint addr_h_offset_ns;          /* _WINBUF_ADDR_H_OFFSET_NS_0 */
+       uint addr_v_offset;             /* _WINBUF_ADDR_V_OFFSET_0 */
+       uint addr_v_offset_ns;          /* _WINBUF_ADDR_V_OFFSET_NS_0 */
+       uint uflow_status;              /* _WINBUF_UFLOW_STATUS_0 */
+};
+
+/* Display Controller (DC_) regs */
+struct dc_ctlr {
+       struct dc_cmd_reg cmd;          /* CMD register 0x000 ~ 0x43 */
+       uint reserved0[0x2bc];
+
+       struct dc_com_reg com;          /* COM register 0x300 ~ 0x329 */
+       uint reserved1[0xd6];
+
+       struct dc_disp_reg disp;        /* DISP register 0x400 ~ 0x4c1 */
+       uint reserved2[0x3e];
+
+       struct dc_winc_reg winc;        /* Window A/B/C 0x500 ~ 0x628 */
+       uint reserved3[0xd7];
+
+       struct dc_win_reg win;          /* WIN A/B/C 0x700 ~ 0x714*/
+       uint reserved4[0xeb];
+
+       struct dc_winbuf_reg winbuf;    /* WINBUF A/B/C 0x800 ~ 0x80a */
+};
+
+#define BIT(pos)       (1U << pos)
+
+/* DC_CMD_DISPLAY_COMMAND 0x032 */
+#define CTRL_MODE_SHIFT                5
+#define CTRL_MODE_MASK         (0x3 << CTRL_MODE_SHIFT)
+enum {
+       CTRL_MODE_STOP,
+       CTRL_MODE_C_DISPLAY,
+       CTRL_MODE_NC_DISPLAY,
+};
+
+/* _WIN_COLOR_DEPTH_0 */
+enum win_color_depth_id {
+       COLOR_DEPTH_P1,
+       COLOR_DEPTH_P2,
+       COLOR_DEPTH_P4,
+       COLOR_DEPTH_P8,
+       COLOR_DEPTH_B4G4R4A4,
+       COLOR_DEPTH_B5G5R5A,
+       COLOR_DEPTH_B5G6R5,
+       COLOR_DEPTH_AB5G5R5,
+       COLOR_DEPTH_B8G8R8A8 = 12,
+       COLOR_DEPTH_R8G8B8A8,
+       COLOR_DEPTH_B6x2G6x2R6x2A8,
+       COLOR_DEPTH_R6x2G6x2B6x2A8,
+       COLOR_DEPTH_YCbCr422,
+       COLOR_DEPTH_YUV422,
+       COLOR_DEPTH_YCbCr420P,
+       COLOR_DEPTH_YUV420P,
+       COLOR_DEPTH_YCbCr422P,
+       COLOR_DEPTH_YUV422P,
+       COLOR_DEPTH_YCbCr422R,
+       COLOR_DEPTH_YUV422R,
+       COLOR_DEPTH_YCbCr422RA,
+       COLOR_DEPTH_YUV422RA,
+};
+
+/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */
+#define PW0_ENABLE             BIT(0)
+#define PW1_ENABLE             BIT(2)
+#define PW2_ENABLE             BIT(4)
+#define PW3_ENABLE             BIT(6)
+#define PW4_ENABLE             BIT(8)
+#define PM0_ENABLE             BIT(16)
+#define PM1_ENABLE             BIT(18)
+#define SPI_ENABLE             BIT(24)
+#define HSPI_ENABLE            BIT(25)
+
+/* DC_CMD_STATE_CONTROL 0x041 */
+#define GENERAL_ACT_REQ                BIT(0)
+#define WIN_A_ACT_REQ          BIT(1)
+#define WIN_B_ACT_REQ          BIT(2)
+#define WIN_C_ACT_REQ          BIT(3)
+#define GENERAL_UPDATE         BIT(8)
+#define WIN_A_UPDATE           BIT(9)
+#define WIN_B_UPDATE           BIT(10)
+#define WIN_C_UPDATE           BIT(11)
+
+/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
+#define WINDOW_A_SELECT                BIT(4)
+#define WINDOW_B_SELECT                BIT(5)
+#define WINDOW_C_SELECT                BIT(6)
+
+/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
+#define SHIFT_CLK_DIVIDER_SHIFT        0
+#define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT)
+#define        PIXEL_CLK_DIVIDER_SHIFT 8
+#define        PIXEL_CLK_DIVIDER_MSK   (0xf << PIXEL_CLK_DIVIDER_SHIFT)
+enum {
+       PIXEL_CLK_DIVIDER_PCD1,
+       PIXEL_CLK_DIVIDER_PCD1H,
+       PIXEL_CLK_DIVIDER_PCD2,
+       PIXEL_CLK_DIVIDER_PCD3,
+       PIXEL_CLK_DIVIDER_PCD4,
+       PIXEL_CLK_DIVIDER_PCD6,
+       PIXEL_CLK_DIVIDER_PCD8,
+       PIXEL_CLK_DIVIDER_PCD9,
+       PIXEL_CLK_DIVIDER_PCD12,
+       PIXEL_CLK_DIVIDER_PCD16,
+       PIXEL_CLK_DIVIDER_PCD18,
+       PIXEL_CLK_DIVIDER_PCD24,
+       PIXEL_CLK_DIVIDER_PCD13,
+};
+
+/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */
+#define DATA_FORMAT_SHIFT      0
+#define DATA_FORMAT_MASK       (0xf << DATA_FORMAT_SHIFT)
+enum {
+       DATA_FORMAT_DF1P1C,
+       DATA_FORMAT_DF1P2C24B,
+       DATA_FORMAT_DF1P2C18B,
+       DATA_FORMAT_DF1P2C16B,
+       DATA_FORMAT_DF2S,
+       DATA_FORMAT_DF3S,
+       DATA_FORMAT_DFSPI,
+       DATA_FORMAT_DF1P3C24B,
+       DATA_FORMAT_DF1P3C18B,
+};
+#define DATA_ALIGNMENT_SHIFT   8
+enum {
+       DATA_ALIGNMENT_MSB,
+       DATA_ALIGNMENT_LSB,
+};
+#define DATA_ORDER_SHIFT       9
+enum {
+       DATA_ORDER_RED_BLUE,
+       DATA_ORDER_BLUE_RED,
+};
+
+/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
+#define DE_SELECT_SHIFT                0
+#define DE_SELECT_MASK         (0x3 << DE_SELECT_SHIFT)
+#define DE_SELECT_ACTIVE_BLANK 0x0
+#define DE_SELECT_ACTIVE       0x1
+#define DE_SELECT_ACTIVE_IS    0x2
+#define DE_CONTROL_SHIFT       2
+#define DE_CONTROL_MASK                (0x7 << DE_CONTROL_SHIFT)
+enum {
+       DE_CONTROL_ONECLK,
+       DE_CONTROL_NORMAL,
+       DE_CONTROL_EARLY_EXT,
+       DE_CONTROL_EARLY,
+       DE_CONTROL_ACTIVE_BLANK,
+};
+
+/* DC_WIN_WIN_OPTIONS 0x700 */
+#define H_DIRECTION            BIT(0)
+enum {
+       H_DIRECTION_INCREMENT,
+       H_DIRECTION_DECREMENT,
+};
+#define V_DIRECTION            BIT(2)
+enum {
+       V_DIRECTION_INCREMENT,
+       V_DIRECTION_DECREMENT,
+};
+#define COLOR_EXPAND           BIT(6)
+#define CP_ENABLE              BIT(16)
+#define DV_ENABLE              BIT(20)
+#define WIN_ENABLE             BIT(30)
+
+/* DC_WIN_BYTE_SWAP 0x701 */
+#define BYTE_SWAP_SHIFT                0
+#define BYTE_SWAP_MASK         (3 << BYTE_SWAP_SHIFT)
+enum {
+       BYTE_SWAP_NOSWAP,
+       BYTE_SWAP_SWAP2,
+       BYTE_SWAP_SWAP4,
+       BYTE_SWAP_SWAP4HW
+};
+
+/* DC_WIN_POSITION 0x704 */
+#define H_POSITION_SHIFT       0
+#define H_POSITION_MASK                (0x1FFF << H_POSITION_SHIFT)
+#define V_POSITION_SHIFT       16
+#define V_POSITION_MASK                (0x1FFF << V_POSITION_SHIFT)
+
+/* DC_WIN_SIZE 0x705 */
+#define H_SIZE_SHIFT           0
+#define H_SIZE_MASK            (0x1FFF << H_SIZE_SHIFT)
+#define V_SIZE_SHIFT           16
+#define V_SIZE_MASK            (0x1FFF << V_SIZE_SHIFT)
+
+/* DC_WIN_PRESCALED_SIZE 0x706 */
+#define H_PRESCALED_SIZE_SHIFT 0
+#define H_PRESCALED_SIZE_MASK  (0x7FFF << H_PRESCALED_SIZE)
+#define V_PRESCALED_SIZE_SHIFT 16
+#define V_PRESCALED_SIZE_MASK  (0x1FFF << V_PRESCALED_SIZE)
+
+/* DC_WIN_DDA_INCREMENT 0x709 */
+#define H_DDA_INC_SHIFT                0
+#define H_DDA_INC_MASK         (0xFFFF << H_DDA_INC_SHIFT)
+#define V_DDA_INC_SHIFT                16
+#define V_DDA_INC_MASK         (0xFFFF << V_DDA_INC_SHIFT)
+
+#endif /* __ASM_ARCH_TEGRA_DC_H */
diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h
new file mode 100644 (file)
index 0000000..c870959
--- /dev/null
@@ -0,0 +1,152 @@
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
+#define __ASM_ARCH_TEGRA_DISPLAY_H
+
+#include <asm/arch/dc.h>
+#include <fdtdec.h>
+
+/* This holds information about a window which can be displayed */
+struct disp_ctl_win {
+       enum win_color_depth_id fmt;    /* Color depth/format */
+       unsigned        bpp;            /* Bits per pixel */
+       phys_addr_t     phys_addr;      /* Physical address in memory */
+       unsigned        x;              /* Horizontal address offset (bytes) */
+       unsigned        y;              /* Veritical address offset (bytes) */
+       unsigned        w;              /* Width of source window */
+       unsigned        h;              /* Height of source window */
+       unsigned        stride;         /* Number of bytes per line */
+       unsigned        out_x;          /* Left edge of output window (col) */
+       unsigned        out_y;          /* Top edge of output window (row) */
+       unsigned        out_w;          /* Width of output window in pixels */
+       unsigned        out_h;          /* Height of output window in pixels */
+};
+
+#define FDT_LCD_TIMINGS        4
+
+enum {
+       FDT_LCD_TIMING_REF_TO_SYNC,
+       FDT_LCD_TIMING_SYNC_WIDTH,
+       FDT_LCD_TIMING_BACK_PORCH,
+       FDT_LCD_TIMING_FRONT_PORCH,
+
+       FDT_LCD_TIMING_COUNT,
+};
+
+enum lcd_cache_t {
+       FDT_LCD_CACHE_OFF               = 0,
+       FDT_LCD_CACHE_WRITE_THROUGH     = 1 << 0,
+       FDT_LCD_CACHE_WRITE_BACK        = 1 << 1,
+       FDT_LCD_CACHE_FLUSH             = 1 << 2,
+       FDT_LCD_CACHE_WRITE_BACK_FLUSH  = FDT_LCD_CACHE_WRITE_BACK |
+                                               FDT_LCD_CACHE_FLUSH,
+};
+
+/* Information about the display controller */
+struct fdt_disp_config {
+       int valid;                      /* config is valid */
+       int width;                      /* width in pixels */
+       int height;                     /* height in pixels */
+       int bpp;                        /* number of bits per pixel */
+
+       /*
+        * log2 of number of bpp, in general, unless it bpp is 24 in which
+        * case this field holds 24 also! This is a U-Boot thing.
+        */
+       int log2_bpp;
+       struct disp_ctlr *disp;         /* Display controller to use */
+       fdt_addr_t frame_buffer;        /* Address of frame buffer */
+       unsigned pixel_clock;           /* Pixel clock in Hz */
+       uint horiz_timing[FDT_LCD_TIMING_COUNT];        /* Horizontal timing */
+       uint vert_timing[FDT_LCD_TIMING_COUNT];         /* Vertical timing */
+       int panel_node;                 /* node offset of panel information */
+};
+
+/* Information about the LCD panel */
+struct fdt_panel_config {
+       int pwm_channel;                /* PWM channel to use for backlight */
+       enum lcd_cache_t cache_type;
+
+       struct fdt_gpio_state backlight_en;     /* GPIO for backlight enable */
+       struct fdt_gpio_state lvds_shutdown;    /* GPIO for lvds shutdown */
+       struct fdt_gpio_state backlight_vdd;    /* GPIO for backlight vdd */
+       struct fdt_gpio_state panel_vdd;        /* GPIO for panel vdd */
+       /*
+        * Panel required timings
+        * Timing 1: delay between panel_vdd-rise and data-rise
+        * Timing 2: delay between data-rise and backlight_vdd-rise
+        * Timing 3: delay between backlight_vdd and pwm-rise
+        * Timing 4: delay between pwm-rise and backlight_en-rise
+        */
+       uint panel_timings[FDT_LCD_TIMINGS];
+};
+
+/**
+ * Register a new display based on device tree configuration.
+ *
+ * The frame buffer can be positioned by U-Boot or overriden by the fdt.
+ * You should pass in the U-Boot address here, and check the contents of
+ * struct fdt_disp_config to see what was actually chosen.
+ *
+ * @param blob                 Device tree blob
+ * @param default_lcd_base     Default address of LCD frame buffer
+ * @return 0 if ok, -1 on error (unsupported bits per pixel)
+ */
+int tegra_display_probe(const void *blob, void *default_lcd_base);
+
+/**
+ * Return the current display configuration
+ *
+ * @return pointer to display configuration, or NULL if there is no valid
+ * config
+ */
+struct fdt_disp_config *tegra_display_get_config(void);
+
+/**
+ * Perform the next stage of the LCD init if it is time to do so.
+ *
+ * LCD init can be time-consuming because of the number of delays we need
+ * while waiting for the backlight power supply, etc. This function can
+ * be called at various times during U-Boot operation to advance the
+ * initialization of the LCD to the next stage if sufficient time has
+ * passed since the last stage. It keeps track of what stage it is up to
+ * and the time that it is permitted to move to the next stage.
+ *
+ * The final call should have wait=1 to complete the init.
+ *
+ * @param blob fdt blob containing LCD information
+ * @param wait 1 to wait until all init is complete, and then return
+ *             0 to return immediately, potentially doing nothing if it is
+ *             not yet time for the next init.
+ */
+int tegra_lcd_check_next_stage(const void *blob, int wait);
+
+/**
+ * Set up the maximum LCD size so we can size the frame buffer.
+ *
+ * @param blob fdt blob containing LCD information
+ */
+void tegra_lcd_early_init(const void *blob);
+
+#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
index 03fa7ca643b78af7d6e4dc11b1a6a15009391ee5..797e158e68ae49b14cf646a76add1d5098eff8da 100644 (file)
@@ -339,7 +339,7 @@ void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
 
 /* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
+void pinmux_config_pingroup(const struct pingroup_config *config);
 
 void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
 
@@ -349,6 +349,6 @@ void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
  * @param config       List of config items
  * @param len          Number of config items in list
  */
-void pinmux_config_table(struct pingroup_config *config, int len);
+void pinmux_config_table(const struct pingroup_config *config, int len);
 
 #endif /* PINMUX_H */
diff --git a/arch/arm/include/asm/arch-tegra20/pwm.h b/arch/arm/include/asm/arch-tegra20/pwm.h
new file mode 100644 (file)
index 0000000..9e03837
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_PWM_H
+#define __ASM_ARCH_TEGRA_PWM_H
+
+/* This is a single PWM channel */
+struct pwm_ctlr {
+       uint control;           /* Control register */
+       uint reserved[3];       /* Space space */
+};
+
+#define PWM_NUM_CHANNELS       4
+
+/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
+#define PWM_ENABLE_SHIFT       31
+#define PWM_ENABLE_MASK        (0x1 << PWM_ENABLE_SHIFT)
+
+#define PWM_WIDTH_SHIFT        16
+#define PWM_WIDTH_MASK         (0x7FFF << PWM_WIDTH_SHIFT)
+
+#define PWM_DIVIDER_SHIFT      0
+#define PWM_DIVIDER_MASK       (0x1FFF << PWM_DIVIDER_SHIFT)
+
+/**
+ * Program the PWM with the given parameters.
+ *
+ * @param channel      PWM channel to update
+ * @param rate         Clock rate to use for PWM
+ * @param pulse_width  high pulse width: 0=always low, 1=1/256 pulse high,
+ *                     n = n/256 pulse high
+ * @param freq_divider frequency divider value (1 to use rate as is)
+ */
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider);
+
+/**
+ * Request a pwm channel as referenced by a device tree node.
+ *
+ * This channel can then be passed to pwm_enable().
+ *
+ * @param blob         Device tree blob
+ * @param node         Node containing reference to pwm
+ * @param prop_name    Property name of pwm reference
+ * @return channel number, if ok, else -1
+ */
+int pwm_request(const void *blob, int node, const char *prop_name);
+
+/**
+ * Set up the pwm controller, by looking it up in the fdt.
+ *
+ * @return 0 if ok, -1 if the device tree node was not found or invalid.
+ */
+int pwm_init(const void *blob);
+
+#endif /* __ASM_ARCH_TEGRA_PWM_H */
index 516cc4260c13ffe7d61f8a75f63ffd5990543d7b..1ebfa8694f6a02644fff72e81df109c8de610d19 100644 (file)
@@ -49,4 +49,11 @@ extern const struct gpio_bank *const omap_gpio_bank;
 
 #define METHOD_GPIO_24XX       4
 
+/**
+ * Check if gpio is valid.
+ *
+ * @param gpio GPIO number
+ * @return 1 if ok, 0 on error
+ */
+int gpio_is_valid(int gpio);
 #endif /* _GPIO_H_ */
index 2b28a261ba0218692cf0a121807d44429ce026af..78ca8e0a6dc10741469753edff8d73cc96b61d29 100644 (file)
@@ -75,6 +75,37 @@ static inline void set_cr(unsigned int val)
        isb();
 }
 
+/* options available for data cache on each page */
+enum dcache_option {
+       DCACHE_OFF = 0x12,
+       DCACHE_WRITETHROUGH = 0x1a,
+       DCACHE_WRITEBACK = 0x1e,
+};
+
+/* Size of an MMU section */
+enum {
+       MMU_SECTION_SHIFT       = 20,
+       MMU_SECTION_SIZE        = 1 << MMU_SECTION_SHIFT,
+};
+
+/**
+ * Change the cache settings for a region.
+ *
+ * \param start                start address of memory region to change
+ * \param size         size of memory region to change
+ * \param option       dcache option to select
+ */
+void mmu_set_region_dcache_behaviour(u32 start, int size,
+                                    enum dcache_option option);
+
+/**
+ * Register an update to the page tables, and flush the TLB
+ *
+ * \param start                start address of update in page table
+ * \param stop         stop address of update in page table
+ */
+void mmu_page_table_flush(unsigned long start, unsigned long stop);
+
 #endif /* __ASSEMBLY__ */
 
 #define arch_align_stack(x) (x)
index 22a4d9cc0e59d4c877fb8892e2f960b0cad32843..e0cb6353a3feb95fc35734875d53e16b633c3cd7 100644 (file)
@@ -540,15 +540,13 @@ void board_init_r(gd_t *id, ulong dest_addr)
        flash_size = flash_init();
        if (flash_size > 0) {
 # ifdef CONFIG_SYS_FLASH_CHECKSUM
-               char *s = getenv("flashchecksum");
-
                print_size(flash_size, "");
                /*
                 * Compute and print flash CRC if flashchecksum is set to 'y'
                 *
                 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
                 */
-               if (s && (*s == 'y')) {
+               if (getenv_yesno("flashchecksum") == 1) {
                        printf("  CRC: %08X", crc32(0,
                                (const unsigned char *) CONFIG_SYS_FLASH_BASE,
                                flash_size));
index 939de10e039153d0fd1ef29cb962366d5357a355..6edf815d4d7b85f9b6197260b9b870acb01b586f 100644 (file)
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-#define CACHE_SETUP    0x1a
-#else
-#define CACHE_SETUP    0x1e
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void __arm_init_before_mmu(void)
@@ -50,9 +44,41 @@ static void cp_delay (void)
        asm volatile("" : : : "memory");
 }
 
-static inline void dram_bank_mmu_setup(int bank)
+void set_section_dcache(int section, enum dcache_option option)
 {
        u32 *page_table = (u32 *)gd->tlb_addr;
+       u32 value;
+
+       value = (section << MMU_SECTION_SHIFT) | (3 << 10);
+       value |= option;
+       page_table[section] = value;
+}
+
+void __mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+       debug("%s: Warning: not implemented\n", __func__);
+}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+       __attribute__((weak, alias("__mmu_page_table_flush")));
+
+void mmu_set_region_dcache_behaviour(u32 start, int size,
+                                    enum dcache_option option)
+{
+       u32 *page_table = (u32 *)gd->tlb_addr;
+       u32 upto, end;
+
+       end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
+       start = start >> MMU_SECTION_SHIFT;
+       debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
+             option);
+       for (upto = start; upto < end; upto++)
+               set_section_dcache(upto, option);
+       mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+}
+
+static inline void dram_bank_mmu_setup(int bank)
+{
        bd_t *bd = gd->bd;
        int     i;
 
@@ -60,21 +86,24 @@ static inline void dram_bank_mmu_setup(int bank)
        for (i = bd->bi_dram[bank].start >> 20;
             i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
             i++) {
-               page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+               set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+               set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
        }
 }
 
 /* to activate the MMU we need to set up virtual memory: use 1M areas */
 static inline void mmu_setup(void)
 {
-       u32 *page_table = (u32 *)gd->tlb_addr;
        int i;
        u32 reg;
 
        arm_init_before_mmu();
        /* Set up an identity-mapping for all 4GB, rw for everyone */
        for (i = 0; i < 4096; i++)
-               page_table[i] = i << 20 | (3 << 10) | 0x12;
+               set_section_dcache(i, DCACHE_OFF);
 
        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
                dram_bank_mmu_setup(i);
@@ -82,7 +111,7 @@ static inline void mmu_setup(void)
 
        /* Copy the page table address to cp15 */
        asm volatile("mcr p15, 0, %0, c2, c0, 0"
-                    : : "r" (page_table) : "memory");
+                    : : "r" (gd->tlb_addr) : "memory");
        /* Set the access control to all-supervisor */
        asm volatile("mcr p15, 0, %0, c3, c0, 0"
                     : : "r" (~0));
index e0773a88285a726c45a6f61f7a4f47557e227221..ecf5e56e1078d1fb583ca6421d16d919144bdd91 100644 (file)
@@ -16,7 +16,7 @@
 #endif
 
 extern int strcasecmp(const char *, const char *);
-extern int strncasecmp(const char *, const char *, int);
+extern int strncasecmp(const char *, const char *, __kernel_size_t);
 extern char * strcpy(char *,const char *);
 extern char * strncpy(char *,const char *, __kernel_size_t);
 extern __kernel_size_t strlen(const char *);
index 02d73fda6111045052d5be20e1efe19e833bbc14..794b8679fefe2696bef4a8857f5b6d036b0c8882 100644 (file)
@@ -462,8 +462,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
                 *
                 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
                 */
-               s = getenv ("flashchecksum");
-               if (s && (*s == 'y')) {
+               if (getenv_yesno("flashchecksum") == 1) {
                        printf ("  CRC: %08X",
                                        crc32 (0,
                                                   (const unsigned char *) CONFIG_SYS_FLASH_BASE,
index efd63cd341213de1c81865cb6994b64367af5916..a7c2f7623392fc1fce53dd2eb992a6f74d8620d7 100644 (file)
@@ -74,7 +74,6 @@ void board_init_f(ulong not_used)
        gd = (gd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET);
        bd = (bd_t *) (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
                                                - GENERATED_BD_INFO_SIZE);
-       __maybe_unused char *s;
 #if defined(CONFIG_CMD_FLASH)
        ulong flash_size = 0;
 #endif
@@ -143,8 +142,7 @@ void board_init_f(ulong not_used)
                 *
                 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
                 */
-               s = getenv ("flashchecksum");
-               if (s && (*s == 'y')) {
+               if (getenv_yesno("flashchecksum") == 1) {
                        printf ("  CRC: %08X",
                                crc32(0, (const u8 *)bd->bi_flashstart,
                                                        flash_size)
index 4112de7026a51f8c854a14414f9d9f920b7ef28f..2b8d531e73b84ef9d2e0280165ed1668dad9d318 100644 (file)
@@ -108,7 +108,12 @@ reset:
        mtc0    t0, CP0_CONFIG
 #endif
 
-       /* Initialize $gp */
+       /*
+        * Initialize $gp, force 8 byte alignment of bal instruction to forbid
+        * the compiler to put nop's between bal and _gp. This is required to
+        * keep _gp and ra aligned to 8 byte.
+        */
+       .align  3
        bal     1f
         nop
        .dword  _gp
index 1c8f4c05003ba83ff0aacf66d94268d901dbf21a..f2dc5335690de97517c58ff5bbaf7627fbc3636f 100644 (file)
@@ -566,7 +566,7 @@ static __inline__ int __test_and_change_bit(int nr, volatile void * addr)
  * @nr: bit number to test
  * @addr: Address to start counting from
  */
-static __inline__ int test_bit(int nr, volatile void *addr)
+static __inline__ int test_bit(int nr, const volatile void *addr)
 {
        return ((1UL << (nr & 31)) & (((const unsigned int *) addr)[nr >> 5])) != 0;
 }
index 7ddd77832cc5f165111d5b553d212002fa6d1047..d79e1837d9a37c21c07556618a22dc9c60e173e7 100644 (file)
@@ -24,6 +24,7 @@
 #include <common.h>
 #include <command.h>
 #include <malloc.h>
+#include <serial.h>
 #include <stdio_dev.h>
 #include <version.h>
 #include <net.h>
@@ -46,7 +47,7 @@ static char *failed = "*** failed ***\n";
  * mips_io_port_base is the begin of the address space to which x86 style
  * I/O ports are mapped.
  */
-unsigned long mips_io_port_base = -1;
+const unsigned long mips_io_port_base = -1;
 
 int __board_early_init_f(void)
 {
@@ -262,6 +263,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
 
        monitor_flash_len = (ulong)&uboot_end_data - dest_addr;
 
+       serial_initialize();
+
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
        /*
         * We have to relocate the command table manually
index e1197ac9e5e70ac9e843298d9bf5e367a7fdb6be..43d4836303d4f02149ce6f9f117dbf5e395be17b 100644 (file)
@@ -46,10 +46,8 @@ u32 get_my_id()
  */
 int hold_cores_in_reset(int verbose)
 {
-       const char *s = getenv("mp_holdoff");
-
        /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */
-       if (s && (*s == 'y' || *s == 'Y' || *s == '1')) {
+       if (getenv_yesno("mp_holdoff") == 1) {
                if (verbose) {
                        puts("Secondary cores are being held in reset.\n");
                        puts("See 'mp_holdoff' environment variable\n");
index d912a6b5fed2649156f0658a7e8d1a500f8dc550..036805ede2990800288d83ff52bee364d0147b8e 100644 (file)
@@ -14,7 +14,7 @@
 #define __HAVE_ARCH_MEMCHR
 
 extern int strcasecmp(const char *, const char *);
-extern int strncasecmp(const char *, const char *, int);
+extern int strncasecmp(const char *, const char *, __kernel_size_t);
 extern char * strcpy(char *,const char *);
 extern char * strncpy(char *,const char *, __kernel_size_t);
 extern __kernel_size_t strlen(const char *);
index 1b051e11c4928b84ef5ee57b7d65d9fe7244749b..6a7bf4b6c21588a02b3d3bb57ed751948e5ceb73 100644 (file)
@@ -739,16 +739,13 @@ void board_init_r(gd_t *id, ulong dest_addr)
                flash_size = 0;
        } else if ((flash_size = flash_init()) > 0) {
 #ifdef CONFIG_SYS_FLASH_CHECKSUM
-               char *s;
-
                print_size(flash_size, "");
                /*
                 * Compute and print flash CRC if flashchecksum is set to 'y'
                 *
                 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
                 */
-               s = getenv("flashchecksum");
-               if (s && (*s == 'y')) {
+               if (getenv_yesno("flashchecksum") == 1) {
                        printf("  CRC: %08X",
                               crc32(0,
                                     (const unsigned char *)
@@ -841,9 +838,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
         * "i2cfast" into account
         */
        {
-               char *s = getenv("i2cfast");
-
-               if (s && ((*s == 'y') || (*s == 'Y'))) {
+               if (getenv_yesno("i2cfast") == 1) {
                        bd->bi_iic_fast[0] = 1;
                        bd->bi_iic_fast[1] = 1;
                }
index c6bbc203d5dc78f9cae96af7f18f22f89e8acbb8..af6faea234c9229f6c274b057e8911c28fcfb24a 100644 (file)
@@ -40,7 +40,7 @@
 */
 
 extern int strcasecmp(const char *, const char *);
-extern int strncasecmp(const char *, const char *, int);
+extern int strncasecmp(const char *, const char *, __kernel_size_t);
 extern char *strcpy(char *, const char *);
 extern char *strncpy(char *, const char *, __kernel_size_t);
 extern __kernel_size_t strlen(const char *);
index 32d025a34237c89c443314035f58c3f6264105f3..1b5e995b15aaae971624fa0b584084c182f646f0 100644 (file)
@@ -284,8 +284,7 @@ void board_init_f(ulong bootflag)
                 *
                 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
                 */
-               s = getenv("flashchecksum");
-               if (s && (*s == 'y')) {
+               if (getenv_yesno("flashchecksum") == 1) {
                        printf("  CRC: %08lX",
                               crc32(0, (const unsigned char *)CONFIG_SYS_FLASH_BASE,
                                     flash_size)
index 6cae68601d34bffdad9760746b0c97600066fbfa..38769e03c536b27ff3b4d6b89a9b11e2bf909141 100644 (file)
@@ -834,15 +834,11 @@ int mem_test_walk (void)
 /*********************************************************************/
 int testdram (void)
 {
-       char *s;
        int rundata, runaddress, runwalk;
 
-       s = getenv ("testdramdata");
-       rundata = (s && (*s == 'y')) ? 1 : 0;
-       s = getenv ("testdramaddress");
-       runaddress = (s && (*s == 'y')) ? 1 : 0;
-       s = getenv ("testdramwalk");
-       runwalk = (s && (*s == 'y')) ? 1 : 0;
+       rundata = getenv_yesno("testdramdata") == 1;
+       runaddress = getenv_yesno("testdramaddress") == 1;
+       runwalk = getenv_yesno("testdramwalk") == 1;
 
 /*    rundata = 1; */
 /*    runaddress = 0; */
index d4f58b3216adf0bdc1e622a71a769c1b64d01ab8..ddb7ed5551d83ebd8ea39e0afcede78730efea3a 100644 (file)
@@ -834,15 +834,11 @@ int mem_test_walk (void)
 /*********************************************************************/
 int testdram (void)
 {
-       char *s;
        int rundata, runaddress, runwalk;
 
-       s = getenv ("testdramdata");
-       rundata = (s && (*s == 'y')) ? 1 : 0;
-       s = getenv ("testdramaddress");
-       runaddress = (s && (*s == 'y')) ? 1 : 0;
-       s = getenv ("testdramwalk");
-       runwalk = (s && (*s == 'y')) ? 1 : 0;
+       rundata = getenv_yesno("testdramdata") == 1;
+       runaddress = getenv_yesno("testdramaddress") == 1;
+       runwalk = getenv_yesno("testdramwalk") == 1;
 
 /*    rundata = 1; */
 /*    runaddress = 0; */
index 0725989de06938a4f259bb0630f450befd1dda25..6492d4168e1dacc08f13b4320b062c724d23906a 100644 (file)
@@ -61,9 +61,8 @@ int board_mmc_init(bd_t *bd)
        pin_mux_mmc();
 
        debug("board_mmc_init: init eMMC\n");
-       /* init dev 0, eMMC chip, with 4-bit bus */
-       /* The board has an 8-bit bus, but 8-bit doesn't work yet */
-       tegra_mmc_init(0, 4, -1, -1);
+       /* init dev 0, eMMC chip, with 8-bit bus */
+       tegra_mmc_init(0, 8, -1, -1);
 
        debug("board_mmc_init: init SD slot\n");
        /* init dev 3, SD slot, with 4-bit bus */
index db79e7796d09c0351d08207b6a38aef6641633fe..4450674a75989f8f87fe763acdf0535364b3492e 100644 (file)
@@ -8,6 +8,7 @@
 
        aliases {
                usb0 = "/usb@c5008000";
+               usb1 = "/usb@c5000000";
        };
 
        memory {
@@ -48,7 +49,7 @@
        };
 
        usb@c5000000 {
-               status = "disabled";
+               nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
        };
 
        usb@c5004000 {
index 9ef66fd86535d45b113aed417b6557c3bcc43626..8f4dd09faa345c08088cbdd79612037bbdb0db33 100644 (file)
 #include <mmc.h>
 #endif
 
+void pin_mux_usb(void)
+{
+       /*
+        * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
+        * in the current device tree.
+        */
+       pinmux_tristate_disable(PINGRP_UAC);
+}
 
 void pin_mux_spi(void)
 {
index aaff2e868ba2e99e90e55afad877a9111838b058..56fe495277ee7d6ad84df39ab4494de81f2f6784 100644 (file)
@@ -91,15 +91,14 @@ int board_mmc_init(bd_t *bis)
  * provides the timing values back to the function that configures
  * the memory.  We have either one or two banks of 128MB DDR.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-                               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
        /* General SDRC config */
-       *mcfg = MICRON_V_MCFG_165(128 << 20);
-       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+       timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
        /* AC timings */
-       *ctrla = MICRON_V_ACTIMA_165;
-       *ctrlb = MICRON_V_ACTIMB_165;
-       *mr = MICRON_V_MR_165;
+       timings->ctrla = MICRON_V_ACTIMA_165;
+       timings->ctrlb = MICRON_V_ACTIMB_165;
+       timings->mr = MICRON_V_MR_165;
 }
index 98051fb3fbe426985b2a0c2e8ab1a318135d84c5..d7deae4a541c81790a065c6174a9bd12998fea4b 100644 (file)
@@ -953,22 +953,18 @@ int mem_test_walk (void)
 /*********************************************************************/
 int testdram (void)
 {
-       char *s;
        int rundata    = 0;
        int runaddress = 0;
        int runwalk    = 0;
 
 #ifdef CONFIG_SYS_DRAM_TEST_DATA
-       s = getenv ("testdramdata");
-       rundata = (s && (*s == 'y')) ? 1 : 0;
+       rundata = getenv_yesno("testdramdata") == 1;
 #endif
 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
-       s = getenv ("testdramaddress");
-       runaddress = (s && (*s == 'y')) ? 1 : 0;
+       runaddress = getenv_yesno("testdramaddress") == 1;
 #endif
 #ifdef CONFIG_SYS_DRAM_TEST_WALK
-       s = getenv ("testdramwalk");
-       runwalk = (s && (*s == 'y')) ? 1 : 0;
+       runwalk = getenv_yesno("testdramwalk") == 1;
 #endif
 
        if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
index f1ffb7b540782d0578ca2cf0c4dd6bc5610c5352..e9a78a303ca9797624ea531db49261b759d5ce4c 100644 (file)
@@ -391,7 +391,7 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
        envp = (env_t *)nextbase;
        res = (char *)envp->data;
-       len = hexport_r(&env_htab, '\0', &res, ENV_SIZE, 0, NULL);
+       len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
        if (len < 0) {
                error("Cannot export environment: errno = %d\n", errno);
                return 1;
index 77a1e1d3ac1624779e169ce77984eed5f8d8f1a9..64c54d5e8453554729447567b177f5836d37a0b5 100644 (file)
@@ -544,15 +544,11 @@ int mem_test_walk (void)
 /*********************************************************************/
 int testdram (void)
 {
-       char *s;
        int rundata, runaddress, runwalk;
 
-       s = getenv ("testdramdata");
-       rundata = (s && (*s == 'y')) ? 1 : 0;
-       s = getenv ("testdramaddress");
-       runaddress = (s && (*s == 'y')) ? 1 : 0;
-       s = getenv ("testdramwalk");
-       runwalk = (s && (*s == 'y')) ? 1 : 0;
+       rundata = getenv_yesno("testdramdata") == 1;
+       runaddress = getenv_yesno("testdramaddress") == 1;
+       runwalk = getenv_yesno("testdramwalk") == 1;
 
        if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
                printf ("Testing RAM ... ");
index a8257a3005fab8d93d0b373afd15e64954d23ccb..a0f2aa3e4e2ad89e41de4cf52a0dca325662a708 100644 (file)
@@ -72,27 +72,26 @@ void omap_rev_string(void)
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
 #ifdef CONFIG_BOOT_NAND
-       *mcfg = MICRON_V_MCFG_200(256 << 20);
-       *ctrla = MICRON_V_ACTIMA_200;
-       *ctrlb = MICRON_V_ACTIMB_200;
-       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+       timings->ctrla = MICRON_V_ACTIMA_200;
+       timings->ctrlb = MICRON_V_ACTIMB_200;
+       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 #else
        if (get_cpu_family() == CPU_OMAP34XX) {
-               *mcfg = NUMONYX_V_MCFG_165(256 << 20);
-               *ctrla = NUMONYX_V_ACTIMA_165;
-               *ctrlb = NUMONYX_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+               timings->ctrla = NUMONYX_V_ACTIMA_165;
+               timings->ctrlb = NUMONYX_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
        } else {
-               *mcfg = NUMONYX_V_MCFG_200(256 << 20);
-               *ctrla = NUMONYX_V_ACTIMA_200;
-               *ctrlb = NUMONYX_V_ACTIMB_200;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+               timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+               timings->ctrla = NUMONYX_V_ACTIMA_200;
+               timings->ctrlb = NUMONYX_V_ACTIMB_200;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
        }
 #endif
 }
index 107cb7f8e0581d0f8c7c5487773e6873eec70cfe..a41e752b8206da9c38b1c3e879ca3d08d597bd3d 100644 (file)
@@ -59,27 +59,26 @@ void omap_rev_string(void)
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-                          u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
 #ifdef CONFIG_BOOT_NAND
-       *mcfg = MICRON_V_MCFG_200(256 << 20);
-       *ctrla = MICRON_V_ACTIMA_200;
-       *ctrlb = MICRON_V_ACTIMB_200;
-       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+       timings->ctrla = MICRON_V_ACTIMA_200;
+       timings->ctrlb = MICRON_V_ACTIMB_200;
+       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 #else
        if (get_cpu_family() == CPU_OMAP34XX) {
-               *mcfg = NUMONYX_V_MCFG_165(256 << 20);
-               *ctrla = NUMONYX_V_ACTIMA_165;
-               *ctrlb = NUMONYX_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+               timings->ctrla = NUMONYX_V_ACTIMA_165;
+               timings->ctrlb = NUMONYX_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
        } else {
-               *mcfg = NUMONYX_V_MCFG_200(256 << 20);
-               *ctrla = NUMONYX_V_ACTIMA_200;
-               *ctrlb = NUMONYX_V_ACTIMB_200;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+               timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+               timings->ctrla = NUMONYX_V_ACTIMA_200;
+               timings->ctrlb = NUMONYX_V_ACTIMB_200;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
        }
 #endif
 }
index 2c7cd0d401f790d0cba72ed32c89e37891e30ffd..76ec6876e21b51d4ea4da512109c2fc76215cfc1 100644 (file)
 #include <linux/compiler.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/display.h>
 #include <asm/arch/emc.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/pmu.h>
+#include <asm/arch/pwm.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch/usb.h>
 #include <asm/arch-tegra/board.h>
@@ -118,6 +120,13 @@ int board_init(void)
 #ifdef CONFIG_TEGRA_SPI
        pin_mux_spi();
        spi_init();
+#endif
+#ifdef CONFIG_PWM_TEGRA
+       if (pwm_init(gd->fdt_blob))
+               debug("%s: Failed to init pwm\n", __func__);
+#endif
+#ifdef CONFIG_LCD
+       tegra_lcd_check_next_stage(gd->fdt_blob, 0);
 #endif
        /* boot param addr */
        gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
@@ -144,6 +153,9 @@ int board_init(void)
        pin_mux_usb();
        board_usb_init(gd->fdt_blob);
 #endif
+#ifdef CONFIG_LCD
+       tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
 
 #ifdef CONFIG_TEGRA_NAND
        pin_mux_nand();
@@ -174,7 +186,19 @@ int board_early_init_f(void)
        /* Initialize periph GPIOs */
        gpio_early_init();
        gpio_early_init_uart();
+#ifdef CONFIG_LCD
+       tegra_lcd_early_init(gd->fdt_blob);
+#endif
 
        return 0;
 }
 #endif /* EARLY_INIT */
+
+int board_late_init(void)
+{
+#ifdef CONFIG_LCD
+       /* Make sure we finish initing the LCD */
+       tegra_lcd_check_next_stage(gd->fdt_blob, 1);
+#endif
+       return 0;
+}
index 25a63a05d0ca3439d505a616926da39973753942..dd98ca48e9f26bcb54e0ba49cf43f4544534745b 100644 (file)
                        compatible = "hynix,hy27uf4g2b", "nand-flash";
                };
        };
+
+       host1x {
+               status = "okay";
+               dc@54200000 {
+                       status = "okay";
+                       rgb {
+                               status = "okay";
+                               nvidia,panel = <&lcd_panel>;
+                       };
+               };
+       };
+
+       lcd_panel: panel {
+               /* Seaboard has 1366x768 */
+               clock = <70600000>;
+               xres = <1366>;
+               yres = <768>;
+               left-margin = <58>;
+               right-margin = <58>;
+               hsync-len = <58>;
+               lower-margin = <4>;
+               upper-margin = <4>;
+               vsync-len = <4>;
+               hsync-active-high;
+               nvidia,bits-per-pixel = <16>;
+               nvidia,pwm = <&pwm 2 0>;
+               nvidia,backlight-enable-gpios = <&gpio 28 0>;   /* PD4 */
+               nvidia,lvds-shutdown-gpios = <&gpio 10 0>;      /* PB2 */
+               nvidia,backlight-vdd-gpios = <&gpio 176 0>;     /* PW0 */
+               nvidia,panel-vdd-gpios = <&gpio 22 0>;          /* PC6 */
+               nvidia,panel-timings = <400 4 203 17 15>;
+       };
+
 };
index c7590ac6cff8292e814a412fe04a5a75dd8e91a9..93430edd3bdb489b75bc7f2ad4ba7ed0573655d8 100644 (file)
@@ -64,9 +64,8 @@ int board_mmc_init(bd_t *bd)
        pin_mux_mmc();
 
        debug("board_mmc_init: init SD slot J26\n");
-       /* init dev 0, SD slot J26, with 4-bit bus */
-       /* The board has an 8-bit bus, but 8-bit doesn't work yet */
-       tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+       /* init dev 0, SD slot J26, with 8-bit bus */
+       tegra_mmc_init(0, 8, GPIO_PI6, GPIO_PH2);
 
        debug("board_mmc_init: init SD slot J5\n");
        /* init dev 2, SD slot J5, with 4-bit bus */
index c412c077da02f26022d2b4381e3b306b3e5e1bfe..3e33da0afc37976fe8c04e170a78532c4b962e5a 100644 (file)
@@ -71,9 +71,8 @@ int board_mmc_init(bd_t *bd)
        pin_mux_mmc();
 
        debug("board_mmc_init: init eMMC\n");
-       /* init dev 0, eMMC chip, with 4-bit bus */
-       /* The board has an 8-bit bus, but 8-bit doesn't work yet */
-       tegra_mmc_init(0, 4, -1, -1);
+       /* init dev 0, eMMC chip, with 8-bit bus */
+       tegra_mmc_init(0, 8, -1, -1);
 
        debug("board_mmc_init: init SD slot\n");
        /* init dev 1, SD slot, with 4-bit bus */
index c6d50a07acabc18296474b5581c5c41026a86c99..fdf46a2aae92101bc2957eab45144f3a6c6571eb 100644 (file)
@@ -147,34 +147,33 @@ int get_board_revision(void)
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
        switch (get_board_revision()) {
        case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
-               *mcfg = MICRON_V_MCFG_165(128 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                break;
        case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
-               *mcfg = MICRON_V_MCFG_165(256 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_165(256 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                break;
        case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
-               *mcfg = HYNIX_V_MCFG_165(256 << 20);
-               *ctrla = HYNIX_V_ACTIMA_165;
-               *ctrlb = HYNIX_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = HYNIX_V_MCFG_165(256 << 20);
+               timings->ctrla = HYNIX_V_ACTIMA_165;
+               timings->ctrlb = HYNIX_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                break;
        default:
-               *mcfg = MICRON_V_MCFG_165(128 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
        }
 }
 #endif
index 389affcde0fda0718c954bb638a1eddad1d5f63d..c3fd19169c95beaa8d22a2ac148c4bcbdfa5b4a8 100644 (file)
@@ -768,22 +768,18 @@ int mem_test_walk (void)
 /*********************************************************************/
 int testdram (void)
 {
-       char *s;
        int rundata    = 0;
        int runaddress = 0;
        int runwalk    = 0;
 
 #ifdef CONFIG_SYS_DRAM_TEST_DATA
-       s = getenv ("testdramdata");
-       rundata = (s && (*s == 'y')) ? 1 : 0;
+       rundata = getenv_yesno("testdramdata") == 1;
 #endif
 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
-       s = getenv ("testdramaddress");
-       runaddress = (s && (*s == 'y')) ? 1 : 0;
+       runaddress = getenv_yesno("testdramaddress") == 1;
 #endif
 #ifdef CONFIG_SYS_DRAM_TEST_WALK
-       s = getenv ("testdramwalk");
-       runwalk = (s && (*s == 'y')) ? 1 : 0;
+       runwalk = getenv_yesno("testdramwalk") == 1;
 #endif
 
        if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
index 1474fa8a15a7b3825c356a843f5626a1851765e2..47c6a5a46b51b805bddedd5f06ff9de33bd61e47 100644 (file)
@@ -36,7 +36,7 @@ COBJS += smdk5250.o
 endif
 
 ifdef CONFIG_SPL_BUILD
-COBJS  += mmc_boot.o
+COBJS  += spl_boot.o
 endif
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
index a5816e445c80308f9843728c6ea64428088d03fb..9c926d6ecf2e9ae6f1db1bc390633b6cf3cb14d0 100644 (file)
 #include <asm/io.h>
 #include <i2c.h>
 #include <netdev.h>
+#include <spi.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/sromc.h>
+#include <power/pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -63,6 +65,9 @@ static int smc9115_pre_init(void)
 int board_init(void)
 {
        gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#ifdef CONFIG_EXYNOS_SPI
+       spi_init();
+#endif
        return 0;
 }
 
@@ -79,6 +84,16 @@ int dram_init(void)
        return 0;
 }
 
+#if defined(CONFIG_POWER)
+int power_init_board(void)
+{
+       if (pmic_init(I2C_PMIC))
+               return -1;
+       else
+               return 0;
+}
+#endif
+
 void dram_init_banksize(void)
 {
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
similarity index 66%
rename from board/samsung/smdk5250/mmc_boot.c
rename to board/samsung/smdk5250/spl_boot.c
index 449a919d5f223a632d3c1b00b78fe99bbdb421f9..d8f3c1e184881f8c1a2a32a509a3269ecc61b169 100644 (file)
 #include<common.h>
 #include<config.h>
 
+enum boot_mode {
+       BOOT_MODE_MMC = 4,
+       BOOT_MODE_SERIAL = 20,
+       /* Boot based on Operating Mode pin settings */
+       BOOT_MODE_OM = 32,
+       BOOT_MODE_USB,  /* Boot using USB download */
+};
+
+       typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst);
+
 /*
 * Copy U-boot from mmc to RAM:
 * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
 */
 void copy_uboot_to_ram(void)
 {
-       u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+       spi_copy_func_t spi_copy;
+       enum boot_mode bootmode;
+       u32 (*copy_bl2)(u32, u32, u32);
+
+       bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
 
-       copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
+       switch (bootmode) {
+       case BOOT_MODE_SERIAL:
+               spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR;
+               spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
+                                               CONFIG_SYS_TEXT_BASE);
+               break;
+       case BOOT_MODE_MMC:
+               copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+               copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
+                                               CONFIG_SYS_TEXT_BASE);
+               break;
+       default:
+               break;
+       }
 }
 
 void board_init_f(unsigned long bootflag)
index e540190984740da822678724a71ffed0764b1cb2..472402942442da0c16e2d530e33c89e36fed7927 100644 (file)
@@ -29,6 +29,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/mipi_dsim.h>
@@ -361,7 +362,9 @@ int power_init_board(void)
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
-               get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+               get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
+               get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
+               get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
 
        return 0;
 }
@@ -372,6 +375,10 @@ void dram_init_banksize(void)
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
        gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+       gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+       gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
 }
 
 static unsigned int get_hw_revision(void)
@@ -419,54 +426,22 @@ int board_mmc_init(bd_t *bis)
 {
        struct exynos4_gpio_part2 *gpio =
                (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
-       int i, err;
+       int err;
 
        /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
        s5p_gpio_direction_output(&gpio->k0, 2, 1);
        s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 
-       /*
-        * eMMC GPIO:
-        * SDR 8-bit@48MHz at MMC0
-        * GPK0[0]      SD_0_CLK(2)
-        * GPK0[1]      SD_0_CMD(2)
-        * GPK0[2]      SD_0_CDn        -> Not used
-        * GPK0[3:6]    SD_0_DATA[0:3](2)
-        * GPK1[3:6]    SD_0_DATA[0:3](3)
-        *
-        * DDR 4-bit@26MHz at MMC4
-        * GPK0[0]      SD_4_CLK(3)
-        * GPK0[1]      SD_4_CMD(3)
-        * GPK0[2]      SD_4_CDn        -> Not used
-        * GPK0[3:6]    SD_4_DATA[0:3](3)
-        * GPK1[3:6]    SD_4_DATA[4:7](4)
-        */
-       for (i = 0; i < 7; i++) {
-               if (i == 2)
-                       continue;
-               /* GPK0[0:6] special function 2 */
-               s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
-               /* GPK0[0:6] pull disable */
-               s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
-               /* GPK0[0:6] drv 4x */
-               s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
-       }
-
-       for (i = 3; i < 7; i++) {
-               /* GPK1[3:6] special function 3 */
-               s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
-               /* GPK1[3:6] pull disable */
-               s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
-               /* GPK1[3:6] drv 4x */
-               s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
-       }
-
        /*
         * MMC device init
         * mmc0  : eMMC (8-bit buswidth)
         * mmc2  : SD card (4-bit buswidth)
         */
-       err = s5p_mmc_init(0, 8);
+       err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+       if (err)
+               debug("SDMMC0 not configured\n");
+       else
+               err = s5p_mmc_init(0, 8);
 
        /* T-flash detect */
        s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
@@ -477,24 +452,11 @@ int board_mmc_init(bd_t *bis)
         * GPX3[4] T-flash detect pin
         */
        if (!s5p_gpio_get_value(&gpio->x3, 4)) {
-               /*
-                * SD card GPIO:
-                * GPK2[0]      SD_2_CLK(2)
-                * GPK2[1]      SD_2_CMD(2)
-                * GPK2[2]      SD_2_CDn        -> Not used
-                * GPK2[3:6]    SD_2_DATA[0:3](2)
-                */
-               for (i = 0; i < 7; i++) {
-                       if (i == 2)
-                               continue;
-                       /* GPK2[0:6] special function 2 */
-                       s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
-                       /* GPK2[0:6] pull disable */
-                       s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
-                       /* GPK2[0:6] drv 4x */
-                       s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
-               }
-               err = s5p_mmc_init(2, 4);
+               err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+               if (err)
+                       debug("SDMMC2 not configured\n");
+               else
+                       err = s5p_mmc_init(2, 4);
        }
 
        return err;
@@ -629,6 +591,10 @@ static void board_power_init(void)
        writel(0, (unsigned int)&pwr->lcd1_configuration);
        writel(0, (unsigned int)&pwr->gps_configuration);
        writel(0, (unsigned int)&pwr->gps_alive_configuration);
+
+       /* It is necessary to power down core 1 */
+       /* to successfully boot CPU1 in kernel */
+       writel(0, (unsigned int)&pwr->arm_core1_configuration);
 }
 
 static void board_uart_init(void)
index bfec08fa8ea6c2676a5e06e9c92c467ff4c540a2..587cc1b8c70dded76858e4151908e4f6e40c6627 100644 (file)
@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
 LIB    = $(obj)lib$(BOARD).o
 
 COBJS-y        := universal.o onenand.o
-SOBJS  := lowlevel_init.o
 
 SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S
deleted file mode 100644 (file)
index dc7f69e..0000000
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * Lowlevel setup for universal board based on EXYNOS4210
- *
- * Copyright (C) 2010 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has GPIO part1 base 0x11400000
- * r6 has GPIO part2 base 0x11000000
- */
-
-       .globl lowlevel_init
-lowlevel_init:
-       mov     r11, lr
-
-       /* r5 has always zero */
-       mov     r5, #0
-
-       ldr     r7, =EXYNOS4_GPIO_PART1_BASE
-       ldr     r6, =EXYNOS4_GPIO_PART2_BASE
-
-       /* System Timer */
-       ldr     r0, =EXYNOS4_SYSTIMER_BASE
-       ldr     r1, =0x5000
-       str     r1, [r0, #0x0]
-       ldr     r1, =0xffffffff
-       str     r1, [r0, #0x8]
-       ldr     r1, =0x49
-       str     r1, [r0, #0x4]
-
-       /* PMIC manual reset */
-       /* nPOWER: XEINT_23: GPX2[7] */
-       add     r0, r6, #0xC40                  @ EXYNOS4_GPIO_X2_OFFSET
-       ldr     r1, [r0, #0x0]
-       bic     r1, r1, #(0xf << 28)            @ 28 = 7 * 4-bit
-       orr     r1, r1, #(0x1 << 28)            @ Output
-       str     r1, [r0, #0x0]
-
-       ldr     r1, [r0, #0x4]
-       orr     r1, r1, #(1 << 7)               @ 7 = 7 * 1-bit
-       str     r1, [r0, #0x4]
-
-       /* init system clock */
-       bl      system_clock_init
-
-       /* Disable Watchdog */
-       ldr     r0, =EXYNOS4_WATCHDOG_BASE              @0x10060000
-       str     r5, [r0]
-
-       /* UART */
-       bl      uart_asm_init
-
-       /* PMU init */
-       bl      system_power_init
-
-       bl      tzpc_init
-
-       mov     lr, r11
-       mov     pc, lr
-       nop
-       nop
-       nop
-
-/*
- * uart_asm_init: Initialize UART's pins
- */
-uart_asm_init:
-       /*
-        * setup UART0-UART4 GPIOs (part1)
-        * GPA1CON[3] = I2C_3_SCL (3)
-        * GPA1CON[2] = I2C_3_SDA (3)
-        */
-       mov     r0, r7
-       ldr     r1, =0x22222222
-       str     r1, [r0, #0x00]                 @ EXYNOS4_GPIO_A0_OFFSET
-       ldr     r1, =0x00223322
-       str     r1, [r0, #0x20]                 @ EXYNOS4_GPIO_A1_OFFSET
-
-       /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
-       add     r0, r6, #0x1A0                  @ EXYNOS4_GPIO_Y4_OFFSET
-       ldr     r1, [r0, #0x0]
-       bic     r1, r1, #(0xf << 28)            @ 28 = 7 * 4-bit
-       orr     r1, r1, #(0x1 << 28)
-       str     r1, [r0, #0x0]
-
-       ldr     r1, [r0, #0x8]
-       bic     r1, r1, #(0x3 << 14)            @ 14 = 7 * 2-bit
-       orr     r1, r1, #(0x3 << 14)            @ Pull-up enabled
-       str     r1, [r0, #0x8]
-
-       ldr     r1, [r0, #0x4]
-       orr     r1, r1, #(1 << 7)               @ 7 = 7 * 1-bit
-       str     r1, [r0, #0x4]
-
-       mov     pc, lr
-       nop
-       nop
-       nop
-
-system_clock_init:
-       ldr     r0, =EXYNOS4_CLOCK_BASE
-
-       /* APLL(1), MPLL(1), CORE(0), HPM(0) */
-       ldr     r1, =0x0101
-       ldr     r2, =0x14200                    @ CLK_SRC_CPU
-       str     r1, [r0, r2]
-
-       /* wait ?us */
-       mov     r1, #0x10000
-1:     subs    r1, r1, #1
-       bne     1b
-
-       /*
-        * CLK_SRC_TOP0
-        * MUX_ONENAND_SEL[28]  0: DOUT133, 1: DOUT166
-        * MUX_VPLL_SEL[8]      0: FINPLL,  1: FOUTVPLL
-        * MUX_EPLL_SEL[4]      0: FINPLL,  1: FOUTEPLL
-        */
-       ldr     r1, =0x10000110
-       ldr     r2, =0x0C210                    @ CLK_SRC_TOP
-       str     r1, [r0, r2]
-
-       /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
-       ldr     r1, =0x0066666
-       ldr     r2, =0x0C240                    @ CLK_SRC_FSYS
-       str     r1, [r0, r2]
-       /* UART[0:5], PWM: SCLKMPLL(6) */
-       ldr     r1, =0x6666666
-       ldr     r2, =0x0C250                    @ CLK_SRC_PERIL0_OFFSET
-       str     r1, [r0, r2]
-
-       /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
-       ldr     r1, =0x0133730
-       ldr     r2, =0x14500                    @ CLK_DIV_CPU0
-       str     r1, [r0, r2]
-       /* CPU1: COPY, HPM */
-       ldr     r1, =0x03
-       ldr     r2, =0x14504                    @ CLK_DIV_CPU1
-       str     r1, [r0, r2]
-       /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
-       ldr     r1, =0x13111113
-       ldr     r2, =0x10500                    @ CLK_DIV_DMC0
-       str     r1, [r0, r2]
-       /* DMC1: PWI, DVSEM, DPM */
-       ldr     r1, =0x01010100
-       ldr     r2, =0x10504                    @ CLK_DIV_DMC1
-       str     r1, [r0, r2]
-       /* LEFTBUS: GDL, GPL */
-       ldr     r1, =0x13
-       ldr     r2, =0x04500                    @ CLK_DIV_LEFTBUS
-       str     r1, [r0, r2]
-       /* RIGHHTBUS: GDR, GPR */
-       ldr     r1, =0x13
-       ldr     r2, =0x08500                    @ CLK_DIV_RIGHTBUS
-       str     r1, [r0, r2]
-       /*
-        * CLK_DIV_TOP
-        * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
-        * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
-        */
-       ldr     r1, =0x00005473
-       ldr     r2, =0x0C510                    @ CLK_DIV_TOP
-       str     r1, [r0, r2]
-       /* MMC[0:1] */
-       ldr     r1, =0x000f000f                 /* 800(MPLL) / (15 + 1) */
-       ldr     r2, =0x0C544                    @ CLK_DIV_FSYS1
-       str     r1, [r0, r2]
-       /* MMC[2:3] */
-       ldr     r1, =0x000f000f                 /* 800(MPLL) / (15 + 1) */
-       ldr     r2, =0x0C548                    @ CLK_DIV_FSYS2
-       str     r1, [r0, r2]
-       /* MMC4 */
-       ldr     r1, =0x000f                     /* 800(MPLL) / (15 + 1) */
-       ldr     r2, =0x0C54C                    @ CLK_DIV_FSYS3
-       str     r1, [r0, r2]
-       /* UART[0:5] */
-       ldr     r1, =0x774777
-       ldr     r2, =0x0C550                    @ CLK_DIV_PERIL0
-       str     r1, [r0, r2]
-       /* SLIMBUS: ???, PWM */
-       ldr     r1, =0x8
-       ldr     r2, =0x0C55C                    @ CLK_DIV_PERIL3
-       str     r1, [r0, r2]
-
-       /* PLL Setting */
-       ldr     r1, =0x1C20
-       ldr     r2, =0x14000                    @ APLL_LOCK
-       str     r1, [r0, r2]
-       ldr     r2, =0x14008                    @ MPLL_LOCK
-       str     r1, [r0, r2]
-       ldr     r2, =0x0C010                    @ EPLL_LOCK
-       str     r1, [r0, r2]
-       ldr     r2, =0x0C020                    @ VPLL_LOCK
-       str     r1, [r0, r2]
-
-       /* APLL */
-       ldr     r1, =0x8000001c
-       ldr     r2, =0x14104                    @ APLL_CON1
-       str     r1, [r0, r2]
-       ldr     r1, =0x80c80601                 @ 800MHz
-       ldr     r2, =0x14100                    @ APLL_CON0
-       str     r1, [r0, r2]
-       /* MPLL */
-       ldr     r1, =0x8000001C
-       ldr     r2, =0x1410C                    @ MPLL_CON1
-       str     r1, [r0, r2]
-       ldr     r1, =0x80c80601                 @ 800MHz
-       ldr     r2, =0x14108                    @ MPLL_CON0
-       str     r1, [r0, r2]
-       /* EPLL */
-       ldr     r1, =0x0
-       ldr     r2, =0x0C114                    @ EPLL_CON1
-       str     r1, [r0, r2]
-       ldr     r1, =0x80300302                 @ 96MHz
-       ldr     r2, =0x0C110                    @ EPLL_CON0
-       str     r1, [r0, r2]
-       /* VPLL */
-       ldr     r1, =0x11000400
-       ldr     r2, =0x0C124                    @ VPLL_CON1
-       str     r1, [r0, r2]
-       ldr     r1, =0x80350302                 @ 108MHz
-       ldr     r2, =0x0C120                    @ VPLL_CON0
-       str     r1, [r0, r2]
-
-       /*
-        * SMMUJPEG[11], JPEG[6], CSIS1[5]              : 0111 1001
-        * Turn off all
-        */
-       ldr     r1, =0xFFF80000
-       ldr     r2, =0x0C920                    @ CLK_GATE_IP_CAM
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFFC0
-       ldr     r2, =0x0C924                    @ CLK_GATE_IP_VP
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFFE0
-       ldr     r2, =0x0C928                    @ CLK_GATE_IP_MFC
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFFFC
-       ldr     r2, =0x0C92C                    @ CLK_GATE_IP_G3D
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFC00
-       ldr     r2, =0x0C930                    @ CLK_GATE_IP_IMAGE
-       str     r1, [r0, r2]
-
-       /* DSIM0[3], MDNIE0[2], MIE0[1]                 : 0001 */
-       ldr     r1, =0xFFFFFFF1
-       ldr     r2, =0x0C934                    @ CLK_GATE_IP_LCD0
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFFC0
-       ldr     r2, =0x0C938                    @ CLK_GATE_IP_LCD1
-       str     r1, [r0, r2]
-
-       /*
-        * SMMUPCIE[18], NFCON[16]                      : 1111 1010
-        * PCIE[14],  SATA[10], SDMMC43[9:8]            : 1011 1000
-        * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2]    : 1010 0011
-        */
-       ldr     r1, =0xFFFAB8A3
-       ldr     r2, =0x0C940                    @ CLK_GATE_IP_FSYS
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFFFC
-       ldr     r2, =0x0C94C                    @ CLK_GATE_IP_GPS
-       str     r1, [r0, r2]
-
-       /*
-        * AC97[27], SPDIF[26], SLIMBUS[25]             : 1111 0001
-        * I2C2[8]                                      : 1111 1110
-        */
-       ldr     r1, =0xF1FFFEFF
-       ldr     r2, =0x0C950                    @ CLK_GATE_IP_PERIL
-       str     r1, [r0, r2]
-
-       /*
-        * KEYIF[16]                                    : 1111 1110
-        */
-       ldr     r1, =0xFFFEFFFF
-       ldr     r2, =0x0C960                    @ CLK_GATE_IP_PERIR
-       str     r1, [r0, r2]
-
-       /* LCD1[5], G3D[3], MFC[2], TV[1]               : 1101 0001 */
-       ldr     r1, =0xFFFFFFD1
-       ldr     r2, =0x0C970                    @ CLK_GATE_BLOCK
-       str     r1, [r0, r2]
-       mov     pc, lr
-       nop
-       nop
-       nop
-
-system_power_init:
-       ldr     r0, =EXYNOS4_POWER_BASE         @ 0x10020000
-
-       ldr     r2, =0x330C                     @ PS_HOLD_CONTROL
-       ldr     r1, [r0, r2]
-       orr     r1, r1, #(0x3 << 8)             @ Data High, Output En
-       str     r1, [r0, r2]
-
-       /* Power Down */
-       add     r2, r0, #0x3000
-       str     r5, [r2, #0xC20]                @ TV_CONFIGURATION
-       str     r5, [r2, #0xC40]                @ MFC_CONFIGURATION
-       str     r5, [r2, #0xC60]                @ G3D_CONFIGURATION
-       str     r5, [r2, #0xCA0]                @ LCD1_CONFIGURATION
-       str     r5, [r2, #0xCE0]                @ GPS_CONFIGURATION
-
-       mov     pc, lr
-       nop
-       nop
-       nop
-
-tzpc_init:
-       ldr     r0, =0x10110000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10120000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10130000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10140000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10150000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       mov     pc, lr
index 36a047217c57cbdac1b07196fbb137bf0eb7f2d1..e742707f79659dca95b19fb4b6b91f27f093e0e8 100644 (file)
  */
 
 #include <common.h>
+#include <spi.h>
+#include <lcd.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/adc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/watchdog.h>
+#include <libtizen.h>
+#include <ld9040.h>
 #include <power/pmic.h>
 #include <usb/s3c_udc.h>
 #include <asm/arch/cpu.h>
@@ -48,21 +55,7 @@ static int get_hwrev(void)
        return board_rev & 0xFF;
 }
 
-static void check_hw_revision(void);
-
-int board_init(void)
-{
-       gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
-       gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
-       gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
-       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-       check_hw_revision();
-       printf("HW Revision:\t0x%x\n", board_rev);
-
-       return 0;
-}
+static void init_pmic_lcd(void);
 
 int power_init_board(void)
 {
@@ -72,6 +65,8 @@ int power_init_board(void)
        if (ret)
                return ret;
 
+       init_pmic_lcd();
+
        return 0;
 }
 
@@ -186,7 +181,7 @@ int checkboard(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-       int i, err;
+       int err;
 
        switch (get_hwrev()) {
        case 0:
@@ -209,75 +204,30 @@ int board_mmc_init(bd_t *bis)
        }
 
        /*
-        * eMMC GPIO:
-        * SDR 8-bit@48MHz at MMC0
-        * GPK0[0]      SD_0_CLK(2)
-        * GPK0[1]      SD_0_CMD(2)
-        * GPK0[2]      SD_0_CDn        -> Not used
-        * GPK0[3:6]    SD_0_DATA[0:3](2)
-        * GPK1[3:6]    SD_0_DATA[0:3](3)
-        *
-        * DDR 4-bit@26MHz at MMC4
-        * GPK0[0]      SD_4_CLK(3)
-        * GPK0[1]      SD_4_CMD(3)
-        * GPK0[2]      SD_4_CDn        -> Not used
-        * GPK0[3:6]    SD_4_DATA[0:3](3)
-        * GPK1[3:6]    SD_4_DATA[4:7](4)
+        * MMC device init
+        * mmc0  : eMMC (8-bit buswidth)
+        * mmc2  : SD card (4-bit buswidth)
         */
-       for (i = 0; i < 7; i++) {
-               if (i == 2)
-                       continue;
-               /* GPK0[0:6] special function 2 */
-               s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2);
-               /* GPK0[0:6] pull disable */
-               s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
-               /* GPK0[0:6] drv 4x */
-               s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
-       }
-
-       for (i = 3; i < 7; i++) {
-               /* GPK1[3:6] special function 3 */
-               s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3);
-               /* GPK1[3:6] pull disable */
-               s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
-               /* GPK1[3:6] drv 4x */
-               s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
-       }
+       err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+       if (err)
+               debug("SDMMC0 not configured\n");
+       else
+               err = s5p_mmc_init(0, 8);
 
        /* T-flash detect */
        s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
        s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
 
-       /*
-        * MMC device init
-        * mmc0  : eMMC (8-bit buswidth)
-        * mmc2  : SD card (4-bit buswidth)
-        */
-       err = s5p_mmc_init(0, 8);
-
        /*
         * Check the T-flash  detect pin
         * GPX3[4] T-flash detect pin
         */
        if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
-               /*
-                * SD card GPIO:
-                * GPK2[0]      SD_2_CLK(2)
-                * GPK2[1]      SD_2_CMD(2)
-                * GPK2[2]      SD_2_CDn        -> Not used
-                * GPK2[3:6]    SD_2_DATA[0:3](2)
-                */
-               for (i = 0; i < 7; i++) {
-                       if (i == 2)
-                               continue;
-                       /* GPK2[0:6] special function 2 */
-                       s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2);
-                       /* GPK2[0:6] pull disable */
-                       s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
-                       /* GPK2[0:6] drv 4x */
-                       s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
-               }
-               err = s5p_mmc_init(2, 4);
+               err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+               if (err)
+                       debug("SDMMC2 not configured\n");
+               else
+                       err = s5p_mmc_init(2, 4);
        }
 
        return err;
@@ -331,3 +281,242 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
        .usb_flags = PHY0_SLEEP,
 };
 #endif
+
+int board_early_init_f(void)
+{
+       wdt_stop();
+
+       return 0;
+}
+
+#ifdef CONFIG_SOFT_SPI
+static void soft_spi_init(void)
+{
+       gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
+               CONFIG_SOFT_SPI_MODE & SPI_CPOL);
+       gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
+       gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO);
+       gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS,
+               !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+               !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+       SPI_SCL(1);
+       gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+               CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+               !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+int  spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       return bus == 0 && cs == 0;
+}
+
+void universal_spi_scl(int bit)
+{
+       gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit);
+}
+
+void universal_spi_sda(int bit)
+{
+       gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit);
+}
+
+int universal_spi_read(void)
+{
+       return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO);
+}
+#endif
+
+static void init_pmic_lcd(void)
+{
+       unsigned char val;
+       int ret = 0;
+
+       struct pmic *p = pmic_get("MAX8998_PMIC");
+
+       if (!p)
+               return;
+
+       if (pmic_probe(p))
+               return;
+
+       /* LDO7 1.8V */
+       val = 0x02; /* (1800 - 1600) / 100; */
+       ret |= pmic_reg_write(p,  MAX8998_REG_LDO7, val);
+
+       /* LDO17 3.0V */
+       val = 0xe; /* (3000 - 1600) / 100; */
+       ret |= pmic_reg_write(p,  MAX8998_REG_LDO17, val);
+
+       /* Disable unneeded regulators */
+       /*
+        * ONOFF1
+        * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
+        * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
+        */
+       val = 0xB9;
+       ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF1, val);
+
+       /* ONOFF2
+        * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
+        * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
+        */
+       val = 0x50;
+       ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF2, val);
+
+       /* ONOFF3
+        * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
+        * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
+        */
+       val = 0x00;
+       ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF3, val);
+
+       if (ret)
+               puts("LCD pmic initialisation error!\n");
+}
+
+static void lcd_cfg_gpio(void)
+{
+       unsigned int i, f3_end = 4;
+
+       for (i = 0; i < 8; i++) {
+               /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
+               s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
+               s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
+               s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+               /* pull-up/down disable */
+               s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
+               s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
+               s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+
+               /* drive strength to max (24bit) */
+               s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
+               s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+               s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
+               s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
+               s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
+               s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+       }
+
+       for (i = 0; i < f3_end; i++) {
+               /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
+               s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+               /* pull-up/down disable */
+               s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+               /* drive strength to max (24bit) */
+               s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
+               s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+       }
+
+       /* gpio pad configuration for LCD reset. */
+       s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+
+       spi_init();
+}
+
+static void reset_lcd(void)
+{
+       s5p_gpio_set_value(&gpio2->y4, 5, 1);
+       udelay(10000);
+       s5p_gpio_set_value(&gpio2->y4, 5, 0);
+       udelay(10000);
+       s5p_gpio_set_value(&gpio2->y4, 5, 1);
+       udelay(100);
+}
+
+static void lcd_power_on(void)
+{
+       struct pmic *p = pmic_get("MAX8998_PMIC");
+
+       if (!p)
+               return;
+
+       if (pmic_probe(p))
+               return;
+
+       pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
+       pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
+}
+
+vidinfo_t panel_info = {
+       .vl_freq        = 60,
+       .vl_col         = 480,
+       .vl_row         = 800,
+       .vl_width       = 480,
+       .vl_height      = 800,
+       .vl_clkp        = CONFIG_SYS_HIGH,
+       .vl_hsp         = CONFIG_SYS_HIGH,
+       .vl_vsp         = CONFIG_SYS_HIGH,
+       .vl_dp          = CONFIG_SYS_HIGH,
+
+       .vl_bpix        = 5,    /* Bits per pixel */
+
+       /* LD9040 LCD Panel */
+       .vl_hspw        = 2,
+       .vl_hbpd        = 16,
+       .vl_hfpd        = 16,
+
+       .vl_vspw        = 2,
+       .vl_vbpd        = 8,
+       .vl_vfpd        = 8,
+       .vl_cmd_allow_len = 0xf,
+
+       .win_id         = 0,
+       .cfg_gpio       = lcd_cfg_gpio,
+       .backlight_on   = NULL,
+       .lcd_power_on   = lcd_power_on,
+       .reset_lcd      = reset_lcd,
+       .dual_lcd_enabled = 0,
+
+       .init_delay     = 0,
+       .power_on_delay = 10000,
+       .reset_delay    = 10000,
+       .interface_mode = FIMD_RGB_INTERFACE,
+       .mipi_enabled   = 0,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+       vid->logo_on    = 1;
+       vid->resolution = HD_RESOLUTION;
+       vid->rgb_mode   = MODE_RGB_P;
+
+#ifdef CONFIG_TIZEN
+       get_tizen_logo_info(vid);
+#endif
+
+       /* for LD9040. */
+       vid->pclk_name = 1;     /* MPLL */
+       vid->sclk_div = 1;
+
+       vid->cfg_ldo = ld9040_cfg_ldo;
+       vid->enable_ldo = ld9040_enable_ldo;
+
+       setenv("lcdinfo", "lcd=ld9040");
+}
+
+int board_init(void)
+{
+       gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+       gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
+
+       gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#ifdef CONFIG_SOFT_SPI
+       soft_spi_init();
+#endif
+       check_hw_revision();
+       printf("HW Revision:\t0x%x\n", board_rev);
+
+       return 0;
+}
index 1471559909d3ad378e97e3ca08235fba0f4f167b..c9eea9b3045d92ed18845184f839a6154f83a09a 100644 (file)
@@ -98,9 +98,12 @@ int board_init(void)
        return 0;
 }
 
+#ifndef CONFIG_SPL_BUILD
 int misc_init_r(void)
 {
        char *eth_addr;
+       struct tam3517_module_info info;
+       int ret;
 
        dieid_num_r();
 
@@ -108,12 +111,13 @@ int misc_init_r(void)
        if (eth_addr)
                return 0;
 
-#ifndef CONFIG_SPL_BUILD
-       TAM3517_READ_MAC_FROM_EEPROM;
-#endif
+       TAM3517_READ_EEPROM(&info, ret);
+       if (!ret)
+               TAM3517_READ_MAC_FROM_EEPROM(&info);
 
        return 0;
 }
+#endif
 
 /*
  * Routine: set_muxconf_regs
index 9622a81280c8f87218e62be4b3d71454a0cc7649..c516c75a0066d2341365057fdb7d27e61734253f 100644 (file)
@@ -73,10 +73,10 @@ static struct {
 
 static struct panel_config lcd_cfg[] = {
        {
-       .timing_h       = PANEL_TIMING_H(4, 8, 41),
-       .timing_v       = PANEL_TIMING_V(2, 4, 10),
-       .pol_freq       = 0x00000000, /* Pol Freq */
-       .divisor        = 0x0001000d, /* 33Mhz Pixel Clock */
+       .timing_h       = PANEL_TIMING_H(40, 5, 2),
+       .timing_v       = PANEL_TIMING_V(8, 8, 2),
+       .pol_freq       = 0x00003000, /* Pol Freq */
+       .divisor        = 0x00010033, /* 9 Mhz Pixel Clock */
        .panel_type     = 0x01, /* TFT */
        .data_lines     = 0x03, /* 24 Bit RGB */
        .load_mode      = 0x02, /* Frame Mode */
@@ -258,21 +258,26 @@ int board_init(void)
        return 0;
 }
 
+#ifndef CONFIG_SPL_BUILD
 int misc_init_r(void)
 {
        char *eth_addr;
+       struct tam3517_module_info info;
+       int ret;
 
+       TAM3517_READ_EEPROM(&info, ret);
        dieid_num_r();
 
-       eth_addr = getenv("ethaddr");
-       if (eth_addr)
+       if (ret)
                return 0;
+       eth_addr = getenv("ethaddr");
+       if (!eth_addr)
+               TAM3517_READ_MAC_FROM_EEPROM(&info);
 
-#ifndef CONFIG_SPL_BUILD
-       TAM3517_READ_MAC_FROM_EEPROM;
-#endif
+       TAM3517_PRINT_SOM_INFO(&info);
        return 0;
 }
+#endif
 
 /*
  * Routine: set_muxconf_regs
index f0eca54c9e9626bcdd187e60d6b8b03501831f34..ed4229e258d24e58584b059abbf720625ebffbc8 100644 (file)
@@ -44,7 +44,7 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 
 /* MII mode defines */
 #define MII_MODE_ENABLE                0x0
-#define RGMII_MODE_ENABLE      0xA
+#define RGMII_MODE_ENABLE      0x3A
 
 /* GPIO that controls power to DDR on EVM-SK */
 #define GPIO_DDR_VTT_EN                7
@@ -318,6 +318,8 @@ int board_init(void)
 
        gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 
+       gpmc_init();
+
        return 0;
 }
 
index 8437ef515afed9dc4fa27162f2a1407400ed0fd2..02837082cb807fad040f8c4007c7bb7d218cdbfc 100644 (file)
@@ -171,6 +171,25 @@ static struct module_pin_mux mii1_pin_mux[] = {
        {-1},
 };
 
+static struct module_pin_mux nand_pin_mux[] = {
+       {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD0 */
+       {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD1 */
+       {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD2 */
+       {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD3 */
+       {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD4 */
+       {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD5 */
+       {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD6 */
+       {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},   /* NAND AD7 */
+       {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+       {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},   /* NAND_WPN */
+       {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},      /* NAND_CS0 */
+       {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+       {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},   /* NAND_OE */
+       {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},       /* NAND_WEN */
+       {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},  /* NAND_BE_CLE */
+       {-1},
+};
+
 void enable_uart0_pin_mux(void)
 {
        configure_module_pin_mux(uart0_pin_mux);
@@ -257,6 +276,9 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
                /* In profile #2 i2c1 and spi0 conflict. */
                if (profile & ~PROFILE_2)
                        configure_module_pin_mux(i2c1_pin_mux);
+               /* Profiles 2 & 3 don't have NAND */
+               if (profile & ~(PROFILE_2 | PROFILE_3))
+                       configure_module_pin_mux(nand_pin_mux);
                else if (profile == PROFILE_2) {
                        configure_module_pin_mux(mmc1_pin_mux);
                        configure_module_pin_mux(spi0_pin_mux);
index f20ebed4524298c4d5bb777dd732f7ae509d1b1c..b829a792b2c49b06e04508ce3b2bf9b4f3eb225a 100644 (file)
@@ -144,8 +144,7 @@ static int get_board_revision(void)
  * Description: If we use SPL then there is no x-loader nor config header
  * so we have to setup the DDR timings ourself on both banks.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(struct board_sdrc_timings *timings)
 {
        int pop_mfr, pop_id;
 
@@ -156,29 +155,29 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
         */
        identify_nand_chip(&pop_mfr, &pop_id);
 
-       *mr = MICRON_V_MR_165;
+       timings->mr = MICRON_V_MR_165;
        switch (get_board_revision()) {
        case REVISION_C4:
                if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
                        /* 512MB DDR */
-                       *mcfg = NUMONYX_V_MCFG_165(512 << 20);
-                       *ctrla = NUMONYX_V_ACTIMA_165;
-                       *ctrlb = NUMONYX_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+                       timings->ctrla = NUMONYX_V_ACTIMA_165;
+                       timings->ctrlb = NUMONYX_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                        break;
                } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
                        /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
-                       *mcfg = MICRON_V_MCFG_165(128 << 20);
-                       *ctrla = MICRON_V_ACTIMA_165;
-                       *ctrlb = MICRON_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_165;
+                       timings->ctrlb = MICRON_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                        break;
                } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
                        /* Beagleboard Rev C5, 256MB DDR */
-                       *mcfg = MICRON_V_MCFG_200(256 << 20);
-                       *ctrla = MICRON_V_ACTIMA_200;
-                       *ctrlb = MICRON_V_ACTIMB_200;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+                       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_200;
+                       timings->ctrlb = MICRON_V_ACTIMB_200;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                        break;
                }
        case REVISION_XM_A:
@@ -186,24 +185,24 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
        case REVISION_XM_C:
                if (pop_mfr == 0) {
                        /* 256MB DDR */
-                       *mcfg = MICRON_V_MCFG_200(256 << 20);
-                       *ctrla = MICRON_V_ACTIMA_200;
-                       *ctrlb = MICRON_V_ACTIMB_200;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+                       timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+                       timings->ctrla = MICRON_V_ACTIMA_200;
+                       timings->ctrlb = MICRON_V_ACTIMB_200;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                } else {
                        /* 512MB DDR */
-                       *mcfg = NUMONYX_V_MCFG_165(512 << 20);
-                       *ctrla = NUMONYX_V_ACTIMA_165;
-                       *ctrlb = NUMONYX_V_ACTIMB_165;
-                       *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+                       timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
+                       timings->ctrla = NUMONYX_V_ACTIMA_165;
+                       timings->ctrlb = NUMONYX_V_ACTIMB_165;
+                       timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                }
                break;
        default:
                /* Assume 128MB and Micron/165MHz timings to be safe */
-               *mcfg = MICRON_V_MCFG_165(128 << 20);
-               *ctrla = MICRON_V_ACTIMA_165;
-               *ctrlb = MICRON_V_ACTIMB_165;
-               *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_165;
+               timings->ctrlb = MICRON_V_ACTIMB_165;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
        }
 }
 #endif
index 61fc7b55310f7748770c06ce457e623f6816988e..8a3aa0c5bfdad3234d424f0b98e34e58ab3b3791 100644 (file)
@@ -128,8 +128,7 @@ int board_init(void)
  * provides the timing values back to the function that configures
  * the memory.
  */
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
-               u32 *mr)
+void get_board_mem_timings(s