Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 8 Jan 2013 13:59:37 +0000 (14:59 +0100)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Tue, 8 Jan 2013 13:59:37 +0000 (14:59 +0100)
14 files changed:
board/freescale/mx35pdk/mx35pdk.c
board/freescale/mx53loco/mx53loco.c
board/freescale/mx6qsabresd/mx6qsabresd.c
drivers/mmc/fsl_esdhc.c
include/configs/m28evk.h
include/configs/mx35pdk.h
include/configs/mx51evk.h
include/configs/mx53loco.h
include/configs/mx6qsabre_common.h
include/configs/mx6qsabreauto.h
include/configs/mx6qsabrelite.h
include/configs/mx6qsabresd.h
include/image.h
tools/imximage.c

index 2aa000f238e43313bf4c2cd30ff0eb9fe0cbd2b7..b7f474e5ef49a8c6a27e37e7323df0c2a8691b96 100644 (file)
@@ -274,7 +274,7 @@ int board_late_init(void)
                mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO);
                mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0);
 
-               gpio_direction_output(37, 1);
+               gpio_direction_output(IMX_GPIO_NR(2, 5), 1);
        }
 
        val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
index 2c8cb7a1cc58d16bbacc7dd8376b59c76eba43be..60cd4f0cfbae4388461a938b97e559dbef0f4d42 100644 (file)
@@ -343,14 +343,13 @@ static void setup_iomux_i2c(void)
 static int power_init(void)
 {
        unsigned int val;
-       int ret = -1;
+       int ret;
        struct pmic *p;
-       int retval;
 
        if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
-               retval = pmic_dialog_init(I2C_PMIC);
-               if (retval)
-                       return retval;
+               ret = pmic_dialog_init(I2C_PMIC);
+               if (ret)
+                       return ret;
 
                p = pmic_get("DIALOG_PMIC");
                if (!p)
@@ -359,20 +358,39 @@ static int power_init(void)
                /* Set VDDA to 1.25V */
                val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
                ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
+               if (ret) {
+                       printf("Writing to BUCKCORE_REG failed: %d\n", ret);
+                       return ret;
+               }
 
-               ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
+               pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
                val |= DA9052_SUPPLY_VBCOREGO;
-               ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+               ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
+               if (ret) {
+                       printf("Writing to SUPPLY_REG failed: %d\n", ret);
+                       return ret;
+               }
 
                /* Set Vcc peripheral to 1.30V */
-               ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
-               ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+               ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
+               if (ret) {
+                       printf("Writing to BUCKPRO_REG failed: %d\n", ret);
+                       return ret;
+               }
+
+               ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
+               if (ret) {
+                       printf("Writing to SUPPLY_REG failed: %d\n", ret);
+                       return ret;
+               }
+
+               return ret;
        }
 
        if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
-               retval = pmic_init(I2C_PMIC);
-               if (retval)
-                       return retval;
+               ret = pmic_init(I2C_PMIC);
+               if (ret)
+                       return ret;
 
                p = pmic_get("FSL_PMIC");
                if (!p)
@@ -382,28 +400,50 @@ static int power_init(void)
                pmic_reg_read(p, REG_SW_0, &val);
                val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
                ret = pmic_reg_write(p, REG_SW_0, val);
+               if (ret) {
+                       printf("Writing to REG_SW_0 failed: %d\n", ret);
+                       return ret;
+               }
 
                /* Set VCC as 1.30V on SW2 */
                pmic_reg_read(p, REG_SW_1, &val);
                val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
-               ret |= pmic_reg_write(p, REG_SW_1, val);
+               ret = pmic_reg_write(p, REG_SW_1, val);
+               if (ret) {
+                       printf("Writing to REG_SW_1 failed: %d\n", ret);
+                       return ret;
+               }
 
                /* Set global reset timer to 4s */
                pmic_reg_read(p, REG_POWER_CTL2, &val);
                val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
-               ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
+               ret = pmic_reg_write(p, REG_POWER_CTL2, val);
+               if (ret) {
+                       printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
+                       return ret;
+               }
 
                /* Set VUSBSEL and VUSBEN for USB PHY supply*/
                pmic_reg_read(p, REG_MODE_0, &val);
                val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
-               ret |= pmic_reg_write(p, REG_MODE_0, val);
+               ret = pmic_reg_write(p, REG_MODE_0, val);
+               if (ret) {
+                       printf("Writing to REG_MODE_0 failed: %d\n", ret);
+                       return ret;
+               }
 
                /* Set SWBST to 5V in auto mode */
                val = SWBST_AUTO;
-               ret |= pmic_reg_write(p, SWBST_CTRL, val);
+               ret = pmic_reg_write(p, SWBST_CTRL, val);
+               if (ret) {
+                       printf("Writing to SWBST_CTRL failed: %d\n", ret);
+                       return ret;
+               }
+
+               return ret;
        }
 
-       return ret;
+       return -1;
 }
 
 static void clock_1GHz(void)
@@ -462,12 +502,18 @@ int board_init(void)
 
        mxc_set_sata_internal_clock();
        setup_iomux_i2c();
+
+       lcd_enable();
+
+       return 0;
+}
+
+int board_late_init(void)
+{
        if (!power_init())
                clock_1GHz();
        print_cpuinfo();
 
-       lcd_enable();
-
        return 0;
 }
 
index 0240fb54792bb259ad3bbc95aac6574f8dcd9e27..65c4a1a4f3cd4b67579a6cc2348a796a96bb0d51 100644 (file)
@@ -86,6 +86,20 @@ static void setup_iomux_enet(void)
        gpio_set_value(IMX_GPIO_NR(1, 25), 1);
 }
 
+iomux_v3_cfg_t const usdhc2_pads[] = {
+       MX6Q_PAD_SD2_CLK__USDHC2_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD2_CMD__USDHC2_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD2_DAT0__USDHC2_DAT0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD2_DAT1__USDHC2_DAT1  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD2_DAT2__USDHC2_DAT2  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD2_DAT3__USDHC2_DAT3  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_NANDF_D4__USDHC2_DAT4  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_NANDF_D5__USDHC2_DAT5  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_NANDF_D6__USDHC2_DAT6  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_NANDF_D7__USDHC2_DAT7  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_NANDF_D2__GPIO_2_2     | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
 iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -100,28 +114,82 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6Q_PAD_NANDF_D0__GPIO_2_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
+iomux_v3_cfg_t const usdhc4_pads[] = {
+       MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
 static void setup_iomux_uart(void)
 {
        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
 #ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+       {USDHC2_BASE_ADDR},
        {USDHC3_BASE_ADDR},
+       {USDHC4_BASE_ADDR},
 };
 
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+
 int board_mmc_getcd(struct mmc *mmc)
 {
-       gpio_direction_input(IMX_GPIO_NR(2, 0));
-       return !gpio_get_value(IMX_GPIO_NR(2, 0));
+       struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+       switch (cfg->esdhc_base) {
+       case USDHC2_BASE_ADDR:
+               return !gpio_get_value(USDHC2_CD_GPIO);
+       case USDHC3_BASE_ADDR:
+               return !gpio_get_value(USDHC3_CD_GPIO);
+       default:
+               return 1; /* eMMC/uSDHC4 is always present */
+       }
 }
 
 int board_mmc_init(bd_t *bis)
 {
-       imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+       int i;
+
+       for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+               switch (i) {
+               case 0:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+                       gpio_direction_input(USDHC2_CD_GPIO);
+                       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+                       break;
+               case 1:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+                       gpio_direction_input(USDHC3_CD_GPIO);
+                       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+                       break;
+               case 2:
+                       imx_iomux_v3_setup_multiple_pads(
+                               usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+                       usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+                       break;
+               default:
+                       printf("Warning: you configured more USDHC controllers"
+                               "(%d) than supported by the board\n", i + 1);
+                       return 0;
+              }
+
+              if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+                       printf("Warning: failed to initialize mmc dev %d\n", i);
+       }
 
-       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-       return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+       return 0;
 }
 #endif
 
index e93e38ac4346fdebe203621aa5eac95e9355e660..3d5c9c0f77ef9f3910590c7a36212675d2b17b56 100644 (file)
@@ -577,7 +577,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
                return -1;
        }
 
-       mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+       mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
 
        if (caps & ESDHC_HOSTCAPBLT_HSS)
                mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
index 3f37e8430c516b3367904ab62c14c9daa12143b4..688717158b53cc0d209a994dfb80c2875a14973a 100644 (file)
                "512k(environment),"            \
                "512k(redundant-environment),"  \
                "4m(kernel),"                   \
+               "128k(fdt),"                    \
+               "8m(ramdisk),"                  \
                "-(filesystem)"
 #else
 #define        CONFIG_ENV_IS_NOWHERE
index 88b2bd6ed4407a76c720c8eb03af539e41460388..0db92a7803ee7458b46b8a4f20fac676b79e875f 100644 (file)
@@ -95,6 +95,7 @@
 
 #include <config_cmd_default.h>
 
+#define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
index fa0db3824b53449f3e1b9c3b89193b7bb2b955b4..cb3d93890c2e4a7535c4be7ce86eb33c30a50b97 100644 (file)
 #define CONFIG_SYS_TEXT_BASE   0x97800000
 
 #include <asm/arch/imx-regs.h>
-/*
- * Disabled for now due to build problems under Debian and a significant
- * increase in the final file size: 144260 vs. 109536 Bytes.
- */
 
 #define CONFIG_CMDLINE_TAG                     /* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
index e30502b4e216a176f1d1f085e92ebae196151a68..996396b99b65760bfc055d3d8c30aefe956a19e4 100644 (file)
@@ -39,6 +39,7 @@
 #define CONFIG_SYS_MALLOC_LEN          (10 * 1024 * 1024)
 
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MXC_GPIO
 #define CONFIG_REVISION_TAG
 
 
 #define CONFIG_ETHPRIME                "FEC0"
 
-#define CONFIG_LOADADDR                0x70800000      /* loadaddr env var */
+#define CONFIG_LOADADDR                0x72000000      /* loadaddr env var */
 #define CONFIG_SYS_TEXT_BASE    0x77800000
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "uimage=uImage\0" \
        "mmcdev=0\0" \
        "mmcpart=2\0" \
-       "mmcroot=/dev/mmcblk0p3 rw\0" \
-       "mmcrootfstype=ext3 rootwait\0" \
-       "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
-               "root=${mmcroot} " \
-               "rootfstype=${mmcrootfstype}\0" \
+       "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
+       "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot} " \
        "loadbootscript=" \
                "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
        "bootscript=echo Running bootscript from mmc ...; " \
index 0f226f790ec0ba32e7553bd7d92090c08aa6bf70..bd2fb108f4e4f0fe005e2fce7caae14559cdf711 100644 (file)
@@ -41,7 +41,6 @@
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
-#define CONFIG_SYS_FSL_USDHC_NUM       2
 
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
@@ -78,7 +77,7 @@
 
 #define CONFIG_BOOTDELAY               1
 
-#define CONFIG_LOADADDR                        0x10800000
+#define CONFIG_LOADADDR                        0x12000000
 #define CONFIG_SYS_TEXT_BASE           0x17800000
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 
 #if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_ENV_OFFSET              (6 * 64 * 1024)
-#define CONFIG_SYS_MMC_ENV_DEV         0
 #endif
 
 #define CONFIG_OF_LIBFDT
index 760f3ce0c9a3810d790c541a4f647e5a7fb2d0cf..f1ff20169b9906aed22cd9e026f97b036961b30c 100644 (file)
@@ -20,4 +20,9 @@
 
 #include "mx6qsabre_common.h"
 
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#endif
+
 #endif                         /* __MX6QSABREAUTO_CONFIG_H */
index 4ce4d4c086580a683e53195df7b7155b8c4225d9..0f6bbb4be24f671af84f565621583fea44039990 100644 (file)
 
 #define CONFIG_PREBOOT                 ""
 
-#define CONFIG_LOADADDR                               0x10800000
+#define CONFIG_LOADADDR                               0x12000000
 #define CONFIG_SYS_TEXT_BASE          0x17800000
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
index 771d1297f7a33863a57129861372d15ce000b49b..a1d92850c82338949195c918b63b8d0a5394519b 100644 (file)
 
 #include "mx6qsabre_common.h"
 
+#define CONFIG_SYS_FSL_USDHC_NUM       3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV         2       /* eMMC/uSDHC4 */
+#define CONFIG_SYS_MMC_ENV_PART                1       /* Boot partition 1 */
+#endif
+
 #endif                         /* __MX6QSABRESD_CONFIG_H */
index b958b18a4de2fd8fc6e8638c90149f74ced088ad..f5adc5035360633024de1b67cfee73f8811f17c8 100644 (file)
 #define IH_MAGIC       0x27051956      /* Image Magic Number           */
 #define IH_NMLEN               32      /* Image Name Length            */
 
+/* Reused from common.h */
+#define ROUND(a, b)            (((a) + (b) - 1) & ~((b) - 1))
+
 /*
  * Legacy format image header,
  * all data in network byte order (aka natural aka bigendian).
index 63f88b6c422390fa27b47b781f051776cc7978ff..a93d7eb543a22df27a187e023c2eba030a670ea5 100644 (file)
@@ -515,7 +515,14 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
 
        /* Set the imx header */
        (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
-       *header_size_ptr = sbuf->st_size + imxhdr->flash_offset;
+
+       /*
+        * ROM bug alert
+        * mx53 only loads 512 byte multiples.
+        * The remaining fraction of a block bytes would
+        * not be loaded.
+        */
+       *header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 512);
 }
 
 int imximage_check_params(struct mkimage_params *params)