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raw | patch | inline | side by side (parent: c48c895)
raw | patch | inline | side by side (parent: c48c895)
author | Tom Rini <trini@ti.com> | |
Tue, 24 Jul 2012 21:54:41 +0000 (14:54 -0700) | ||
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | |
Sat, 1 Sep 2012 12:58:12 +0000 (14:58 +0200) |
A number of memory initalization functions were int and always returned
0. Further it's not feasible to be doing error checking here, so simply
turn them into void functions.
Signed-off-by: Tom Rini <trini@ti.com>
0. Further it's not feasible to be doing error checking here, so simply
turn them into void functions.
Signed-off-by: Tom Rini <trini@ti.com>
arch/arm/cpu/armv7/am33xx/ddr.c | patch | blob | history | |
arch/arm/cpu/armv7/am33xx/emif4.c | patch | blob | history | |
arch/arm/include/asm/arch-am33xx/ddr_defs.h | patch | blob | history |
index b4b3c01e5bfb51a4c41c0509a029b821d3b1a9bf..7ac144a981c0688ce8a8324cbd6960f1a17a2351 100644 (file)
static struct ddr_cmdtctrl *ioctrl_reg = {
(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
-/**
- * As a convention, all functions here return 0 on success
- * -1 on failure.
- */
-
/**
* Configure SDRAM
*/
-int config_sdram(struct sdram_config *cfg)
+void config_sdram(struct sdram_config *cfg)
{
writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
-
- return 0;
}
/**
* Set SDRAM timings
*/
-int set_sdram_timings(struct sdram_timing *t)
+void set_sdram_timings(struct sdram_timing *t)
{
writel(t->time1, &emif_reg->emif_sdram_tim_1);
writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw);
writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw);
writel(t->time3, &emif_reg->emif_sdram_tim_3);
writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw);
-
- return 0;
}
/**
* Configure DDR PHY
*/
-int config_ddr_phy(struct ddr_phy_control *p)
+void config_ddr_phy(struct ddr_phy_control *p)
{
writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1);
writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
-
- return 0;
}
/**
* Configure DDR CMD control registers
*/
-int config_cmd_ctrl(const struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd)
{
writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
-
- return 0;
}
/**
* Configure DDR DATA registers
*/
-int config_ddr_data(int macrono, const struct ddr_data *data)
+void config_ddr_data(int macrono, const struct ddr_data *data)
{
writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
-
- return 0;
}
-int config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_io_ctrl(struct ddr_ioctrl *ioctrl)
{
writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
-
- return 0;
}
index e04e97067896b83703f995d1b92fe8b958198498..66ab892bf1a124d7ea52bac0e56b99fc5a93d6fe 100644 (file)
static void config_emif_ddr2(void)
{
- int ret;
struct sdram_config cfg;
struct sdram_timing tmg;
struct ddr_phy_control phyc;
cfg.refresh_sh = DDR2_EMIF_SDREF;
/* Program EMIF instance */
- ret = config_ddr_phy(&phyc);
- if (ret < 0)
- printf("Couldn't configure phyc\n");
-
-
- ret = set_sdram_timings(&tmg);
- if (ret < 0)
- printf("Couldn't configure timings\n");
-
- ret = config_sdram(&cfg);
- if (ret < 0)
- printf("Couldn't configure SDRAM\n");
+ config_ddr_phy(&phyc);
+ set_sdram_timings(&tmg);
+ config_sdram(&cfg);
}
void config_ddr(short ddr_type)
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index f755736a4c3f8d2677bff296e8248c09760d57dd..997480bae6075ec3841970e6324af31c7ed2d88e 100644 (file)
/**
* Configure SDRAM
*/
-int config_sdram(struct sdram_config *cfg);
+void config_sdram(struct sdram_config *cfg);
/**
* Set SDRAM timings
*/
-int set_sdram_timings(struct sdram_timing *val);
+void set_sdram_timings(struct sdram_timing *val);
/**
* Configure DDR PHY
*/
-int config_ddr_phy(struct ddr_phy_control *cfg);
+void config_ddr_phy(struct ddr_phy_control *cfg);
/**
* This structure represents the DDR registers on AM33XX devices.
/**
* Configure DDR CMD control registers
*/
-int config_cmd_ctrl(const struct cmd_control *cmd);
+void config_cmd_ctrl(const struct cmd_control *cmd);
/**
* Configure DDR DATA registers
*/
-int config_ddr_data(int data_macrono, const struct ddr_data *data);
+void config_ddr_data(int data_macrono, const struct ddr_data *data);
/**
* This structure represents the DDR io control on AM33XX devices.
/**
* Configure DDR io control registers
*/
-int config_io_ctrl(struct ddr_ioctrl *ioctrl);
+void config_io_ctrl(struct ddr_ioctrl *ioctrl);
struct ddr_ctrl {
unsigned int ddrioctrl;