s5pc1xx: add support SMDKC100 board

Adds new board SMDKC100 that uses s5pc100 SoC

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index 22976516e9365c6ba2450ac3524f8e995bc3af39..1bb25218673e0aa8ad63918cc174b0aa1cc273c9 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -735,6 +735,10 @@ Alex Z
        lart            SA1100
        dnp1110         SA1110
 
+Minkyu Kang <mk7.kang@samsung.com>
+
+       SMDKC100        ARM CORTEX-A8 (S5PC100 SoC)
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:

diff --git a/MAKEALL b/MAKEALL
index 38cd0768dcb1f2b75df0b46d06ed87027df704a1..6122e9f52e0810a64384bfe041b272766db5e296 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -605,6 +605,7 @@ LIST_ARM_CORTEX_A8="                \
        omap3_pandora           \
        omap3_zoom1             \
        omap3_zoom2             \
+       smdkc100                \
 "
 
 #########################################################################

diff --git a/Makefile b/Makefile
index 9637643cd5b00b22fe4dbdb2575a864a8cac23a4..1df7e9d8ec7bd50f7101ed9bc7aca2bc63438585 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -3144,6 +3144,9 @@ omap3_zoom1_config :      unconfig
 omap3_zoom2_config :   unconfig
        @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
 
+smdkc100_config:       unconfig
+       @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx
+
 #########################################################################
 ## XScale Systems
 #########################################################################

diff --git a/board/samsung/smdkc100/Makefile b/board/samsung/smdkc100/Makefile
new file mode 100644 (file)
index 0000000..808d0dd
--- /dev/null
+++ b/board/samsung/smdkc100/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS-y        := smdkc100.o
+COBJS-$(CONFIG_SAMSUNG_ONENAND)        += onenand.o
+SOBJS  := lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(SOBJS) $(OBJS)
+       $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

diff --git a/board/samsung/smdkc100/config.mk b/board/samsung/smdkc100/config.mk
new file mode 100644 (file)
index 0000000..ebab420
--- /dev/null
+++ b/board/samsung/smdkc100/config.mk
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2008 # Samsung Elecgtronics
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+
+# On S5PC100 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x38000000 to 0x40000000 (128MiB)
+#
+# On S5PC110 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x40000000 to 0x48000000 (128MiB)
+#
+TEXT_BASE = 0x34800000

diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S
new file mode 100644 (file)
index 0000000..32572c5
--- /dev/null
+++ b/board/samsung/smdkc100/lowlevel_init.S
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ */
+
+_TEXT_BASE:
+       .word   TEXT_BASE
+
+       .globl lowlevel_init
+lowlevel_init:
+       mov     r9, lr
+
+       /* r5 has always zero */
+       mov     r5, #0
+
+       ldr     r8, =S5PC100_GPIO_BASE
+
+       /* Disable Watchdog */
+       ldr     r0, =S5PC100_WATCHDOG_BASE              @0xEA200000
+       orr     r0, r0, #0x0
+       str     r5, [r0]
+
+#ifndef CONFIG_ONENAND_IPL
+       /* setting SRAM */
+       ldr     r0, =S5PC100_SROMC_BASE
+       ldr     r1, =0x9
+       str     r1, [r0]
+#endif
+
+       /* S5PC100 has 3 groups of interrupt sources */
+       ldr     r0, =S5PC100_VIC0_BASE                  @0xE4000000
+       ldr     r1, =S5PC100_VIC1_BASE                  @0xE4000000
+       ldr     r2, =S5PC100_VIC2_BASE                  @0xE4000000
+
+       /* Disable all interrupts (VIC0, VIC1 and VIC2) */
+       mvn     r3, #0x0
+       str     r3, [r0, #0x14]                         @INTENCLEAR
+       str     r3, [r1, #0x14]                         @INTENCLEAR
+       str     r3, [r2, #0x14]                         @INTENCLEAR
+
+#ifndef CONFIG_ONENAND_IPL
+       /* Set all interrupts as IRQ */
+       str     r5, [r0, #0xc]                          @INTSELECT
+       str     r5, [r1, #0xc]                          @INTSELECT
+       str     r5, [r2, #0xc]                          @INTSELECT
+
+       /* Pending Interrupt Clear */
+       str     r5, [r0, #0xf00]                        @INTADDRESS
+       str     r5, [r1, #0xf00]                        @INTADDRESS
+       str     r5, [r2, #0xf00]                        @INTADDRESS
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+       /* for UART */
+       bl uart_asm_init
+
+       /* for TZPC */
+       bl tzpc_asm_init
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+       /* init system clock */
+       bl      system_clock_init
+
+       bl      mem_ctrl_asm_init
+
+       /* Wakeup support. Don't know if it's going to be used, untested. */
+       ldr     r0, =S5PC100_RST_STAT
+       ldr     r1, [r0]
+       bic     r1, r1, #0xfffffff7
+       cmp     r1, #0x8
+       beq     wakeup_reset
+#endif
+
+1:
+       mov     lr, r9
+       mov     pc, lr
+
+#ifdef CONFIG_ONENAND_IPL
+wakeup_reset:
+
+       /* Clear wakeup status register */
+       ldr     r0, =S5PC100_WAKEUP_STAT
+       ldr     r1, [r0]
+       str     r1, [r0]
+
+       /* Load return address and jump to kernel */
+       ldr     r0, =S5PC100_INFORM0
+
+       /* r1 = physical address of s5pc100_cpu_resume function */
+       ldr     r1, [r0]
+
+       /* Jump to kernel (sleep.S) */
+       mov     pc, r1
+       nop
+       nop
+#endif
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+       ldr     r8, =S5PC1XX_CLOCK_BASE         @ 0xE0100000
+
+       /* Set Clock divider */
+       ldr     r1, =0x00011110
+       str     r1, [r8, #0x304]
+       ldr     r1, =0x1
+       str     r1, [r8, #0x308]
+       ldr     r1, =0x00011301
+       str     r1, [r8, #0x300]
+
+       /* Set Lock Time */
+       ldr     r1, =0xe10                      @ Locktime : 0xe10 = 3600
+       str     r1, [r8, #0x000]                @ APLL_LOCK
+       str     r1, [r8, #0x004]                @ MPLL_LOCK
+       str     r1, [r8, #0x008]                @ EPLL_LOCK
+       str     r1, [r8, #0x00C]                @ HPLL_LOCK
+
+       /* APLL_CON */
+       ldr     r1, =0x81bc0400         @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
+       str     r1, [r8, #0x100]
+       /* MPLL_CON */
+       ldr     r1, =0x80590201         @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+       str     r1, [r8, #0x104]
+       /* EPLL_CON */
+       ldr     r1, =0x80870303         @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+       str     r1, [r8, #0x108]
+       /* HPLL_CON */
+       ldr     r1, =0x80600603
+       str     r1, [r8, #0x10C]
+
+       /* Set Source Clock */
+       ldr     r1, =0x1111                     @ A, M, E, HPLL Muxing
+       str     r1, [r8, #0x200]                @ CLK_SRC0
+
+       ldr     r1, =0x1000001                  @ Uart Clock & CLK48M Muxing
+       str     r1, [r8, #0x204]                @ CLK_SRC1
+
+       ldr     r1, =0x9000                     @ ARMCLK/4
+       str     r1, [r8, #0x400]                @ CLK_OUT
+
+       /* wait at least 200us to stablize all clock */
+       mov     r2, #0x10000
+1:     subs    r2, r2, #1
+       bne     1b
+
+       mov     pc, lr
+
+#ifndef CONFIG_ONENAND_IPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+       mov     r0, r8
+       ldr     r1, =0x22222222
+       str     r1, [r0, #0x0]                  @ GPA0_CON
+       ldr     r1, =0x00022222
+       str     r1, [r0, #0x20]                 @ GPA1_CON
+
+       mov     pc, lr
+
+/*
+ * tzpc_asm_init: Initialize TZPC
+ */
+tzpc_asm_init:
+       ldr     r0, =0xE3800000
+       mov     r1, #0x0
+       str     r1, [r0]
+       mov     r1, #0xff
+       str     r1, [r0, #0x804]
+       str     r1, [r0, #0x810]
+
+       ldr     r0, =0xE2800000
+       str     r1, [r0, #0x804]
+       str     r1, [r0, #0x810]
+       str     r1, [r0, #0x81C]
+
+       ldr     r0, =0xE2900000
+       str     r1, [r0, #0x804]
+       str     r1, [r0, #0x810]
+
+       mov     pc, lr
+#endif

diff --git a/board/samsung/smdkc100/mem_setup.S b/board/samsung/smdkc100/mem_setup.S
new file mode 100644 (file)
index 0000000..94a701d
--- /dev/null
+++ b/board/samsung/smdkc100/mem_setup.S
@@ -0,0 +1,197 @@
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
+ *
+ * Copyright (C) 2009 Samsung Electrnoics
+ * Inki Dae <inki.dae@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+       .globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+       ldr     r6, =S5PC100_DMC_BASE                   @ 0xE6000000
+
+       /* DLL parameter setting */
+       ldr     r1, =0x50101000
+       str     r1, [r6, #0x018]                        @ PHYCONTROL0
+       ldr     r1, =0xf4
+       str     r1, [r6, #0x01C]                        @ PHYCONTROL1
+       ldr     r1, =0x0
+       str     r1, [r6, #0x020]                        @ PHYCONTROL2
+
+       /* DLL on */
+       ldr     r1, =0x50101002
+       str     r1, [r6, #0x018]                        @ PHYCONTROL0
+
+       /* DLL start */
+       ldr     r1, =0x50101003
+       str     r1, [r6, #0x018]                        @ PHYCONTROL0
+
+       /* Force value locking for DLL off */
+       str     r1, [r6, #0x018]                        @ PHYCONTROL0
+
+       /* DLL off */
+       ldr     r1, =0x50101001
+       str     r1, [r6, #0x018]                        @ PHYCONTROL0
+
+       /* auto refresh off */
+       ldr     r1, =0xff001010
+       str     r1, [r6, #0x000]                        @ CONCONTROL
+
+       /*
+        * Burst Length 4, 2 chips, 32-bit, LPDDR
+        * OFF: dynamic self refresh, force precharge, dynamic power down off
+        */
+       ldr     r1, =0x00212100
+       str     r1, [r6, #0x004]                        @ MEMCONTROL
+
+       /*
+        * Note:
+        * If Bank0 has OneDRAM we place it at 0x2800'0000
+        * So finally Bank1 should address start at at 0x2000'0000
+        */
+       mov     r4, #0x0
+
+swap_memory:
+       /*
+        * Bank0
+        * 0x30 -> 0x30000000
+        * 0xf8 -> 0x37FFFFFF
+        * [15:12] 0: Linear
+        * [11:8 ] 2: 9 bits
+        * [ 7:4 ] 2: 14 bits
+        * [ 3:0 ] 2: 4 banks
+        */
+       ldr     r1, =0x30f80222
+       /* if r4 is 1, swap the bank */
+       cmp     r4, #0x1
+       orreq   r1, r1, #0x08000000
+       str     r1, [r6, #0x008]                        @ MEMCONFIG0
+
+       /*
+        * Bank1
+        * 0x38 -> 0x38000000
+        * 0xf8 -> 0x3fFFFFFF
+        * [15:12] 0: Linear
+        * [11:8 ] 2: 9 bits
+        * [ 7:4 ] 2: 14 bits
+        * [ 3:0 ] 2: 4 banks
+        */
+       ldr     r1, =0x38f80222
+       /* if r4 is 1, swap the bank */
+       cmp     r4, #0x1
+       biceq   r1, r1, #0x08000000
+       str     r1, [r6, #0x00c]                        @ MEMCONFIG1
+
+       ldr     r1, =0x20000000
+       str     r1, [r6, #0x014]                        @ PRECHCONFIG
+
+       /*
+        * FIXME: Please verify these values
+        * 7.8us * 166MHz %LE %LONG1294(0x50E)
+        * 7.8us * 133MHz %LE %LONG1038(0x40E),
+        * 7.8us * 100MHz %LE %LONG780(0x30C),
+        * 7.8us * 20MHz  %LE %LONG156(0x9C),
+        * 7.8us * 10MHz  %LE %LONG78(0x4E)
+        */
+       ldr     r1, =0x0000050e
+       str     r1, [r6, #0x030]                        @ TIMINGAREF
+
+       /* 166 MHz */
+       ldr     r1, =0x0c233287
+       str     r1, [r6, #0x034]                        @ TIMINGROW
+
+       /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
+       ldr     r1, =0x32330303
+       str     r1, [r6, #0x038]                        @ TIMINGDATA
+
+       /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
+       ldr     r1, =0x04141433
+       str     r1, [r6, #0x03C]                        @ TIMINGPOWER
+
+       /* chip0 Deselect */
+       ldr     r1, =0x07000000
+       str     r1, [r6, #0x010]                        @ DIRECTCMD
+
+       /* chip0 PALL */
+       ldr     r1, =0x01000000
+       str     r1, [r6, #0x010]                        @ DIRECTCMD
+
+       /* chip0 REFA */
+       ldr     r1, =0x05000000
+       str     r1, [r6, #0x010]                        @ DIRECTCMD
+       /* chip0 REFA */
+       str     r1, [r6, #0x010]                        @ DIRECTCMD
+
+       /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+       ldr     r1, =0x00000032
+       str     r1, [r6, #0x010]                        @ DIRECTCMD
+
+       /* chip1 Deselect */
+       ldr     r1, =0x07100000
+       str     r1, [r6, #0x010]                        @ DIRECTCMD
+
+       /* chip1 PALL */
+       ldr     r1, =0x01100000
+       str     r1, [r6, #0x010]                        @ DIRECTCMD
+
+       /* chip1 REFA */
+       ldr     r1, =0x05100000
+       str     r1, [r6, #0x010]                        @ DIRECTCMD
+       /* chip1 REFA */
+       str     r1, [r6, #0x010]                        @ DIRECTCMD
+
+       /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+       ldr     r1, =0x00100032
+       str     r1, [r6, #0x010]                        @ DIRECTCMD
+
+       /* auto refresh on */
+       ldr     r1, =0xff002030
+       str     r1, [r6, #0x000]                        @ CONCONTROL
+
+       /* PwrdnConfig */
+       ldr     r1, =0x00100002
+       str     r1, [r6, #0x028]                        @ PWRDNCONFIG
+
+       /* BL%LE %LONG */
+       ldr     r1, =0xff212100
+       str     r1, [r6, #0x004]                        @ MEMCONTROL
+
+
+       /* Try to test memory area */
+       cmp     r4, #0x1
+       beq     1f
+
+       mov     r4, #0x1
+       ldr     r1, =0x37ffff00
+       str     r4, [r1]
+       str     r4, [r1, #0x4]                          @ dummy write
+       ldr     r0, [r1]
+       cmp     r0, r4
+       bne     swap_memory
+
+1:
+       mov     pc, lr
+
+       .ltorg

diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c
new file mode 100644 (file)
index 0000000..c25869e
--- /dev/null
+++ b/board/samsung/smdkc100/onenand.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+#include <onenand_uboot.h>
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+       struct onenand_chip *this = mtd->priv;
+       struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+       struct samsung_onenand *onenand;
+       int value;
+
+       this->base = (void *)S5PC100_ONENAND_BASE;
+       onenand = (struct samsung_onenand *)this->base;
+
+       /* D0 Domain memory clock gating */
+       value = readl(&clk->gate_d01);
+       value &= ~(1 << 2);             /* CLK_ONENANDC */
+       value |= (1 << 2);
+       writel(value, &clk->gate_d01);
+
+       value = readl(&clk->src0);
+       value &= ~(1 << 24);            /* MUX_1nand: 0 from HCLKD0 */
+       value &= ~(1 << 20);            /* MUX_HREF: 0 from FIN_27M */
+       writel(value, &clk->src0);
+
+       value = readl(&clk->div1);
+       value &= ~(3 << 16);            /* PCLKD1_RATIO */
+       value |= (1 << 16);
+       writel(value, &clk->div1);
+
+       writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
+
+       while (!(readl(&onenand->int_err_stat) & RST_CMP))
+               continue;
+
+       writel(RST_CMP, &onenand->int_err_ack);
+
+       /*
+        * Access_Clock [2:0]
+        * 166 MHz, 134 Mhz : 3
+        * 100 Mhz, 60 Mhz  : 2
+        */
+       writel(0x3, &onenand->acc_clock);
+
+       writel(INT_ERR_ALL, &onenand->int_err_mask);
+       writel(1 << 0, &onenand->int_pin_en);   /* Enable */
+
+       value = readl(&onenand->int_err_mask);
+       value &= ~RDY_ACT;
+       writel(value, &onenand->int_err_mask);
+
+       s3c_onenand_init(mtd);
+}

diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c
new file mode 100644 (file)
index 0000000..15a1a27
--- /dev/null
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -0,0 +1,51 @@
+/*
+ *  Copyright (C) 2008-2009 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+       gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+                                               PHYS_SDRAM_1_SIZE);
+
+       return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+       printf("Board:\tSMDKC100\n");
+       return 0;
+}
+#endif

diff --git a/doc/README.s5pc1xx b/doc/README.s5pc1xx
new file mode 100644 (file)
index 0000000..5a0fe33
--- /dev/null
+++ b/doc/README.s5pc1xx
@@ -0,0 +1,56 @@
+
+Summary
+=======
+
+This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx
+family of SoCs (S5PC100 [1] and S5PC110).
+
+Currently the following board is supported:
+
+* SMDKC100 [2]
+
+Toolchain
+=========
+
+While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
+with -march=armv5 to allow more compilers to work. For U-Boot code this has
+no performance impact.
+
+Build
+=====
+
+* SMDKC100
+
+make smdkc100_config
+make
+
+
+Interfaces
+==========
+
+cpu
+
+To check SoC:
+
+       if (cpu_is_s5pc100())
+               printf("cpu is s5pc100\n");
+
+       or
+
+       if (cpu_is_s5pc110())
+               printf("cpu is s5pc110\n");
+
+gpio
+       not supported yet.
+
+Links
+=====
+
+[1] S5PC100:
+
+http://www.samsung.com/global/business/semiconductor/productInfo.do?
+fmly_id=229&partnum=S5PC100
+
+[2] SMDKC100:
+
+http://meritech.co.kr/eng/products/product_view.php?num=28

diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
new file mode 100644 (file)
index 0000000..8c472af
--- /dev/null
+++ b/include/configs/smdkc100.h
@@ -0,0 +1,242 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * HeungJun Kim <riverful.kim@samsung.com>
+ * Inki Dae <inki.dae@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG SMDKC100 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARMCORTEXA8     1       /* This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG         1       /* in a SAMSUNG core */
+#define CONFIG_S5PC1XX         1       /* which is in a S5PC1XX Family */
+#define CONFIG_S5PC100         1       /* which is in a S5PC100 */
+#define CONFIG_SMDKC100                1       /* working with SMDKC100 */
+
+#include <asm/arch/cpu.h>              /* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_L2_OFF
+
+/* input clock of PLL: SMDKC100 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ            12000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE          0x30000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes for */
+                                               /* initial data */
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL0                 1       /* use SERIAL 0 on SMDKC100 */
+#define CONFIG_SERIAL_MULTI            1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE                        115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NET
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_BOOTDELAY       3
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#define MTDIDS_DEFAULT         "onenand0=s3c-onenand"
+#define MTDPARTS_DEFAULT       "mtdparts=s3c-onenand:256k(bootloader)"\
+                               ",128k@0x40000(params)"\
+                               ",3m@0x60000(kernel)"\
+                               ",16m@0x360000(test)"\
+                               ",-(UBI)"
+
+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTCOMMAND     "run ubifsboot"
+
+#define CONFIG_RAMDISK_BOOT    "root=/dev/ram0 rw rootfstype=ext2" \
+                               " console=ttySAC0,115200n8" \
+                               " mem=128M"
+
+#define CONFIG_COMMON_BOOT     "console=ttySAC0,115200n8" \
+                               " mem=128M " \
+                               " " MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTARGS        "root=/dev/mtdblock5 ubi.mtd=4" \
+                       " rootfstype=cramfs " CONFIG_COMMON_BOOT
+
+#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
+                       " onenand write 0x32008000 0x0 0x40000\0"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_EXTRA_ENV_SETTINGS                                      \
+       CONFIG_UPDATEB \
+       "updatek=" \
+               "onenand erase 0x60000 0x300000;" \
+               "onenand write 0x31008000 0x60000 0x300000\0" \
+       "updateu=" \
+               "onenand erase block 147-4095;" \
+               "onenand write 0x32000000 0x1260000 0x8C0000\0" \
+       "bootk=" \
+               "onenand read 0x30007FC0 0x60000 0x300000;" \
+               "bootm 0x30007FC0\0" \
+       "flashboot=" \
+               "set bootargs root=/dev/mtdblock${bootblock} " \
+               "rootfstype=${rootfstype} " \
+               "ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \
+               "run bootk\0" \
+       "ubifsboot=" \
+               "set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+               " ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
+               "run bootk\0" \
+       "boottrace=setenv opts initcall_debug; run bootcmd\0" \
+       "android=" \
+               "set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
+               "rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
+               "run bootk\0" \
+       "nfsboot=" \
+               "set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \
+               "nfsroot=${nfsroot},nolock " \
+               "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+               "${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \
+               "run bootk\0" \
+       "ramboot=" \
+               "set bootargs " CONFIG_RAMDISK_BOOT \
+               " initrd=0x33000000,8M ramdisk=8192\0" \
+       "rootfstype=cramfs\0" \
+       "mtdparts=" MTDPARTS_DEFAULT "\0" \
+       "meminfo=mem=128M\0" \
+       "nfsroot=/nfsroot/arm\0" \
+       "bootblock=5\0" \
+       "ubiblock=4\0" \
+       "ubi=enabled"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP            /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER         /* use "hush" command parser    */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_PROMPT              "SMDKC100 # "
+#define CONFIG_SYS_CBSIZE      256     /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE      384     /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS     16      /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START       CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END         (CONFIG_SYS_SDRAM_BASE + 0x5e00000)
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE
+
+#define CONFIG_SYS_HZ                  1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE       (256 << 10)     /* 256 KiB */
+
+/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
+#define CONFIG_NR_DRAM_BANKS   1
+#define PHYS_SDRAM_1           CONFIG_SYS_SDRAM_BASE   /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE      (128 << 20)     /* 0x8000000, 128 MB Bank #1 */
+
+#define CONFIG_SYS_MONITOR_BASE        0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH            1
+
+#define CONFIG_SYS_MONITOR_LEN         (256 << 10)     /* 256 KiB */
+#define CONFIG_IDENT_STRING            " for SMDKC100"
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+#define CONFIG_SYS_MAPPED_RAM_BASE     0xc0000000
+#else
+#define CONFIG_SYS_MAPPED_RAM_BASE     CONFIG_SYS_SDRAM_BASE
+#endif
+
+/*-----------------------------------------------------------------------
+ * Boot configuration
+ */
+#define CONFIG_ENV_IS_IN_ONENAND       1
+#define CONFIG_ENV_SIZE                        (128 << 10)     /* 128KiB, 0x20000 */
+#define CONFIG_ENV_ADDR                        (256 << 10)     /* 256KiB, 0x40000 */
+#define CONFIG_ENV_OFFSET              (256 << 10)     /* 256KiB, 0x40000 */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND         1
+#define CONFIG_SYS_ONENAND_BASE                0xE7100000
+
+#define CONFIG_DOS_PARTITION           1
+
+#endif /* __CONFIG_H */