Merge branch 'master' of git://git.denx.de/u-boot-arm
authorTom Rini <trini@ti.com>
Tue, 12 Feb 2013 15:18:31 +0000 (10:18 -0500)
committerTom Rini <trini@ti.com>
Tue, 12 Feb 2013 15:18:31 +0000 (10:18 -0500)
308 files changed:
MAINTAINERS
Makefile
README
arch/arm/cpu/arm1136/mx31/timer.c
arch/arm/cpu/arm1136/mx35/generic.c
arch/arm/cpu/arm1136/mx35/timer.c
arch/arm/cpu/arm1136/omap24xx/timer.c
arch/arm/cpu/arm920t/a320/timer.c
arch/arm/cpu/arm920t/at91/clock.c
arch/arm/cpu/arm920t/at91/timer.c
arch/arm/cpu/arm920t/s3c24x0/timer.c
arch/arm/cpu/arm926ejs/armada100/timer.c
arch/arm/cpu/arm926ejs/at91/clock.c
arch/arm/cpu/arm926ejs/at91/timer.c
arch/arm/cpu/arm926ejs/davinci/timer.c
arch/arm/cpu/arm926ejs/kirkwood/timer.c
arch/arm/cpu/arm926ejs/mb86r0x/timer.c
arch/arm/cpu/arm926ejs/mx25/generic.c
arch/arm/cpu/arm926ejs/mx25/timer.c
arch/arm/cpu/arm926ejs/mx27/timer.c
arch/arm/cpu/arm926ejs/mxs/timer.c
arch/arm/cpu/arm926ejs/omap/timer.c
arch/arm/cpu/arm926ejs/orion5x/timer.c
arch/arm/cpu/arm926ejs/pantheon/timer.c
arch/arm/cpu/arm926ejs/spear/timer.c
arch/arm/cpu/arm926ejs/versatile/timer.c
arch/arm/cpu/armv7/omap-common/timer.c
arch/arm/cpu/armv7/s5p-common/timer.c
arch/arm/cpu/armv7/socfpga/timer.c
arch/arm/cpu/armv7/u8500/timer.c
arch/arm/cpu/armv7/zynq/timer.c
arch/arm/cpu/ixp/timer.c
arch/arm/cpu/pxa/timer.c
arch/arm/cpu/tegra-common/timer.c
arch/arm/imx-common/speed.c
arch/arm/imx-common/timer.c
arch/arm/include/asm/arch-at91/clk.h
arch/arm/include/asm/global_data.h
arch/arm/lib/board.c
arch/arm/lib/bootm.c
arch/arm/lib/cache-cp15.c
arch/avr32/cpu/cpu.c
arch/avr32/cpu/exception.c
arch/avr32/cpu/interrupts.c
arch/avr32/include/asm/global_data.h
arch/avr32/lib/board.c
arch/avr32/lib/bootm.c
arch/blackfin/include/asm/global_data.h
arch/m68k/cpu/mcf5227x/cpu.c
arch/m68k/cpu/mcf5227x/speed.c
arch/m68k/cpu/mcf523x/speed.c
arch/m68k/cpu/mcf52x2/speed.c
arch/m68k/cpu/mcf532x/speed.c
arch/m68k/cpu/mcf5445x/cpu.c
arch/m68k/cpu/mcf5445x/speed.c
arch/m68k/cpu/mcf547x_8x/speed.c
arch/m68k/include/asm/global_data.h
arch/m68k/lib/board.c
arch/microblaze/include/asm/global_data.h
arch/microblaze/lib/Makefile
arch/microblaze/lib/muldi3.c [new file with mode: 0644]
arch/mips/cpu/mips32/config.mk
arch/mips/cpu/mips32/start.S
arch/mips/cpu/mips64/start.S
arch/mips/cpu/u-boot.lds [moved from board/micronas/vct/u-boot.lds with 73% similarity]
arch/mips/cpu/xburst/config.mk
arch/mips/cpu/xburst/start.S
arch/mips/cpu/xburst/timer.c
arch/mips/include/asm/global_data.h
arch/mips/include/asm/io.h
arch/mips/lib/bootm.c
arch/nds32/include/asm/global_data.h
arch/nds32/lib/board.c
arch/nios2/cpu/fdt.c
arch/nios2/include/asm/global_data.h
arch/openrisc/include/asm/global_data.h
arch/powerpc/cpu/mpc512x/cpu.c
arch/powerpc/cpu/mpc512x/cpu_init.c
arch/powerpc/cpu/mpc512x/i2c.c
arch/powerpc/cpu/mpc512x/ide.c
arch/powerpc/cpu/mpc512x/serial.c
arch/powerpc/cpu/mpc512x/speed.c
arch/powerpc/cpu/mpc5xxx/cpu.c
arch/powerpc/cpu/mpc5xxx/i2c.c
arch/powerpc/cpu/mpc5xxx/ide.c
arch/powerpc/cpu/mpc5xxx/serial.c
arch/powerpc/cpu/mpc5xxx/speed.c
arch/powerpc/cpu/mpc8220/fec.c
arch/powerpc/cpu/mpc8220/speed.c
arch/powerpc/cpu/mpc8260/commproc.c
arch/powerpc/cpu/mpc8260/cpu.c
arch/powerpc/cpu/mpc8260/cpu_init.c
arch/powerpc/cpu/mpc8260/i2c.c
arch/powerpc/cpu/mpc8260/speed.c
arch/powerpc/cpu/mpc83xx/Makefile
arch/powerpc/cpu/mpc83xx/cpu.c
arch/powerpc/cpu/mpc83xx/cpu_init.c
arch/powerpc/cpu/mpc83xx/fdt.c
arch/powerpc/cpu/mpc83xx/pcie.c
arch/powerpc/cpu/mpc83xx/speed.c
arch/powerpc/cpu/mpc83xx/spl_minimal.c [moved from arch/powerpc/cpu/mpc83xx/nand_init.c with 100% similarity]
arch/powerpc/cpu/mpc83xx/start.S
arch/powerpc/cpu/mpc83xx/u-boot-spl.lds [moved from nand_spl/board/freescale/mpc8313erdb/u-boot.lds with 100% similarity]
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/b4860_ids.c
arch/powerpc/cpu/mpc85xx/b4860_serdes.c
arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/commproc.c
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc85xx/tlb.c
arch/powerpc/cpu/mpc86xx/cpu.c
arch/powerpc/cpu/mpc86xx/fdt.c
arch/powerpc/cpu/mpc86xx/speed.c
arch/powerpc/cpu/mpc8xx/commproc.c
arch/powerpc/cpu/mpc8xx/cpu.c
arch/powerpc/cpu/mpc8xx/fdt.c
arch/powerpc/cpu/mpc8xx/speed.c
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
arch/powerpc/cpu/mpc8xxx/ddr/main.c
arch/powerpc/cpu/mpc8xxx/fdt.c
arch/powerpc/cpu/mpc8xxx/law.c
arch/powerpc/cpu/ppc4xx/4xx_uart.c
arch/powerpc/cpu/ppc4xx/fdt.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/global_data.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/mmu.h
arch/powerpc/include/asm/processor.h
arch/powerpc/lib/Makefile
arch/powerpc/lib/board.c
arch/powerpc/lib/bootm.c
arch/sandbox/cpu/cpu.c
arch/sandbox/include/asm/global_data.h
arch/sandbox/lib/board.c
arch/sh/include/asm/global_data.h
arch/sparc/include/asm/global_data.h
arch/x86/cpu/cpu.c
arch/x86/cpu/start.S
arch/x86/include/asm/arch-coreboot/sysinfo.h
arch/x86/include/asm/global_data.h
board/ait/cam_enc_4xx/config.mk
board/cm5200/cm5200.c
board/dbau1x00/u-boot.lds [deleted file]
board/evb64260/mpsc.c
board/freescale/b4860qds/Makefile [new file with mode: 0644]
board/freescale/b4860qds/b4860qds.c [new file with mode: 0644]
board/freescale/b4860qds/b4860qds.h [new file with mode: 0644]
board/freescale/b4860qds/b4860qds_crossbar_con.h [new file with mode: 0644]
board/freescale/b4860qds/b4860qds_qixis.h [new file with mode: 0644]
board/freescale/b4860qds/ddr.c [new file with mode: 0644]
board/freescale/b4860qds/eth_b4860qds.c [new file with mode: 0644]
board/freescale/b4860qds/law.c [new file with mode: 0644]
board/freescale/b4860qds/pci.c [moved from board/qi/qi_lb60/u-boot.lds with 50% similarity]
board/freescale/b4860qds/tlb.c [new file with mode: 0644]
board/freescale/bsc9131rdb/bsc9131rdb.c
board/freescale/bsc9132qds/Makefile [new file with mode: 0644]
board/freescale/bsc9132qds/README [new file with mode: 0644]
board/freescale/bsc9132qds/bsc9132qds.c [new file with mode: 0644]
board/freescale/bsc9132qds/ddr.c [new file with mode: 0644]
board/freescale/bsc9132qds/law.c [new file with mode: 0644]
board/freescale/bsc9132qds/tlb.c [new file with mode: 0644]
board/freescale/common/qixis.c
board/freescale/common/qixis.h
board/freescale/corenet_ds/corenet_ds.c
board/freescale/corenet_ds/rcw_p2041rdb.cfg [new file with mode: 0644]
board/freescale/mpc8313erdb/mpc8313erdb.c
board/freescale/p1010rdb/ddr.c
board/freescale/p1010rdb/p1010rdb.c
board/freescale/p1_p2_rdb/ddr.c
board/freescale/p1_p2_rdb/p1_p2_rdb.c
board/freescale/p2041rdb/eth.c
board/freescale/p2041rdb/p2041rdb.c
board/freescale/t4qds/law.c
board/freescale/t4qds/t4qds.c
board/freescale/t4qds/t4qds.h
board/freescale/t4qds/tlb.c
board/gdsys/405ep/405ep.c
board/gdsys/405ex/405ex.c
board/gdsys/405ex/io64.c
board/incaip/u-boot.lds [deleted file]
board/inka4x0/inkadiag.c
board/lwmon/lwmon.c
board/lwmon5/kbd.c
board/lwmon5/lwmon5.c
board/pb1x00/u-boot.lds [deleted file]
board/qemu-mips/u-boot.lds [deleted file]
board/sc3/init.S
board/xilinx/common/xbasic_types.c [deleted file]
board/xilinx/common/xbasic_types.h [deleted file]
board/xilinx/common/xbuf_descriptor.h [deleted file]
board/xilinx/common/xdma_channel.c [deleted file]
board/xilinx/common/xdma_channel.h [deleted file]
board/xilinx/common/xdma_channel_i.h [deleted file]
board/xilinx/common/xdma_channel_sg.c [deleted file]
board/xilinx/common/xio.h [deleted file]
board/xilinx/common/xipif_v1_23_b.c [deleted file]
board/xilinx/common/xipif_v1_23_b.h [deleted file]
board/xilinx/common/xpacket_fifo_v1_00_b.c [deleted file]
board/xilinx/common/xpacket_fifo_v1_00_b.h [deleted file]
board/xilinx/common/xstatus.h [deleted file]
board/xilinx/common/xversion.c [deleted file]
board/xilinx/common/xversion.h [deleted file]
board/xilinx/microblaze-generic/microblaze-generic.c
board/xilinx/xilinx_iic/xiic_l.c [deleted file]
board/xilinx/xilinx_iic/xiic_l.h [deleted file]
board/xilinx/zynq/Makefile
boards.cfg
common/cmd_bdinfo.c
common/cmd_bootm.c
common/cmd_fdt.c
common/cmd_immap.c
common/cmd_time.c
common/command.c
common/env_mmc.c
common/fdt_support.c
common/hush.c
common/image.c
common/main.c
common/stdio.c
doc/README.b4860qds [new file with mode: 0644]
doc/README.fsl-ddr
doc/README.mips
doc/README.qemu-mips [moved from board/qemu-mips/README with 88% similarity]
drivers/block/systemace.c
drivers/i2c/fsl_i2c.c
drivers/i2c/mxs_i2c.c
drivers/input/ps2ser.c
drivers/mmc/fsl_esdhc.c
drivers/mtd/spi/spansion.c
drivers/mtd/spi/stmicro.c
drivers/mtd/spi/winbond.c
drivers/net/fm/Makefile
drivers/net/fm/b4860.c [new file with mode: 0644]
drivers/net/mpc512x_fec.c
drivers/net/mpc5xxx_fec.c
drivers/qe/fdt.c
drivers/qe/qe.c
drivers/serial/arm_dcc.c
drivers/spi/xilinx_spi.c
drivers/spi/xilinx_spi.h
examples/standalone/mem_to_mem_idma2intr.c
fs/fat/fat.c
fs/fat/fat_write.c
include/asm-generic/global_data.h [new file with mode: 0644]
include/command.h
include/configs/B4860QDS.h [new file with mode: 0644]
include/configs/BSC9132QDS.h [new file with mode: 0644]
include/configs/MPC8313ERDB.h
include/configs/MPC8544DS.h
include/configs/MPC8572DS.h
include/configs/P2020DS.h
include/configs/P2041RDB.h
include/configs/am3517_crane.h
include/configs/am3517_evm.h
include/configs/apx4devkit.h
include/configs/cm_t35.h
include/configs/devkit8000.h
include/configs/dig297.h
include/configs/igep00x0.h
include/configs/mcx.h
include/configs/microblaze-generic.h
include/configs/omap3_beagle.h
include/configs/omap3_evm_common.h
include/configs/omap3_logic.h
include/configs/omap3_mvblx.h
include/configs/omap3_pandora.h
include/configs/omap3_sdp3430.h
include/configs/omap3_zoom1.h
include/configs/omap3_zoom2.h
include/configs/omap4_common.h
include/configs/sc_sps_1.h
include/configs/t4qds.h
include/configs/tam3517-common.h
include/configs/tricorder.h
include/fat.h
include/fdt.h
include/fdt_support.h
include/image.h
include/libfdt.h
include/libfdt_env.h
include/stdio_dev.h
lib/libfdt/fdt.c
lib/libfdt/fdt_ro.c
lib/libfdt/fdt_rw.c
lib/libfdt/fdt_sw.c
lib/libfdt/fdt_wip.c
nand_spl/board/freescale/mpc8313erdb/Makefile [deleted file]
nand_spl/board/freescale/mpc8315erdb/Makefile
nand_spl/board/sheldon/simpc8313/Makefile
tools/fdt_host.h
tools/imls/imls.c
tools/patman/README
tools/patman/checkpatch.py
tools/patman/get_maintainer.py [new file with mode: 0644]
tools/patman/gitutil.py
tools/patman/patman.py
tools/patman/project.py [new file with mode: 0644]
tools/patman/series.py
tools/patman/settings.py
tools/patman/test.py

index 64a7ec893ac8ee6ea17babf94bd4d07d2ca3c42c..45e2dd45411fda77564c0b1a1781efe17d76889d 100644 (file)
@@ -27,6 +27,10 @@ Poonam Aggrwal <poonam.aggrwal@freescale.com>
 
        BSC9131RDB      BSC9131
 
+Naveen Burmi <NaveenBurmi@freescale.com>
+
+       BSC9132QDS      BSC9132
+
 Greg Allen <gallen@arlut.utexas.edu>
 
        UTX8245         MPC8245
index 107ee4f909af8c65a4ac738a7ccc7a5d90a9df44..35eee704dd18aed084a06e1b6cc464499ab3a29e 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -485,8 +485,12 @@ $(obj)u-boot.sha1: $(obj)u-boot.bin
 $(obj)u-boot.dis:      $(obj)u-boot
                $(OBJDUMP) -d $< > $@
 
+
+
 $(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-               $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+               $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(or $(CONFIG_SPL_PAD_TO),0) \
+                       -O binary $(obj)spl/u-boot-spl \
+                       $(obj)spl/u-boot-spl-pad.bin
                cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
                rm $(obj)spl/u-boot-spl-pad.bin
 
diff --git a/README b/README
index a33647623767f52c971e5ca2cc70c653cecf24dc..2352e3862bfa81f4ad2bca262cc26529ac008fd7 100644 (file)
--- a/README
+++ b/README
@@ -2819,6 +2819,12 @@ FIT uImage format:
                CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
                Filename to read to load U-Boot when reading from FAT
 
+               CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
+               Set this for NAND SPL on PPC mpc83xx targets, so that
+               start.S waits for the rest of the SPL to load before
+               continuing (the hardware starts execution after just
+               loading the first page rather than the full 4K).
+
                CONFIG_SPL_NAND_BASE
                Include nand_base.c in the SPL.  Requires
                CONFIG_SPL_NAND_DRIVERS.
@@ -2876,6 +2882,10 @@ FIT uImage format:
                CONFIG_SPL_LIBGENERIC_SUPPORT
                Support for lib/libgeneric.o in SPL binary
 
+               CONFIG_SPL_PAD_TO
+               Linker address to which the SPL should be padded before
+               appending the SPL payload.
+
                CONFIG_SPL_TARGET
                Final target image containing SPL and payload.  Some SPLs
                use an arch-specific makefile fragment instead, for
index 86916d1edb1c603f40039b5ab3ae8da05ef0cbc1..b006b6015de45928b668049b2e0ed7a1fdea833b 100644 (file)
@@ -115,13 +115,13 @@ unsigned long long get_ticks(void)
 {
        ulong now = GPTCNT; /* current tick value */
 
-       if (now >= gd->lastinc) /* normal mode (non roll) */
+       if (now >= gd->arch.lastinc)    /* normal mode (non roll) */
                /* move stamp forward with absolut diff ticks */
-               gd->tbl += (now - gd->lastinc);
+               gd->arch.tbl += (now - gd->arch.lastinc);
        else                    /* we have rollover of incrementer */
-               gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
-       gd->lastinc = now;
-       return gd->tbl;
+               gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
+       gd->arch.lastinc = now;
+       return gd->arch.tbl;
 }
 
 ulong get_timer_masked(void)
index 295a98ea4b6d5fabf9de1c01fb03a4f40c668b94..d11e6f6270cd4b3c5a2e8b5b99380a7a61045536 100644 (file)
@@ -478,11 +478,11 @@ int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
 #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 #else
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 #endif
 #endif
        return 0;
index 9680b7fde7bb18a6bb0615c698c76094a612b438..584ad15135cf58ca0b024ff53a931c96b2936681 100644 (file)
@@ -32,8 +32,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp      (gd->tbl)
-#define lastinc                (gd->lastinc)
+#define timestamp      (gd->arch.tbl)
+#define lastinc                (gd->arch.lastinc)
 
 /* General purpose timers bitfields */
 #define GPTCR_SWR       (1<<15)        /* Software reset */
index e929ae45bbf7023248608d3cf055692da423fc7f..53015cb77dc954016d6bbbec541d4d9c54d8cd02 100644 (file)
@@ -51,8 +51,8 @@ int timer_init (void)
        *((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;     /* start timer */
 
        /* reset time */
-       gd->lastinc = READ_TIMER;       /* capture current incrementer value */
-       gd->tbl = 0;                    /* start "advancing" time stamp */
+       gd->arch.lastinc = READ_TIMER;  /* capture current incrementer value */
+       gd->arch.tbl = 0;               /* start "advancing" time stamp */
 
        return(0);
 }
@@ -81,8 +81,8 @@ void __udelay (unsigned long usec)
        tmp = get_timer (0);            /* get current timestamp */
        if ((tmo + tmp + 1) < tmp) {    /* if setting this forward will roll */
                                        /* time stamp, then reset time */
-               gd->lastinc = READ_TIMER;       /* capture incrementer value */
-               gd->tbl = 0;                    /* start time stamp */
+               gd->arch.lastinc = READ_TIMER;  /* capture incrementer value */
+               gd->arch.tbl = 0;                       /* start time stamp */
        } else {
                tmo     += tmp;         /* else, set advancing stamp wake up time */
        }
@@ -94,12 +94,15 @@ ulong get_timer_masked (void)
 {
        ulong now = READ_TIMER;         /* current tick value */
 
-       if (now >= gd->lastinc)         /* normal mode (non roll) */
-               gd->tbl += (now - gd->lastinc); /* move stamp fordward with absoulte diff ticks */
-       else                            /* we have rollover of incrementer */
-               gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
-       gd->lastinc = now;
-       return gd->tbl;
+       if (now >= gd->arch.lastinc) {          /* normal mode (non roll) */
+               /* move stamp fordward with absoulte diff ticks */
+               gd->arch.tbl += (now - gd->arch.lastinc);
+       } else {
+               /* we have rollover of incrementer */
+               gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
+       }
+       gd->arch.lastinc = now;
+       return gd->arch.tbl;
 }
 
 /* waits specified delay value and resets timestamp */
index 4bfcef2379b456ac645ce4d659c44b735a914765..512fb9d73db8dfb7cf7331c914ff62c84c84b19d 100644 (file)
@@ -31,14 +31,14 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
        tick *= CONFIG_SYS_HZ;
-       do_div(tick, gd->timer_rate_hz);
+       do_div(tick, gd->arch.timer_rate_hz);
 
        return tick;
 }
 
 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-       usec *= gd->timer_rate_hz;
+       usec *= gd->arch.timer_rate_hz;
        do_div(usec, 1000000);
 
        return usec;
@@ -74,8 +74,8 @@ int timer_init(void)
        cr |= FTTMR010_TM3_ENABLE;
        writel(cr, &tmr->cr);
 
-       gd->timer_rate_hz = TIMER_CLOCK;
-       gd->tbu = gd->tbl = 0;
+       gd->arch.timer_rate_hz = TIMER_CLOCK;
+       gd->arch.tbu = gd->arch.tbl = 0;
 
        return 0;
 }
@@ -89,10 +89,10 @@ unsigned long long get_ticks(void)
        ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
 
        /* increment tbu if tbl has rolled over */
-       if (now < gd->tbl)
-               gd->tbu++;
-       gd->tbl = now;
-       return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+       if (now < gd->arch.tbl)
+               gd->arch.tbu++;
+       gd->arch.tbl = now;
+       return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
 }
 
 void __udelay(unsigned long usec)
@@ -126,5 +126,5 @@ ulong get_timer(ulong base)
  */
 ulong get_tbclk(void)
 {
-       return gd->timer_rate_hz;
+       return gd->arch.timer_rate_hz;
 }
index 09d2799831a2511293c984b21413f4c478918232..696200d04a027658b1761a1c6347dc24b2330abb 100644 (file)
@@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
        case AT91_PMC_MCKR_CSS_SLOW:
                return CONFIG_SYS_AT91_SLOW_CLOCK;
        case AT91_PMC_MCKR_CSS_MAIN:
-               return gd->main_clk_rate_hz;
+               return gd->arch.main_clk_rate_hz;
        case AT91_PMC_MCKR_CSS_PLLA:
-               return gd->plla_rate_hz;
+               return gd->arch.plla_rate_hz;
        case AT91_PMC_MCKR_CSS_PLLB:
-               return gd->pllb_rate_hz;
+               return gd->arch.pllb_rate_hz;
        }
 
        return 0;
@@ -124,10 +124,10 @@ int at91_clock_init(unsigned long main_clock)
                main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
        }
 #endif
-       gd->main_clk_rate_hz = main_clock;
+       gd->arch.main_clk_rate_hz = main_clock;
 
        /* report if PLLA is more than mildly overclocked */
-       gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+       gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 
 #ifdef CONFIG_USB_ATMEL
        /*
@@ -136,9 +136,10 @@ int at91_clock_init(unsigned long main_clock)
         *
         * REVISIT:  assumes MCK doesn't derive from PLLB!
         */
-       gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+       gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
                             AT91_PMC_PLLBR_USBDIV_2;
-       gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
+       gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+                                             gd->arch.at91_pllb_usb_init);
 #endif
 
        /*
@@ -146,13 +147,14 @@ int at91_clock_init(unsigned long main_clock)
         * For now, assume this parentage won't change.
         */
        mckr = readl(&pmc->mckr);
-       gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-       freq = gd->mck_rate_hz;
+       gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+       freq = gd->arch.mck_rate_hz;
 
        freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
        /* mdiv */
-       gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
-       gd->cpu_clk_rate_hz = freq;
+       gd->arch.mck_rate_hz = freq /
+                       (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+       gd->arch.cpu_clk_rate_hz = freq;
 
        return 0;
 }
index 91607b525e40efd616db06440e6a7c8c32ecae02..8ce75843a0e239e7000621f3b56fe278ed848db7 100644 (file)
@@ -63,8 +63,8 @@ int timer_init(void)
        writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
 
        writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
-       gd->lastinc = 0;
-       gd->tbl = 0;
+       gd->arch.lastinc = 0;
+       gd->arch.tbl = 0;
 
        return 0;
 }
@@ -89,16 +89,16 @@ ulong get_timer_raw(void)
 
        now = readl(&tc->tc[0].cv) & 0x0000ffff;
 
-       if (now >= gd->lastinc) {
+       if (now >= gd->arch.lastinc) {
                /* normal mode */
-               gd->tbl += now - gd->lastinc;
+               gd->arch.tbl += now - gd->arch.lastinc;
        } else {
                /* we have an overflow ... */
-               gd->tbl += now + TIMER_LOAD_VAL - gd->lastinc;
+               gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
        }
-       gd->lastinc = now;
+       gd->arch.lastinc = now;
 
-       return gd->tbl;
+       return gd->arch.tbl;
 }
 
 ulong get_timer_masked(void)
index d8668bec5edd90ca9dbb6b084c8224bcc5c643bd..d76bf186b6516891f2044a92a3a8c29ff2c2540e 100644 (file)
@@ -45,25 +45,25 @@ int timer_init(void)
        /* use PWM Timer 4 because it has no output */
        /* prescaler for Timer 4 is 16 */
        writel(0x0f00, &timers->tcfg0);
-       if (gd->tbu == 0) {
+       if (gd->arch.tbu == 0) {
                /*
                 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
                 * (default) and prescaler = 16. Should be 10390
                 * @33.25MHz and 15625 @ 50 MHz
                 */
-               gd->tbu = get_PCLK() / (2 * 16 * 100);
-               gd->timer_rate_hz = get_PCLK() / (2 * 16);
+               gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
+               gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
        }
        /* load value for 10 ms timeout */
-       writel(gd->tbu, &timers->tcntb4);
+       writel(gd->arch.tbu, &timers->tcntb4);
        /* auto load, manual update of timer 4 */
        tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
        writel(tmr, &timers->tcon);
        /* auto load, start timer 4 */
        tmr = (tmr & ~0x0700000) | 0x0500000;
        writel(tmr, &timers->tcon);
-       gd->lastinc = 0;
-       gd->tbl = 0;
+       gd->arch.lastinc = 0;
+       gd->arch.tbl = 0;
 
        return 0;
 }
@@ -82,7 +82,7 @@ void __udelay (unsigned long usec)
        ulong start = get_ticks();
 
        tmo = usec / 1000;
-       tmo *= (gd->tbu * 100);
+       tmo *= (gd->arch.tbu * 100);
        tmo /= 1000;
 
        while ((ulong) (get_ticks() - start) < tmo)
@@ -93,7 +93,7 @@ ulong get_timer_masked(void)
 {
        ulong tmr = get_ticks();
 
-       return tmr / (gd->timer_rate_hz / CONFIG_SYS_HZ);
+       return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
 }
 
 void udelay_masked(unsigned long usec)
@@ -104,10 +104,10 @@ void udelay_masked(unsigned long usec)
 
        if (usec >= 1000) {
                tmo = usec / 1000;
-               tmo *= (gd->tbu * 100);
+               tmo *= (gd->arch.tbu * 100);
                tmo /= 1000;
        } else {
-               tmo = usec * (gd->tbu * 100);
+               tmo = usec * (gd->arch.tbu * 100);
                tmo /= (1000 * 1000);
        }
 
@@ -128,16 +128,16 @@ unsigned long long get_ticks(void)
        struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
        ulong now = readl(&timers->tcnto4) & 0xffff;
 
-       if (gd->lastinc >= now) {
+       if (gd->arch.lastinc >= now) {
                /* normal mode */
-               gd->tbl += gd->lastinc - now;
+               gd->arch.tbl += gd->arch.lastinc - now;
        } else {
                /* we have an overflow ... */
-               gd->tbl += gd->lastinc + gd->tbu - now;
+               gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now;
        }
-       gd->lastinc = now;
+       gd->arch.lastinc = now;
 
-       return gd->tbl;
+       return gd->arch.tbl;
 }
 
 /*
index 355cd6d1d8200e055b639698273b7fc70a12f9b2..948607f8c033f41ceb6bcd31d3a0488b6978635a 100644 (file)
@@ -61,7 +61,7 @@ struct armd1tmr_registers {
 #define        COUNT_RD_REQ            0x1
 
 DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
 
 /* For preventing risk of instability in reading counter value,
  * first set read request to register cvwr and then read same
@@ -82,16 +82,16 @@ ulong get_timer_masked(void)
 {
        ulong now = read_timer();
 
-       if (now >= gd->tbl) {
+       if (now >= gd->arch.tbl) {
                /* normal mode */
-               gd->tbu += now - gd->tbl;
+               gd->arch.tbu += now - gd->arch.tbl;
        } else {
                /* we have an overflow ... */
-               gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+               gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
        }
-       gd->tbl = now;
+       gd->arch.tbl = now;
 
-       return gd->tbu;
+       return gd->arch.tbu;
 }
 
 ulong get_timer(ulong base)
@@ -135,9 +135,9 @@ int timer_init(void)
 
        /* Enable timer 0 */
        writel(0x1, &armd1timers->cer);
-       /* init the gd->tbu and gd->tbl value */
-       gd->tbl = read_timer();
-       gd->tbu = 0;
+       /* init the gd->arch.tbu and gd->arch.tbl value */
+       gd->arch.tbl = read_timer();
+       gd->arch.tbu = 0;
 
        return 0;
 }
index dc5c6c4b0b29b0f2f69a3ec732b6a87185c1c219..f825388ae994f3dde7dca9fd1bb4cbe67beac897 100644 (file)
@@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
        case AT91_PMC_MCKR_CSS_SLOW:
                return CONFIG_SYS_AT91_SLOW_CLOCK;
        case AT91_PMC_MCKR_CSS_MAIN:
-               return gd->main_clk_rate_hz;
+               return gd->arch.main_clk_rate_hz;
        case AT91_PMC_MCKR_CSS_PLLA:
-               return gd->plla_rate_hz;
+               return gd->arch.plla_rate_hz;
        case AT91_PMC_MCKR_CSS_PLLB:
-               return gd->pllb_rate_hz;
+               return gd->arch.pllb_rate_hz;
        }
 
        return 0;
@@ -132,10 +132,10 @@ int at91_clock_init(unsigned long main_clock)
                main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
        }
 #endif
-       gd->main_clk_rate_hz = main_clock;
+       gd->arch.main_clk_rate_hz = main_clock;
 
        /* report if PLLA is more than mildly overclocked */
-       gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+       gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
 
 #ifdef CONFIG_USB_ATMEL
        /*
@@ -144,9 +144,10 @@ int at91_clock_init(unsigned long main_clock)
         *
         * REVISIT:  assumes MCK doesn't derive from PLLB!
         */
-       gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+       gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
                             AT91_PMC_PLLBR_USBDIV_2;
-       gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
+       gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+                                             gd->arch.at91_pllb_usb_init);
 #endif
 
        /*
@@ -157,15 +158,15 @@ int at91_clock_init(unsigned long main_clock)
 #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
                || defined(CONFIG_AT91SAM9X5)
        /* plla divisor by 2 */
-       gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+       gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
 #endif
-       gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-       freq = gd->mck_rate_hz;
+       gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+       freq = gd->arch.mck_rate_hz;
 
        freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
 #if defined(CONFIG_AT91SAM9G20)
        /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
-       gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+       gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
                freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
        if (mckr & AT91_PMC_MCKR_MDIV_MASK)
                freq /= 2;                      /* processor clock division */
@@ -177,14 +178,15 @@ int at91_clock_init(unsigned long main_clock)
         *  2   <==>   4
         *  3   <==>   3
         */
-       gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+       gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
                (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
                ? freq / 3
                : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #else
-       gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+       gd->arch.mck_rate_hz = freq /
+                       (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
 #endif
-       gd->cpu_clk_rate_hz = freq;
+       gd->arch.cpu_clk_rate_hz = freq;
 
        return 0;
 }
index f70ce83f08391e5378e96f5269a52f86ce4e984a..4443fefb6472f984a9072002d88239bc8b66602a 100644 (file)
@@ -52,14 +52,14 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
        tick *= CONFIG_SYS_HZ;
-       do_div(tick, gd->timer_rate_hz);
+       do_div(tick, gd->arch.timer_rate_hz);
 
        return tick;
 }
 
 static inline unsigned long long usec_to_tick(unsigned long long usec)
 {
-       usec *= gd->timer_rate_hz;
+       usec *= gd->arch.timer_rate_hz;
        do_div(usec, 1000000);
 
        return usec;
@@ -79,8 +79,8 @@ int timer_init(void)
        /* Enable PITC */
        writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
 
-       gd->timer_rate_hz = gd->mck_rate_hz / 16;
-       gd->tbu = gd->tbl = 0;
+       gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+       gd->arch.tbu = gd->arch.tbl = 0;
 
        return 0;
 }
@@ -95,10 +95,10 @@ unsigned long long get_ticks(void)
        ulong now = readl(&pit->piir);
 
        /* increment tbu if tbl has rolled over */
-       if (now < gd->tbl)
-               gd->tbu++;
-       gd->tbl = now;
-       return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+       if (now < gd->arch.tbl)
+               gd->arch.tbu++;
+       gd->arch.tbl = now;
+       return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
 }
 
 void __udelay(unsigned long usec)
@@ -132,5 +132,5 @@ ulong get_timer(ulong base)
  */
 ulong get_tbclk(void)
 {
-       return gd->timer_rate_hz;
+       return gd->arch.timer_rate_hz;
 }
index 93c9e60b792626618d20c8f8002d83bc7348342d..4142932d08eaa830c56434ba1161dcf43e1ef5d9 100644 (file)
@@ -60,8 +60,8 @@ int timer_init(void)
        writel(0x0, &timer->tim34);
        writel(TIMER_LOAD_VAL, &timer->prd34);
        writel(2 << 22, &timer->tcr);
-       gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
-       gd->timer_reset_value = 0;
+       gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+       gd->arch.timer_reset_value = 0;
 
        return(0);
 }
@@ -74,27 +74,28 @@ unsigned long long get_ticks(void)
        unsigned long now = readl(&timer->tim34);
 
        /* increment tbu if tbl has rolled over */
-       if (now < gd->tbl)
-               gd->tbu++;
-       gd->tbl = now;
+       if (now < gd->arch.tbl)
+               gd->arch.tbu++;
+       gd->arch.tbl = now;
 
-       return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+       return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
 }
 
 ulong get_timer(ulong base)
 {
        unsigned long long timer_diff;
 
-       timer_diff = get_ticks() - gd->timer_reset_value;
+       timer_diff = get_ticks() - gd->arch.timer_reset_value;
 
-       return lldiv(timer_diff, (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
+       return lldiv(timer_diff,
+                    (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
 }
 
 void __udelay(unsigned long usec)
 {
        unsigned long long endtime;
 
-       endtime = lldiv((unsigned long long)usec * gd->timer_rate_hz,
+       endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
                        1000000UL);
        endtime += get_ticks();
 
@@ -108,7 +109,7 @@ void __udelay(unsigned long usec)
  */
 ulong get_tbclk(void)
 {
-       return gd->timer_rate_hz;
+       return gd->arch.timer_rate_hz;
 }
 
 #ifdef CONFIG_HW_WATCHDOG
index f5d01603977a01affebaacfc87dd67da986d3109..85e81e3f4438e0443db0317836a96a41fa6ceb39 100644 (file)
@@ -86,8 +86,8 @@ struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 ulong get_timer_masked(void)
 {
index 75314b91b3fbd0f5fab4c690fdffee8b69d7665d..c6486c13eb26acd00dcf488dbbcde1fc503757f0 100644 (file)
@@ -35,8 +35,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
index b9914186b19bad91dbd9202eefc54b38573cbcf1..679273b2b4dc66828726877ffb9bb74b91da1ca8 100644 (file)
@@ -229,9 +229,9 @@ int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #else
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
 #endif
 #endif
        return 0;
index 4dc4041c08dd15008bee089720e4d2c3c81489e4..f8bebccd63d4c844351cc82b6e0188dd64743763 100644 (file)
@@ -44,8 +44,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp      (gd->tbl)
-#define lastinc                (gd->lastinc)
+#define timestamp      (gd->arch.tbl)
+#define lastinc                (gd->arch.lastinc)
 
 /*
  * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
index a5dd68425aafd4fc1a6cc14f43b13d278ca23073..07e132ad2f7d957fc2230d7c850fdfb4030ad87a 100644 (file)
@@ -45,8 +45,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp      (gd->tbl)
-#define lastinc                (gd->lastinc)
+#define timestamp      (gd->arch.tbl)
+#define lastinc                (gd->arch.lastinc)
 
 /*
  * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
index 4ed75e604ca8b589ffb0592cff24c0b3a0d866c9..373841180ff84af4811695674170f278c5846c76 100644 (file)
@@ -36,8 +36,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp (gd->tbl)
-#define lastdec (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastdec (gd->arch.lastinc)
 
 /*
  * This driver uses 1kHz clock source.
index 390c9c8abb5fd40bb0503eb9060af717e1c3f6df..34ec7b2b1ccc6f6a7b24dcb7378978f07c250399 100644 (file)
@@ -44,8 +44,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 int timer_init (void)
 {
index 8a8aaf15d901b440f4437afa56efb68233586866..f7233512cd78ef7db6f7cbaf762d95fa7815daa5 100644 (file)
@@ -92,8 +92,8 @@ static inline ulong read_timer(void)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 ulong get_timer_masked(void)
 {
index 28aadada7033bad0e82a9a4b7a2e2e34198b4935..2d9ddbad24001ae6a546cb03ff4edb30d3512d66 100644 (file)
@@ -60,7 +60,7 @@ struct panthtmr_registers {
 #define        COUNT_RD_REQ            0x1
 
 DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
 
 /*
  * For preventing risk of instability in reading counter value,
@@ -90,16 +90,16 @@ ulong get_timer_masked(void)
 {
        ulong now = read_timer();
 
-       if (now >= gd->tbl) {
+       if (now >= gd->arch.tbl) {
                /* normal mode */
-               gd->tbu += now - gd->tbl;
+               gd->arch.tbu += now - gd->arch.tbl;
        } else {
                /* we have an overflow ... */
-               gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+               gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
        }
-       gd->tbl = now;
+       gd->arch.tbl = now;
 
-       return gd->tbu;
+       return gd->arch.tbu;
 }
 
 ulong get_timer(ulong base)
@@ -144,9 +144,9 @@ int timer_init(void)
 
        /* Enable timer 0 */
        writel(0x1, &panthtimers->cer);
-       /* init the gd->tbu and gd->tbl value */
-       gd->tbl = read_timer();
-       gd->tbu = 0;
+       /* init the gd->arch.tbu and gd->arch.tbl value */
+       gd->arch.tbl = read_timer();
+       gd->arch.tbu = 0;
 
        return 0;
 }
index 1dc78600c2b17d5d688ab4fb10b8f434cff17445..de4ba7b21345cfbc85abb178e118250c681be432 100644 (file)
@@ -38,8 +38,8 @@ static struct misc_regs *const misc_regs_p =
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 int timer_init(void)
 {
index f58e151662086694cd7f4192bcd9d2069fe18e80..b36d6d93a57a865e36fbb301a859c59c03d93eff 100644 (file)
@@ -44,8 +44,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
 
 #define TIMER_ENABLE   (1 << 7)
 #define TIMER_MODE_MSK (1 << 6)
index 9f8bc934470bf2129459e1d6934997f98ca93218..36bea5f94c118c8adeb69e83eb99800107c41921 100644 (file)
@@ -56,8 +56,9 @@ int timer_init(void)
                &timer_base->tclr);
 
        /* reset time, capture current incrementer value time */
-       gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-       gd->tbl = 0;            /* start "advancing" time stamp from 0 */
+       gd->arch.lastinc = readl(&timer_base->tcrr) /
+                                       (TIMER_CLOCK / CONFIG_SYS_HZ);
+       gd->arch.tbl = 0;       /* start "advancing" time stamp from 0 */
 
        return 0;
 }
@@ -91,14 +92,15 @@ ulong get_timer_masked(void)
        /* current tick value */
        ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
 
-       if (now >= gd->lastinc) /* normal mode (non roll) */
+       if (now >= gd->arch.lastinc) {  /* normal mode (non roll) */
                /* move stamp fordward with absoulte diff ticks */
-               gd->tbl += (now - gd->lastinc);
-       else    /* we have rollover of incrementer */
-               gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
-                            - gd->lastinc) + now;
-       gd->lastinc = now;
-       return gd->tbl;
+               gd->arch.tbl += (now - gd->arch.lastinc);
+       } else {        /* we have rollover of incrementer */
+               gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
+                               CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
+       }
+       gd->arch.lastinc = now;
+       return gd->arch.tbl;
 }
 
 /*
index bb0e795e66823d4963acd309ebbdd3e67bf7d4a4..e78c716d3fa4e88953f05c31daac6a4e1f34eefe 100644 (file)
@@ -105,8 +105,8 @@ void reset_timer_masked(void)
        struct s5p_timer *const timer = s5p_get_base_timer();
 
        /* reset time */
-       gd->lastinc = readl(&timer->tcnto4);
-       gd->tbl = 0;
+       gd->arch.lastinc = readl(&timer->tcnto4);
+       gd->arch.tbl = 0;
 }
 
 unsigned long get_timer_masked(void)
@@ -123,14 +123,14 @@ unsigned long get_current_tick(void)
        unsigned long now = readl(&timer->tcnto4);
        unsigned long count_value = readl(&timer->tcntb4);
 
-       if (gd->lastinc >= now)
-               gd->tbl += gd->lastinc - now;
+       if (gd->arch.lastinc >= now)
+               gd->arch.tbl += gd->arch.lastinc - now;
        else
-               gd->tbl += gd->lastinc + count_value - now;
+               gd->arch.tbl += gd->arch.lastinc + count_value - now;
 
-       gd->lastinc = now;
+       gd->arch.lastinc = now;
 
-       return gd->tbl;
+       return gd->arch.tbl;
 }
 
 /*
index 321e9b4181357ab797cbda4433e4bc19941804ba..efa28c2ae9440e1352676ebd32942cf81af97395 100644 (file)
@@ -80,16 +80,16 @@ ulong get_timer_masked(void)
 {
        /* current tick value */
        ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
-       if (gd->lastinc >= now) {
+       if (gd->arch.lastinc >= now) {
                /* normal mode (non roll) */
                /* move stamp forward with absolute diff ticks */
-               gd->tbl += gd->lastinc - now;
+               gd->arch.tbl += gd->arch.lastinc - now;
        } else {
                /* we have overflow of the count down timer */
-               gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+               gd->arch.tbl += TIMER_LOAD_VAL - gd->arch.lastinc + now;
        }
-       gd->lastinc = now;
-       return gd->tbl;
+       gd->arch.lastinc = now;
+       return gd->arch.tbl;
 }
 
 /*
@@ -98,7 +98,8 @@ ulong get_timer_masked(void)
 void reset_timer(void)
 {
        /* capture current decrementer value time */
-       gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+       gd->arch.lastinc = read_timer() /
+                               (CONFIG_TIMER_CLOCK_KHZ / CONFIG_SYS_HZ);
        /* start "advancing" time stamp from 0 */
-       gd->tbl = 0;
+       gd->arch.tbl = 0;
 }
index 79aad9983a5982ab0d7cc406a21bcf1afe174c6a..a4b88f3815c096aa1db369918f02585c1d0a3e31 100644 (file)
@@ -100,12 +100,14 @@ ulong get_timer_masked(void)
        /* current tick value */
        ulong now = TICKS_TO_HZ(READ_TIMER());
 
-       if (now >= gd->lastinc) /* normal (non rollover) */
-               gd->tbl += (now - gd->lastinc);
-       else                    /* rollover */
-               gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now;
-       gd->lastinc = now;
-       return gd->tbl;
+       if (now >= gd->arch.lastinc) {  /* normal (non rollover) */
+               gd->arch.tbl += (now - gd->arch.lastinc);
+       } else {                        /* rollover */
+               gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) -
+                                       gd->arch.lastinc) + now;
+       }
+       gd->arch.lastinc = now;
+       return gd->arch.tbl;
 }
 
 /* Delay x useconds */
@@ -132,7 +134,7 @@ ulong get_timer(ulong base)
 /*
  * Emulation of Power architecture long long timebase.
  *
- * TODO: Support gd->tbu for real long long timebase.
+ * TODO: Support gd->arch.tbu for real long long timebase.
  */
 unsigned long long get_ticks(void)
 {
index 323e7b5a49bd0bc3f5ffec7ee50f58f75c4d3b12..45b405a4ba2a764831615a24ecd86d2cb6214466 100644 (file)
@@ -83,9 +83,9 @@ int timer_init(void)
                                                                emask);
 
        /* Reset time */
-       gd->lastinc = readl(&timer_base->counter) /
+       gd->arch.lastinc = readl(&timer_base->counter) /
                                        (TIMER_TICK_HZ / CONFIG_SYS_HZ);
-       gd->tbl = 0;
+       gd->arch.tbl = 0;
 
        return 0;
 }
@@ -100,16 +100,16 @@ ulong get_timer_masked(void)
 
        now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
 
-       if (gd->lastinc >= now) {
+       if (gd->arch.lastinc >= now) {
                /* Normal mode */
-               gd->tbl += gd->lastinc - now;
+               gd->arch.tbl += gd->arch.lastinc - now;
        } else {
                /* We have an overflow ... */
-               gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now;
+               gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now;
        }
-       gd->lastinc = now;
+       gd->arch.lastinc = now;
 
-       return gd->tbl;
+       return gd->arch.tbl;
 }
 
 void __udelay(unsigned long usec)
index 087ddf80ef7c9f28ea62c3ca4d7a14530edffa22..663d9890899603b47b52a41d3139b312b5ad96d8 100644 (file)
@@ -70,23 +70,23 @@ unsigned long long get_ticks(void)
 
        if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
                /* rollover of timestamp timer register */
-               gd->timestamp += (0xFFFFFFFF - gd->lastinc) + now + 1;
+               gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1;
                writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
        } else {
                /* move stamp forward with absolut diff ticks */
-               gd->timestamp += (now - gd->lastinc);
+               gd->arch.timestamp += (now - gd->arch.lastinc);
        }
-       gd->lastinc = now;
-       return gd->timestamp;
+       gd->arch.lastinc = now;
+       return gd->arch.timestamp;
 }
 
 
 void reset_timer_masked(void)
 {
        /* capture current timestamp counter */
-       gd->lastinc = readl(IXP425_OSTS_B);
+       gd->arch.lastinc = readl(IXP425_OSTS_B);
        /* start "advancing" time stamp from 0 */
-       gd->timestamp = 0;
+       gd->arch.timestamp = 0;
 }
 
 ulong get_timer_masked(void)
index a8f7462c1b75aca4a9687852eec274a845a706c2..212b31eb6853f7d4182ef2b2b745dfe37abf8989 100644 (file)
@@ -31,8 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define        TIMER_LOAD_VAL  0xffffffff
 
-#define        timestamp       (gd->tbl)
-#define        lastinc         (gd->lastinc)
+#define        timestamp       (gd->arch.tbl)
+#define        lastinc         (gd->arch.lastinc)
 
 #if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define        TIMER_FREQ_HZ   3250000
index 034ea5ad28847eb1d9fc44fd40c11585c97364f5..51902e9544bc6a6d319482a355e636adbeb0bad8 100644 (file)
@@ -75,14 +75,14 @@ ulong get_timer_masked(void)
        /* current tick value */
        now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ);
 
-       if (now >= gd->lastinc) /* normal mode (non roll) */
+       if (now >= gd->arch.lastinc)    /* normal mode (non roll) */
                /* move stamp forward with absolute diff ticks */
-               gd->tbl += (now - gd->lastinc);
+               gd->arch.tbl += (now - gd->arch.lastinc);
        else    /* we have rollover of incrementer */
-               gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
-                               - gd->lastinc) + now;
-       gd->lastinc = now;
-       return gd->tbl;
+               gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
+                               - gd->arch.lastinc) + now;
+       gd->arch.lastinc = now;
+       return gd->arch.tbl;
 }
 
 /*
index fbf4de3b30042d0e5d2f608681888555e41add06..638ee1aa75cbcb81ab2b26572cae6dd48f236108 100644 (file)
@@ -37,23 +37,23 @@ int get_clocks(void)
 #ifdef CONFIG_FSL_ESDHC
 #ifdef CONFIG_FSL_USDHC
 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 #else
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 #endif
 #else
 #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 #else
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 #endif
 #endif
 #endif
index b021903d9b443bca0d74202d8997ed94b1509adf..ab37d641ece97c82f230ad9e6a89511fea8fddff 100644 (file)
@@ -48,8 +48,8 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp (gd->tbl)
-#define lastinc (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastinc (gd->arch.lastinc)
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
index 1e8522b83980a4eb32e94133e19777d3c52f796d..d4852a38c19c3eb25b960626f03eaad9d55fc39f 100644 (file)
 static inline unsigned long get_cpu_clk_rate(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->cpu_clk_rate_hz;
+       return gd->arch.cpu_clk_rate_hz;
 }
 
 static inline unsigned long get_main_clk_rate(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->main_clk_rate_hz;
+       return gd->arch.main_clk_rate_hz;
 }
 
 static inline unsigned long get_mck_clk_rate(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->mck_rate_hz;
+       return gd->arch.mck_rate_hz;
 }
 
 static inline unsigned long get_plla_clk_rate(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->plla_rate_hz;
+       return gd->arch.plla_rate_hz;
 }
 
 static inline unsigned long get_pllb_clk_rate(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->pllb_rate_hz;
+       return gd->arch.pllb_rate_hz;
 }
 
 static inline u32 get_pllb_init(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-       return gd->at91_pllb_usb_init;
+       return gd->arch.at91_pllb_usb_init;
 }
 
 static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
index 41a26edfb54d597d905d591a565053f8b70b0966..37ac0daa70b05c1aedfcaf6a6251117e28ab6ead 100644 (file)
 
 #ifndef        __ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory which is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
 
-typedef        struct  global_data {
-       bd_t            *bd;
-       unsigned long   flags;
-       unsigned int    baudrate;
-       unsigned long   have_console;   /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-       unsigned long   precon_buf_idx; /* Pre-Console buffer index */
-#endif
-       unsigned long   env_addr;       /* Address  of Environment struct */
-       unsigned long   env_valid;      /* Checksum of Environment valid? */
-       unsigned long   fb_base;        /* base address of frame buffer */
-#ifdef CONFIG_FSL_ESDHC
-       unsigned long   sdhc_clk;
+/* Architecture-specific global data */
+struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC)
+       u32 sdhc_clk;
 #endif
 #ifdef CONFIG_AT91FAMILY
        /* "static data" needed by at91's clock.c */
@@ -54,38 +38,22 @@ typedef     struct  global_data {
        unsigned long   pllb_rate_hz;
        unsigned long   at91_pllb_usb_init;
 #endif
-#ifdef CONFIG_ARM
        /* "static data" needed by most of timer.c on ARM platforms */
-       unsigned long   timer_rate_hz;
-       unsigned long   tbl;
-       unsigned long   tbu;
-       unsigned long long      timer_reset_value;
-       unsigned long   lastinc;
-#endif
+       unsigned long timer_rate_hz;
+       unsigned long tbu;
+       unsigned long tbl;
+       unsigned long lastinc;
+       unsigned long long timer_reset_value;
 #ifdef CONFIG_IXP425
-       unsigned long   timestamp;
+       unsigned long timestamp;
 #endif
-       unsigned long   relocaddr;      /* Start address of U-Boot in RAM */
-       phys_size_t     ram_size;       /* RAM size */
-       unsigned long   mon_len;        /* monitor len */
-       unsigned long   irq_sp;         /* irq stack pointer */
-       unsigned long   start_addr_sp;  /* start_addr_stackpointer */
-       unsigned long   reloc_off;
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-       unsigned long   tlb_addr;
-       unsigned long   tlb_size;
-#endif
-       const void      *fdt_blob;      /* Our device tree, NULL if none */
-       void            **jt;           /* jump table */
-       char            env_buf[32];    /* buffer for getenv() before reloc. */
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-       unsigned long   post_log_word; /* Record POST activities */
-       unsigned long   post_log_res; /* success of POST test */
-       unsigned long   post_init_f_time; /* When post_init_f started */
+       unsigned long tlb_addr;
+       unsigned long tlb_size;
 #endif
-} gd_t;
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
 
index 9f861ccaf6693364f76f78d9c66fbb7c605bcce5..162e2cc86385df0f7489eef0ae2ac00c3be12fc9 100644 (file)
@@ -355,14 +355,14 @@ void board_init_f(ulong bootflag)
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
        /* reserve TLB table */
-       gd->tlb_size = 4096 * 4;
-       addr -= gd->tlb_size;
+       gd->arch.tlb_size = 4096 * 4;
+       addr -= gd->arch.tlb_size;
 
        /* round down to next 64 kB limit */
        addr &= ~(0x10000 - 1);
 
-       gd->tlb_addr = addr;
-       debug("TLB table from %08lx to %08lx\n", addr, addr + gd->tlb_size);
+       gd->arch.tlb_addr = addr;
+       debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);
 #endif
 
        /* round down to next 4 kB limit */
index 1bd273085685ba9c4d424e7ac761a6b8bde5828d..f3b30c57a37cd03b0c368dcd73aff49fc0b29478 100644 (file)
@@ -30,7 +30,6 @@
 #include <image.h>
 #include <u-boot/zlib.h>
 #include <asm/byteorder.h>
-#include <fdt.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/bootm.h>
index 1cab27c22629fe5bd034d8278efa8d09e36f7378..b6e5e95530b3793f0be70289eb53ed7207cb305b 100644 (file)
@@ -46,7 +46,7 @@ static void cp_delay (void)
 
 void set_section_dcache(int section, enum dcache_option option)
 {
-       u32 *page_table = (u32 *)gd->tlb_addr;
+       u32 *page_table = (u32 *)gd->arch.tlb_addr;
        u32 value;
 
        value = (section << MMU_SECTION_SHIFT) | (3 << 10);
@@ -65,7 +65,7 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop)
 void mmu_set_region_dcache_behaviour(u32 start, int size,
                                     enum dcache_option option)
 {
-       u32 *page_table = (u32 *)gd->tlb_addr;
+       u32 *page_table = (u32 *)gd->arch.tlb_addr;
        u32 upto, end;
 
        end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
@@ -111,7 +111,7 @@ static inline void mmu_setup(void)
 
        /* Copy the page table address to cp15 */
        asm volatile("mcr p15, 0, %0, c2, c0, 0"
-                    : : "r" (gd->tlb_addr) : "memory");
+                    : : "r" (gd->arch.tlb_addr) : "memory");
        /* Set the access control to all-supervisor */
        asm volatile("mcr p15, 0, %0, c3, c0, 0"
                     : : "r" (~0));
index 790783767f12a4430c1a1707e17620095ad4850a..9d82ca4ad231bce6a22c905b4c58206834959a5c 100644 (file)
@@ -47,7 +47,7 @@ int cpu_init(void)
 {
        extern void _evba(void);
 
-       gd->cpu_hz = CONFIG_SYS_OSC0_HZ;
+       gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ;
 
        /* TODO: Move somewhere else, but needs to be run before we
         * increase the clock frequency. */
@@ -59,7 +59,7 @@ int cpu_init(void)
        clk_init();
 
        /* Update the CPU speed according to the PLL configuration */
-       gd->cpu_hz = get_cpu_clk_rate();
+       gd->arch.cpu_hz = get_cpu_clk_rate();
 
        /* Set up the exception handler table and enable exceptions */
        sysreg_write(EVBA, (unsigned long)&_evba);
index b21ef1f928daaf891d8d749ee158b44fd33bb359..828fc00a49d3b5af488e9cd20ce709c39f4bef03 100644 (file)
@@ -112,11 +112,11 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
        printf("CPU Mode: %s\n", cpu_modes[mode]);
 
        /* Avoid exception loops */
-       if (regs->sp < (gd->stack_end - CONFIG_STACKSIZE)
-                       || regs->sp >= gd->stack_end)
+       if (regs->sp < (gd->arch.stack_end - CONFIG_STACKSIZE)
+                       || regs->sp >= gd->arch.stack_end)
                printf("\nStack pointer seems bogus, won't do stack dump\n");
        else
-               dump_mem("\nStack: ", regs->sp, gd->stack_end);
+               dump_mem("\nStack: ", regs->sp, gd->arch.stack_end);
 
        panic("Unhandled exception\n");
 }
index 49a00f1c8ca7e4b6e57edb32844dc1f348c0dac1..d87c6e11665daa9ffe0a486a03ec769e7ff77f38 100644 (file)
@@ -46,7 +46,7 @@ static unsigned long tb_factor;
 
 unsigned long get_tbclk(void)
 {
-       return gd->cpu_hz;
+       return gd->arch.cpu_hz;
 }
 
 unsigned long long get_ticks(void)
@@ -115,8 +115,8 @@ int timer_init(void)
        sysreg_write(COUNT, 0);
 
        tmp = (u64)CONFIG_SYS_HZ << 32;
-       tmp += gd->cpu_hz / 2;
-       do_div(tmp, gd->cpu_hz);
+       tmp += gd->arch.cpu_hz / 2;
+       do_div(tmp, gd->arch.cpu_hz);
        tb_factor = (u32)tmp;
 
        if (set_interrupt_handler(0, &timer_interrupt_handler, 3))
index bf661e23be93d9384f03618aa34e1e3c1a279504..a71f199b750f45f1ba4025d8a9c9838f094bbc1f 100644 (file)
 #ifndef __ASM_GLOBAL_DATA_H__
 #define __ASM_GLOBAL_DATA_H__
 
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef        struct  global_data {
-       bd_t            *bd;
-       unsigned long   flags;
-       unsigned int    baudrate;
-       unsigned long   stack_end;      /* highest stack address */
-       unsigned long   have_console;   /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-       unsigned long   precon_buf_idx; /* Pre-Console buffer index */
-#endif
-       unsigned long   reloc_off;      /* Relocation Offset */
-       unsigned long   env_addr;       /* Address of env struct */
-       unsigned long   env_valid;      /* Checksum of env valid? */
-       unsigned long   cpu_hz;         /* cpu core clock frequency */
-#if defined(CONFIG_LCD)
-       void            *fb_base;       /* framebuffer address */
-#endif
-       void            **jt;           /* jump table */
-       char            env_buf[32];    /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+       unsigned long stack_end;        /* highest stack address */
+       unsigned long cpu_hz;           /* cpu core clock frequency */
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
 
index e3287c486b1b985d462e1085b20cb09b8db781b7..d3c8cb76dde081661ad0916641da1cd5fc6d363a 100644 (file)
@@ -231,7 +231,7 @@ void board_init_f(ulong board_type)
 
        /* And finally, a new, bigger stack. */
        new_sp = (unsigned long *)addr;
-       gd->stack_end = addr;
+       gd->arch.stack_end = addr;
        *(--new_sp) = 0;
        *(--new_sp) = 0;
 
index 74ebeca058a7ed3f3a268a95cd0625f4da9388cd..87f3f9c35d3b966c5366351c60d06ebc1b72c825 100644 (file)
@@ -109,7 +109,7 @@ static struct tag *setup_clock_tags(struct tag *params)
        params->hdr.size = tag_size(tag_clock);
        params->u.clock.clock_id = ACLOCK_BOOTCPU;
        params->u.clock.clock_flags = 0;
-       params->u.clock.clock_hz = gd->cpu_hz;
+       params->u.clock.clock_hz = gd->arch.cpu_hz;
 
 #ifdef CONFIG_AT32AP7000
        /*
index d91e5a40d314f2dd96b8cf28739bf798e7a7a30b..c2c4d4d41dfd7d699e5f1a3c7e8789ef6c30bec8 100644 (file)
 
 #include <asm/u-boot.h>
 
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-typedef struct global_data {
-       bd_t *bd;
-       unsigned long flags;
-       unsigned long board_type;
-       unsigned int baudrate;
-       unsigned long have_console;     /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-       unsigned long   precon_buf_idx; /* Pre-Console buffer index */
-#endif
-       phys_size_t ram_size;           /* RAM size */
-       unsigned long env_addr; /* Address  of Environment struct */
-       unsigned long env_valid;        /* Checksum of Environment valid? */
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-       unsigned long post_log_word;    /* Record POST activities */
-       unsigned long post_log_res;     /* success of POST test */
-       unsigned long post_init_f_time; /* When post_init_f started */
-#endif
-
-       void    **jt;                   /* jump table */
-       char    env_buf[32];            /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("P3")
 
index 3a0ab9746b457215b6bcab033993e3a4d7e61ba9..705bd4428cb7be5366522d7618727caadc6e58b3 100644 (file)
@@ -68,10 +68,10 @@ int checkcpu(void)
                printf("       CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
                       strmhz(buf1, gd->cpu_clk),
                       strmhz(buf2, gd->bus_clk),
-                      strmhz(buf3, gd->flb_clk));
+                      strmhz(buf3, gd->arch.flb_clk));
                printf("       INP CLK %s MHz VCO CLK %s MHz\n",
-                      strmhz(buf1, gd->inp_clk),
-                      strmhz(buf2, gd->vco_clk));
+                      strmhz(buf1, gd->arch.inp_clk),
+                      strmhz(buf2, gd->arch.vco_clk));
        }
 
        return 0;
index b94a9eda48266e30e6d4bab3bcb9a81bd589ac27..98f554aa7f5099d409271b18cac05deec43dc361 100644 (file)
@@ -114,28 +114,28 @@ int get_clocks(void)
                            ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
                            CONFIG_SYS_INPUT_CLKSRC;
                }
-               gd->vco_clk = vco;      /* Vco clock */
+               gd->arch.vco_clk = vco; /* Vco clock */
        } else if (bootmode == 3) {
                /* serial mode */
                vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-               gd->vco_clk = vco;      /* Vco clock */
+               gd->arch.vco_clk = vco; /* Vco clock */
        }
 
        if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
                /* Limp mode */
        } else {
-               gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;  /* Input clock */
+               gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
 
                temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
                gd->cpu_clk = vco / temp;       /* cpu clock */
 
                temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
-               gd->flb_clk = vco / temp;       /* flexbus clock */
-               gd->bus_clk = gd->flb_clk;
+               gd->arch.flb_clk = vco / temp;  /* flexbus clock */
+               gd->bus_clk = gd->arch.flb_clk;
        }
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
        return (0);
index e2a6ae3a58fd5a9a0ce96b5afaba8a07aa490ad6..ae462579e27d61d147d9d18eb6995794b817a721 100644 (file)
@@ -48,7 +48,7 @@ int get_clocks(void)
        gd->cpu_clk = (gd->bus_clk * 2);
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
        return (0);
index 70abed25c4171fa4f7eae52bfed05eb007a39d1a..ba7dbaa1cfc34a1cd4bb3dad218d1deec893e6e2 100644 (file)
@@ -91,9 +91,9 @@ int get_clocks (void)
 #endif
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #ifdef CONFIG_SYS_I2C2_OFFSET
-       gd->i2c2_clk = gd->bus_clk;
+       gd->arch.i2c2_clk = gd->bus_clk;
 #endif
 #endif
 
index cfdcc8b80770d1062d3282e4334531ab2d40886d..8efb451dc133b8659873cc84d3f4b7324e90eec9 100644 (file)
@@ -271,7 +271,7 @@ int get_clocks(void)
        gd->cpu_clk = (gd->bus_clk * 3);
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
        return (0);
index b612cdaea1ac28975184fbb090c79c40f69d7ab6..08930f48d7be4d0dc8605a4b962cfb4471cc7fab 100644 (file)
@@ -101,16 +101,16 @@ int checkcpu(void)
                printf("       CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
                       strmhz(buf1, gd->cpu_clk),
                       strmhz(buf2, gd->bus_clk),
-                      strmhz(buf3, gd->flb_clk));
+                      strmhz(buf3, gd->arch.flb_clk));
 #ifdef CONFIG_PCI
                printf("       PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
                       strmhz(buf1, gd->pci_clk),
-                      strmhz(buf2, gd->inp_clk),
-                      strmhz(buf3, gd->vco_clk));
+                      strmhz(buf2, gd->arch.inp_clk),
+                      strmhz(buf3, gd->arch.vco_clk));
 #else
                printf("       INP CLK %s MHz VCO CLK %s MHz\n",
-                      strmhz(buf1, gd->inp_clk),
-                      strmhz(buf2, gd->vco_clk));
+                      strmhz(buf1, gd->arch.inp_clk),
+                      strmhz(buf2, gd->arch.vco_clk));
 #endif
        }
 
index 55d1c488a317f5e11e803fb2a2a2f7901062c93d..aa73e1f0252e33f1b9b9d95b7cf0e35fb06f15b7 100644 (file)
@@ -233,7 +233,7 @@ void setup_5445x_clocks(void)
 
                        out_be32(&pll->pcr, pcrvalue);
                }
-               gd->vco_clk = vco;      /* Vco clock */
+               gd->arch.vco_clk = vco; /* Vco clock */
        } else if (bootmode == 2) {
                /* Normal mode */
                vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
@@ -244,17 +244,17 @@ void setup_5445x_clocks(void)
                        out_be32(&pll->pcr, pcrvalue);
                        vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
                }
-               gd->vco_clk = vco;      /* Vco clock */
+               gd->arch.vco_clk = vco; /* Vco clock */
        } else if (bootmode == 3) {
                /* serial mode */
                vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-               gd->vco_clk = vco;      /* Vco clock */
+               gd->arch.vco_clk = vco; /* Vco clock */
        }
 
        if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
                /* Limp mode */
        } else {
-               gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;  /* Input clock */
+               gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
 
                temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
                gd->cpu_clk = vco / temp;       /* cpu clock */
@@ -263,7 +263,7 @@ void setup_5445x_clocks(void)
                gd->bus_clk = vco / temp;       /* bus clock */
 
                temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
-               gd->flb_clk = vco / temp;       /* FlexBus clock */
+               gd->arch.flb_clk = vco / temp;  /* FlexBus clock */
 
 #ifdef CONFIG_PCI
                if (bPci) {
@@ -274,7 +274,7 @@ void setup_5445x_clocks(void)
        }
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 }
 #endif
@@ -290,7 +290,7 @@ int get_clocks(void)
 #endif
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
        return (0);
index 31130b54115203dfc262aafba2948ed8275934a3..41aae9d9eb27c51ed3da1629683a8df2a6e89868 100644 (file)
@@ -41,7 +41,7 @@ int get_clocks(void)
        gd->cpu_clk = (gd->bus_clk * 2);
 
 #ifdef CONFIG_FSL_I2C
-       gd->i2c1_clk = gd->bus_clk;
+       gd->arch.i2c1_clk = gd->bus_clk;
 #endif
 
        return (0);
index 0cdb11cf99eeccce75df5d9482c3e4a066a4b3af..3ec298ff4a2be56d41cee406abfc7273d16c4fd6 100644 (file)
 
 #ifndef        __ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
 
-typedef        struct  global_data {
-       bd_t            *bd;
-       unsigned long   flags;
-       unsigned int    baudrate;
-       unsigned long   cpu_clk;        /* CPU clock in Hz!             */
-       unsigned long   bus_clk;
-#ifdef CONFIG_PCI
-       unsigned long   pci_clk;
-#endif
-#ifdef CONFIG_EXTRA_CLOCK
-       unsigned long   inp_clk;
-       unsigned long   vco_clk;
-       unsigned long   flb_clk;
-#endif
+/* Architecture-specific global data */
+struct arch_global_data {
 #ifdef CONFIG_FSL_I2C
        unsigned long   i2c1_clk;
        unsigned long   i2c2_clk;
 #endif
-       phys_size_t     ram_size;       /* RAM size */
-       unsigned long   reloc_off;      /* Relocation Offset */
-       unsigned long   reset_status;   /* reset status register at boot        */
-       unsigned long   env_addr;       /* Address  of Environment struct       */
-       unsigned long   env_valid;      /* Checksum of Environment valid?       */
-       unsigned long   have_console;   /* serial_init() was called             */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-       unsigned long   precon_buf_idx; /* Pre-Console buffer index */
-#endif
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
-       unsigned long   fb_base;        /* Base addr of framebuffer memory */
-#endif
-#ifdef CONFIG_BOARD_TYPES
-       unsigned long   board_type;
+#ifdef CONFIG_EXTRA_CLOCK
+       unsigned long inp_clk;
+       unsigned long vco_clk;
+       unsigned long flb_clk;
 #endif
-       void            **jt;           /* Standalone app jump table */
-       char            env_buf[32];    /* buffer for getenv() before reloc. */
-} gd_t;
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #if 0
 extern gd_t *global_data;
index e934cb6c25f5d49eebcb50b8535d1e74ae6f7e92..c372ae228b5572c2208daa6a07973ffc48c73e9d 100644 (file)
@@ -349,9 +349,9 @@ board_init_f (ulong bootflag)
        bd->bi_pcifreq = gd->pci_clk;           /* PCI Freq in Hz */
 #endif
 #ifdef CONFIG_EXTRA_CLOCK
-       bd->bi_inpfreq = gd->inp_clk;           /* input Freq in Hz */
-       bd->bi_vcofreq = gd->vco_clk;           /* vco Freq in Hz */
-       bd->bi_flbfreq = gd->flb_clk;           /* flexbus Freq in Hz */
+       bd->bi_inpfreq = gd->arch.inp_clk;              /* input Freq in Hz */
+       bd->bi_vcofreq = gd->arch.vco_clk;              /* vco Freq in Hz */
+       bd->bi_flbfreq = gd->arch.flb_clk;              /* flexbus Freq in Hz */
 #endif
        bd->bi_baudrate = gd->baudrate; /* Console Baudrate     */
 
index 2111c7cba27fb7a1e3e65e82c1e8cd7091f774aa..89dcef7c7e7d7b3149308194fa75591985b56e53 100644 (file)
 
 #ifndef        __ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
 
-typedef        struct  global_data {
-       bd_t            *bd;
-       unsigned long   flags;
-       unsigned int    baudrate;
-       unsigned long   have_console;   /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-       unsigned long   precon_buf_idx; /* Pre-Console buffer index */
-#endif
-       unsigned long   env_addr;       /* Address  of Environment struct */
-       const void      *fdt_blob;      /* Our device tree, NULL if none */
-       unsigned long   env_valid;      /* Checksum of Environment valid? */
-       unsigned long   fb_base;        /* base address of frame buffer */
-       void            **jt;           /* jump table */
-       char            env_buf[32];    /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r31")
 
index 7730695be4d725322cf870a17cd853127b5c54c3..8d7febd47826a3ff3b78f9e00f8170e77ec87e12 100644 (file)
@@ -29,6 +29,7 @@ SOBJS-y       +=
 
 COBJS-y        += board.o
 COBJS-y        += bootm.o
+COBJS-y        += muldi3.o
 
 SRCS   := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/microblaze/lib/muldi3.c b/arch/microblaze/lib/muldi3.c
new file mode 100644 (file)
index 0000000..76d7590
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * U-boot - muldi3.c contains routines for mult and div
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Generic function got from GNU gcc package, libgcc2.c */
+#ifndef SI_TYPE_SIZE
+#define SI_TYPE_SIZE 32
+#endif
+#define __ll_B (1L << (SI_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
+#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+#define BITS_PER_UNIT 8
+
+#if !defined(umul_ppmm)
+#define umul_ppmm(w1, w0, u, v)                                                \
+       do {                                                            \
+       USItype __x0, __x1, __x2, __x3;                                 \
+       USItype __ul, __vl, __uh, __vh;                                 \
+                                                                       \
+               __ul = __ll_lowpart(u);                                 \
+               __uh = __ll_highpart(u);                                \
+               __vl = __ll_lowpart(v);                                 \
+               __vh = __ll_highpart(v);                                \
+                                                                       \
+       __x0 = (USItype) __ul * __vl;                                   \
+       __x1 = (USItype) __ul * __vh;                                   \
+       __x2 = (USItype) __uh * __vl;                                   \
+       __x3 = (USItype) __uh * __vh;                                   \
+                                                                       \
+               __x1 += __ll_highpart(__x0); /* this can't give carry */\
+               __x1 += __x2; /* but this indeed can */                 \
+               if (__x1 < __x2) /* did we get it? */                   \
+               __x3 += __ll_B; /* yes, add it in the proper pos. */    \
+                                                                       \
+               (w1) = __x3 + __ll_highpart(__x1);                      \
+               (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0);\
+       } while (0)
+#endif
+
+#if !defined(__umulsidi3)
+#define __umulsidi3(u, v)                                              \
+       ({DIunion __w;                                                  \
+       umul_ppmm(__w.s.high, __w.s.low, u, v);         \
+       __w.ll; })
+#endif
+
+typedef unsigned int USItype __attribute__ ((mode(SI)));
+typedef int SItype __attribute__ ((mode(SI)));
+typedef int DItype __attribute__ ((mode(DI)));
+typedef int word_type __attribute__ ((mode(__word__)));
+
+struct DIstruct {
+       SItype low, high;
+};
+typedef union {
+       struct DIstruct s;
+       DItype ll;
+} DIunion;
+
+DItype __muldi3(DItype u, DItype v)
+{
+       DIunion w;
+       DIunion uu, vv;
+
+       uu.ll = u, vv.ll = v;
+       /*  panic("kernel panic for __muldi3"); */
+       w.ll = __umulsidi3(uu.s.low, vv.s.low);
+       w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+                    + (USItype) uu.s.high * (USItype) vv.s.low);
+
+       return w.ll;
+}
index 481e9844db232474da43344bac63b6f226924a97..7399701fe9656d9ef5e7e49d99f1d7974030ee11 100644 (file)
 MIPSFLAGS := -march=mips32r2
 
 PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS  += -m elf32btsmip
+else
+PLATFORM_LDFLAGS  += -m elf32ltsmip
+endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
index 9c1b2f76d09bcff61c4d617da0795b7f35b9085c..51ce914fadb642bece1aa9ae760de466e9531561 100644 (file)
@@ -258,8 +258,7 @@ reset:
 #endif
 
        /* Set up temporary stack */
-       li      t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-       la      sp, 0(t0)
+       li      sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
 
        la      t9, board_init_f
        jr      t9
@@ -280,55 +279,41 @@ reset:
 relocate_code:
        move    sp, a0                  # set new stack pointer
 
+       move    s0, a1                  # save gd in s0
+       move    s2, a2                  # save destination address in s2
+
        li      t0, CONFIG_SYS_MONITOR_BASE
+       sub     s1, s2, t0              # s1 <-- relocation offset
+
        la      t3, in_ram
        lw      t2, -12(t3)             # t2 <-- uboot_end_data
        move    t1, a2
-       move    s2, a2                  # s2 <-- destination address
 
-       /*
-        * Fix $gp:
-        *
-        * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
-        */
-       move    t6, gp
-       sub     gp, CONFIG_SYS_MONITOR_BASE
-       add     gp, a2                  # gp now adjusted
-       sub     s1, gp, t6              # s1 <-- relocation offset
+       add     gp, s1                  # adjust gp
 
        /*
         * t0 = source address
         * t1 = target address
         * t2 = source end address
         */
-
-       /*
-        * Save destination address and size for later usage in flush_cache()
-        */
-       move    s0, a1                  # save gd in s0
-       move    a0, t1                  # a0 <-- destination addr
-       sub     a1, t2, t0              # a1 <-- size
-
 1:
        lw      t3, 0(t0)
        sw      t3, 0(t1)
        addu    t0, 4
-       ble     t0, t2, 1b
+       blt     t0, t2, 1b
         addu   t1, 4
 
        /* If caches were enabled, we would have to flush them here. */
-
-       /* a0 & a1 are already set up for flush_cache(start, size) */
+       sub     a1, t1, s2              # a1 <-- size
        la      t9, flush_cache
        jalr    t9
-        nop
+        move   a0, s2                  # a0 <-- destination address
 
        /* Jump to where we've relocated ourselves */
        addi    t0, s2, in_ram - _start
        jr      t0
         nop
 
-       .word   _gp
        .word   _GLOBAL_OFFSET_TABLE_
        .word   uboot_end_data
        .word   uboot_end
@@ -343,9 +328,7 @@ in_ram:
         */
        lw      t3, -4(t0)              # t3 <-- num_got_entries
        lw      t4, -16(t0)             # t4 <-- _GLOBAL_OFFSET_TABLE_
-       lw      t5, -20(t0)             # t5 <-- _gp
-       sub     t4, t5                  # compute offset
-       add     t4, t4, gp              # t4 now holds relocated _G_O_T_
+       add     t4, s1                  # t4 now holds relocated _G_O_T_
        addi    t4, t4, 8               # skipping first two entries
        li      t2, 2
 1:
@@ -380,6 +363,8 @@ in_ram:
        /* Exception handlers */
 romReserved:
        b       romReserved
+        nop
 
 romExcHandle:
        b       romExcHandle
+        nop
index 2b8d531e73b84ef9d2e0280165ed1668dad9d318..15225945e9b89ecada9caabcbd5ef6ba6fcccda7 100644 (file)
@@ -137,8 +137,7 @@ reset:
 #endif
 
        /* Set up temporary stack */
-       dli     t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
-       dla     sp, 0(t0)
+       dli     sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
 
        dla     t9, board_init_f
        jr      t9
@@ -159,55 +158,41 @@ reset:
 relocate_code:
        move    sp, a0                  # set new stack pointer
 
+       move    s0, a1                  # save gd in s0
+       move    s2, a2                  # save destination address in s2
+
        dli     t0, CONFIG_SYS_MONITOR_BASE
+       dsub    s1, s2, t0              # s1 <-- relocation offset
+
        dla     t3, in_ram
        ld      t2, -24(t3)             # t2 <-- uboot_end_data
        move    t1, a2
-       move    s2, a2                  # s2 <-- destination address
 
-       /*
-        * Fix $gp:
-        *
-        * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
-        */
-       move    t8, gp
-       dsub    gp, CONFIG_SYS_MONITOR_BASE
-       dadd    gp, a2                  # gp now adjusted
-       dsub    s1, gp, t8              # s1 <-- relocation offset
+       dadd    gp, s1                  # adjust gp
 
        /*
         * t0 = source address
         * t1 = target address
         * t2 = source end address
         */
-
-       /*
-        * Save destination address and size for dlater usage in flush_cache()
-        */
-       move    s0, a1                  # save gd in s0
-       move    a0, t1                  # a0 <-- destination addr
-       dsub    a1, t2, t0              # a1 <-- size
-
 1:
        lw      t3, 0(t0)
        sw      t3, 0(t1)
        daddu   t0, 4
-       ble     t0, t2, 1b
+       blt     t0, t2, 1b
         daddu  t1, 4
 
        /* If caches were enabled, we would have to flush them here. */
-
-       /* a0 & a1 are already set up for flush_cache(start, size) */
+       dsub    a1, t1, s2              # a1 <-- size
        dla     t9, flush_cache
        jalr    t9
-        nop
+        move   a0, s2                  # a0 <-- destination address
 
        /* Jump to where we've relocated ourselves */
        daddi   t0, s2, in_ram - _start
        jr      t0
         nop
 
-       .dword  _gp
        .dword  _GLOBAL_OFFSET_TABLE_
        .dword  uboot_end_data
        .dword  uboot_end
@@ -222,9 +207,7 @@ in_ram:
         */
        ld      t3, -8(t0)              # t3 <-- num_got_entries
        ld      t8, -32(t0)             # t8 <-- _GLOBAL_OFFSET_TABLE_
-       ld      t9, -40(t0)             # t9 <-- _gp
-       dsub    t8, t9                  # compute offset
-       dadd    t8, t8, gp              # t8 now holds relocated _G_O_T_
+       dadd    t8, s1                  # t8 now holds relocated _G_O_T_
        daddi   t8, t8, 16              # skipping first two entries
        dli     t2, 2
 1:
@@ -259,3 +242,4 @@ in_ram:
        /* Exception handlers */
 romReserved:
        b       romReserved
+        nop
similarity index 73%
rename from board/micronas/vct/u-boot.lds
rename to arch/mips/cpu/u-boot.lds
index 2ce8d0e158f4cb29b5d05ebc4e762000b26f92f4..37c9d2364aab9a21fd7d8f8f673814ca5576021b 100644 (file)
  * MA 02111-1307 USA
  */
 
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+#if defined(CONFIG_64BIT)
+#define PTR_COUNT_SHIFT        3
+#else
+#define PTR_COUNT_SHIFT        2
+#endif
+
 OUTPUT_ARCH(mips)
 ENTRY(_start)
 SECTIONS
@@ -29,41 +34,51 @@ SECTIONS
        . = 0x00000000;
 
        . = ALIGN(4);
-       .text       :
-       {
-         *(.text*)
+       .text : {
+               *(.text*)
        }
 
        . = ALIGN(4);
-       .rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+       .rodata : {
+               *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+       }
 
        . = ALIGN(4);
-       .data  : { *(.data*) }
+       .data : {
+               *(.data*)
+       }
 
        . = .;
        _gp = ALIGN(16) + 0x7ff0;
 
        .got : {
-         __got_start = .;
-         *(.got)
-         __got_end = .;
+               __got_start = .;
+               *(.got)
+               __got_end = .;
        }
 
        . = ALIGN(4);
-       .sdata  : { *(.sdata*) }
+       .sdata : {
+               *(.sdata*)
+       }
 
        . = ALIGN(4);
        .u_boot_list : {
                #include <u-boot.lst>
        }
 
-       . = ALIGN(4);
        uboot_end_data = .;
-       num_got_entries = (__got_end - __got_start) >> 2;
+
+       num_got_entries = (__got_end - __got_start) >> PTR_COUNT_SHIFT;
 
        . = ALIGN(4);
-       .sbss (NOLOAD)  : { *(.sbss*) }
-       . = ALIGN(4);
-       .bss (NOLOAD)  : { *(.bss*) }
+       .sbss : {
+               *(.sbss*)
+       }
+
+       .bss : {
+               *(.bss*)
+               . = ALIGN(4);
+       }
        uboot_end = .;
 }
index 1536746c974b4cf4ae7294e18096b9101a2e5761..cf5fa6ab6bd5b29e2a0d629563d21a77ae12752a 100644 (file)
 #
 
 PLATFORM_CPPFLAGS += -march=mips32
+PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS  += -m elf32btsmip
+else
+PLATFORM_LDFLAGS  += -m elf32ltsmip
+endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
index 3a8280cb0ab850deaf36731e4c705f449a832866..50b7fb102172f6c32ea50b2f8b65ebf6485f9a1f 100644 (file)
@@ -64,19 +64,13 @@ relocate_code:
        move    sp, a0                  # set new stack pointer
 
        li      t0, CONFIG_SYS_MONITOR_BASE
+       sub     t6, a2, t0              # t6 <-- relocation offset
+
        la      t3, in_ram
        lw      t2, -12(t3)             # t2 <-- uboot_end_data
        move    t1, a2
 
-       /*
-        * Fix $gp:
-        *
-        * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
-        */
-       move    t6, gp
-       sub     gp, CONFIG_SYS_MONITOR_BASE
-       add     gp, a2                  # gp now adjusted
-       sub     t6, gp, t6              # t6 <-- relocation offset
+       add     gp, t6                  # adjust gp
 
        /*
         * t0 = source address
@@ -87,7 +81,7 @@ relocate_code:
        lw      t3, 0(t0)
        sw      t3, 0(t1)
        addu    t0, 4
-       ble     t0, t2, 1b
+       blt     t0, t2, 1b
         addu   t1, 4
 
        /* If caches were enabled, we would have to flush them here. */
@@ -122,7 +116,6 @@ relocate_code:
        jr      t0
         nop
 
-       .word   _gp
        .word   _GLOBAL_OFFSET_TABLE_
        .word   uboot_end_data
        .word   uboot_end
@@ -137,9 +130,7 @@ in_ram:
         */
        lw      t3, -4(t0)              # t3 <-- num_got_entries
        lw      t4, -16(t0)             # t4 <-- _GLOBAL_OFFSET_TABLE_
-       lw      t5, -20(t0)             # t5 <-- _gp
-       sub     t4, t5                  # compute offset
-       add     t4, t4, gp              # t4 now holds relocated _G_O_T_
+       add     t4, t6                  # t4 now holds relocated _G_O_T_
        addi    t4, t4, 8               # skipping first two entries
        li      t2, 2
 1:
index b6b3855ea193a6e7ecd2747da749b2d5058f9704..8c33d3ca3c339266743e53fc9bbf39c812150848 100644 (file)
@@ -34,24 +34,24 @@ static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
 void reset_timer_masked(void)
 {
        /* reset time */
-       gd->lastinc = readl(&tcu->tcnt0);
-       gd->tbl = 0;
+       gd->arch.lastinc = readl(&tcu->tcnt0);
+       gd->arch.tbl = 0;
 }
 
 ulong get_timer_masked(void)
 {
        ulong now = readl(&tcu->tcnt0);
 
-       if (gd->lastinc <= now)
-               gd->tbl += now - gd->lastinc; /* normal mode */
+       if (gd->arch.lastinc <= now)
+               gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */
        else {
                /* we have an overflow ... */
-               gd->tbl += TIMER_FDATA + now - gd->lastinc;
+               gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc;
        }
 
-       gd->lastinc = now;
+       gd->arch.lastinc = now;
 
-       return gd->tbl;
+       return gd->arch.tbl;
 }
 
 void udelay_masked(unsigned long usec)
@@ -94,8 +94,8 @@ int timer_init(void)
        writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
        writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */
 
-       gd->lastinc = 0;
-       gd->tbl = 0;
+       gd->arch.lastinc = 0;
+       gd->arch.tbl = 0;
 
        return 0;
 }
@@ -112,7 +112,7 @@ ulong get_timer(ulong base)
 
 void set_timer(ulong t)
 {
-       gd->tbl = t;
+       gd->arch.tbl = t;
 }
 
 void __udelay(unsigned long usec)
index a735a8a2c76d0cc3986dc705fd8f2e709d214008..b39737fea32cfc0c9b5e4c40b195e801ca190085 100644 (file)
 
 #include <asm/regdef.h>
 
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef        struct  global_data {
-       bd_t            *bd;
-       unsigned long   flags;
+/* Architecture-specific global data */
+struct arch_global_data {
 #ifdef CONFIG_JZSOC
        /* There are other clocks in the jz4740 */
-       unsigned long   cpu_clk;        /* CPU core clock */
-       unsigned long   sys_clk;        /* System bus clock */
-       unsigned long   per_clk;        /* Peripheral bus clock */
-       unsigned long   mem_clk;        /* Memory bus clock */
-       unsigned long   dev_clk;        /* Device clock */
-       /* "static data" needed by most of timer.c */
-       unsigned long   tbl;
-       unsigned long   lastinc;
-#endif
-       unsigned int    baudrate;
-       unsigned long   have_console;   /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-       unsigned long   precon_buf_idx; /* Pre-Console buffer index */
+       unsigned long per_clk;  /* Peripheral bus clock */
+       unsigned long dev_clk;  /* Device clock */
 #endif
-       phys_size_t     ram_size;       /* RAM size */
-       unsigned long   reloc_off;      /* Relocation Offset */
-       unsigned long   env_addr;       /* Address  of Environment struct */
-       unsigned long   env_valid;      /* Checksum of Environment valid? */
-       void            **jt;           /* jump table */
-       char            env_buf[32];    /* buffer for getenv() before reloc. */
-} gd_t;
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("k0")
 
index 80eab75e153afdfff91beeea87152291edf54426..3864c804c0500b2322fe25fb0ca296f728130fee 100644 (file)
@@ -254,7 +254,7 @@ out:
  */
 
 #define __OUT1(s) \
-extern inline void __out##s(unsigned int value, unsigned int port) {
+static inline void __out##s(unsigned int value, unsigned int port) {
 
 #define __OUT2(m) \
 __asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
@@ -268,7 +268,7 @@ __OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io
        SLOW_DOWN_IO; }
 
 #define __IN1(t,s) \
-extern __inline__ t __in##s(unsigned int port) { t _v;
+static inline t __in##s(unsigned int port) { t _v;
 
 /*
  * Required nops will be inserted by the assembler
@@ -283,7 +283,7 @@ __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SL
 __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
 
 #define __INS1(s) \
-extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
+static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
 
 #define __INS2(m) \
 if (count) \
@@ -311,7 +311,7 @@ __INS1(s##c) __INS2(m) \
        : "$1");}
 
 #define __OUTS1(s) \
-extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
+static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
 
 #define __OUTS2(m) \
 if (count) \
index 608c1a78db895fd2f9432788712126d2976be3cf..a36154a892c1ea687b5148772d1d384da664712d 100644 (file)
@@ -43,27 +43,12 @@ static int linux_env_idx;
 static void linux_params_init(ulong start, char *commandline);
 static void linux_env_set(char *env_name, char *env_val);
 
-int do_bootm_linux(int flag, int argc, char * const argv[],
-                       bootm_headers_t *images)
+static void boot_prep_linux(bootm_headers_t *images)
 {
-       void (*theKernel) (int, char **, char **, int *);
        char *commandline = getenv("bootargs");
        char env_buf[12];
        char *cp;
 
-       if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
-               return 1;
-
-       /* find kernel entry point */
-       theKernel = (void (*)(int, char **, char **, int *))images->ep;
-
-       bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
-#ifdef DEBUG
-       printf("## Transferring control to Linux (at address %08lx) ...\n",
-               (ulong) theKernel);
-#endif
-
        linux_params_init(UNCACHED_SDRAM(gd->bd->bi_boot_params), commandline);
 
 #ifdef CONFIG_MEMSIZE_IN_BYTES
@@ -96,11 +81,45 @@ int do_bootm_linux(int flag, int argc, char * const argv[],
        cp = getenv("eth1addr");
        if (cp)
                linux_env_set("eth1addr", cp);
+}
+
+static void boot_jump_linux(bootm_headers_t *images)
+{
+       void (*theKernel) (int, char **, char **, int *);
+
+       /* find kernel entry point */
+       theKernel = (void (*)(int, char **, char **, int *))images->ep;
+
+       debug("## Transferring control to Linux (at address %08lx) ...\n",
+               (ulong) theKernel);
+
+       bootstage_mark(BOOTSTAGE_ID_RUN_OS);
 
        /* we assume that the kernel is in place */
        printf("\nStarting kernel ...\n\n");
 
        theKernel(linux_argc, linux_argv, linux_env, 0);
+}
+
+int do_bootm_linux(int flag, int argc, char * const argv[],
+                       bootm_headers_t *images)
+{
+       /* No need for those on MIPS */
+       if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+               return -1;
+
+       if (flag & BOOTM_STATE_OS_PREP) {
+               boot_prep_linux(images);
+               return 0;
+       }
+
+       if (flag & BOOTM_STATE_OS_GO) {
+               boot_jump_linux(images);
+               return 0;
+       }
+
+       boot_prep_linux(images);
+       boot_jump_linux(images);
 
        /* does not return */
        return 1;
index b1feb2c0d0fc05558c9cb69a7ad00e3637a5d564..4927d5254b65682b4d007ea9afbebd43906343cd 100644 (file)
 
 #ifndef        __ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef        struct global_data {
-       bd_t            *bd;
-       unsigned long   flags;
-       unsigned int    baudrate;
-       unsigned long   have_console;   /* serial_init() was called */
-
-       unsigned long   reloc_off;      /* Relocation Offset */
-       unsigned long   env_addr;       /* Address  of Environment struct */
-       unsigned long   env_valid;      /* Checksum of Environment valid? */
-       unsigned long   fb_base;        /* base address of frame buffer */
-
-       unsigned long   relocaddr;      /* Start address of U-Boot in RAM */
-       phys_size_t     ram_size;       /* RAM size */
-       unsigned long   mon_len;        /* monitor len */
-       unsigned long   irq_sp;         /* irq stack pointer */
-       unsigned long   start_addr_sp;  /* start_addr_stackpointer */
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-       unsigned long   tlb_addr;
-#endif
 
-       void            **jt;           /* jump table */
-       char            env_buf[32];    /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #ifdef CONFIG_GLOBAL_DATA_NOT_REG10
 extern volatile gd_t g_gd;
index 91395cabf35dde2bbbc70c58a910270c1e407bf3..09feaf3733057ce1b30ffef87aa1214943c57b04 100644 (file)
@@ -207,17 +207,6 @@ void board_init_f(ulong bootflag)
 
        addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
 
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-       /* reserve TLB table */
-       addr -= (4096 * 4);
-
-       /* round down to next 64 kB limit */
-       addr &= ~(0x10000 - 1);
-
-       gd->tlb_addr = addr;
-       debug("TLB table at: %08lx\n", addr);
-#endif
-
        /* round down to next 4 kB limit */
        addr &= ~(4096 - 1);
        debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
index b1ed9e17f2db8ed7799c808a1319955029ea759b..f238665915343946f2d31a13b663750101600417 100644 (file)
@@ -30,7 +30,6 @@
 
 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
index 413b485b61bc72af1a85c2091774a6e158313dd4..39c570023bcfd5eed776a6aaf6fa2909fc4275ac 100644 (file)
 #ifndef        __ASM_NIOS2_GLOBALDATA_H_
 #define __ASM_NIOS2_GLOBALDATA_H_
 
-typedef        struct  global_data {
-       bd_t            *bd;
-       unsigned long   flags;
-       unsigned int    baudrate;
-       unsigned long   cpu_clk;        /* CPU clock in Hz!             */
-       unsigned long   have_console;   /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
-       unsigned long   precon_buf_idx; /* Pre-Console buffer index */
-#endif
-       phys_size_t     ram_size;       /* RAM size */
-       unsigned long   env_addr;       /* Address  of Environment struct */
-       unsigned long   env_valid;      /* Checksum of Environment valid */
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
-       unsigned long   post_log_word;  /* Record POST activities */
-       unsigned long   post_log_res; /* success of POST test */
-       unsigned long   post_init_f_time; /* When post_init_f started */
-#endif
-       void            **jt;           /* Standalone app jump table */
-       char            env_buf[32];    /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register gd_t *gd asm ("gp")
 
index 96f3f1cdbbd6d27436d8555ceeb7128feab354ae..d267ccd652fcc92a1af8d9d039bf87bce6e98fe0 100644 (file)
 
 #ifndef __ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
 
-typedef struct global_data {
-       bd_t            *bd;
-       unsigned long   flags;
-       unsigned int    baudrate;
-       unsigned long   cpu_clk;        /* CPU clock in Hz! */
-       unsigned long   have_console;   /* serial_init() was called */
-       phys_size_t     ram_size;       /* RAM size */
-       unsigned long   env_addr;       /* Address  of Environment struct */
-       unsigned long   env_valid;      /* Checksum of Environment valid? */
-       unsigned long   fb_base;        /* base address of frame buffer */
-       void            **jt;           /* jump table */
-       char            env_buf[32];    /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
 
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
 
 /* OR32 GCC already has r10 set as fixed-use */
 #define DECLARE_GLOBAL_DATA_PTR        register volatile gd_t *gd asm ("r10")
index a1a3bd4adf156ae0f125284aef658109f6b82a8a..bb03c6d88575445e865443f0c34bbc1e4658c998 100644 (file)
@@ -68,8 +68,8 @@ int checkcpu (void)
        }
        printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
                strmhz(buf1, clock),
-               strmhz(buf2, gd->csb_clk),
-               gd->reset_status & 0xffff);
+               strmhz(buf2, gd->arch.csb_clk),
+               gd->arch.reset_status & 0xffff);
        return 0;
 }
 
index fe6beaf84d28843edf9043a2b088b63af29c3557..32ade1b0b9215eff9a66ff65a026acdde4ca8811 100644 (file)
@@ -62,7 +62,7 @@ void cpu_init_f (volatile immap_t * im)
 #endif
 
        /* RSR - Reset Status Register - clear all status */
-       gd->reset_status = im->reset.rsr;
+       gd->arch.reset_status = im->reset.rsr;
        out_be32(&im->reset.rsr, ~RSR_RES);
 
        /*
index 0ea12806b92c718648d8677bd9b5f61a12e13d10..59040f83c9251b87b5b91a277ac077079ed2160b 100644 (file)
@@ -250,7 +250,7 @@ static int mpc_get_fdr (int speed)
                        {126, 128}
                };
 
-               ips = gd->ips_clk;
+               ips = gd->arch.ips_clk;
                for (i = 7; i >= 0; i--) {
                        for (j = 7; j >= 0; j--) {
                                scl = 2 * (scltap[j].scl2tap +
index dd6b2f4673d70ddb4274a580af9e6e1756e98643..7a496734e7c6b683f2ad3c6bfd8455f084a9f4e5 100644 (file)
@@ -100,7 +100,7 @@ int ide_preinit (void)
        ide_set_reset(0);
 
        /* Init timings : we use PIO mode 0 timings */
-       t = 1000000000 / gd->ips_clk;   /* period in ns */
+       t = 1000000000 / gd->arch.ips_clk;      /* period in ns */
        cfg.bytes.field1 = 3;
        cfg.bytes.field2 = 3;
        cfg.bytes.field3 = (pio_specs.t1 + t) / t;
index 58587fd5bcf59c78446a5a52f89e055ededdff39..3afbe810184500784afe0c0bcaebc0fb21806f0a 100644 (file)
@@ -140,7 +140,7 @@ void serial_setbrg_dev(unsigned int idx)
        }
 
        /* calculate divisor for setting PSC CTUR and CTLR registers */
-       baseclk = (gd->ips_clk + 8) / 16;
+       baseclk = (gd->arch.ips_clk + 8) / 16;
        div = (baseclk + (baudrate / 2)) / baudrate;
 
        out_8(&psc->ctur, (div >> 8) & 0xff);
index 9d749f22e4d6abc6d471e0f6cddac4ed483045a9..9a8f315d8255325e7fd81ea2ce834737a30564f4 100644 (file)
@@ -113,9 +113,9 @@ int get_clocks (void)
                pci_clk = 333333;
        }
 
-       gd->ips_clk = ips_clk;
+       gd->arch.ips_clk = ips_clk;
        gd->pci_clk = pci_clk;
-       gd->csb_clk = csb_clk;
+       gd->arch.csb_clk = csb_clk;
        gd->cpu_clk = core_clk;
        gd->bus_clk = csb_clk;
        return 0;
@@ -128,7 +128,7 @@ int get_clocks (void)
  *********************************************/
 ulong get_bus_freq (ulong dummy)
 {
-       return gd->csb_clk;
+       return gd->arch.csb_clk;
 }
 
 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
@@ -137,10 +137,13 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 
        printf("Clock configuration:\n");
        printf("  CPU:                 %-4s MHz\n", strmhz(buf, gd->cpu_clk));
-       printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-       printf("  IPS Bus:             %-4s MHz\n", strmhz(buf, gd->ips_clk));
+       printf("  Coherent System Bus: %-4s MHz\n",
+              strmhz(buf, gd->arch.csb_clk));
+       printf("  IPS Bus:             %-4s MHz\n",
+              strmhz(buf, gd->arch.ips_clk));
        printf("  PCI:                 %-4s MHz\n", strmhz(buf, gd->pci_clk));
-       printf("  DDR:                 %-4s MHz\n", strmhz(buf, 2*gd->csb_clk));
+       printf("  DDR:                 %-4s MHz\n",
+              strmhz(buf, 2 * gd->arch.csb_clk));
        return 0;
 }
 
index 0c1eebd4ee1ec983ac99ef8c2a9ac6eef2a43974..dc021e35f55c4ba055045a45d210757ea512a885 100644 (file)
@@ -36,7 +36,6 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif
 
index b423d2fe3416a0bfde16ccb9b33f54330f0e9b36..8d5f47b1bba78eaed2125bed82ba4e07693890fd 100644 (file)
@@ -310,7 +310,7 @@ static int mpc_get_fdr(int speed)
                        {126, 128}
                };
 
-               ipb = gd->ipb_clk;
+               ipb = gd->arch.ipb_clk;
                for (i = 7; i >= 0; i--) {
                        for (j = 7; j >= 0; j--) {
                                scl = 2 * (scltap[j].scl2tap +
index d337abb1c9f637e723eda56f57e280f59db3ef64..094f62b6bab82a03384fee5c36d7f9c619ea9a86 100644 (file)
@@ -75,7 +75,7 @@ int ide_preinit (void)
        psdma->PtdCntrl |= 1;
 
        /* Init timings : we use PIO mode 0 timings */
-       period = 1000000000 / gd->ipb_clk;      /* period in ns */
+       period = 1000000000 / gd->arch.ipb_clk; /* period in ns */
 
        t0 = CALC_TIMING (600);
        t2_8 = CALC_TIMING (290);
index eb141619b87448a8aa45c5794ddb8db1d54047d0..1ccb4e35def93f5083e44203956cf9b96edf21ae 100644 (file)
@@ -89,7 +89,7 @@ int serial_init_dev (unsigned long dev_base)
 
        /* select clock sources */
        psc->psc_clock_select = 0;
-       baseclk = (gd->ipb_clk + 16) / 32;
+       baseclk = (gd->arch.ipb_clk + 16) / 32;
 
        /* switch to UART mode */
        psc->sicr = 0;
@@ -169,7 +169,7 @@ void serial_setbrg_dev (unsigned long dev_base)
        volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
        unsigned long baseclk, div;
 
-       baseclk = (gd->ipb_clk + 16) / 32;
+       baseclk = (gd->arch.ipb_clk + 16) / 32;
 
        /* set up UART divisor */
        div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
index 8027d3e08a2c8054a97bbcd00d0200389fccdfa0..5353e3d535071718ac18b1dffcc82f31eecd7456 100644 (file)
@@ -66,14 +66,20 @@ int get_clocks (void)
 
        val = *(vu_long *)MPC5XXX_CDM_CFG;
        if (val & (1 << 8)) {
-               gd->ipb_clk = gd->bus_clk / 2;
+               gd->arch.ipb_clk = gd->bus_clk / 2;
        } else {
-               gd->ipb_clk = gd->bus_clk;
+               gd->arch.ipb_clk = gd->bus_clk;
        }
        switch (val & 3) {
-               case 0: gd->pci_clk = gd->ipb_clk; break;
-               case 1: gd->pci_clk = gd->ipb_clk / 2; break;
-               default: gd->pci_clk = gd->bus_clk / 4; break;
+       case 0:
+               gd->pci_clk = gd->arch.ipb_clk;
+               break;
+       case 1:
+               gd->pci_clk = gd->arch.ipb_clk / 2;
+               break;
+       default:
+               gd->pci_clk = gd->bus_clk / 4;
+               break;
        }
 
        return (0);
@@ -85,7 +91,7 @@ int prt_mpc5xxx_clks (void)
 
        printf ("       Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
                strmhz(buf1, gd->bus_clk),
-               strmhz(buf2, gd->ipb_clk),
+               strmhz(buf2, gd->arch.ipb_clk),
                strmhz(buf3, gd->pci_clk)
        );
        return (0);
index aaf9be107af83fbdd7c1b6963b84ab2c76c7452b..43fa802ca96db0a5a4e6f0542fb5873877d3ecd5 100644 (file)
@@ -288,9 +288,11 @@ static int mpc8220_fec_init (struct eth_device *dev, bd_t * bis)
                 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
                 * and do not drop the Preamble.
                 */
-               /* tbd - rtm */
-               /*fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); */
-               /* No MII for 7-wire mode */
+               /*
+                * tbd - rtm
+                * fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
+                * No MII for 7-wire mode
+                */
                fec->eth->mii_speed = 0x00000030;
        }
 
index 62ac845b7ae8f1aacfae45e623faa404eded5dbf..bb72e5ce126a642ac55327f54a0a55689038bd97 100644 (file)
@@ -71,7 +71,7 @@ int get_clocks (void)
 #error clock measuring not implemented yet - define CONFIG_SYS_MPC8220_CLKIN
 #endif
 
-       gd->inp_clk = CONFIG_SYS_MPC8220_CLKIN;
+       gd->arch.inp_clk = CONFIG_SYS_MPC8220_CLKIN;
 
        /* Read XLB to PCI(INP) clock multiplier */
        pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
@@ -85,7 +85,7 @@ int get_clocks (void)
 
        /* FlexBus is temporary set as the same as input clock */
        /* will do dynamic in the future */
-       gd->flb_clk = CONFIG_SYS_MPC8220_CLKIN;
+       gd->arch.flb_clk = CONFIG_SYS_MPC8220_CLKIN;
 
        /* CPU Clock - Read HID1 */
        asm volatile ("mfspr %0, 1009":"=r" (hid1):);
@@ -97,12 +97,14 @@ int get_clocks (void)
        for (i = 0; i < size; i++)
                if (hid1 == bus2core[i].hid1) {
                        gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1;
-                       gd->vco_clk = CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2;
+                       gd->arch.vco_clk =
+                               CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER *
+                               (gd->pci_clk * bus2core[i].vco_div) / 2;
                        break;
                }
 
        /* hardcoded 81MHz for now */
-       gd->pev_clk = 81000000;
+       gd->arch.pev_clk = 81000000;
 
        return (0);
 }
@@ -115,7 +117,7 @@ int prt_mpc8220_clks (void)
                strmhz(buf1, gd->bus_clk),
                strmhz(buf2, gd->cpu_clk),
                strmhz(buf3, gd->pci_clk),
-               strmhz(buf4, gd->vco_clk)
+               strmhz(buf4, gd->arch.vco_clk)
        );
        return (0);
 }
index 082957ee08e3755142dbf6dd9abed19ce4aede20..22cef3e9839e96101b9bba3212e7068bb6d93acc 100644 (file)
@@ -30,8 +30,8 @@ m8260_cpm_reset(void)
 
        /* Reclaim the DP memory for our use.
        */
-       gd->dp_alloc_base = CPM_DATAONLY_BASE;
-       gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
+       gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+       gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
 
        /*
         * Reset CPM
@@ -60,21 +60,22 @@ m8260_cpm_dpalloc(uint size, uint align)
        uint    savebase;
 
        align_mask = align - 1;
-       savebase = gd->dp_alloc_base;
+       savebase = gd->arch.dp_alloc_base;
 
-       if ((off = (gd->dp_alloc_base & align_mask)) != 0)
-               gd->dp_alloc_base += (align - off);
+       off = gd->arch.dp_alloc_base & align_mask;
+       if (off != 0)
+               gd->arch.dp_alloc_base += (align - off);
 
        if ((off = size & align_mask) != 0)
                size += align - off;
 
-       if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
-               gd->dp_alloc_base = savebase;
+       if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
+               gd->arch.dp_alloc_base = savebase;
                panic("m8260_cpm_dpalloc: ran out of dual port ram!");
        }
 
-       retloc = gd->dp_alloc_base;
-       gd->dp_alloc_base += size;
+       retloc = gd->arch.dp_alloc_base;
+       gd->arch.dp_alloc_base += size;
 
        memset((void *)&immr->im_dprambase[retloc], 0, size);
 
@@ -101,7 +102,7 @@ m8260_cpm_hostalloc(uint size, uint align)
  * Baud rate clocks are zero-based in the driver code (as that maps
  * to port numbers).  Documentation uses 1-based numbering.
  */
-#define BRG_INT_CLK    gd->brg_clk
+#define BRG_INT_CLK    gd->arch.brg_clk
 #define BRG_UART_CLK   (BRG_INT_CLK / 16)
 
 /* This function is used by UARTs, or anything else that uses a 16x
index 220c1e24b1037bdee849fd7b11ca81a412a1ddec..f8bc5a9834b861b54e25f9391ddea6d08cd8949c 100644 (file)
@@ -50,7 +50,6 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif
 
index acd48a9f553def27b6ab70bd3948c4dca0dffc1d..3964e607d0514ffa2d906906618d6ca6ed102b86 100644 (file)
@@ -120,7 +120,7 @@ void cpu_init_f (volatile immap_t * immr)
        memset ((void *) gd, 0, sizeof (gd_t));
 
        /* RSR - Reset Status Register - clear all status (5-4) */
-       gd->reset_status = immr->im_clkrst.car_rsr;
+       gd->arch.reset_status = immr->im_clkrst.car_rsr;
        immr->im_clkrst.car_rsr = RSR_ALLBITS;
 
        /* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
@@ -274,7 +274,7 @@ int prt_8260_rsr (void)
                RSR_EHRS, "External Hard"}
        };
        static int n = sizeof bits / sizeof bits[0];
-       ulong rsr = gd->reset_status;
+       ulong rsr = gd->arch.reset_status;
        int i;
        char *sep;
 
index 7382cbadc7eebb2a38f9f9263240deec5df9b3e8..b720b1fb882b1b4261939a18479a08e2b2243a2d 100644 (file)
@@ -259,7 +259,7 @@ void i2c_init(int speed, int slaveadd)
         * divide BRGCLK by 1)
         */
        debug("[I2C] Setting rate...\n");
-       i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED);
+       i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED);
 
        /* Set I2C controller in master mode */
        i2c->i2c_i2com = 0x01;
index bb50dee9602de8bfb535df38c68cdf1b3d7d76c6..7841e8a898c8e64229aada14afd9c8b682230f74 100644 (file)
@@ -135,17 +135,17 @@ int get_clocks (void)
            (get_pvr () == PVR_8260_HIP7R1) ||
            (get_pvr () == PVR_8260_HIP7RA)) {
                pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
-               gd->vco_out = clkin * (pllmf + 1);
+               gd->arch.vco_out = clkin * (pllmf + 1);
        } else {                        /* HiP3, HiP4 */
                pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
                plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
-               gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
+               gd->arch.vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
        }
 
-       gd->cpm_clk = gd->vco_out / 2;
+       gd->arch.cpm_clk = gd->arch.vco_out / 2;
        gd->bus_clk = clkin;
-       gd->scc_clk = gd->vco_out / 4;
-       gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+       gd->arch.scc_clk = gd->arch.vco_out / 4;
+       gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
 
        if (cp->b2c_mult > 0) {
                gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
@@ -173,7 +173,7 @@ int get_clocks (void)
                        pci_div = pcidf + 1;
                }
 
-               gd->pci_clk = (gd->cpm_clk * 2) / pci_div;
+               gd->pci_clk = (gd->arch.cpm_clk * 2) / pci_div;
        }
 #endif
 
@@ -231,10 +231,10 @@ int prt_8260_clks (void)
                        plldf, pllmf, pcidf);
 
        printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
-                       gd->vco_out, gd->scc_clk, gd->brg_clk);
+                       gd->arch.vco_out, gd->arch.scc_clk, gd->arch.brg_clk);
 
        printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
-                       gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
+                       gd->cpu_clk, gd->arch.cpm_clk, gd->bus_clk);
 #ifdef CONFIG_PCI
        printf (" - pci_clk %10ld\n", gd->pci_clk);
 #endif
index 687f5e90a4d5f6dcdce3236db3a7a779cba5ba96..8a470b84b84ca3f04c30aaca351316aed74cc10a 100644 (file)
@@ -27,8 +27,22 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(CPU).o
 
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
 START  = start.o
 
+ifdef MINIMAL
+
+COBJS-y        += spl_minimal.o
+
+else
+
 COBJS-y += traps.o
 COBJS-y += cpu.o
 COBJS-y += cpu_init.o
@@ -51,6 +65,8 @@ COBJS-y += spd_sdram.o
 endif
 COBJS-$(CONFIG_FSL_DDR2) += law.o
 
+endif # not minimal
+
 COBJS  := $(COBJS-y)
 SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c))
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y))
index e64b0c3411827dd1a06ec9bdb72c8cf9abefce1b..cc2023429828b0cf44b1152e4b8e435139f2009a 100644 (file)
@@ -122,7 +122,7 @@ int checkcpu(void)
 
        printf(" at %s MHz, ", strmhz(buf, clock));
 
-       printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
+       printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
 
        return 0;
 }
index 20d06003e57794cd7633906a34beac4e3b52a5bd..51533519626576bc608ea1f73f7b3487d25e880a 100644 (file)
@@ -232,12 +232,12 @@ void cpu_init_f (volatile immap_t * im)
        clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 
        /* RSR - Reset Status Register - clear all status (4.6.1.3) */
-       gd->reset_status = __raw_readl(&im->reset.rsr);
+       gd->arch.reset_status = __raw_readl(&im->reset.rsr);
        __raw_writel(~(RSR_RES), &im->reset.rsr);
 
        /* AER - Arbiter Event Register - store status */
-       gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
-       gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
+       gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
+       gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 
        /*
         * RMR - Reset Mode Register
@@ -440,42 +440,44 @@ static int print_83xx_arb_event(int force)
                "reserved"
        };
 
-       int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
+       int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
                    >> AEATR_EVENT_SHIFT;
-       int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
+       int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
                      >> AEATR_MSTR_ID_SHIFT;
-       int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
+       int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
                   >> AEATR_TBST_SHIFT;
-       int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
+       int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
                    >> AEATR_TSIZE_SHIFT;
-       int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
+       int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
                    >> AEATR_TTYPE_SHIFT;
 
-       if (!force && !gd->arbiter_event_address)
+       if (!force && !gd->arch.arbiter_event_address)
                return 0;
 
        puts("Arbiter Event Status:\n");
-       printf("       Event Address: 0x%08lX\n", gd->arbiter_event_address);
+       printf("       Event Address: 0x%08lX\n",
+              gd->arch.arbiter_event_address);
        printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
        printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
        printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
                                tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
        printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 
-       return gd->arbiter_event_address;
+       return gd->arch.arbiter_event_address;
 }
 
 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 
 static int print_83xx_arb_event(int force)
 {
-       if (!force && !gd->arbiter_event_address)
+       if (!force && !gd->arch.arbiter_event_address)
                return 0;
 
        printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
-               gd->arbiter_event_attributes, gd->arbiter_event_address);
+               gd->arch.arbiter_event_attributes,
+               gd->arch.arbiter_event_address);
 
-       return gd->arbiter_event_address;
+       return gd->arch.arbiter_event_address;
 }
 #endif /* CONFIG_DISPLAY_AER_xxxx */
 
@@ -499,7 +501,7 @@ int prt_83xx_rsr(void)
                RSR_HRS,  "External/Internal Hard"}
        };
        static int n = sizeof bits / sizeof bits[0];
-       ulong rsr = gd->reset_status;
+       ulong rsr = gd->arch.reset_status;
        int i;
        char *sep;
 
index 1f54781b7e2d3b7e8e1e58e1dce64b727b21e9ba..fe553a74f001e465250a2ffd67d96203e892ca0e 100644 (file)
@@ -118,7 +118,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
                "bus-frequency", bd->bi_busfreq, 1);
        do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
-               "clock-frequency", gd->core_clk, 1);
+               "clock-frequency", gd->arch.core_clk, 1);
        do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
                "bus-frequency", bd->bi_busfreq, 1);
        do_fixup_by_compat_u32(blob, "fsl,soc",
index 52d446175aa5992e1e1c3a36c550d61d22bd818e..609b133215c44d958e74d56b3c1d6bd6bd103938 100644 (file)
@@ -286,8 +286,8 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
        get_clocks();
        /* Configure the PCIE controller core clock ratio */
        out_le32(hose_cfg_base + PEX_GCLK_RATIO,
-               (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
-               / 333);
+               (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
+                       / 1000000) * 16) / 333);
        udelay(1000000);
 
        /* Do Type 1 bridge configuration */
index b8c05d15929ce33800e9848a5419a50560633f17..6be0e3a2ee41c7f36258cf0550d651a349ab1696 100644 (file)
@@ -462,53 +462,53 @@ int get_clocks(void)
        brg_clk = qe_clk / 2;
 #endif
 
-       gd->csb_clk = csb_clk;
+       gd->arch.csb_clk = csb_clk;
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
        defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
-       gd->tsec1_clk = tsec1_clk;
-       gd->tsec2_clk = tsec2_clk;
-       gd->usbdr_clk = usbdr_clk;
+       gd->arch.tsec1_clk = tsec1_clk;
+       gd->arch.tsec2_clk = tsec2_clk;
+       gd->arch.usbdr_clk = usbdr_clk;
 #elif defined(CONFIG_MPC8309)
-       gd->usbdr_clk = usbdr_clk;
+       gd->arch.usbdr_clk = usbdr_clk;
 #endif
 #if defined(CONFIG_MPC834x)
-       gd->usbmph_clk = usbmph_clk;
+       gd->arch.usbmph_clk = usbmph_clk;
 #endif
 #if defined(CONFIG_MPC8315)
-       gd->tdm_clk = tdm_clk;
+       gd->arch.tdm_clk = tdm_clk;
 #endif
 #if defined(CONFIG_FSL_ESDHC)
-       gd->sdhc_clk = sdhc_clk;
+       gd->arch.sdhc_clk = sdhc_clk;
 #endif
-       gd->core_clk = core_clk;
-       gd->i2c1_clk = i2c1_clk;
+       gd->arch.core_clk = core_clk;
+       gd->arch.i2c1_clk = i2c1_clk;
 #if !defined(CONFIG_MPC832x)
-       gd->i2c2_clk = i2c2_clk;
+       gd->arch.i2c2_clk = i2c2_clk;
 #endif
 #if !defined(CONFIG_MPC8309)
-       gd->enc_clk = enc_clk;
+       gd->arch.enc_clk = enc_clk;
 #endif
-       gd->lbiu_clk = lbiu_clk;
-       gd->lclk_clk = lclk_clk;
+       gd->arch.lbiu_clk = lbiu_clk;
+       gd->arch.lclk_clk = lclk_clk;
        gd->mem_clk = mem_clk;
 #if defined(CONFIG_MPC8360)
-       gd->mem_sec_clk = mem_sec_clk;
+       gd->arch.mem_sec_clk = mem_sec_clk;
 #endif
 #if defined(CONFIG_QE)
-       gd->qe_clk = qe_clk;
-       gd->brg_clk = brg_clk;
+       gd->arch.qe_clk = qe_clk;
+       gd->arch.brg_clk = brg_clk;
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
        defined(CONFIG_MPC837x)
-       gd->pciexp1_clk = pciexp1_clk;
-       gd->pciexp2_clk = pciexp2_clk;
+       gd->arch.pciexp1_clk = pciexp1_clk;
+       gd->arch.pciexp2_clk = pciexp2_clk;
 #endif
 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
-       gd->sata_clk = sata_clk;
+       gd->arch.sata_clk = sata_clk;
 #endif
        gd->pci_clk = pci_sync_in;
-       gd->cpu_clk = gd->core_clk;
-       gd->bus_clk = gd->csb_clk;
+       gd->cpu_clk = gd->arch.core_clk;
+       gd->bus_clk = gd->arch.csb_clk;
        return 0;
 
 }
@@ -519,7 +519,7 @@ int get_clocks(void)
  *********************************************/
 ulong get_bus_freq(ulong dummy)
 {
-       return gd->csb_clk;
+       return gd->arch.csb_clk;
 }
 
 /********************************************
@@ -536,49 +536,69 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        char buf[32];
 
        printf("Clock configuration:\n");
-       printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
-       printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
+       printf("  Core:                %-4s MHz\n",
+              strmhz(buf, gd->arch.core_clk));
+       printf("  Coherent System Bus: %-4s MHz\n",
+              strmhz(buf, gd->arch.csb_clk));
 #if defined(CONFIG_QE)
-       printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
-       printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
-#endif
-       printf("  Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
-       printf("  Local Bus:           %-4s MHz\n", strmhz(buf, gd->lclk_clk));
+       printf("  QE:                  %-4s MHz\n",
+              strmhz(buf, gd->arch.qe_clk));
+       printf("  BRG:                 %-4s MHz\n",
+              strmhz(buf, gd->arch.brg_clk));
+#endif
+       printf("  Local Bus Controller:%-4s MHz\n",
+              strmhz(buf, gd->arch.lbiu_clk));
+       printf("  Local Bus:           %-4s MHz\n",
+              strmhz(buf, gd->arch.lclk_clk));
        printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
 #if defined(CONFIG_MPC8360)
-       printf("  DDR Secondary:       %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
+       printf("  DDR Secondary:       %-4s MHz\n",
+              strmhz(buf, gd->arch.mem_sec_clk));
 #endif
 #if !defined(CONFIG_MPC8309)
-       printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
+       printf("  SEC:                 %-4s MHz\n",
+              strmhz(buf, gd->arch.enc_clk));
 #endif
-       printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
+       printf("  I2C1:                %-4s MHz\n",
+              strmhz(buf, gd->arch.i2c1_clk));
 #if !defined(CONFIG_MPC832x)
-       printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
+       printf("  I2C2:                %-4s MHz\n",
+              strmhz(buf, gd->arch.i2c2_clk));
 #endif
 #if defined(CONFIG_MPC8315)
-       printf("  TDM:                 %-4s MHz\n", strmhz(buf, gd->tdm_clk));
+       printf("  TDM:                 %-4s MHz\n",
+              strmhz(buf, gd->arch.tdm_clk));
 #endif
 #if defined(CONFIG_FSL_ESDHC)
-       printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
+       printf("  SDHC:                %-4s MHz\n",
+              strmhz(buf, gd->arch.sdhc_clk));
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
        defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
-       printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
-       printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
-       printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+       printf("  TSEC1:               %-4s MHz\n",
+              strmhz(buf, gd->arch.tsec1_clk));
+       printf("  TSEC2:               %-4s MHz\n",
+              strmhz(buf, gd->arch.tsec2_clk));
+       printf("  USB DR:              %-4s MHz\n",
+              strmhz(buf, gd->arch.usbdr_clk));
 #elif defined(CONFIG_MPC8309)
-       printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+       printf("  USB DR:              %-4s MHz\n",
+              strmhz(buf, gd->arch.usbdr_clk));
 #endif
 #if defined(CONFIG_MPC834x)
-       printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
+       printf("  USB MPH:             %-4s MHz\n",
+              strmhz(buf, gd->arch.usbmph_clk));
 #endif
 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
        defined(CONFIG_MPC837x)
-       printf("  PCIEXP1:             %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
-       printf("  PCIEXP2:             %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
+       printf("  PCIEXP1:             %-4s MHz\n",
+              strmhz(buf, gd->arch.pciexp1_clk));
+       printf("  PCIEXP2:             %-4s MHz\n",
+              strmhz(buf, gd->arch.pciexp2_clk));
 #endif
 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
-       printf("  SATA:                %-4s MHz\n", strmhz(buf, gd->sata_clk));
+       printf("  SATA:                %-4s MHz\n",
+              strmhz(buf, gd->arch.sata_clk));
 #endif
        return 0;
 }
index b70b4ca12cea1540a4697654b1e41a527eb1078c..44a64b7acd9cda4ea674ce250e55f960b0551f4f 100644 (file)
 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
 #endif
 
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_NAND_SPL) || \
+       (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
+#define MINIMAL_SPL
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
+       !defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_SYS_FLASHBOOT
 #endif
 
@@ -72,7 +78,7 @@
        GOT_ENTRY(__bss_start)
        GOT_ENTRY(__bss_end__)
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
        GOT_ENTRY(_FIXUP_TABLE_)
        GOT_ENTRY(_start)
        GOT_ENTRY(_start_of_vectors)
@@ -206,7 +212,8 @@ _start: /* time t 0 */
        /* Initialise the E300 processor core           */
        /*------------------------------------------*/
 
-#ifdef CONFIG_NAND_SPL
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
+               defined(CONFIG_NAND_SPL)
        /* The FCM begins execution after only the first page
         * is loaded.  Wait for the rest before branching
         * to another flash page.
@@ -292,7 +299,7 @@ in_flash:
 
        /* NOTREACHED - board_init_f() does not return */
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 /*
  * Vector Table
  */
@@ -467,7 +474,7 @@ int_return:
        lwz     r1,GPR1(r1)
        SYNC
        rfi
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
 
 /*
  * This code initialises the E300 processor core
@@ -724,7 +731,7 @@ setup_bats:
  * Note: requires that all cache bits in
  * HID0 are in the low half word.
  */
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
        .globl  icache_enable
 icache_enable:
        mfspr   r3, HID0
@@ -753,7 +760,7 @@ icache_status:
        mfspr   r3, HID0
        rlwinm  r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
        blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
 
        .globl  dcache_enable
 dcache_enable:
@@ -936,7 +943,7 @@ in_ram:
        stw     r0,0(r3)
 2:     bdnz    1b
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
        /*
         * Now adjust the fixups and the pointers to the fixups
         * in case we need to move ourselves again.
@@ -991,7 +998,7 @@ clear_bss:
        mr      r4, r10         /* Destination Address          */
        bl      board_init_r
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
        /*
         * Copy exception vector code to low memory
         *
@@ -1061,7 +1068,7 @@ trap_init:
        mtlr    r4                      /* restore link register    */
        blr
 
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
 
 #ifdef CONFIG_SYS_INIT_RAM_LOCK
 lock_ram_in_cache:
@@ -1085,7 +1092,7 @@ lock_ram_in_cache:
        sync
        blr
 
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
        /* invalidate the INIT_RAM section */
@@ -1111,7 +1118,7 @@ unlock_ram_in_cache:
        sync
        mtspr   HID0, r3                /* no invalidate, unlock */
        blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
 #endif /* CONFIG_SYS_INIT_RAM_LOCK */
 
 #ifdef CONFIG_SYS_FLASHBOOT
index 4c2b1040d4613317b2365ddce77bdf23ffc21493..6776c85e4998b5db946ef3d9bc9511aea49e0edc 100644 (file)
@@ -83,8 +83,10 @@ COBJS-$(CONFIG_PPC_P4080)    += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5040)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_T4240)      += ddr-gen3.o
+COBJS-$(CONFIG_PPC_B4420)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4860)      += ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)                += ddr-gen3.o
+COBJS-$(CONFIG_BSC9132)                += ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)   += ether_fcc.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
@@ -100,6 +102,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
 
 COBJS-$(CONFIG_QE)     += qe_io.o
@@ -134,7 +137,9 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
+COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
 
 COBJS-y        += cpu.o
 COBJS-y        += cpu_init.o
index 7d33731a7ba455615b1cb21c1143d48c9e585467..0f4e82e05b3a185e4755469f8927b78f437ac22a 100644 (file)
@@ -55,11 +55,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
 };
 #endif
 
+#ifdef CONFIG_SYS_SRIO
 struct srio_liodn_id_table srio_liodn_tbl[] = {
        SET_SRIO_LIODN_1(1, 307),
        SET_SRIO_LIODN_1(2, 387),
 };
 int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
 
 struct liodn_id_table liodn_tbl[] = {
 #ifdef CONFIG_SYS_DPAA_QBMAN
@@ -76,10 +78,12 @@ struct liodn_id_table liodn_tbl[] = {
        SET_DMA_LIODN(1, 147),
        SET_DMA_LIODN(2, 227),
 
+#ifndef CONFIG_PPC_B4420
        SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
        SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
        SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
        SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+#endif
 
        /* SET_NEXUS_LIODN(557), -- not yet implemented */
 };
@@ -93,8 +97,10 @@ struct liodn_id_table fman1_liodn_tbl[] = {
        SET_FMAN_RX_1G_LIODN(1, 3, 91),
        SET_FMAN_RX_1G_LIODN(1, 4, 92),
        SET_FMAN_RX_1G_LIODN(1, 5, 93),
+#ifndef CONFIG_PPC_B4420
        SET_FMAN_RX_10G_LIODN(1, 0, 94),
        SET_FMAN_RX_10G_LIODN(1, 1, 95),
+#endif
 };
 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
 #endif
index 9990202f421af77c459f2810b340af4bfb8c879d..bd3234271a1da1f1b644c827e7c9ad70e2f59565 100644 (file)
@@ -31,6 +31,7 @@ struct serdes_config {
        u8 lanes[SRDS_MAX_LANES];
 };
 
+#ifdef CONFIG_PPC_B4860
 static struct serdes_config serdes1_cfg_tbl[] = {
        /* SerDes 1 */
        {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
@@ -41,6 +42,12 @@ static struct serdes_config serdes1_cfg_tbl[] = {
                CPRI4, CPRI3, CPRI2, CPRI1}},
        {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
                CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+       {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+       {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+       {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
        {0x30, {AURORA, AURORA,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
                CPRI4, CPRI3, CPRI2, CPRI1}},
@@ -84,6 +91,8 @@ static struct serdes_config serdes2_cfg_tbl[] = {
        {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, AURORA,
                SRIO1, SRIO1, SRIO1, SRIO1}},
+       {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
+               SRIO1, SRIO1, SRIO1, SRIO1}},
        {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SRIO2, SRIO2, AURORA, AURORA,
                XFI_FM1_MAC9, XFI_FM1_MAC10}},
@@ -94,6 +103,9 @@ static struct serdes_config serdes2_cfg_tbl[] = {
                SRIO2, SRIO2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
                XFI_FM1_MAC9, XFI_FM1_MAC10}},
+       {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               XFI_FM1_MAC9, XFI_FM1_MAC10}},
        {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
                SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
                XAUI_FM1_MAC10, XAUI_FM1_MAC10,
@@ -111,8 +123,56 @@ static struct serdes_config serdes2_cfg_tbl[] = {
        {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
                XAUI_FM1_MAC9, XAUI_FM1_MAC9,
                SRIO1, SRIO1, SRIO1, SRIO1}},
+       {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+               XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+               XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+               XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
        {}
 };
+#endif
+
+#ifdef CONFIG_PPC_B4420
+static struct serdes_config serdes1_cfg_tbl[] = {
+       {0x0D, {NONE, NONE, CPRI6, CPRI5,
+               CPRI4, CPRI3, NONE, NONE} },
+       {0x0E, {NONE, NONE, CPRI8, CPRI5,
+               CPRI4, CPRI3, NONE, NONE} },
+       {0x0F, {NONE, NONE, CPRI6, CPRI5,
+               CPRI4, CPRI3, NONE, NONE} },
+       {0x18, {NONE, NONE,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               NONE, NONE, NONE, NONE} },
+       {0x1B, {NONE, NONE,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               NONE, NONE, NONE, NONE} },
+       {0x1E, {NONE, NONE, AURORA, AURORA,
+               NONE, NONE, NONE, NONE} },
+       {0x21, {NONE, NONE, AURORA, AURORA,
+               NONE, NONE, NONE, NONE} },
+       {0x3E, {NONE, NONE, CPRI6, CPRI5,
+               CPRI4, CPRI3, NONE, NONE} },
+       {}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+       {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, AURORA,
+               NONE, NONE, NONE, NONE} },
+       {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, AURORA,
+               NONE, NONE, NONE, NONE} },
+       {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               AURORA, AURORA, NONE, NONE, NONE, NONE} },
+       {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               AURORA, AURORA, NONE, NONE, NONE, NONE} },
+       {0x9A, {PCIE1, PCIE1,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+               NONE, NONE, NONE, NONE} },
+       {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
+               NONE, NONE, NONE, NONE} },
+       {}
+};
+#endif
+
 static struct serdes_config *serdes_cfg_tbl[] = {
        serdes1_cfg_tbl,
        serdes2_cfg_tbl,
diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
new file mode 100644 (file)
index 0000000..300a4db
--- /dev/null
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES                4
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+        [0] = {NONE, NONE, NONE, NONE},
+        [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
+        [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
+        [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
+        [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
+        [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
+        [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+        [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+        [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+        [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
+       [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [22] = {PCIE1, PCIE2, CPRI2, CPRI1},
+       [23] = {PCIE1, PCIE2, CPRI2, CPRI1},
+       [24] = {PCIE1, PCIE2, CPRI2, CPRI1},
+       [25] = {PCIE1, PCIE2, CPRI2, CPRI1},
+       [26] = {PCIE1, PCIE2, CPRI2, CPRI1},
+       [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
+       [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+       [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+       [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+       [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+       [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+       return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 pordevsr = in_be32(&gur->pordevsr);
+       u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+                               MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+       int lane;
+
+       debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
+               printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+               return;
+       }
+
+       for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+               enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+               serdes1_prtcl_map |= (1 << lane_prtcl);
+       }
+}
index e5ecf5dae59d2384cdf671a58fc49a4a66a7e457..5d72f4c342d36dcb9462b67ed71e35e72426aec4 100644 (file)
@@ -240,6 +240,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
        puts("Work-around for Erratum A004934 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
+       if (IS_SVR_REV(svr, 1, 0))
+               puts("Work-around for Erratum A005871 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
        /* This work-around is implemented in PBI, so just check for it */
        check_erratum_a4849(svr);
index 292b723dcddf00178b757cc03ae02ddbe5e1f6f5..37e706238b6fc92607c7729699afccdb4edef1e6 100644 (file)
@@ -43,8 +43,8 @@ m8560_cpm_reset(void)
 
        /* Reclaim the DP memory for our use.
        */
-       gd->dp_alloc_base = CPM_DATAONLY_BASE;
-       gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
+       gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+       gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
 
        /*
         * Reset CPM
@@ -69,21 +69,22 @@ m8560_cpm_dpalloc(uint size, uint align)
        uint    savebase;
 
        align_mask = align - 1;
-       savebase = gd->dp_alloc_base;
+       savebase = gd->arch.dp_alloc_base;
 
-       if ((off = (gd->dp_alloc_base & align_mask)) != 0)
-               gd->dp_alloc_base += (align - off);
+       off = gd->arch.dp_alloc_base & align_mask;
+       if (off != 0)
+               gd->arch.dp_alloc_base += (align - off);
 
        if ((off = size & align_mask) != 0)
                size += align - off;
 
-       if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
-               gd->dp_alloc_base = savebase;
+       if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
+               gd->arch.dp_alloc_base = savebase;
                panic("m8560_cpm_dpalloc: ran out of dual port ram!");
        }
 
-       retloc = gd->dp_alloc_base;
-       gd->dp_alloc_base += size;
+       retloc = gd->arch.dp_alloc_base;
+       gd->arch.dp_alloc_base += size;
 
        memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
 
@@ -110,7 +111,7 @@ m8560_cpm_hostalloc(uint size, uint align)
  * Baud rate clocks are zero-based in the driver code (as that maps
  * to port numbers).  Documentation uses 1-based numbering.
  */
-#define BRG_INT_CLK    gd->brg_clk
+#define BRG_INT_CLK    gd->arch.brg_clk
 #define BRG_UART_CLK   ((BRG_INT_CLK + 15) / 16)
 
 /* This function is used by UARTS, or anything else that uses a 16x
index 9b9832cfc3363b71d53893f85a7e90b8fbd46895..df2ab6d73cbd73a3872c5263233483f3a277da41 100644 (file)
@@ -104,7 +104,7 @@ int checkcpu (void)
                puts("CPU:   ");
        }
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
 
        puts(cpu->name);
        if (IS_E_PROCESSOR(svr))
index d1155e81263e8d948144cb1d84a3098e3c41f161..de9d9161115d1713fb02ee90c22845b04f7e58bd 100644 (file)
@@ -312,19 +312,33 @@ int enable_cluster_l2(void)
 
        /* Look through the remaining clusters, and set up their caches */
        do {
+               int j, cluster_valid = 0;
+
                l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+
                cluster = in_be32(&gur->tp_cluster[i].lower);
 
-               /* set stash ID to (cluster) * 2 + 32 + 1 */
-               clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+               /* check that at least one core/accel is enabled in cluster */
+               for (j = 0; j < 4; j++) {
+                       u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
+                       u32 type = in_be32(&gur->tp_ityp[idx]);
+
+                       if (type & TP_ITYP_AV)
+                               cluster_valid = 1;
+               }
 
-               printf("enable l2 for cluster %d %p\n", i, l2cache);
+               if (cluster_valid) {
+                       /* set stash ID to (cluster) * 2 + 32 + 1 */
+                       clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
 
-               out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
-               while ((in_be32(&l2cache->l2csr0) &
-                       (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
-                       ;
-               out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+                       printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+                       out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+                       while ((in_be32(&l2cache->l2csr0)
+                               & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+                                       ;
+                       out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+               }
                i++;
        } while (!(cluster & TP_CLUSTER_EOC));
 
@@ -534,6 +548,20 @@ skip_l2:
        /* needs to be in ram since code uses global static vars */
        fsl_serdes_init();
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
+       if (IS_SVR_REV(svr, 1, 0)) {
+               int i;
+               __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
+
+               for (i = 0; i < 12; i++) {
+                       p += i + (i > 5 ? 11 : 0);
+                       out_be32(p, 0x2);
+               }
+               p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
+               out_be32(p, 0x34);
+       }
+#endif
+
 #ifdef CONFIG_SYS_SRIO
        srio_init();
 #ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 
index ab0933076df9352b7ecb401686941c9cf7cbc1c1..24eb9789be9708cd5ffca1d7c4c8d47ad85e29d4 100644 (file)
@@ -100,6 +100,22 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
                        printf("Failed to reserve memory for bootpg: %s\n",
                                fdt_strerror(off));
        }
+
+#ifndef CONFIG_MPC8xxx_DISABLE_BPTR
+       /*
+        * Reserve the default boot page so OSes dont use it.
+        * The default boot page is always mapped to bootpg above using
+        * boot page translation.
+        */
+       if (0xfffff000ull < memory_limit) {
+               off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
+               if (off < 0) {
+                       printf("Failed to reserve memory for 0xfffff000: %s\n",
+                               fdt_strerror(off));
+               }
+       }
+#endif
+
        /* Reserve spin table page */
        if (spin_tbl_addr < memory_limit) {
                off = fdt_add_mem_rsv(blob,
@@ -591,6 +607,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        /* delete crypto node if not on an E-processor */
        if (!IS_E_PROCESSOR(get_svr()))
                fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+       else {
+               ccsr_sec_t __iomem *sec;
+
+               sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+               fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms));
+       }
+#endif
 
        fdt_fixup_ethernet(blob);
 
@@ -613,9 +637,9 @@ void ft_cpu_setup(void *blob, bd_t *bd)
                "bus-frequency", bd->bi_busfreq, 1);
 
        do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
-               "bus-frequency", gd->lbc_clk, 1);
+               "bus-frequency", gd->arch.lbc_clk, 1);
        do_fixup_by_compat_u32(blob, "fsl,elbc",
-               "bus-frequency", gd->lbc_clk, 1);
+               "bus-frequency", gd->arch.lbc_clk, 1);
 #ifdef CONFIG_QE
        ft_qe_setup(blob);
        ft_fixup_qe_snum(blob);
@@ -787,7 +811,7 @@ int ft_verify_fdt(void *fdt)
 #ifdef CONFIG_SYS_LBC_ADDR
        off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
        if (off > 0) {
-               const u32 *reg = fdt_getprop(fdt, off, "reg", NULL);
+               const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
                if (reg) {
                        uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
 
index 801ee078c088c135dfe110aea276ca11a73a045e..297f2ed4739f2080e35207cb9521511c98ee27f8 100644 (file)
@@ -391,11 +391,11 @@ int get_clocks (void)
        gd->cpu_clk = sys_info.freqProcessor[0];
        gd->bus_clk = sys_info.freqSystemBus;
        gd->mem_clk = sys_info.freqDDRBus;
-       gd->lbc_clk = sys_info.freqLocalBus;
+       gd->arch.lbc_clk = sys_info.freqLocalBus;
 
 #ifdef CONFIG_QE
-       gd->qe_clk = sys_info.freqQE;
-       gd->brg_clk = gd->qe_clk / 2;
+       gd->arch.qe_clk = sys_info.freqQE;
+       gd->arch.brg_clk = gd->arch.qe_clk / 2;
 #endif
        /*
         * The base clock for I2C depends on the actual SOC.  Unfortunately,
@@ -406,7 +406,7 @@ int get_clocks (void)
         */
 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
        defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
-       gd->i2c1_clk = sys_info.freqSystemBus;
+       gd->arch.i2c1_clk = sys_info.freqSystemBus;
 #elif defined(CONFIG_MPC8544)
        /*
         * On the 8544, the I2C clock is the same as the SEC clock.  This can be
@@ -416,29 +416,29 @@ int get_clocks (void)
         * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
         */
        if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
-               gd->i2c1_clk = sys_info.freqSystemBus / 3;
+               gd->arch.i2c1_clk = sys_info.freqSystemBus / 3;
        else
-               gd->i2c1_clk = sys_info.freqSystemBus / 2;
+               gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #else
        /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
-       gd->i2c1_clk = sys_info.freqSystemBus / 2;
+       gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #endif
-       gd->i2c2_clk = gd->i2c1_clk;
+       gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
 #if defined(CONFIG_FSL_ESDHC)
 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
        defined(CONFIG_P1014)
-       gd->sdhc_clk = gd->bus_clk;
+       gd->arch.sdhc_clk = gd->bus_clk;
 #else
-       gd->sdhc_clk = gd->bus_clk / 2;
+       gd->arch.sdhc_clk = gd->bus_clk / 2;
 #endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
 #if defined(CONFIG_CPM2)
-       gd->vco_out = 2*sys_info.freqSystemBus;
-       gd->cpm_clk = gd->vco_out / 2;
-       gd->scc_clk = gd->vco_out / 4;
-       gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+       gd->arch.vco_out = 2*sys_info.freqSystemBus;
+       gd->arch.cpm_clk = gd->arch.vco_out / 2;
+       gd->arch.scc_clk = gd->arch.vco_out / 4;
+       gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
 #endif
 
        if(gd->cpu_clk != 0) return (0);
index bb0dc1a653e193fb1f141e13ede0980f0c075198..fb674694e4363bdc14c8e73f0db377f8cb46843d 100644 (file)
@@ -449,7 +449,7 @@ nexti:      mflr    r1              /* R1 = our PC */
 
        /* Set the size of the TLB to 4KB */
        mfspr   r3, MAS1
-       li      r2, 0xF00
+       li      r2, 0xF80
        andc    r3, r3, r2      /* Clear the TSIZE bits */
        ori     r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
        oris    r3, r3, MAS1_IPROT@h
index f44fadcffd80599143faca65b6f38c278e34e097..0dff37f77cd20c26b75c5ff28bd65856a0fc7afa 100644 (file)
@@ -66,7 +66,7 @@ void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
        _mas1 = mfspr(MAS1);
 
        *valid = (_mas1 & MAS1_VALID);
-       *tsize = (_mas1 >> 8) & 0xf;
+       *tsize = (_mas1 >> 7) & 0x1f;
        *epn = mfspr(MAS2) & MAS2_EPN;
        *rpn = mfspr(MAS3) & MAS3_RPN;
 #ifdef CONFIG_ENABLE_36BIT_PHYS
@@ -99,7 +99,7 @@ static inline void use_tlb_cam(u8 idx)
        int i = idx / 32;
        int bit = idx % 32;
 
-       gd->used_tlb_cams[i] |= (1 << bit);
+       gd->arch.used_tlb_cams[i] |= (1 << bit);
 }
 
 static inline void free_tlb_cam(u8 idx)
@@ -107,7 +107,7 @@ static inline void free_tlb_cam(u8 idx)
        int i = idx / 32;
        int bit = idx % 32;
 
-       gd->used_tlb_cams[i] &= ~(1 << bit);
+       gd->arch.used_tlb_cams[i] &= ~(1 << bit);
 }
 
 void init_used_tlb_cams(void)
@@ -116,7 +116,7 @@ void init_used_tlb_cams(void)
        unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
 
        for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
-               gd->used_tlb_cams[i] = 0;
+               gd->arch.used_tlb_cams[i] = 0;
 
        /* walk all the entries */
        for (i = 0; i < num_cam; i++) {
@@ -133,7 +133,7 @@ int find_free_tlbcam(void)
        u32 idx;
 
        for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
-               idx = ffz(gd->used_tlb_cams[i]);
+               idx = ffz(gd->arch.used_tlb_cams[i]);
 
                if (idx != 32)
                        break;
@@ -156,6 +156,13 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
        if (tlb == 1)
                use_tlb_cam(esel);
 
+       if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
+           tsize & 1) {
+               printf("%s: bad tsize %d on entry %d at 0x%08x\n",
+                       __func__, tsize, tlb, epn);
+               return;
+       }
+
        _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
        _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
        _mas2 = FSL_BOOKE_MAS2(epn, wimge);
@@ -251,7 +258,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
        unsigned int tlb_size;
        unsigned int wimge = MAS2_M;
        unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
-       unsigned int max_cam;
+       unsigned int max_cam, tsize_mask;
        u64 size, memsize = (u64)memsize_in_meg << 20;
 
 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
@@ -261,15 +268,17 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
        if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
                /* Convert (4^max) kB to (2^max) bytes */
                max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+               tsize_mask = ~1U;
        } else {
                /* Convert (2^max) kB to (2^max) bytes */
                max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+               tsize_mask = ~0U;
        }
 
        for (i = 0; size && i < 8; i++) {
                int ram_tlb_index = find_free_tlbcam();
-               u32 camsize = __ilog2_u64(size) & ~1U;
-               u32 align = __ilog2(ram_tlb_address) & ~1U;
+               u32 camsize = __ilog2_u64(size) & tsize_mask;
+               u32 align = __ilog2(ram_tlb_address) & tsize_mask;
 
                if (ram_tlb_index == -1)
                        break;
@@ -281,7 +290,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
                if (camsize > max_cam)
                        camsize = max_cam;
 
-               tlb_size = (camsize - 10) / 2;
+               tlb_size = camsize - 10;
 
                set_tlb(1, ram_tlb_address, p_addr,
                        MAS3_SX|MAS3_SW|MAS3_SR, wimge,
index d2c8c78e864b279d88cc9b86e0fbb153b329141d..c553415b555a5a122b5f4966d97c9915ad2efc1e 100644 (file)
@@ -67,7 +67,7 @@ checkcpu(void)
        }
        puts("CPU:   ");
 
-       cpu = gd->cpu;
+       cpu = gd->arch.cpu;
 
        puts(cpu->name);
 
index 2f955fe9309220fcc8af6b6803b30e2624bed76b..26a65c586d5da49ca1f3437594e2ee9a7489f7d2 100644 (file)
@@ -34,10 +34,10 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
 #if defined(CONFIG_MPC8641)
        do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus",
-                              "bus-frequency", gd->lbc_clk, 1);
+                              "bus-frequency", gd->arch.lbc_clk, 1);
 #endif
        do_fixup_by_compat_u32(blob, "fsl,elbc",
-                              "bus-frequency", gd->lbc_clk, 1);
+                              "bus-frequency", gd->arch.lbc_clk, 1);
 
        fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
index a2d0a8ac6ebdf6f75b3661e002318e4ba0651c4c..18c1eea0c1ae1b7242051da35170a26e3044eac5 100644 (file)
@@ -120,7 +120,7 @@ int get_clocks(void)
        get_sys_info(&sys_info);
        gd->cpu_clk = sys_info.freqProcessor;
        gd->bus_clk = sys_info.freqSystemBus;
-       gd->lbc_clk = sys_info.freqLocalBus;
+       gd->arch.lbc_clk = sys_info.freqLocalBus;
 
        /*
         * The base clock for I2C depends on the actual SOC.  Unfortunately,
@@ -130,11 +130,11 @@ int get_clocks(void)
         * AN2919.
         */
 #ifdef CONFIG_MPC8610
-       gd->i2c1_clk = sys_info.freqSystemBus;
+       gd->arch.i2c1_clk = sys_info.freqSystemBus;
 #else
-       gd->i2c1_clk = sys_info.freqSystemBus / 2;
+       gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #endif
-       gd->i2c2_clk = gd->i2c1_clk;
+       gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
        if (gd->cpu_clk != 0)
                return 0;
index 5fe01fffae26f8e4538ea379fafff75ed2aa8935..a364782096778de7dfb1221cb8712de9c595cd30 100644 (file)
@@ -31,8 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
 int dpram_init (void)
 {
        /* Reclaim the DP memory for our use. */
-       gd->dp_alloc_base = CPM_DATAONLY_BASE;
-       gd->dp_alloc_top  = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE;
+       gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+       gd->arch.dp_alloc_top  = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE;
 
        return (0);
 }
@@ -43,19 +43,19 @@ int dpram_init (void)
  */
 uint dpram_alloc (uint size)
 {
-       uint addr = gd->dp_alloc_base;
+       uint addr = gd->arch.dp_alloc_base;
 
-       if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top)
+       if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top)
                return (CPM_DP_NOSPACE);
 
-       gd->dp_alloc_base += size;
+       gd->arch.dp_alloc_base += size;
 
        return addr;
 }
 
 uint dpram_base (void)
 {
-       return gd->dp_alloc_base;
+       return gd->arch.dp_alloc_base;
 }
 
 /* Allocate some memory from the dual ported ram.  We may want to
@@ -66,12 +66,12 @@ uint dpram_alloc_align (uint size, uint align)
 {
        uint addr, mask = align - 1;
 
-       addr = (gd->dp_alloc_base + mask) & ~mask;
+       addr = (gd->arch.dp_alloc_base + mask) & ~mask;
 
-       if ((addr + size) >= gd->dp_alloc_top)
+       if ((addr + size) >= gd->arch.dp_alloc_top)
                return (CPM_DP_NOSPACE);
 
-       gd->dp_alloc_base = addr + size;
+       gd->arch.dp_alloc_base = addr + size;
 
        return addr;
 }
@@ -80,6 +80,6 @@ uint dpram_base_align (uint align)
 {
        uint mask = align - 1;
 
-       return (gd->dp_alloc_base + mask) & ~mask;
+       return (gd->arch.dp_alloc_base + mask) & ~mask;
 }
 #endif /* CONFIG_SYS_ALLOC_DPRAM */
index b3fcfe5626a5e1cb5aadfa16e1acd39c64726a1f..b6b733d77fd356b6231c958f2da326c3468c3855 100644 (file)
@@ -45,7 +45,6 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #include <fdt_support.h>
 #endif
 
index 7130983ff222f19e17d59c395af6fc5fe3a72ac1..7edd7e4204e20e894b11de7ac028edbcc95256bd 100644 (file)
@@ -37,7 +37,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
                "clock-frequency", bd->bi_intfreq, 1);
        do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
-               gd->brg_clk, 1);
+               gd->arch.brg_clk, 1);
 
        /* Fixup ethernet MAC addresses */
        fdt_fixup_ethernet(blob);
index 6e13e5de028b800a4bb2721938aba056cc5b97ee..091b49f24a9f628abaf95ef6b3a0cb8d7ca4eda5 100644 (file)
@@ -192,7 +192,7 @@ void get_brgclk(uint sccr)
                        divider = 64;
                        break;
        }
-       gd->brg_clk = gd->cpu_clk/divider;
+       gd->arch.brg_clk = gd->cpu_clk/divider;
 }
 
 #if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
index e8613be39310ced159744d8115ac2f198c791742..39525fb29d55ed6163a2c748b594a7160b959117 100644 (file)
@@ -86,6 +86,8 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(B4220, B4220, 0),
        CPU_TYPE_ENTRY(BSC9130, 9130, 1),
        CPU_TYPE_ENTRY(BSC9131, 9131, 1),
+       CPU_TYPE_ENTRY(BSC9132, 9132, 2),
+       CPU_TYPE_ENTRY(BSC9232, 9232, 2),
 #elif defined(CONFIG_MPC86xx)
        CPU_TYPE_ENTRY(8610, 8610, 1),
        CPU_TYPE_ENTRY(8641, 8641, 2),
@@ -146,7 +148,7 @@ struct cpu_type *identify_cpu(u32 ver)
 u32 cpu_mask(void)
 {
        ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
 
        /* better to query feature reporting register than just assume 1 */
        if (cpu == &cpu_type_unknown)
@@ -164,7 +166,7 @@ u32 cpu_mask(void)
  */
 int cpu_numcores(void)
 {
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
 
        /*
         * Report # of cores in terms of the cpu_mask if we haven't
@@ -194,7 +196,7 @@ int probecpu (void)
        svr = get_svr();
        ver = SVR_SOC_VER(svr);
 
-       gd->cpu = identify_cpu(ver);
+       gd->arch.cpu = identify_cpu(ver);
 
        return 0;
 }
@@ -202,7 +204,7 @@ int probecpu (void)
 /* Once in memory, compute mask & # cores once and save them off */
 int fixup_cpu(void)
 {
-       struct cpu_type *cpu = gd->cpu;
+       struct cpu_type *cpu = gd->arch.cpu;
 
        if (cpu->num_cores == 0) {
                cpu->mask = cpu_mask();
index 8016bcdc22ec8b54a12ef1d7f7cf7bf4aa0d5f27..26c42f7039033d82a8829e7b48396e6105c2daee 100644 (file)
@@ -1190,7 +1190,11 @@ static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
 {
        unsigned int init_value;        /* Initialization value */
 
+#ifdef CONFIG_MEM_INIT_VALUE
+       init_value = CONFIG_MEM_INIT_VALUE;
+#else
        init_value = 0xDEADBEEF;
+#endif
        ddr->ddr_data_init = init_value;
 }
 
index c8b0f916763340a0fead834dbce1a5fb4411401d..4dd55fc4c3f923ea3bf942346cf41380edc1b8d6 100644 (file)
@@ -86,7 +86,8 @@ void fsl_ddr_set_lawbar(
                unsigned int memctl_interleaved,
                unsigned int ctrl_num);
 
-unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo);
+int fsl_ddr_interactive_env_var_exists(void);
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
                           unsigned int ctrl_num);
 
index cb71f94ba1ecd1540728892dc0bf3c72d3b1f94c..46257c9529ef924dc0c92827d0591a8231d18f48 100644 (file)
@@ -1369,14 +1369,15 @@ struct data_strings {
 
 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
 
-unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
-{
-       unsigned long long ddrsize;
-       const char *prompt = "FSL DDR>";
-       char buffer[CONFIG_SYS_CBSIZE];
-       char *argv[CONFIG_SYS_MAXARGS + 1];     /* NULL terminated */
-       int argc;
-       unsigned int next_step = STEP_GET_SPD;
+static unsigned int fsl_ddr_parse_interactive_cmd(
+       char **argv,
+       int argc,
+       unsigned int *pstep_mask,
+       unsigned int *pctlr_mask,
+       unsigned int *pdimm_mask,
+       unsigned int *pdimm_number_required
+        ) {
+
        static const struct data_strings options[] = {
                DATA_OPTIONS(spd, STEP_GET_SPD, 1),
                DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
@@ -1386,6 +1387,69 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
                DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
        };
        static const unsigned int n_opts = ARRAY_SIZE(options);
+
+       unsigned int i, j;
+       unsigned int error = 0;
+
+       for (i = 1; i < argc; i++) {
+               unsigned int matched = 0;
+
+               for (j = 0; j < n_opts; j++) {
+                       if (strcmp(options[j].data_name, argv[i]) != 0)
+                               continue;
+                       *pstep_mask |= options[j].step_mask;
+                       *pdimm_number_required =
+                               options[j].dimm_number_required;
+                       matched = 1;
+                       break;
+               }
+
+               if (matched)
+                       continue;
+
+               if (argv[i][0] == 'c') {
+                       char c = argv[i][1];
+                       if (isdigit(c))
+                               *pctlr_mask |= 1 << (c - '0');
+                       continue;
+               }
+
+               if (argv[i][0] == 'd') {
+                       char c = argv[i][1];
+                       if (isdigit(c))
+                               *pdimm_mask |= 1 << (c - '0');
+                       continue;
+               }
+
+               printf("unknown arg %s\n", argv[i]);
+               *pstep_mask = 0;
+               error = 1;
+               break;
+       }
+
+       return error;
+}
+
+int fsl_ddr_interactive_env_var_exists(void)
+{
+       char buffer[CONFIG_SYS_CBSIZE];
+
+       if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
+               return 1;
+
+       return 0;
+}
+
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
+{
+       unsigned long long ddrsize;
+       const char *prompt = "FSL DDR>";
+       char buffer[CONFIG_SYS_CBSIZE];
+       char buffer2[CONFIG_SYS_CBSIZE];
+       char *p = NULL;
+       char *argv[CONFIG_SYS_MAXARGS + 1];     /* NULL terminated */
+       int argc;
+       unsigned int next_step = STEP_GET_SPD;
        const char *usage = {
                "commands:\n"
                "print      print SPD and intermediate computed data\n"
@@ -1393,21 +1457,45 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
                "recompute  reload SPD and options to default and recompute regs\n"
                "edit       modify spd, parameter, or option\n"
                "compute    recompute registers from current next_step to end\n"
+               "copy       copy parameters\n"
                "next_step  shows current next_step\n"
                "help       this message\n"
                "go         program the memory controller and continue with u-boot\n"
        };
 
+       if (var_is_set) {
+               if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
+                       p = buffer2;
+               } else {
+                       var_is_set = 0;
+               }
+       }
+
        /*
         * The strategy for next_step is that it points to the next
         * step in the computation process that needs to be done.
         */
        while (1) {
-               /*
-                * No need to worry for buffer overflow here in
-                * this function;  readline() maxes out at CFG_CBSIZE
-                */
-               readline_into_buffer(prompt, buffer, 0);
+               if (var_is_set) {
+                       char *pend = strchr(p, ';');
+                       if (pend) {
+                               /* found command separator, copy sub-command */
+                               *pend = '\0';
+                               strcpy(buffer, p);
+                               p = pend + 1;
+                       } else {
+                               /* separator not found, copy whole string */
+                               strcpy(buffer, p);
+                               p = NULL;
+                               var_is_set = 0;
+                       }
+               } else {
+                       /*
+                        * No need to worry for buffer overflow here in
+                        * this function;  readline() maxes out at CFG_CBSIZE
+                        */
+                       readline_into_buffer(prompt, buffer, 0);
+               }
                argc = parse_line(buffer, argv);
                if (argc == 0)
                        continue;
@@ -1425,64 +1513,160 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
                        continue;
                }
 
-               if (strcmp(argv[0], "edit") == 0) {
-                       unsigned int i, j;
+               if (strcmp(argv[0], "copy") == 0) {
                        unsigned int error = 0;
                        unsigned int step_mask = 0;
-                       unsigned int ctlr_mask = 0;
-                       unsigned int dimm_mask = 0;
-                       char *p_element = NULL;
-                       char *p_value = NULL;
+                       unsigned int src_ctlr_mask = 0;
+                       unsigned int src_dimm_mask = 0;
                        unsigned int dimm_number_required = 0;
-                       unsigned int ctrl_num;
-                       unsigned int dimm_num;
-                       unsigned int matched = 0;
+                       unsigned int src_ctlr_num = 0;
+                       unsigned int src_dimm_num = 0;
+                       unsigned int dst_ctlr_num = -1;
+                       unsigned int dst_dimm_num = -1;
+                       unsigned int i, num_dest_parms;
 
                        if (argc == 1) {
-                               /* Only the element and value must be last */
-                               printf("edit <c#> <d#> "
-                                       "<spd|dimmparms|commonparms|opts|"
-                                       "addresses|regs> <element> <value>\n");
-                               printf("for spd, specify byte number for "
-                                       "element\n");
+                               printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
                                continue;
                        }
 
-                       for (i = 1; i < argc - 2; i++) {
-                               for (j = 0; j < n_opts; j++) {
-                                       if (strcmp(options[j].data_name,
-                                               argv[i]) != 0)
-                                               continue;
-                                       step_mask |= options[j].step_mask;
-                                       dimm_number_required =
-                                               options[j].dimm_number_required;
-                                       matched = 1;
-                                       break;
+                       error = fsl_ddr_parse_interactive_cmd(
+                               argv, argc,
+                               &step_mask,
+                               &src_ctlr_mask,
+                               &src_dimm_mask,
+                               &dimm_number_required
+                       );
+
+                       /* XXX: only dimm_number_required and step_mask will
+                          be used by this function.  Parse the controller and
+                          DIMM number separately because it is easier.  */
+
+                       if (error)
+                               continue;
+
+                       /* parse source destination controller / DIMM */
+
+                       num_dest_parms = dimm_number_required ? 2 : 1;
+
+                       for (i = 0; i < argc; i++) {
+                               if (argv[i][0] == 'c') {
+                                       char c = argv[i][1];
+                                       if (isdigit(c)) {
+                                               src_ctlr_num = (c - '0');
+                                               break;
+                                       }
                                }
+                       }
 
-                               if (matched)
-                                       continue;
+                       for (i = 0; i < argc; i++) {
+                               if (argv[i][0] == 'd') {
+                                       char c = argv[i][1];
+                                       if (isdigit(c)) {
+                                               src_dimm_num = (c - '0');
+                                               break;
+                                       }
+                               }
+                       }
+
+                       /* parse destination controller / DIMM */
 
+                       for (i = argc - 1; i >= argc - num_dest_parms; i--) {
                                if (argv[i][0] == 'c') {
                                        char c = argv[i][1];
-                                       if (isdigit(c))
-                                               ctlr_mask |= 1 << (c - '0');
-                                       continue;
+                                       if (isdigit(c)) {
+                                               dst_ctlr_num = (c - '0');
+                                               break;
+                                       }
                                }
+                       }
 
+                       for (i = argc - 1; i >= argc - num_dest_parms; i--) {
                                if (argv[i][0] == 'd') {
                                        char c = argv[i][1];
-                                       if (isdigit(c))
-                                               dimm_mask |= 1 << (c - '0');
-                                       continue;
+                                       if (isdigit(c)) {
+                                               dst_dimm_num = (c - '0');
+                                               break;
+                                       }
                                }
+                       }
+
+                       /* TODO: validate inputs */
+
+                       debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
+                               src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
 
-                               printf("unknown arg %s\n", argv[i]);
-                               step_mask = 0;
-                               error = 1;
+
+                       switch (step_mask) {
+
+                       case STEP_GET_SPD:
+                               memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
+                                       &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
+                                       sizeof(pinfo->spd_installed_dimms[0][0]));
                                break;
+
+                       case STEP_COMPUTE_DIMM_PARMS:
+                               memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
+                                       &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
+                                       sizeof(pinfo->dimm_params[0][0]));
+                               break;
+
+                       case STEP_COMPUTE_COMMON_PARMS:
+                               memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
+                                       &(pinfo->common_timing_params[src_ctlr_num]),
+                                       sizeof(pinfo->common_timing_params[0]));
+                               break;
+
+                       case STEP_GATHER_OPTS:
+                               memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
+                                       &(pinfo->memctl_opts[src_ctlr_num]),
+                                       sizeof(pinfo->memctl_opts[0]));
+                               break;
+
+                       /* someday be able to have addresses to copy addresses... */
+
+                       case STEP_COMPUTE_REGS:
+                               memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
+                                       &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
+                                       sizeof(pinfo->memctl_opts[0]));
+                               break;
+
+                       default:
+                               printf("unexpected step_mask value\n");
+                       }
+
+                       continue;
+
+               }
+
+               if (strcmp(argv[0], "edit") == 0) {
+                       unsigned int error = 0;
+                       unsigned int step_mask = 0;
+                       unsigned int ctlr_mask = 0;
+                       unsigned int dimm_mask = 0;
+                       char *p_element = NULL;
+                       char *p_value = NULL;
+                       unsigned int dimm_number_required = 0;
+                       unsigned int ctrl_num;
+                       unsigned int dimm_num;
+
+                       if (argc == 1) {
+                               /* Only the element and value must be last */
+                               printf("edit <c#> <d#> "
+                                       "<spd|dimmparms|commonparms|opts|"
+                                       "addresses|regs> <element> <value>\n");
+                               printf("for spd, specify byte number for "
+                                       "element\n");
+                               continue;
                        }
 
+                       error = fsl_ddr_parse_interactive_cmd(
+                               argv, argc - 2,
+                               &step_mask,
+                               &ctlr_mask,
+                               &dimm_mask,
+                               &dimm_number_required
+                       );
 
                        if (error)
                                continue;
@@ -1629,12 +1813,11 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
                }
 
                if (strcmp(argv[0], "print") == 0) {
-                       unsigned int i, j;
                        unsigned int error = 0;
                      &n