| author | Stefano Babic <sbabic@denx.de> | |
| Sat, 23 Feb 2013 09:13:40 +0000 (10:13 +0100) | ||
| committer | Stefano Babic <sbabic@denx.de> | |
| Sat, 23 Feb 2013 09:13:40 +0000 (10:13 +0100) |
487 files changed:
diff --git a/MAINTAINERS b/MAINTAINERS
index faa9b5e92f8fe35e2d2bc6da139fe8d6097bd354..175bbe26669c38096240483e9c072d2b99c06206 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
BSC9131RDB BSC9131
+Naveen Burmi <NaveenBurmi@freescale.com>
+
+ BSC9132QDS BSC9132
+
Greg Allen <gallen@arlut.utexas.edu>
UTX8245 MPC8245
igep0020 ARM ARMV7 (OMAP3xx SoC)
igep0030 ARM ARMV7 (OMAP3xx SoC)
+ igep0032 ARM ARMV7 (OMAP3xx SoC)
Eric Benard <eric@eukrea.com>
omap730p2 ARM926EJS
+Lars Poeschel <poeschel@lemonage.de>
+ pcm051 ARM ARMV7 (AM33xx Soc)
+
Mathieu Poirier <mathieu.poirier@linaro.org>
snowball ARM ARMV7 (u8500 SoC)
diff --git a/Makefile b/Makefile
index a8c7b7b77a9ba988e1d8b5cdf1414c4c4be09aa6..33d4253e78ec179e75cdcd6939596115ed69034f 100644 (file)
--- a/Makefile
+++ b/Makefile
# U-Boot objects....order is important (i.e. start must be first)
OBJS = $(CPUDIR)/start.o
-ifeq ($(CPU),x86)
-RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/start16.o
-RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += $(CPUDIR)/resetvec.o
-endif
ifeq ($(CPU),ppc4xx)
OBJS += $(CPUDIR)/resetvec.o
endif
OBJS += $(CPUDIR)/resetvec.o
endif
-OBJS := $(addprefix $(obj),$(OBJS) $(RESET_OBJS-))
+OBJS := $(addprefix $(obj),$(OBJS))
HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
ifeq ($(SOC),exynos)
LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
endif
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
# enable combined SPL/u-boot/dtb rules for tegra
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_OF_SEPARATE),y)
ALL-y += $(obj)u-boot-dtb-tegra.bin
else
$(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $< > $@
+
+
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(or $(CONFIG_SPL_PAD_TO),0) \
+ -O binary $(obj)spl/u-boot-spl \
+ $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
conv=notrunc 2>/dev/null
cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
ifeq ($(CONFIG_OF_SEPARATE),y)
nodtb=dtb
dtbfile=$(obj)u-boot.dtb
index a33647623767f52c971e5ca2cc70c653cecf24dc..d8cb3940d4f04810dcc6fe88a5f03f0b0cd5d8a8 100644 (file)
--- a/README
+++ b/README
CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME
Filename to read to load U-Boot when reading from FAT
+ CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
+ Set this for NAND SPL on PPC mpc83xx targets, so that
+ start.S waits for the rest of the SPL to load before
+ continuing (the hardware starts execution after just
+ loading the first page rather than the full 4K).
+
CONFIG_SPL_NAND_BASE
Include nand_base.c in the SPL. Requires
CONFIG_SPL_NAND_DRIVERS.
CONFIG_SPL_LIBGENERIC_SUPPORT
Support for lib/libgeneric.o in SPL binary
+ CONFIG_SPL_PAD_TO
+ Linker address to which the SPL should be padded before
+ appending the SPL payload.
+
CONFIG_SPL_TARGET
Final target image containing SPL and payload. Some SPLs
use an arch-specific makefile fragment instead, for
be used if available. These functions may be faster under some
conditions but may increase the binary size.
-- CONFIG_X86_NO_RESET_VECTOR
- If defined, the x86 reset vector code is excluded. You will need
- to do this when U-Boot is running from Coreboot.
-
-- CONFIG_X86_NO_REAL_MODE
- If defined, x86 real mode code is omitted. This assumes a
- 32-bit environment where such code is not needed. You will
- need to do this when U-Boot is running from Coreboot.
+- CONFIG_X86_RESET_VECTOR
+ If defined, the x86 reset vector code is included. This is not
+ needed when U-Boot is running from Coreboot.
Freescale QE/FMAN Firmware Support:
index 86916d1edb1c603f40039b5ab3ae8da05ef0cbc1..b006b6015de45928b668049b2e0ed7a1fdea833b 100644 (file)
{
ulong now = GPTCNT; /* current tick value */
- if (now >= gd->lastinc) /* normal mode (non roll) */
+ if (now >= gd->arch.lastinc) /* normal mode (non roll) */
/* move stamp forward with absolut diff ticks */
- gd->tbl += (now - gd->lastinc);
+ gd->arch.tbl += (now - gd->arch.lastinc);
else /* we have rollover of incrementer */
- gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
- gd->lastinc = now;
- return gd->tbl;
+ gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
+ gd->arch.lastinc = now;
+ return gd->arch.tbl;
}
ulong get_timer_masked(void)
index 295a98ea4b6d5fabf9de1c01fb03a4f40c668b94..d11e6f6270cd4b3c5a2e8b5b99380a7a61045536 100644 (file)
{
#ifdef CONFIG_FSL_ESDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#else
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
index 9680b7fde7bb18a6bb0615c698c76094a612b438..584ad15135cf58ca0b024ff53a931c96b2936681 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp (gd->tbl)
-#define lastinc (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastinc (gd->arch.lastinc)
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
index e929ae45bbf7023248608d3cf055692da423fc7f..53015cb77dc954016d6bbbec541d4d9c54d8cd02 100644 (file)
*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val; /* start timer */
/* reset time */
- gd->lastinc = READ_TIMER; /* capture current incrementer value */
- gd->tbl = 0; /* start "advancing" time stamp */
+ gd->arch.lastinc = READ_TIMER; /* capture current incrementer value */
+ gd->arch.tbl = 0; /* start "advancing" time stamp */
return(0);
}
tmp = get_timer (0); /* get current timestamp */
if ((tmo + tmp + 1) < tmp) { /* if setting this forward will roll */
/* time stamp, then reset time */
- gd->lastinc = READ_TIMER; /* capture incrementer value */
- gd->tbl = 0; /* start time stamp */
+ gd->arch.lastinc = READ_TIMER; /* capture incrementer value */
+ gd->arch.tbl = 0; /* start time stamp */
} else {
tmo += tmp; /* else, set advancing stamp wake up time */
}
{
ulong now = READ_TIMER; /* current tick value */
- if (now >= gd->lastinc) /* normal mode (non roll) */
- gd->tbl += (now - gd->lastinc); /* move stamp fordward with absoulte diff ticks */
- else /* we have rollover of incrementer */
- gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
- gd->lastinc = now;
- return gd->tbl;
+ if (now >= gd->arch.lastinc) { /* normal mode (non roll) */
+ /* move stamp fordward with absoulte diff ticks */
+ gd->arch.tbl += (now - gd->arch.lastinc);
+ } else {
+ /* we have rollover of incrementer */
+ gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
+ }
+ gd->arch.lastinc = now;
+ return gd->arch.tbl;
}
/* waits specified delay value and resets timestamp */
diff --git a/arch/arm/cpu/arm720t/tegra-common/Makefile b/arch/arm/cpu/arm720t/tegra-common/Makefile
index febd2e301fd9f0bc86777b2860cfbe6b16bcc63b..6cbc6adaa16667b0c77b7c1436e561c6853d7510 100644 (file)
LIB = $(obj)libtegra-common.o
COBJS-$(CONFIG_SPL_BUILD) += spl.o
+COBJS-y += cpu.o
SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
--- /dev/null
@@ -0,0 +1,333 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include "cpu.h"
+
+int get_num_cpus(void)
+{
+ struct apb_misc_gp_ctlr *gp;
+ uint rev;
+
+ gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+ rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
+
+ switch (rev) {
+ case CHIPID_TEGRA20:
+ return 2;
+ break;
+ case CHIPID_TEGRA30:
+ case CHIPID_TEGRA114:
+ default:
+ return 4;
+ break;
+ }
+}
+
+/*
+ * Timing tables for each SOC for all four oscillator options.
+ */
+struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
+ /* T20: 1 GHz */
+ /* n, m, p, cpcon */
+ {{ 1000, 13, 0, 12}, /* OSC 13M */
+ { 625, 12, 0, 8}, /* OSC 19.2M */
+ { 1000, 12, 0, 12}, /* OSC 12M */
+ { 1000, 26, 0, 12}, /* OSC 26M */
+ },
+
+ /* T25: 1.2 GHz */
+ {{ 923, 10, 0, 12},
+ { 750, 12, 0, 8},
+ { 600, 6, 0, 12},
+ { 600, 13, 0, 12},
+ },
+
+ /* T30: 1.4 GHz */
+ {{ 862, 8, 0, 8},
+ { 583, 8, 0, 4},
+ { 700, 6, 0, 8},
+ { 700, 13, 0, 8},
+ },
+
+ /* T114: 1.4 GHz */
+ {{ 862, 8, 0, 8},
+ { 583, 8, 0, 4},
+ { 696, 12, 0, 8},
+ { 700, 13, 0, 8},
+ },
+};
+
+void adjust_pllp_out_freqs(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
+ u32 reg;
+
+ /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+ reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
+ reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
+ | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
+ writel(reg, &pll->pll_out[0]);
+
+ reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
+ reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
+ | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
+ writel(reg, &pll->pll_out[1]);
+}
+
+int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
+ u32 divp, u32 cpcon)
+{
+ u32 reg;
+
+ /* If PLLX is already enabled, just return */
+ if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
+ debug("pllx_set_rate: PLLX already enabled, returning\n");
+ return 0;
+ }
+
+ debug(" pllx_set_rate entry\n");
+
+ /* Set BYPASS, m, n and p to PLLX_BASE */
+ reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
+ reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
+ writel(reg, &pll->pll_base);
+
+ /* Set cpcon to PLLX_MISC */
+ reg = (cpcon << PLL_CPCON_SHIFT);
+
+ /* Set dccon to PLLX_MISC if freq > 600MHz */
+ if (divn > 600)
+ reg |= (1 << PLL_DCCON_SHIFT);
+ writel(reg, &pll->pll_misc);
+
+ /* Enable PLLX */
+ reg = readl(&pll->pll_base);
+ reg |= PLL_ENABLE_MASK;
+
+ /* Disable BYPASS */
+ reg &= ~PLL_BYPASS_MASK;
+ writel(reg, &pll->pll_base);
+
+ /* Set lock_enable to PLLX_MISC */
+ reg = readl(&pll->pll_misc);
+ reg |= PLL_LOCK_ENABLE_MASK;
+ writel(reg, &pll->pll_misc);
+
+ return 0;
+}
+
+void init_pllx(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
+ int chip_type;
+ enum clock_osc_freq osc;
+ struct clk_pll_table *sel;
+
+ debug("init_pllx entry\n");
+
+ /* get chip type */
+ chip_type = tegra_get_chip_type();
+ debug(" init_pllx: chip_type = %d\n", chip_type);
+
+ /* get osc freq */
+ osc = clock_get_osc_freq();
+ debug(" init_pllx: osc = %d\n", osc);
+
+ /* set pllx */
+ sel = &tegra_pll_x_table[chip_type][osc];
+ pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
+
+ /* adjust PLLP_out1-4 on T30/T114 */
+ if (chip_type == TEGRA_SOC_T30 || chip_type == TEGRA_SOC_T114) {
+ debug(" init_pllx: adjusting PLLP out freqs\n");
+ adjust_pllp_out_freqs();
+ }
+}
+
+void enable_cpu_clock(int enable)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 clk;
+
+ /*
+ * NOTE:
+ * Regardless of whether the request is to enable or disable the CPU
+ * clock, every processor in the CPU complex except the master (CPU 0)
+ * will have it's clock stopped because the AVP only talks to the
+ * master.
+ */
+
+ if (enable) {
+ /* Initialize PLLX */
+ init_pllx();
+
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+ }
+
+ /*
+ * Read the register containing the individual CPU clock enables and
+ * always stop the clocks to CPUs > 0.
+ */
+ clk = readl(&clkrst->crc_clk_cpu_cmplx);
+ clk |= 1 << CPU1_CLK_STP_SHIFT;
+ if (get_num_cpus() == 4)
+ clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
+
+ /* Stop/Unstop the CPU clock */
+ clk &= ~CPU0_CLK_STP_MASK;
+ clk |= !enable << CPU0_CLK_STP_SHIFT;
+ writel(clk, &clkrst->crc_clk_cpu_cmplx);
+
+ clock_enable(PERIPH_ID_CPU);
+}
+
+static int is_cpu_powered(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
+}
+
+static void remove_cpu_io_clamps(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ /* Remove the clamps on the CPU I/O signals */
+ reg = readl(&pmc->pmc_remove_clamping);
+ reg |= CPU_CLMP;
+ writel(reg, &pmc->pmc_remove_clamping);
+
+ /* Give I/O signals time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+}
+
+void powerup_cpu(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+ int timeout = IO_STABILIZATION_DELAY;
+
+ if (!is_cpu_powered()) {
+ /* Toggle the CPU power state (OFF -> ON) */
+ reg = readl(&pmc->pmc_pwrgate_toggle);
+ reg &= PARTID_CP;
+ reg |= START_CP;
+ writel(reg, &pmc->pmc_pwrgate_toggle);
+
+ /* Wait for the power to come up */
+ while (!is_cpu_powered()) {
+ if (timeout-- == 0)
+ printf("CPU failed to power up!\n");
+ else
+ udelay(10);
+ }
+
+ /*
+ * Remove the I/O clamps from CPU power partition.
+ * Recommended only on a Warm boot, if the CPU partition gets
+ * power gated. Shouldn't cause any harm when called after a
+ * cold boot according to HW, probably just redundant.
+ */
+ remove_cpu_io_clamps();
+ }
+}
+
+void reset_A9_cpu(int reset)
+{
+ /*
+ * NOTE: Regardless of whether the request is to hold the CPU in reset
+ * or take it out of reset, every processor in the CPU complex
+ * except the master (CPU 0) will be held in reset because the
+ * AVP only talks to the master. The AVP does not know that there
+ * are multiple processors in the CPU complex.
+ */
+ int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
+ int num_cpus = get_num_cpus();
+ int cpu;
+
+ debug("reset_a9_cpu entry\n");
+ /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
+ for (cpu = 1; cpu < num_cpus; cpu++)
+ reset_cmplx_set_enable(cpu, mask, 1);
+ reset_cmplx_set_enable(0, mask, reset);
+
+ /* Enable/Disable master CPU reset */
+ reset_set_enable(PERIPH_ID_CPU, reset);
+}
+
+void clock_enable_coresight(int enable)
+{
+ u32 rst, src = 2;
+ int chip;
+
+ debug("clock_enable_coresight entry\n");
+ clock_set_enable(PERIPH_ID_CORESIGHT, enable);
+ reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
+
+ if (enable) {
+ /*
+ * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
+ * 1.5, giving an effective frequency of 144MHz.
+ * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
+ * (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
+ *
+ * Clock divider request for 204MHz would setup CSITE clock as
+ * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
+ */
+ chip = tegra_get_chip_type();
+ if (chip == TEGRA_SOC_T30 || chip == TEGRA_SOC_T114)
+ src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
+ else if (chip == TEGRA_SOC_T20 || chip == TEGRA_SOC_T25)
+ src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
+ else
+ printf("%s: Unknown chip type %X!\n", __func__, chip);
+ clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
+
+ /* Unlock the CPU CoreSight interfaces */
+ rst = CORESIGHT_UNLOCK;
+ writel(rst, CSITE_CPU_DBG0_LAR);
+ writel(rst, CSITE_CPU_DBG1_LAR);
+ if (get_num_cpus() == 4) {
+ writel(rst, CSITE_CPU_DBG2_LAR);
+ writel(rst, CSITE_CPU_DBG3_LAR);
+ }
+ }
+}
+
+void halt_avp(void)
+{
+ for (;;) {
+ writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
+ | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
+ FLOW_CTLR_HALT_COP_EVENTS);
+ }
+}
index 6804cd7a3df7159172e1486e3207750d9e5be9c9..e8e05d77aab1c807f6fed6aaef1dd2d26d59c404 100644 (file)
#define PLL_STABILIZATION_DELAY (300)
#define IO_STABILIZATION_DELAY (1000)
+#if defined(CONFIG_TEGRA20)
#define NVBL_PLLP_KHZ (216000)
+#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
+#define NVBL_PLLP_KHZ (408000)
+#else
+#error "Unknown Tegra chip!"
+#endif
#define PLLX_ENABLED (1 << 30)
#define CCLK_BURST_POLICY 0x20008888
#define CORESIGHT_UNLOCK 0xC5ACCE55;
-/* AP20-Specific Base Addresses */
-
-/* AP20 Base physical address of SDRAM. */
-#define AP20_BASE_PA_SDRAM 0x00000000
-/* AP20 Base physical address of internal SRAM. */
-#define AP20_BASE_PA_SRAM 0x40000000
-/* AP20 Size of internal SRAM (256KB). */
-#define AP20_BASE_PA_SRAM_SIZE 0x00040000
-/* AP20 Base physical address of flash. */
-#define AP20_BASE_PA_NOR_FLASH 0xD0000000
-/* AP20 Base physical address of boot information table. */
-#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
-
-/*
- * Super-temporary stacks for EXTREMELY early startup. The values chosen for
- * these addresses must be valid on ALL SOCs because this value is used before
- * we are able to differentiate between the SOC types.
- *
- * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
- * stack is placed below the AVP stack. Once the CPU stack has been moved,
- * the AVP is free to use the IRAM the CPU stack previously occupied if
- * it should need to do so.
- *
- * NOTE: In multi-processor CPU complex configurations, each processor will have
- * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
- * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
- * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
- * CPU.
- */
-
-/* Common AVP early boot stack limit */
-#define AVP_EARLY_BOOT_STACK_LIMIT \
- (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
-/* Common AVP early boot stack size */
-#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
-/* Common CPU early boot stack limit */
-#define CPU_EARLY_BOOT_STACK_LIMIT \
- (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
-/* Common CPU early boot stack size */
-#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
-
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
#define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
+#define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
+#define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
#define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
#define FLOW_MODE_STOP 2
#define HALT_COP_EVENT_IRQ_1 (1 << 11)
#define HALT_COP_EVENT_FIQ_1 (1 << 9)
-void start_cpu(u32 reset_vector);
-int ap20_cpu_is_cortexa9(void);
+#define FLOW_MODE_NONE 0
+
+#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
+
+struct clk_pll_table {
+ u16 n;
+ u16 m;
+ u8 p;
+ u8 cpcon;
+};
+
+void clock_enable_coresight(int enable);
+void enable_cpu_clock(int enable);
void halt_avp(void) __attribute__ ((noreturn));
+void init_pllx(void);
+void powerup_cpu(void);
+void reset_A9_cpu(int reset);
+void start_cpu(u32 reset_vector);
+int tegra_get_chip_type(void);
+void adjust_pllp_out_freqs(void);
index c280ab7d0f9c89bc60fec15077709087999da0fe..a9a1c39c73e0ef31175242e488a7910d56c2ea0c 100644 (file)
* MA 02111-1307 USA
*/
#include <common.h>
-#include "cpu.h"
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch/spl.h>
-
+#include "cpu.h"
void spl_board_init(void)
{
diff --git a/arch/arm/cpu/arm720t/tegra114/Makefile b/arch/arm/cpu/arm720t/tegra114/Makefile
--- /dev/null
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+#COBJS-y += cpu.o t11x.o
+COBJS-y += cpu.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm720t/tegra114/config.mk b/arch/arm/cpu/arm720t/tegra114/config.mk
--- /dev/null
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c
--- /dev/null
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra114-specific CPU init code */
+static void enable_cpu_power_rail(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ debug("enable_cpu_power_rail entry\n");
+
+ /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+ pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
+ pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+
+ /*
+ * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+ * set it for 25ms (102MHz * .025)
+ */
+ reg = 0x26E8F0;
+ writel(reg, &pmc->pmc_cpupwrgood_timer);
+
+ /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+ clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+ setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+
+ /*
+ * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
+ * to 408 to satisfy the requirement of having at least 16 CPU clock
+ * cycles before clamp removal.
+ */
+
+ clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
+ setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
+}
+
+static void enable_cpu_clocks(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ debug("enable_cpu_clocks entry\n");
+
+ /* Wait for PLL-X to lock */
+ do {
+ reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+ } while ((reg & (1 << 27)) == 0);
+
+ /* Wait until all clocks are stable */
+ udelay(PLL_STABILIZATION_DELAY);
+
+ writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+ writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+ /* Always enable the main CPU complex clocks */
+ clock_enable(PERIPH_ID_CPU);
+ clock_enable(PERIPH_ID_CPULP);
+ clock_enable(PERIPH_ID_CPUG);
+}
+
+static void remove_cpu_resets(void)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ debug("remove_cpu_resets entry\n");
+ /* Take the slow non-CPU partition out of reset */
+ reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
+ writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
+
+ /* Take the fast non-CPU partition out of reset */
+ reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
+ writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
+
+ /* Clear the SW-controlled reset of the slow cluster */
+ reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
+ reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
+ writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+ /* Clear the SW-controlled reset of the fast cluster */
+ reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
+ reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
+ reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
+ reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
+ reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
+ writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The T114 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void t114_init_clocks(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ u32 val;
+
+ debug("t114_init_clocks entry\n");
+
+ /* Set active CPU cluster to G */
+ clrbits_le32(&flow->cluster_control, 1);
+
+ /*
+ * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
+ * at 108 MHz. This is glitch free as only the source is changed, no
+ * special precaution needed.
+ */
+ val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+ (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+ (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+ (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+ (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+ writel(val, &clkrst->crc_sclk_brst_pol);
+
+ writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
+
+ debug("Setting up PLLX\n");
+ init_pllx();
+
+ val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+ writel(val, &clkrst->crc_clk_sys_rate);
+
+ /* Enable clocks to required peripherals. TBD - minimize this list */
+ debug("Enabling clocks\n");
+
+ clock_set_enable(PERIPH_ID_CACHE2, 1);
+ clock_set_enable(PERIPH_ID_GPIO, 1);
+ clock_set_enable(PERIPH_ID_TMR, 1);
+ clock_set_enable(PERIPH_ID_RTC, 1);
+ clock_set_enable(PERIPH_ID_CPU, 1);
+ clock_set_enable(PERIPH_ID_EMC, 1);
+ clock_set_enable(PERIPH_ID_I2C5, 1);
+ clock_set_enable(PERIPH_ID_FUSE, 1);
+ clock_set_enable(PERIPH_ID_PMC, 1);
+ clock_set_enable(PERIPH_ID_APBDMA, 1);
+ clock_set_enable(PERIPH_ID_MEM, 1);
+ clock_set_enable(PERIPH_ID_IRAMA, 1);
+ clock_set_enable(PERIPH_ID_IRAMB, 1);
+ clock_set_enable(PERIPH_ID_IRAMC, 1);
+ clock_set_enable(PERIPH_ID_IRAMD, 1);
+ clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+ clock_set_enable(PERIPH_ID_MSELECT, 1);
+ clock_set_enable(PERIPH_ID_EMC1, 1);
+ clock_set_enable(PERIPH_ID_MC1, 1);
+ clock_set_enable(PERIPH_ID_DVFS, 1);
+
+ /* Switch MSELECT clock to PLLP (00) */
+ clock_ll_set_source(PERIPH_ID_MSELECT, 0);
+
+ /*
+ * Clock divider request for 102MHz would setup MSELECT clock as
+ * 102MHz for PLLP base 408MHz
+ */
+ clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+ (NVBL_PLLP_KHZ/102000));
+
+ /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+ clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+ /* Give clocks time to stabilize */
+ udelay(1000);
+
+ /* Take required peripherals out of reset */
+ debug("Taking periphs out of reset\n");
+ reset_set_enable(PERIPH_ID_CACHE2, 0);
+ reset_set_enable(PERIPH_ID_GPIO, 0);
+ reset_set_enable(PERIPH_ID_TMR, 0);
+ reset_set_enable(PERIPH_ID_COP, 0);
+ reset_set_enable(PERIPH_ID_EMC, 0);
+ reset_set_enable(PERIPH_ID_I2C5, 0);
+ reset_set_enable(PERIPH_ID_FUSE, 0);
+ reset_set_enable(PERIPH_ID_APBDMA, 0);
+ reset_set_enable(PERIPH_ID_MEM, 0);
+ reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+ reset_set_enable(PERIPH_ID_MSELECT, 0);
+ reset_set_enable(PERIPH_ID_EMC1, 0);
+ reset_set_enable(PERIPH_ID_MC1, 0);
+
+ debug("t114_init_clocks exit\n");
+}
+
+static int is_partition_powered(u32 mask)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ /* Get power gate status */
+ reg = readl(&pmc->pmc_pwrgate_status);
+ return (reg & mask) == mask;
+}
+
+static int is_clamp_enabled(u32 mask)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
+ reg = readl(&pmc->pmc_pwrgate_timer_on);
+ return (reg & mask) == mask;
+}
+
+static void power_partition(u32 status, u32 partid)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+ debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
+ /* Is the partition already on? */
+ if (!is_partition_powered(status)) {
+ /* No, toggle the partition power state (OFF -> ON) */
+ debug("power_partition, toggling state\n");
+ clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
+ setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
+ setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
+
+ /* Wait for the power to come up */
+ while (!is_partition_powered(status))
+ ;
+
+ /* Wait for the clamp status to be cleared */
+ while (is_clamp_enabled(status))
+ ;
+
+ /* Give I/O signals time to stabilize */
+ udelay(IO_STABILIZATION_DELAY);
+ }
+}
+
+void powerup_cpus(void)
+{
+ debug("powerup_cpus entry\n");
+
+ /* We boot to the fast cluster */
+ debug("powerup_cpus entry: G cluster\n");
+ /* Power up the fast cluster rail partition */
+ power_partition(CRAIL, CRAILID);
+
+ /* Power up the fast cluster non-CPU partition */
+ power_partition(C0NC, C0NCID);
+
+ /* Power up the fast cluster CPU0 partition */
+ power_partition(CE0, CE0ID);
+}
+
+void start_cpu(u32 reset_vector)
+{
+ debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+ t114_init_clocks();
+
+ /* Enable VDD_CPU */
+ enable_cpu_power_rail();
+
+ /* Get the CPU(s) running */
+ enable_cpu_clocks();
+
+ /* Enable CoreSight */
+ clock_enable_coresight(1);
+
+ /* Take CPU(s) out of reset */
+ remove_cpu_resets();
+
+ /*
+ * Set the entry point for CPU execution from reset,
+ * if it's a non-zero value.
+ */
+ if (reset_vector)
+ writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+ /* If the CPU(s) don't already have power, power 'em up */
+ powerup_cpus();
+}
index ef7f375e79de92a1336d64aed2efc8ab02157964..253389955fb2a7b045c09e08e633c2fed80b9093 100644 (file)
/*
-* (C) Copyright 2010-2011
-* NVIDIA Corporation <www.nvidia.com>
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
#include "../tegra-common/cpu.h"
-/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
-int ap20_cpu_is_cortexa9(void)
-{
- u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
- return id == (PG_UP_TAG_0_PID_CPU & 0xff);
-}
-
-void init_pllx(void)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
- u32 reg;
-
- /* If PLLX is already enabled, just return */
- if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
- return;
-
- /* Set PLLX_MISC */
- writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
-
- /* Use 12MHz clock here */
- reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
- reg |= 1000 << PLL_DIVN_SHIFT;
- writel(reg, &pll->pll_base);
-
- reg |= PLL_ENABLE_MASK;
- writel(reg, &pll->pll_base);
-
- reg &= ~PLL_BYPASS_MASK;
- writel(reg, &pll->pll_base);
-}
-
-static void enable_cpu_clock(int enable)
-{
- struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 clk;
-
- /*
- * NOTE:
- * Regardless of whether the request is to enable or disable the CPU
- * clock, every processor in the CPU complex except the master (CPU 0)
- * will have it's clock stopped because the AVP only talks to the
- * master. The AVP does not know (nor does it need to know) that there
- * are multiple processors in the CPU complex.
- */
-
- if (enable) {
- /* Initialize PLLX */
- init_pllx();
-
- /* Wait until all clocks are stable */
- udelay(PLL_STABILIZATION_DELAY);
-
- writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
- writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
- }
-
- /*
- * Read the register containing the individual CPU clock enables and
- * always stop the clock to CPU 1.
- */
- clk = readl(&clkrst->crc_clk_cpu_cmplx);
- clk |= 1 << CPU1_CLK_STP_SHIFT;
-
- /* Stop/Unstop the CPU clock */
- clk &= ~CPU0_CLK_STP_MASK;
- clk |= !enable << CPU0_CLK_STP_SHIFT;
- writel(clk, &clkrst->crc_clk_cpu_cmplx);
-
- clock_enable(PERIPH_ID_CPU);
-}
-
-static int is_cpu_powered(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
- return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
-}
-
-static void remove_cpu_io_clamps(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
-
- /* Remove the clamps on the CPU I/O signals */
- reg = readl(&pmc->pmc_remove_clamping);
- reg |= CPU_CLMP;
- writel(reg, &pmc->pmc_remove_clamping);
-
- /* Give I/O signals time to stabilize */
- udelay(IO_STABILIZATION_DELAY);
-}
-
-static void powerup_cpu(void)
-{
- struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
- u32 reg;
- int timeout = IO_STABILIZATION_DELAY;
-
- if (!is_cpu_powered()) {
- /* Toggle the CPU power state (OFF -> ON) */
- reg = readl(&pmc->pmc_pwrgate_toggle);
- reg &= PARTID_CP;
- reg |= START_CP;
- writel(reg, &pmc->pmc_pwrgate_toggle);
-
- /* Wait for the power to come up */
- while (!is_cpu_powered()) {
- if (timeout-- == 0)
- printf("CPU failed to power up!\n");
- else
- udelay(10);
- }
-
- /*
- * Remove the I/O clamps from CPU power partition.
- * Recommended only on a Warm boot, if the CPU partition gets
- * power gated. Shouldn't cause any harm when called after a
- * cold boot according to HW, probably just redundant.
- */
- remove_cpu_io_clamps();
- }
-}
-
static void enable_cpu_power_rail(void)
{
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
udelay(3750);
}
-static void reset_A9_cpu(int reset)
-{
- /*
- * NOTE: Regardless of whether the request is to hold the CPU in reset
- * or take it out of reset, every processor in the CPU complex
- * except the master (CPU 0) will be held in reset because the
- * AVP only talks to the master. The AVP does not know that there
- * are multiple processors in the CPU complex.
- */
-
- /* Hold CPU 1 in reset, and CPU 0 if asked */
- reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
- reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
- reset);
-
- /* Enable/Disable master CPU reset */
- reset_set_enable(PERIPH_ID_CPU, reset);
-}
-
-static void clock_enable_coresight(int enable)
-{
- u32 rst, src;
-
- clock_set_enable(PERIPH_ID_CORESIGHT, enable);
- reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
-
- if (enable) {
- /*
- * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
- * 1.5, giving an effective frequency of 144MHz.
- * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
- * (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
- */
- src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
- clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
-
- /* Unlock the CPU CoreSight interfaces */
- rst = 0xC5ACCE55;
- writel(rst, CSITE_CPU_DBG0_LAR);
- writel(rst, CSITE_CPU_DBG1_LAR);
- }
-}
-
void start_cpu(u32 reset_vector)
{
/* Enable VDD_CPU */
/* Take the CPU out of reset */
reset_A9_cpu(0);
}
-
-
-void halt_avp(void)
-{
- for (;;) {
- writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
- | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
- FLOW_CTLR_HALT_COP_EVENTS);
- }
-}
diff --git a/arch/arm/cpu/arm720t/tegra30/Makefile b/arch/arm/cpu/arm720t/tegra30/Makefile
--- /dev/null
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS-y += cpu.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm720t/tegra30/config.mk b/arch/arm/cpu/arm720t/tegra30/config.mk
--- /dev/null
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
--- /dev/null
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra30-specific CPU init code */
+void tegra_i2c_ll_write_addr(uint addr, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(addr, ®->cmd_addr0);
+ writel(config, ®->cnfg);
+}
+
+void tegra_i2c_ll_write_data(uint data, uint config)
+{
+ struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
+
+ writel(data, ®->cmd_data1);
+ writel(config, ®->cnfg);
+}
+
+#define TPS65911_I2C_ADDR 0x5A
+#define TPS65911_VDDCTRL_OP_REG 0x28
+#define TPS65911_VDDCTRL_SR_REG 0x27
+#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
+#define I2C_SEND_2_BYTES 0x0A02
+
+static void enable_cpu_power_rail(void)
+{
+ struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+ u32 reg;
+
+ debug("enable_cpu_power_rail entry\n");
+ reg = readl(&pmc->pmc_cntrl);
+ reg |= CPUPWRREQ_OE;
+ writel(reg, &pmc->pmc_cntrl);
+
+ /*
+ * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
+ * First set VDD to 1.4V, then enable the VDD regulator.
+ */
+ tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
+ tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
+ udelay(1000);
+ tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
+ udelay(10 * 1000);
+}
+
+/**
+ * The T30 requires some special clock initialization, including setting up
+ * the dvc i2c, turning on mselect and selecting the G CPU cluster
+ */
+void t30_init_clocks(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+ u32 val;
+
+ debug("t30_init_clocks entry\n");
+ /* Set active CPU cluster to G */
+ clrbits_le32(flow->cluster_control, 1 << 0);
+
+ /*
+ * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
+ * at 108 MHz. This is glitch free as only the source is changed, no
+ * special precaution needed.
+ */
+ val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+ (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+ (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+ (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+ (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+ writel(val, &clkrst->crc_sclk_brst_pol);
+
+ writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
+
+ val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
+ (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
+ (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
+ (0 << CLK_SYS_RATE_APB_RATE_SHIFT);
+ writel(val, &clkrst->crc_clk_sys_rate);
+
+ /* Put i2c, mselect in reset and enable clocks */
+ reset_set_enable(PERIPH_ID_DVC_I2C, 1);
+ clock_set_enable(PERIPH_ID_DVC_I2C, 1);
+ reset_set_enable(PERIPH_ID_MSELECT, 1);
+ clock_set_enable(PERIPH_ID_MSELECT, 1);
+
+ /* Switch MSELECT clock to PLLP (00) */
+ clock_ll_set_source(PERIPH_ID_MSELECT, 0);
+
+ /*
+ * Our high-level clock routines are not available prior to
+ * relocation. We use the low-level functions which require a
+ * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
+ */
+ clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
+
+ /*
+ * Give clocks time to stabilize, then take i2c and mselect out of
+ * reset
+ */
+ udelay(1000);
+ reset_set_enable(PERIPH_ID_DVC_I2C, 0);
+ reset_set_enable(PERIPH_ID_MSELECT, 0);
+}
+
+static void set_cpu_running(int run)
+{
+ struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+
+ debug("set_cpu_running entry, run = %d\n", run);
+ writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
+}
+
+void start_cpu(u32 reset_vector)
+{
+ debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+ t30_init_clocks();
+
+ /* Enable VDD_CPU */
+ enable_cpu_power_rail();
+
+ set_cpu_running(0);
+
+ /* Hold the CPUs in reset */
+ reset_A9_cpu(1);
+
+ /* Disable the CPU clock */
+ enable_cpu_clock(0);
+
+ /* Enable CoreSight */
+ clock_enable_coresight(1);
+
+ /*
+ * Set the entry point for CPU execution from reset,
+ * if it's a non-zero value.
+ */
+ if (reset_vector)
+ writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+ /* Enable the CPU clock */
+ enable_cpu_clock(1);
+
+ /* If the CPU doesn't already have power, power it up */
+ powerup_cpu();
+
+ /* Take the CPU out of reset */
+ reset_A9_cpu(0);
+
+ set_cpu_running(1);
+}
index 4bfcef2379b456ac645ce4d659c44b735a914765..512fb9d73db8dfb7cf7331c914ff62c84c84b19d 100644 (file)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->timer_rate_hz);
+ do_div(tick, gd->arch.timer_rate_hz);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
- usec *= gd->timer_rate_hz;
+ usec *= gd->arch.timer_rate_hz;
do_div(usec, 1000000);
return usec;
cr |= FTTMR010_TM3_ENABLE;
writel(cr, &tmr->cr);
- gd->timer_rate_hz = TIMER_CLOCK;
- gd->tbu = gd->tbl = 0;
+ gd->arch.timer_rate_hz = TIMER_CLOCK;
+ gd->arch.tbu = gd->arch.tbl = 0;
return 0;
}
ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
/* increment tbu if tbl has rolled over */
- if (now < gd->tbl)
- gd->tbu++;
- gd->tbl = now;
- return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
void __udelay(unsigned long usec)
*/
ulong get_tbclk(void)
{
- return gd->timer_rate_hz;
+ return gd->arch.timer_rate_hz;
}
index 09d2799831a2511293c984b21413f4c478918232..696200d04a027658b1761a1c6347dc24b2330abb 100644 (file)
case AT91_PMC_MCKR_CSS_SLOW:
return CONFIG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
- return gd->main_clk_rate_hz;
+ return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
- return gd->plla_rate_hz;
+ return gd->arch.plla_rate_hz;
case AT91_PMC_MCKR_CSS_PLLB:
- return gd->pllb_rate_hz;
+ return gd->arch.pllb_rate_hz;
}
return 0;
main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
- gd->main_clk_rate_hz = main_clock;
+ gd->arch.main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
- gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+ gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL
/*
*
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
- gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+ gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
AT91_PMC_PLLBR_USBDIV_2;
- gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
+ gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+ gd->arch.at91_pllb_usb_init);
#endif
/*
* For now, assume this parentage won't change.
*/
mckr = readl(&pmc->mckr);
- gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
- freq = gd->mck_rate_hz;
+ gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+ freq = gd->arch.mck_rate_hz;
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
/* mdiv */
- gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
- gd->cpu_clk_rate_hz = freq;
+ gd->arch.mck_rate_hz = freq /
+ (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+ gd->arch.cpu_clk_rate_hz = freq;
return 0;
}
index 91607b525e40efd616db06440e6a7c8c32ecae02..8ce75843a0e239e7000621f3b56fe278ed848db7 100644 (file)
writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
- gd->lastinc = 0;
- gd->tbl = 0;
+ gd->arch.lastinc = 0;
+ gd->arch.tbl = 0;
return 0;
}
now = readl(&tc->tc[0].cv) & 0x0000ffff;
- if (now >= gd->lastinc) {
+ if (now >= gd->arch.lastinc) {
/* normal mode */
- gd->tbl += now - gd->lastinc;
+ gd->arch.tbl += now - gd->arch.lastinc;
} else {
/* we have an overflow ... */
- gd->tbl += now + TIMER_LOAD_VAL - gd->lastinc;
+ gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc;
}
- gd->lastinc = now;
+ gd->arch.lastinc = now;
- return gd->tbl;
+ return gd->arch.tbl;
}
ulong get_timer_masked(void)
index d8668bec5edd90ca9dbb6b084c8224bcc5c643bd..d76bf186b6516891f2044a92a3a8c29ff2c2540e 100644 (file)
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
writel(0x0f00, &timers->tcfg0);
- if (gd->tbu == 0) {
+ if (gd->arch.tbu == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
*/
- gd->tbu = get_PCLK() / (2 * 16 * 100);
- gd->timer_rate_hz = get_PCLK() / (2 * 16);
+ gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
+ gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
}
/* load value for 10 ms timeout */
- writel(gd->tbu, &timers->tcntb4);
+ writel(gd->arch.tbu, &timers->tcntb4);
/* auto load, manual update of timer 4 */
tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->tcon);
/* auto load, start timer 4 */
tmr = (tmr & ~0x0700000) | 0x0500000;
writel(tmr, &timers->tcon);
- gd->lastinc = 0;
- gd->tbl = 0;
+ gd->arch.lastinc = 0;
+ gd->arch.tbl = 0;
return 0;
}
ulong start = get_ticks();
tmo = usec / 1000;
- tmo *= (gd->tbu * 100);
+ tmo *= (gd->arch.tbu * 100);
tmo /= 1000;
while ((ulong) (get_ticks() - start) < tmo)
{
ulong tmr = get_ticks();
- return tmr / (gd->timer_rate_hz / CONFIG_SYS_HZ);
+ return tmr / (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
}
void udelay_masked(unsigned long usec)
if (usec >= 1000) {
tmo = usec / 1000;
- tmo *= (gd->tbu * 100);
+ tmo *= (gd->arch.tbu * 100);
tmo /= 1000;
} else {
- tmo = usec * (gd->tbu * 100);
+ tmo = usec * (gd->arch.tbu * 100);
tmo /= (1000 * 1000);
}
struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
ulong now = readl(&timers->tcnto4) & 0xffff;
- if (gd->lastinc >= now) {
+ if (gd->arch.lastinc >= now) {
/* normal mode */
- gd->tbl += gd->lastinc - now;
+ gd->arch.tbl += gd->arch.lastinc - now;
} else {
/* we have an overflow ... */
- gd->tbl += gd->lastinc + gd->tbu - now;
+ gd->arch.tbl += gd->arch.lastinc + gd->arch.tbu - now;
}
- gd->lastinc = now;
+ gd->arch.lastinc = now;
- return gd->tbl;
+ return gd->arch.tbl;
}
/*
index 355cd6d1d8200e055b639698273b7fc70a12f9b2..948607f8c033f41ceb6bcd31d3a0488b6978635a 100644 (file)
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
/* For preventing risk of instability in reading counter value,
* first set read request to register cvwr and then read same
{
ulong now = read_timer();
- if (now >= gd->tbl) {
+ if (now >= gd->arch.tbl) {
/* normal mode */
- gd->tbu += now - gd->tbl;
+ gd->arch.tbu += now - gd->arch.tbl;
} else {
/* we have an overflow ... */
- gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+ gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
}
- gd->tbl = now;
+ gd->arch.tbl = now;
- return gd->tbu;
+ return gd->arch.tbu;
}
ulong get_timer(ulong base)
/* Enable timer 0 */
writel(0x1, &armd1timers->cer);
- /* init the gd->tbu and gd->tbl value */
- gd->tbl = read_timer();
- gd->tbu = 0;
+ /* init the gd->arch.tbu and gd->arch.tbl value */
+ gd->arch.tbl = read_timer();
+ gd->arch.tbu = 0;
return 0;
}
index dc5c6c4b0b29b0f2f69a3ec732b6a87185c1c219..f825388ae994f3dde7dca9fd1bb4cbe67beac897 100644 (file)
case AT91_PMC_MCKR_CSS_SLOW:
return CONFIG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
- return gd->main_clk_rate_hz;
+ return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
- return gd->plla_rate_hz;
+ return gd->arch.plla_rate_hz;
case AT91_PMC_MCKR_CSS_PLLB:
- return gd->pllb_rate_hz;
+ return gd->arch.pllb_rate_hz;
}
return 0;
main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
}
#endif
- gd->main_clk_rate_hz = main_clock;
+ gd->arch.main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
- gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
+ gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL
/*
*
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
- gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
+ gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
AT91_PMC_PLLBR_USBDIV_2;
- gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
+ gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
+ gd->arch.at91_pllb_usb_init);
#endif
/*
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
|| defined(CONFIG_AT91SAM9X5)
/* plla divisor by 2 */
- gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+ gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
- gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
- freq = gd->mck_rate_hz;
+ gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
+ freq = gd->arch.mck_rate_hz;
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
#if defined(CONFIG_AT91SAM9G20)
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
- gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
+ gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
* 2 <==> 4
* 3 <==> 3
*/
- gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
+ gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
- gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
+ gd->arch.mck_rate_hz = freq /
+ (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#endif
- gd->cpu_clk_rate_hz = freq;
+ gd->arch.cpu_clk_rate_hz = freq;
return 0;
}
index f70ce83f08391e5378e96f5269a52f86ce4e984a..4443fefb6472f984a9072002d88239bc8b66602a 100644 (file)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
- do_div(tick, gd->timer_rate_hz);
+ do_div(tick, gd->arch.timer_rate_hz);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
- usec *= gd->timer_rate_hz;
+ usec *= gd->arch.timer_rate_hz;
do_div(usec, 1000000);
return usec;
/* Enable PITC */
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
- gd->timer_rate_hz = gd->mck_rate_hz / 16;
- gd->tbu = gd->tbl = 0;
+ gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
+ gd->arch.tbu = gd->arch.tbl = 0;
return 0;
}
ulong now = readl(&pit->piir);
/* increment tbu if tbl has rolled over */
- if (now < gd->tbl)
- gd->tbu++;
- gd->tbl = now;
- return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
void __udelay(unsigned long usec)
*/
ulong get_tbclk(void)
{
- return gd->timer_rate_hz;
+ return gd->arch.timer_rate_hz;
}
index 93c9e60b792626618d20c8f8002d83bc7348342d..4142932d08eaa830c56434ba1161dcf43e1ef5d9 100644 (file)
writel(0x0, &timer->tim34);
writel(TIMER_LOAD_VAL, &timer->prd34);
writel(2 << 22, &timer->tcr);
- gd->timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
- gd->timer_reset_value = 0;
+ gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK / TIM_CLK_DIV;
+ gd->arch.timer_reset_value = 0;
return(0);
}
unsigned long now = readl(&timer->tim34);
/* increment tbu if tbl has rolled over */
- if (now < gd->tbl)
- gd->tbu++;
- gd->tbl = now;
+ if (now < gd->arch.tbl)
+ gd->arch.tbu++;
+ gd->arch.tbl = now;
- return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
+ return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
}
ulong get_timer(ulong base)
{
unsigned long long timer_diff;
- timer_diff = get_ticks() - gd->timer_reset_value;
+ timer_diff = get_ticks() - gd->arch.timer_reset_value;
- return lldiv(timer_diff, (gd->timer_rate_hz / CONFIG_SYS_HZ)) - base;
+ return lldiv(timer_diff,
+ (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) - base;
}
void __udelay(unsigned long usec)
{
unsigned long long endtime;
- endtime = lldiv((unsigned long long)usec * gd->timer_rate_hz,
+ endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz,
1000000UL);
endtime += get_ticks();
*/
ulong get_tbclk(void)
{
- return gd->timer_rate_hz;
+ return gd->arch.timer_rate_hz;
}
#ifdef CONFIG_HW_WATCHDOG
index f5d01603977a01affebaacfc87dd67da986d3109..85e81e3f4438e0443db0317836a96a41fa6ceb39 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
ulong get_timer_masked(void)
{
index 75314b91b3fbd0f5fab4c690fdffee8b69d7665d..c6486c13eb26acd00dcf488dbbcde1fc503757f0 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
static inline unsigned long long tick_to_time(unsigned long long tick)
{
index b9914186b19bad91dbd9202eefc54b38573cbcf1..679273b2b4dc66828726877ffb9bb74b91da1ca8 100644 (file)
{
#ifdef CONFIG_FSL_ESDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#else
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
index 4dc4041c08dd15008bee089720e4d2c3c81489e4..f8bebccd63d4c844351cc82b6e0188dd64743763 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp (gd->tbl)
-#define lastinc (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastinc (gd->arch.lastinc)
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
index a5dd68425aafd4fc1a6cc14f43b13d278ca23073..07e132ad2f7d957fc2230d7c850fdfb4030ad87a 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp (gd->tbl)
-#define lastinc (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastinc (gd->arch.lastinc)
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
index 4ed75e604ca8b589ffb0592cff24c0b3a0d866c9..373841180ff84af4811695674170f278c5846c76 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp (gd->tbl)
-#define lastdec (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastdec (gd->arch.lastinc)
/*
* This driver uses 1kHz clock source.
index 390c9c8abb5fd40bb0503eb9060af717e1c3f6df..34ec7b2b1ccc6f6a7b24dcb7378978f07c250399 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
int timer_init (void)
{
index 8a8aaf15d901b440f4437afa56efb68233586866..f7233512cd78ef7db6f7cbaf762d95fa7815daa5 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
ulong get_timer_masked(void)
{
index 28aadada7033bad0e82a9a4b7a2e2e34198b4935..2d9ddbad24001ae6a546cb03ff4edb30d3512d66 100644 (file)
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
-/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
/*
* For preventing risk of instability in reading counter value,
{
ulong now = read_timer();
- if (now >= gd->tbl) {
+ if (now >= gd->arch.tbl) {
/* normal mode */
- gd->tbu += now - gd->tbl;
+ gd->arch.tbu += now - gd->arch.tbl;
} else {
/* we have an overflow ... */
- gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+ gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
}
- gd->tbl = now;
+ gd->arch.tbl = now;
- return gd->tbu;
+ return gd->arch.tbu;
}
ulong get_timer(ulong base)
/* Enable timer 0 */
writel(0x1, &panthtimers->cer);
- /* init the gd->tbu and gd->tbl value */
- gd->tbl = read_timer();
- gd->tbu = 0;
+ /* init the gd->arch.tbu and gd->arch.tbl value */
+ gd->arch.tbl = read_timer();
+ gd->arch.tbu = 0;
return 0;
}
index 1dc78600c2b17d5d688ab4fb10b8f434cff17445..de4ba7b21345cfbc85abb178e118250c681be432 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
int timer_init(void)
{
index f58e151662086694cd7f4192bcd9d2069fe18e80..b36d6d93a57a865e36fbb301a859c59c03d93eff 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp gd->tbl
-#define lastdec gd->lastinc
+#define timestamp gd->arch.tbl
+#define lastdec gd->arch.lastinc
#define TIMER_ENABLE (1 << 7)
#define TIMER_MODE_MSK (1 << 6)
index 4fdbee4bc0e90767f05b4150f5db52046f30e3b7..ee8c2b3fa573e2f138b2bcaa3a6823c0f9a61cc8 100644 (file)
COBJS += cpu.o
COBJS += syslib.o
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA),)
SOBJS += lowlevel_init.o
endif
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 2b584e0a53755ec0164a0412a9449a57760af13f..1c8b6177dd5f8912046222569ecf505a3dc27f86 100644 (file)
#ifdef CONFIG_SPL_NAND_SUPPORT
gpmc_init();
#endif
+#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
+ arch_misc_init();
+#endif
}
int board_mmc_init(bd_t *bis)
index 9f8bc934470bf2129459e1d6934997f98ca93218..36bea5f94c118c8adeb69e83eb99800107c41921 100644 (file)
&timer_base->tclr);
/* reset time, capture current incrementer value time */
- gd->lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
- gd->tbl = 0; /* start "advancing" time stamp from 0 */
+ gd->arch.lastinc = readl(&timer_base->tcrr) /
+ (TIMER_CLOCK / CONFIG_SYS_HZ);
+ gd->arch.tbl = 0; /* start "advancing" time stamp from 0 */
return 0;
}
/* current tick value */
ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
- if (now >= gd->lastinc) /* normal mode (non roll) */
+ if (now >= gd->arch.lastinc) { /* normal mode (non roll) */
/* move stamp fordward with absoulte diff ticks */
- gd->tbl += (now - gd->lastinc);
- else /* we have rollover of incrementer */
- gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
- - gd->lastinc) + now;
- gd->lastinc = now;
- return gd->tbl;
+ gd->arch.tbl += (now - gd->arch.lastinc);
+ } else { /* we have rollover of incrementer */
+ gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK /
+ CONFIG_SYS_HZ)) - gd->arch.lastinc) + now;
+ }
+ gd->arch.lastinc = now;
+ return gd->arch.tbl;
}
/*
index bb0e795e66823d4963acd309ebbdd3e67bf7d4a4..e78c716d3fa4e88953f05c31daac6a4e1f34eefe 100644 (file)
struct s5p_timer *const timer = s5p_get_base_timer();
/* reset time */
- gd->lastinc = readl(&timer->tcnto4);
- gd->tbl = 0;
+ gd->arch.lastinc = readl(&timer->tcnto4);
+ gd->arch.tbl = 0;
}
unsigned long get_timer_masked(void)
unsigned long now = readl(&timer->tcnto4);
unsigned long count_value = readl(&timer->tcntb4);
- if (gd->lastinc >= now)
- gd->tbl += gd->lastinc - now;
+ if (gd->arch.lastinc >= now)
+ gd->arch.tbl += gd->arch.lastinc - now;
else
- gd->tbl += gd->lastinc + count_value - now;
+ gd->arch.tbl += gd->arch.lastinc + count_value - now;
- gd->lastinc = now;
+ gd->arch.lastinc = now;
- return gd->tbl;
+ return gd->arch.tbl;
}
/*
index 321e9b4181357ab797cbda4433e4bc19941804ba..efa28c2ae9440e1352676ebd32942cf81af97395 100644 (file)
{
/* current tick value */
ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
- if (gd->lastinc >= now) {
+ if (gd->arch.lastinc >= now) {
/* normal mode (non roll) */
/* move stamp forward with absolute diff ticks */
- gd->tbl += gd->lastinc - now;
+ gd->arch.tbl += gd->arch.lastinc - now;
} else {
/* we have overflow of the count down timer */
- gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now;
+ gd->arch.tbl += TIMER_LOAD_VAL - gd->arch.lastinc + now;
}
- gd->lastinc = now;
- return gd->tbl;
+ gd->arch.lastinc = now;
+ return gd->arch.tbl;
}
/*
void reset_timer(void)
{
/* capture current decrementer value time */
- gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ);
+ gd->arch.lastinc = read_timer() /
+ (CONFIG_TIMER_CLOCK_KHZ / CONFIG_SYS_HZ);
/* start "advancing" time stamp from 0 */
- gd->tbl = 0;
+ gd->arch.tbl = 0;
}
index dcc1f831bc814a2b47fd034815091561859b7000..6b59529d5dd9c4e5092e7213ef22da911accd472 100644 (file)
/*
* Move vector table
*/
-#if !defined(CONFIG_TEGRA20)
+#if !defined(CONFIG_TEGRA)
/* Set vector address in CP15 VBAR register */
ldr r0, =_start
add r0, r0, r9
mcr p15, 0, r0, c12, c0, 0 @Set VBAR
-#endif /* !Tegra20 */
+#endif /* !Tegra */
bx lr
diff --git a/arch/arm/cpu/armv7/tegra114/Makefile b/arch/arm/cpu/armv7/tegra114/Makefile
--- /dev/null
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra114/config.mk b/arch/arm/cpu/armv7/tegra114/config.mk
--- /dev/null
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+CONFIG_ARCH_DEVICE_TREE := tegra114
diff --git a/arch/arm/cpu/armv7/tegra30/Makefile b/arch/arm/cpu/armv7/tegra30/Makefile
--- /dev/null
@@ -0,0 +1,40 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra30/config.mk b/arch/arm/cpu/armv7/tegra30/config.mk
--- /dev/null
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+CONFIG_ARCH_DEVICE_TREE := tegra30
index 79aad9983a5982ab0d7cc406a21bcf1afe174c6a..a4b88f3815c096aa1db369918f02585c1d0a3e31 100644 (file)
/* current tick value */
ulong now = TICKS_TO_HZ(READ_TIMER());
- if (now >= gd->lastinc) /* normal (non rollover) */
- gd->tbl += (now - gd->lastinc);
- else /* rollover */
- gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now;
- gd->lastinc = now;
- return gd->tbl;
+ if (now >= gd->arch.lastinc) { /* normal (non rollover) */
+ gd->arch.tbl += (now - gd->arch.lastinc);
+ } else { /* rollover */
+ gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) -
+ gd->arch.lastinc) + now;
+ }
+ gd->arch.lastinc = now;
+ return gd->arch.tbl;
}
/* Delay x useconds */
/*
* Emulation of Power architecture long long timebase.
*
- * TODO: Support gd->tbu for real long long timebase.
+ * TODO: Support gd->arch.tbu for real long long timebase.
*/
unsigned long long get_ticks(void)
{
index 499ace4a62970bc108d592cbf29c57796988e651..388085dc2adde5ecadd6d8261ec4408a4de73b9e 100644 (file)
COBJS-y := timer.o
COBJS-y += cpu.o
+COBJS-y += slcr.o
COBJS := $(COBJS-y)
index ab615cc7d4f8f2a92223daf322f8a64642451150..e8f4c19d4908c9d208c0eb6259f53dfef11d4ad7 100644 (file)
* MA 02111-1307 USA
*/
#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
-inline void lowlevel_init(void) {}
+void lowlevel_init(void)
+{
+ zynq_slcr_unlock();
+ /* remap DDR to zero, FILTERSTART */
+ writel(0, &scu_base->filter_start);
+
+ /* Device config APB, unlock the PCAP */
+ writel(0x757BDF0D, &devcfg_base->unlock);
+ writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
+
+ /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
+ writel(0x1F, &slcr_base->ocm_cfg);
+ /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
+ writel(0x0, &slcr_base->fpga_rst_ctrl);
+ /* TZ_DDR_RAM, Set DDR trust zone non-secure */
+ writel(0xFFFFFFFF, &slcr_base->trust_zone);
+ /* Set urgent bits with register */
+ writel(0x0, &slcr_base->ddr_urgent_sel);
+ /* Urgent write, ports S2/S3 */
+ writel(0xC, &slcr_base->ddr_urgent);
+
+ zynq_slcr_lock();
+}
void reset_cpu(ulong addr)
{
+ zynq_slcr_cpu_reset();
while (1)
;
}
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <asm/arch/hardware.h>
+
+#define SLCR_LOCK_MAGIC 0x767B
+#define SLCR_UNLOCK_MAGIC 0xDF0D
+
+static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
+
+void zynq_slcr_lock(void)
+{
+ if (!slcr_lock)
+ writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
+}
+
+void zynq_slcr_unlock(void)
+{
+ if (slcr_lock)
+ writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
+}
+
+/* Reset the entire system */
+void zynq_slcr_cpu_reset(void)
+{
+ /*
+ * Unlock the SLCR then reset the system.
+ * Note that this seems to require raw i/o
+ * functions or there's a lockup?
+ */
+ zynq_slcr_unlock();
+
+ /*
+ * Clear 0x0F000000 bits of reboot status register to workaround
+ * the FSBL not loading the bitstream after soft-reboot
+ * This is a temporary solution until we know more.
+ */
+ clrbits_le32(&slcr_base->reboot_status, 0xF000000);
+
+ writel(1, &slcr_base->pss_rst_ctrl);
+}
index 323e7b5a49bd0bc3f5ffec7ee50f58f75c4d3b12..45b405a4ba2a764831615a24ecd86d2cb6214466 100644 (file)
emask);
/* Reset time */
- gd->lastinc = readl(&timer_base->counter) /
+ gd->arch.lastinc = readl(&timer_base->counter) /
(TIMER_TICK_HZ / CONFIG_SYS_HZ);
- gd->tbl = 0;
+ gd->arch.tbl = 0;
return 0;
}
now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
- if (gd->lastinc >= now) {
+ if (gd->arch.lastinc >= now) {
/* Normal mode */
- gd->tbl += gd->lastinc - now;
+ gd->arch.tbl += gd->arch.lastinc - now;
} else {
/* We have an overflow ... */
- gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now;
+ gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now;
}
- gd->lastinc = now;
+ gd->arch.lastinc = now;
- return gd->tbl;
+ return gd->arch.tbl;
}
void __udelay(unsigned long usec)
index 087ddf80ef7c9f28ea62c3ca4d7a14530edffa22..663d9890899603b47b52a41d3139b312b5ad96d8 100644 (file)
--- a/arch/arm/cpu/ixp/timer.c
+++ b/arch/arm/cpu/ixp/timer.c
if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
/* rollover of timestamp timer register */
- gd->timestamp += (0xFFFFFFFF - gd->lastinc) + now + 1;
+ gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1;
writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
} else {
/* move stamp forward with absolut diff ticks */
- gd->timestamp += (now - gd->lastinc);
+ gd->arch.timestamp += (now - gd->arch.lastinc);
}
- gd->lastinc = now;
- return gd->timestamp;
+ gd->arch.lastinc = now;
+ return gd->arch.timestamp;
}
void reset_timer_masked(void)
{
/* capture current timestamp counter */
- gd->lastinc = readl(IXP425_OSTS_B);
+ gd->arch.lastinc = readl(IXP425_OSTS_B);
/* start "advancing" time stamp from 0 */
- gd->timestamp = 0;
+ gd->arch.timestamp = 0;
}
ulong get_timer_masked(void)
index a8f7462c1b75aca4a9687852eec274a845a706c2..212b31eb6853f7d4182ef2b2b745dfe37abf8989 100644 (file)
--- a/arch/arm/cpu/pxa/timer.c
+++ b/arch/arm/cpu/pxa/timer.c
#define TIMER_LOAD_VAL 0xffffffff
-#define timestamp (gd->tbl)
-#define lastinc (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastinc (gd->arch.lastinc)
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
#define TIMER_FREQ_HZ 3250000
index 38e90d314390fb3a0092a74dc4562d08b606eaab..8e95c7ee1d367fd03b3dbb650941594fdb08f421 100644 (file)
LIB = $(obj)libcputegra-common.o
SOBJS += lowlevel_init.o
-COBJS-y += ap.o board.o sys_info.o timer.o
+COBJS-y += ap.o board.o sys_info.o timer.o clock.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
index c4eb137480340bb660e76ae3abcaca8f6e3bb7eb..236cda8419fc0ce5c4444d201cee35308b35c17a 100644 (file)
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+
+/* Tegra AP (Application Processor) code */
+
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clock.h>
#include <asm/arch-tegra/fuse.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/scu.h>
+#include <asm/arch-tegra/tegra.h>
#include <asm/arch-tegra/warmboot.h>
int tegra_get_chip_type(void)
/*
* This is undocumented, Chip ID is bits 15:8 of the register
* APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
- * Tegra30
+ * Tegra30, and 0x35 for T114.
*/
gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
return TEGRA_SOC_T25;
}
break;
+ case CHIPID_TEGRA30:
+ switch (tegra_sku_id) {
+ case SKU_ID_T30:
+ return TEGRA_SOC_T30;
+ }
+ break;
+ case CHIPID_TEGRA114:
+ switch (tegra_sku_id) {
+ case SKU_ID_T114_ENG:
+ return TEGRA_SOC_T114;
+ }
+ break;
}
/* unknown sku id */
return TEGRA_SOC_UNKNOWN;
u32 bct_start, odmdata;
- bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+ bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
return odmdata;
"orr r0, r0, #0x41\n"
"mcr p15, 0, r0, c1, c0, 1\n");
- /* FIXME: should have ap20's L2 disabled too? */
+ /* FIXME: should have SoC's L2 disabled too? */
}
index b2e10c6db875a9cc12b74ddb27c6bd9c783c3b0f..58ea6289d37bc6a1f039e11ce9c869449b634d23 100644 (file)
/* UARTs which we can enable */
UARTA = 1 << 0,
UARTB = 1 << 1,
+ UARTC = 1 << 2,
UARTD = 1 << 3,
- UART_COUNT = 4,
+ UARTE = 1 << 4,
+ UART_COUNT = 5,
};
/*
reg = readl(&pmc->pmc_scratch20);
debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
- /* bits 31:28 in OdmData are used for RAM size */
+#if defined(CONFIG_TEGRA20)
+ /* bits 30:28 in OdmData are used for RAM size on T20 */
+ reg &= 0x70000000;
+
switch ((reg) >> 28) {
case 1:
return 0x10000000; /* 256 MB */
+ case 0:
case 2:
default:
return 0x20000000; /* 512 MB */
case 3:
return 0x40000000; /* 1GB */
}
+#else /* Tegra30/Tegra114 */
+ /* bits 31:28 in OdmData are used for RAM size on T30 */
+ switch ((reg) >> 28) {
+ case 0:
+ case 1:
+ default:
+ return 0x10000000; /* 256 MB */
+ case 2:
+ return 0x20000000; /* 512 MB */
+ case 3:
+ return 0x30000000; /* 768 MB */
+ case 4:
+ return 0x40000000; /* 1GB */
+ case 8:
+ return 0x7ff00000; /* 2GB - 1MB */
+ }
+#endif
}
int dram_init(void)
#endif /* CONFIG_DISPLAY_BOARDINFO */
static int uart_configs[] = {
-#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
+#if defined(CONFIG_TEGRA20)
+ #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA_UARTA_GPU)
+ #elif defined(CONFIG_TEGRA_UARTA_GPU)
FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
+ #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
FUNCMUX_UART1_SDIO1,
-#else
+ #else
FUNCMUX_UART1_IRRX_IRTX,
#endif
- FUNCMUX_UART2_IRDA,
+ FUNCMUX_UART2_UAD,
-1,
FUNCMUX_UART4_GMC,
-1,
+#elif defined(CONFIG_TEGRA30)
+ FUNCMUX_UART1_ULPI, /* UARTA */
+ -1,
+ -1,
+ -1,
+ -1,
+#else /* Tegra114 */
+ -1,
+ -1,
+ -1,
+ FUNCMUX_UART4_GMI, /* UARTD */
+ -1,
+#endif
};
/**
PERIPH_ID_UART2,
PERIPH_ID_UART3,
PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
};
size_t i;
#ifdef CONFIG_TEGRA_ENABLE_UARTB
uart_ids |= UARTB;
#endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTC
+ uart_ids |= UARTC;
+#endif
#ifdef CONFIG_TEGRA_ENABLE_UARTD
uart_ids |= UARTD;
+#endif
+#ifdef CONFIG_TEGRA_ENABLE_UARTE
+ uart_ids |= UARTE;
#endif
setup_uarts(uart_ids);
}
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
--- /dev/null
@@ -0,0 +1,560 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra SoC common clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * This is our record of the current clock rate of each clock. We don't
+ * fill all of these in since we are only really interested in clocks which
+ * we use as parents.
+ */
+static unsigned pll_rate[CLOCK_ID_COUNT];
+
+/*
+ * The oscillator frequency is fixed to one of four set values. Based on this
+ * the other clocks are set up appropriately.
+ */
+static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
+ 13000000,
+ 19200000,
+ 12000000,
+ 26000000,
+};
+
+/* return 1 if a peripheral ID is in range */
+#define clock_type_id_isvalid(id) ((id) >= 0 && \
+ (id) < CLOCK_TYPE_COUNT)
+
+char pllp_valid = 1; /* PLLP is set up correctly */
+
+/* return 1 if a periphc_internal_id is in range */
+#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
+ (id) < PERIPHC_COUNT)
+
+/* number of clock outputs of a PLL */
+static const u8 pll_num_clkouts[] = {
+ 1, /* PLLC */
+ 1, /* PLLM */
+ 4, /* PLLP */
+ 1, /* PLLA */
+ 0, /* PLLU */
+ 0, /* PLLD */
+};
+
+int clock_get_osc_bypass(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ reg = readl(&clkrst->crc_osc_ctrl);
+ return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
+}
+
+/* Returns a pointer to the registers of the given pll */
+static struct clk_pll *get_pll(enum clock_id clkid)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+ assert(clock_id_is_pll(clkid));
+ return &clkrst->crc_pll[clkid];
+}
+
+int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
+ u32 *divp, u32 *cpcon, u32 *lfcon)
+{
+ struct clk_pll *pll = get_pll(clkid);
+ u32 data;
+
+ assert(clkid != CLOCK_ID_USB);
+
+ /* Safety check, adds to code size but is small */
+ if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
+ return -1;
+ data = readl(&pll->pll_base);
+ *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
+ *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
+ *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
+ data = readl(&pll->pll_misc);
+ *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
+ *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
+
+ return 0;
+}
+
+unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
+ u32 divp, u32 cpcon, u32 lfcon)
+{
+ struct clk_pll *pll = get_pll(clkid);
+ u32 data;
+
+ /*
+ * We cheat by treating all PLL (except PLLU) in the same fashion.
+ * This works only because:
+ * - same fields are always mapped at same offsets, except DCCON
+ * - DCCON is always 0, doesn't conflict
+ * - M,N, P of PLLP values are ignored for PLLP
+ */
+ data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
+ writel(data, &pll->pll_misc);
+
+ data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
+ (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
+
+ if (clkid == CLOCK_ID_USB)
+ data |= divp << PLLU_VCO_FREQ_SHIFT;
+ else
+ data |= divp << PLL_DIVP_SHIFT;
+ writel(data, &pll->pll_base);
+
+ /* calculate the stable time */
+ return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
+}
+
+void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
+ unsigned divisor)
+{
+ u32 *reg = get_periph_source_reg(periph_id);
+ u32 value;
+
+ value = readl(reg);
+
+ value &= ~OUT_CLK_SOURCE_MASK;
+ value |= source << OUT_CLK_SOURCE_SHIFT;
+
+ value &= ~OUT_CLK_DIVISOR_MASK;
+ value |= divisor << OUT_CLK_DIVISOR_SHIFT;
+
+ writel(value, reg);
+}
+
+void clock_ll_set_source(enum periph_id periph_id, unsigned source)
+{
+ u32 *reg = get_periph_source_reg(periph_id);
+
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
+ source << OUT_CLK_SOURCE_SHIFT);
+}
+
+/**
+ * Given the parent's rate and the required rate for the children, this works
+ * out the peripheral clock divider to use, in 7.1 binary format.
+ *
+ * @param divider_bits number of divider bits (8 or 16)
+ * @param parent_rate clock rate of parent clock in Hz
+ * @param rate required clock rate for this clock
+ * @return divider which should be used
+ */
+static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
+ unsigned long rate)
+{
+ u64 divider = parent_rate * 2;
+ unsigned max_divider = 1 << divider_bits;
+
+ divider += rate - 1;
+ do_div(divider, rate);
+
+ if ((s64)divider - 2 < 0)
+ return 0;
+
+ if ((s64)divider - 2 >= max_divider)
+ return -1;
+
+ return divider - 2;
+}
+
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
+{
+ struct clk_pll *pll = get_pll(clkid);
+ int data = 0, div = 0, offset = 0;
+
+ if (!clock_id_is_pll(clkid))
+ return -1;
+
+ if (pllout + 1 > pll_num_clkouts[clkid])
+ return -1;
+
+ div = clk_get_divider(8, pll_rate[clkid], rate);
+
+ if (div < 0)
+ return -1;
+
+ /* out2 and out4 are in the high part of the register */
+ if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
+ offset = 16;
+
+ data = (div << PLL_OUT_RATIO_SHIFT) |
+ PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
+ clrsetbits_le32(&pll->pll_out[pllout >> 1],
+ PLL_OUT_RATIO_MASK << offset, data << offset);
+
+ return 0;
+}
+
+/**
+ * Given the parent's rate and the divider in 7.1 format, this works out the
+ * resulting peripheral clock rate.
+ *
+ * @param parent_rate clock rate of parent clock in Hz
+ * @param divider which should be used in 7.1 format
+ * @return effective clock rate of peripheral
+ */
+static unsigned long get_rate_from_divider(unsigned long parent_rate,
+ int divider)
+{
+ u64 rate;
+
+ rate = (u64)parent_rate * 2;
+ do_div(rate, divider + 2);
+ return rate;
+}
+
+unsigned long clock_get_periph_rate(enum periph_id periph_id,
+ enum clock_id parent)
+{
+ u32 *reg = get_periph_source_reg(periph_id);
+
+ return get_rate_from_divider(pll_rate[parent],
+ (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
+}
+
+/**
+ * Find the best available 7.1 format divisor given a parent clock rate and
+ * required child clock rate. This function assumes that a second-stage
+ * divisor is available which can divide by powers of 2 from 1 to 256.
+ *
+ * @param divider_bits number of divider bits (8 or 16)
+ * @param parent_rate clock rate of parent clock in Hz
+ * @param rate required clock rate for this clock
+ * @param extra_div value for the second-stage divisor (not set if this
+ * function returns -1.
+ * @return divider which should be used, or -1 if nothing is valid
+ *
+ */
+static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
+ unsigned long rate, int *extra_div)
+{
+ int shift;
+ int best_divider = -1;
+ int best_error = rate;
+
+ /* try dividers from 1 to 256 and find closest match */
+ for (shift = 0; shift <= 8 && best_error > 0; shift++) {
+ unsigned divided_parent = parent_rate >> shift;
+ int divider = clk_get_divider(divider_bits, divided_parent,
+ rate);
+ unsigned effective_rate = get_rate_from_divider(divided_parent,
+ divider);
+ int error = rate - effective_rate;
+
+ /* Given a valid divider, look for the lowest error */
+ if (divider != -1 && error < best_error) {
+ best_error = error;
+ *extra_div = 1 << shift;
+ best_divider = divider;
+ }
+ }
+
+ /* return what we found - *extra_div will already be set */
+ return best_divider;
+}
+
+/**
+ * Adjust peripheral PLL to use the given divider and source.
+ *
+ * @param periph_id peripheral to adjust
+ * @param source Source number (0-3 or 0-7)
+ * @param mux_bits Number of mux bits (2 or 4)
+ * @param divider Required divider in 7.1 or 15.1 format
+ * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
+ * for this peripheral)
+ */
+static int adjust_periph_pll(enum periph_id periph_id, int source,
+ int mux_bits, unsigned divider)
+{
+ u32 *reg = get_periph_source_reg(periph_id);
+
+ clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
+ divider << OUT_CLK_DIVISOR_SHIFT);
+ udelay(1);
+
+ /* work out the source clock and set it */
+ if (source < 0)
+ return -1;
+ if (mux_bits == 4) {
+ clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
+ source << OUT_CLK_SOURCE4_SHIFT);
+ } else {
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
+ source << OUT_CLK_SOURCE_SHIFT);
+ }
+ udelay(2);
+ return 0;
+}
+
+unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
+ enum clock_id parent, unsigned rate, int *extra_div)
+{
+ unsigned effective_rate;
+ int mux_bits, divider_bits, source;
+ int divider;
+
+ /* work out the source clock and set it */
+ source = get_periph_clock_source(periph_id, parent, &mux_bits,
+ ÷r_bits);
+
+ if (extra_div)
+ divider = find_best_divider(divider_bits, pll_rate[parent],
+ rate, extra_div);
+ else
+ divider = clk_get_divider(divider_bits, pll_rate[parent],
+ rate);
+ assert(divider >= 0);
+ if (adjust_periph_pll(periph_id, source, mux_bits, divider))
+ return -1U;
+ debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
+ get_periph_source_reg(periph_id),
+ readl(get_periph_source_reg(periph_id)));
+
+ /* Check what we ended up with. This shouldn't matter though */
+ effective_rate = clock_get_periph_rate(periph_id, parent);
+ if (extra_div)
+ effective_rate /= *extra_div;
+ if (rate != effective_rate)
+ debug("Requested clock rate %u not honored (got %u)\n",
+ rate, effective_rate);
+ return effective_rate;
+}
+
+unsigned clock_start_periph_pll(enum periph_id periph_id,
+ enum clock_id parent, unsigned rate)
+{
+ unsigned effective_rate;
+
+ reset_set_enable(periph_id, 1);
+ clock_enable(periph_id);
+
+ effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
+ NULL);
+
+ reset_set_enable(periph_id, 0);
+ return effective_rate;
+}
+
+void clock_enable(enum periph_id clkid)
+{
+ clock_set_enable(clkid, 1);
+}
+
+void clock_disable(enum periph_id clkid)
+{
+ clock_set_enable(clkid, 0);
+}
+
+void reset_periph(enum periph_id periph_id, int us_delay)
+{
+ /* Put peripheral into reset */
+ reset_set_enable(periph_id, 1);
+ udelay(us_delay);
+
+ /* Remove reset */
+ reset_set_enable(periph_id, 0);
+
+ udelay(us_delay);
+}
+
+void reset_cmplx_set_enable(int cpu, int which, int reset)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 mask;
+
+ /* Form the mask, which depends on the cpu chosen (2 or 4) */
+ assert(cpu >= 0 && cpu < MAX_NUM_CPU);
+ mask = which << cpu;
+
+ /* either enable or disable those reset for that CPU */
+ if (reset)
+ writel(mask, &clkrst->crc_cpu_cmplx_set);
+ else
+ writel(mask, &clkrst->crc_cpu_cmplx_clr);
+}
+
+unsigned clock_get_rate(enum clock_id clkid)
+{
+ struct clk_pll *pll;
+ u32 base;
+ u32 divm;
+ u64 parent_rate;
+ u64 rate;
+
+ parent_rate = osc_freq[clock_get_osc_freq()];
+ if (clkid == CLOCK_ID_OSC)
+ return parent_rate;
+
+ pll = get_pll(clkid);
+ base = readl(&pll->pll_base);
+
+ /* Oh for bf_unpack()... */
+ rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
+ divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
+ if (clkid == CLOCK_ID_USB)
+ divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
+ else
+ divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
+ do_div(rate, divm);
+ return rate;
+}
+
+/**
+ * Set the output frequency you want for each PLL clock.
+ * PLL output frequencies are programmed by setting their N, M and P values.
+ * The governing equations are:
+ * VCO = (Fi / m) * n, Fo = VCO / (2^p)
+ * where Fo is the output frequency from the PLL.
+ * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
+ * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
+ * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
+ *
+ * @param n PLL feedback divider(DIVN)
+ * @param m PLL input divider(DIVN)
+ * @param p post divider(DIVP)
+ * @param cpcon base PLL charge pump(CPCON)
+ * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
+ * be overriden), 1 if PLL is already correct
+ */
+int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
+{
+ u32 base_reg;
+ u32 misc_reg;
+ struct clk_pll *pll;
+
+ pll = get_pll(clkid);
+
+ base_reg = readl(&pll->pll_base);
+
+ /* Set BYPASS, m, n and p to PLL_BASE */
+ base_reg &= ~PLL_DIVM_MASK;
+ base_reg |= m << PLL_DIVM_SHIFT;
+
+ base_reg &= ~PLL_DIVN_MASK;
+ base_reg |= n << PLL_DIVN_SHIFT;
+
+ base_reg &= ~PLL_DIVP_MASK;
+ base_reg |= p << PLL_DIVP_SHIFT;
+
+ if (clkid == CLOCK_ID_PERIPH) {
+ /*
+ * If the PLL is already set up, check that it is correct
+ * and record this info for clock_verify() to check.
+ */
+ if (base_reg & PLL_BASE_OVRRIDE_MASK) {
+ base_reg |= PLL_ENABLE_MASK;
+ if (base_reg != readl(&pll->pll_base))
+ pllp_valid = 0;
+ return pllp_valid ? 1 : -1;
+ }
+ base_reg |= PLL_BASE_OVRRIDE_MASK;
+ }
+
+ base_reg |= PLL_BYPASS_MASK;
+ writel(base_reg, &pll->pll_base);
+
+ /* Set cpcon to PLL_MISC */
+ misc_reg = readl(&pll->pll_misc);
+ misc_reg &= ~PLL_CPCON_MASK;
+ misc_reg |= cpcon << PLL_CPCON_SHIFT;
+ writel(misc_reg, &pll->pll_misc);
+
+ /* Enable PLL */
+ base_reg |= PLL_ENABLE_MASK;
+ writel(base_reg, &pll->pll_base);
+
+ /* Disable BYPASS */
+ base_reg &= ~PLL_BYPASS_MASK;
+ writel(base_reg, &pll->pll_base);
+
+ return 0;
+}
+
+void clock_ll_start_uart(enum periph_id periph_id)
+{
+ /* Assert UART reset and enable clock */
+ reset_set_enable(periph_id, 1);
+ clock_enable(periph_id);
+ clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
+
+ /* wait for 2us */
+ udelay(2);
+
+ /* De-assert reset to UART */
+ reset_set_enable(periph_id, 0);
+}
+
+#ifdef CONFIG_OF_CONTROL
+int clock_decode_periph_id(const void *blob, int node)
+{
+ enum periph_id id;
+ u32 cell[2];
+ int err;
+
+ err = fdtdec_get_int_array(blob, node, "clocks", cell,
+ ARRAY_SIZE(cell));
+ if (err)
+ return -1;
+ id = clk_id_to_periph_id(cell[1]);
+ assert(clock_periph_id_isvalid(id));
+ return id;
+}
+#endif /* CONFIG_OF_CONTROL */
+
+int clock_verify(void)
+{
+ struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
+ u32 reg = readl(&pll->pll_base);
+
+ if (!pllp_valid) {
+ printf("Warning: PLLP %x is not correct\n", reg);
+ return -1;
+ }
+ debug("PLLP %x is correct\n", reg);
+ return 0;
+}
+
+void clock_init(void)
+{
+ pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
+ pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
+ pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
+ pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
+ pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
+ pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
+ debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
+ debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
+ debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
+ debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
+ debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
+}
index 1a0bb561a7fee91c0585fd5a1f272cc42b78765a..4632f15d5b446a6beab4528665cfb91f5cb89e4d 100644 (file)
*/
#include <common.h>
+#include <linux/ctype.h>
#ifdef CONFIG_DISPLAY_CPUINFO
+void upstring(char *s)
+{
+ while (*s) {
+ *s = toupper(*s);
+ s++;
+ }
+}
+
/* Print CPU information */
int print_cpuinfo(void)
{
- puts("TEGRA20\n");
+ char soc_name[10];
+
+ strncpy(soc_name, CONFIG_SYS_SOC, 10);
+ upstring(soc_name);
+ puts(soc_name);
+ puts("\n");
/* TBD: Add printf of major/minor rev info, stepping, etc. */
return 0;
index 034ea5ad28847eb1d9fc44fd40c11585c97364f5..51902e9544bc6a6d319482a355e636adbeb0bad8 100644 (file)
/* current tick value */
now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ);
- if (now >= gd->lastinc) /* normal mode (non roll) */
+ if (now >= gd->arch.lastinc) /* normal mode (non roll) */
/* move stamp forward with absolute diff ticks */
- gd->tbl += (now - gd->lastinc);
+ gd->arch.tbl += (now - gd->arch.lastinc);
else /* we have rollover of incrementer */
- gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
- - gd->lastinc) + now;
- gd->lastinc = now;
- return gd->tbl;
+ gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
+ - gd->arch.lastinc) + now;
+ gd->arch.lastinc = now;
+ return gd->arch.tbl;
}
/*
diff --git a/arch/arm/cpu/tegra114-common/Makefile b/arch/arm/cpu/tegra114-common/Makefile
--- /dev/null
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC)-common.o
+
+COBJS-y += clock.o funcmux.o pinmux.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/tegra114-common/clock.c b/arch/arm/cpu/tegra114-common/clock.c
--- /dev/null
@@ -0,0 +1,655 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra114 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+ CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
+ CLOCK_TYPE_MCPA, /* and so on */
+ CLOCK_TYPE_MCPT,
+ CLOCK_TYPE_PCM,
+ CLOCK_TYPE_PCMT,
+ CLOCK_TYPE_PCMT16,
+ CLOCK_TYPE_PDCT,
+ CLOCK_TYPE_ACPT,
+ CLOCK_TYPE_ASPTE,
+ CLOCK_TYPE_PMDACD2T,
+ CLOCK_TYPE_PCST,
+
+ CLOCK_TYPE_COUNT,
+ CLOCK_TYPE_NONE = -1, /* invalid clock type */
+};
+
+enum {
+ CLOCK_MAX_MUX = 8 /* number of source options for each clock */
+};
+
+enum {
+ MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
+ MASK_BITS_31_29,
+ MASK_BITS_29_28,
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ * The extra column in each clock source array is used to store the mask
+ * bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+ { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
+ CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
+ CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_29_28}
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+ /* 0x00 */
+ TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
+ TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
+
+ /* 0x08 */
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_I2C5, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
+
+ /* 0x10 */
+ TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
+
+ /* 0x18 */
+ TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
+ TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
+
+ /* 0x20 */
+ TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
+ TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
+ TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
+
+ /* 0x28 */
+ TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
+
+ /* 0x30 */
+ TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+
+ /* 0x38h */ /* Jumps to reg offset 0x3B0h */
+ TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
+ TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
+
+ /* 0x40 */
+ TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
+ TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+ /* 0x48 */
+ TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
+ TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+
+ /* 0x50 */
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
+ TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ * uint vi_sensor; _VI_SENSOR_0, 0x1A8
+ * SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+ /* Low word: 31:0 */
+ NONE(CPU),
+ NONE(COP),
+ NONE(TRIGSYS),
+ NONE(RESERVED3),
+ NONE(RTC),
+ NONE(TMR),
+ PERIPHC_UART1,
+ PERIPHC_UART2, /* and vfir 0x68 */
+
+ /* 8 */
+ NONE(GPIO),
+ PERIPHC_SDMMC2,
+ NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
+ PERIPHC_I2S1,
+ PERIPHC_I2C1,
+ PERIPHC_NDFLASH,
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC4,
+
+ /* 16 */
+ NONE(RESERVED16),
+ PERIPHC_PWM,
+ PERIPHC_I2S2,
+ PERIPHC_EPP,
+ PERIPHC_VI,
+ PERIPHC_G2D,
+ NONE(USBD),
+ NONE(ISP),
+
+ /* 24 */
+ PERIPHC_G3D,
+ NONE(RESERVED25),
+ PERIPHC_DISP2,
+ PERIPHC_DISP1,
+ PERIPHC_HOST1X,
+ NONE(VCP),
+ PERIPHC_I2S0,
+ NONE(CACHE2),
+
+ /* Middle word: 63:32 */
+ NONE(MEM),
+ NONE(AHBDMA),
+ NONE(APBDMA),
+ NONE(RESERVED35),
+ NONE(RESERVED36),
+ NONE(STAT_MON),
+ NONE(RESERVED38),
+ NONE(RESERVED39),
+
+ /* 40 */
+ NONE(KFUSE),
+ NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
+ PERIPHC_NOR,
+ NONE(RESERVED43),
+ PERIPHC_SBC2,
+ NONE(RESERVED45),
+ PERIPHC_SBC3,
+ PERIPHC_I2C5,
+
+ /* 48 */
+ NONE(DSI),
+ PERIPHC_TVO, /* also CVE 0x40 */
+ PERIPHC_MIPI,
+ PERIPHC_HDMI,
+ NONE(CSI),
+ PERIPHC_TVDAC,
+ PERIPHC_I2C2,
+ PERIPHC_UART3,
+
+ /* 56 */
+ NONE(RESERVED56),
+ PERIPHC_EMC,
+ NONE(USB2),
+ NONE(USB3),
+ PERIPHC_MPE,
+ PERIPHC_VDE,
+ NONE(BSEA),
+ NONE(BSEV),
+
+ /* Upper word 95:64 */
+ PERIPHC_SPEEDO,
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_I2C3,
+ PERIPHC_SBC4,
+ PERIPHC_SDMMC3,
+ NONE(PCIE),
+ PERIPHC_OWR,
+
+ /* 72 */
+ NONE(AFI),
+ PERIPHC_CSITE,
+ NONE(PCIEXCLK),
+ NONE(AVPUCQ),
+ NONE(RESERVED76),
+ NONE(RESERVED77),
+ NONE(RESERVED78),
+ NONE(DTV),
+
+ /* 80 */
+ PERIPHC_NANDSPEED,
+ PERIPHC_I2CSLOW,
+ NONE(DSIB),
+ NONE(RESERVED83),
+ NONE(IRAMA),
+ NONE(IRAMB),
+ NONE(IRAMC),
+ NONE(IRAMD),
+
+ /* 88 */
+ NONE(CRAM2),
+ NONE(RESERVED89),
+ NONE(MDOUBLER),
+ NONE(RESERVED91),
+ NONE(SUSOUT),
+ NONE(RESERVED93),
+ NONE(RESERVED94),
+ NONE(RESERVED95),
+
+ /* V word: 31:0 */
+ NONE(CPUG),
+ NONE(CPULP),
+ PERIPHC_G3D2,
+ PERIPHC_MSELECT,
+ PERIPHC_TSENSOR,
+ PERIPHC_I2S3,
+ PERIPHC_I2S4,
+ PERIPHC_I2C4,
+
+ /* 08 */
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+ PERIPHC_AUDIO,
+ NONE(APBIF),
+ PERIPHC_DAM0,
+ PERIPHC_DAM1,
+ PERIPHC_DAM2,
+ PERIPHC_HDA2CODEC2X,
+
+ /* 16 */
+ NONE(ATOMICS),
+ NONE(RESERVED17),
+ NONE(RESERVED18),
+ NONE(RESERVED19),
+ NONE(RESERVED20),
+ NONE(RESERVED21),
+ NONE(RESERVED22),
+ PERIPHC_ACTMON,
+
+ /* 24 */
+ NONE(RESERVED24),
+ NONE(RESERVED25),
+ NONE(RESERVED26),
+ NONE(RESERVED27),
+ PERIPHC_SATA,
+ PERIPHC_HDA,
+ NONE(RESERVED30),
+ NONE(RESERVED31),
+
+ /* W word: 31:0 */
+ NONE(HDA2HDMICODEC),
+ NONE(RESERVED1_SATACOLD),
+ NONE(RESERVED2_PCIERX0),
+ NONE(RESERVED3_PCIERX1),
+ NONE(RESERVED4_PCIERX2),
+ NONE(RESERVED5_PCIERX3),
+ NONE(RESERVED6_PCIERX4),
+ NONE(RESERVED7_PCIERX5),
+
+ /* 40 */
+ NONE(CEC),
+ NONE(PCIE2_IOBIST),
+ NONE(EMC_IOBIST),
+ NONE(HDMI_IOBIST),
+ NONE(SATA_IOBIST),
+ NONE(MIPI_IOBIST),
+ NONE(EMC1_IOBIST),
+ NONE(XUSB),
+
+ /* 48 */
+ NONE(CILAB),
+ NONE(CILCD),
+ NONE(CILE),
+ NONE(DSIA_LP),
+ NONE(DSIB_LP),
+ NONE(RESERVED21_ENTROPY),
+ NONE(RESERVED22_W),
+ NONE(RESERVED23_W),
+
+ /* 56 */
+ NONE(RESERVED24_W),
+ NONE(AMX0),
+ NONE(ADX0),
+ NONE(DVFS),
+ NONE(XUSB_SS),
+ NONE(EMC_DLL),
+ NONE(MC1),
+ NONE(EMC1),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that T30/T114 support 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ reg = readl(&clkrst->crc_osc_ctrl);
+ reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+ if (reg & 1) /* one of the newer freqs */
+ printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+ return reg >> 2; /* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ enum periphc_internal_id internal_id;
+
+ /* Coresight is a special case */
+ if (periph_id == PERIPH_ID_CSI)
+ return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+ assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+ internal_id = periph_id_to_internal_id[periph_id];
+ assert(internal_id != -1);
+ if (internal_id >= PERIPHC_VW_FIRST) {
+ internal_id -= PERIPHC_VW_FIRST;
+ return &clkrst->crc_clk_src_vw[internal_id];
+ } else
+ return &clkrst->crc_clk_src[internal_id];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id peripheral to start
+ * @param source PLL id of required parent clock
+ * @param mux_bits Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+ enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+ enum clock_type_id type;
+ enum periphc_internal_id internal_id;
+ int mux;
+
+ assert(clock_periph_id_isvalid(periph_id));
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ assert(periphc_internal_id_isvalid(internal_id));
+
+ type = clock_periph_type[internal_id];
+ assert(clock_type_id_isvalid(type));
+
+ *mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+ if (type == CLOCK_TYPE_PCMT16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
+
+ for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+ if (clock_source[type][mux] == parent)
+ return mux;
+
+ /* if we get here, either us or the caller has made a mistake */
+ printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+ parent);
+ return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 *clk;
+ u32 reg;
+
+ /* Enable/disable the clock to this peripheral */
+ assert(clock_periph_id_isvalid(periph_id));
+ if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+ clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+ else
+ clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+ reg = readl(clk);
+ if (enable)
+ reg |= PERIPH_MASK(periph_id);
+ else
+ reg &= ~PERIPH_MASK(periph_id);
+ writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 *reset;
+ u32 reg;
+
+ /* Enable/disable reset to the peripheral */
+ assert(clock_periph_id_isvalid(periph_id));
+ if (periph_id < PERIPH_ID_VW_FIRST)
+ reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+ else
+ reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+ reg = readl(reset);
+ if (enable)
+ reg |= PERIPH_MASK(periph_id);
+ else
+ reg &= ~PERIPH_MASK(periph_id);
+ writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id Clock ID according to tegra114 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+ if (clk_id > PERIPH_ID_COUNT)
+ return PERIPH_ID_NONE;
+
+ switch (clk_id) {
+ case PERIPH_ID_RESERVED3:
+ case PERIPH_ID_RESERVED16:
+ case PERIPH_ID_RESERVED24:
+ case PERIPH_ID_RESERVED35:
+ case PERIPH_ID_RESERVED43:
+ case PERIPH_ID_RESERVED45:
+ case PERIPH_ID_RESERVED56:
+ case PERIPH_ID_RESERVED76:
+ case PERIPH_ID_RESERVED77:
+ case PERIPH_ID_RESERVED78:
+ case PERIPH_ID_RESERVED83:
+ case PERIPH_ID_RESERVED89:
+ case PERIPH_ID_RESERVED91:
+ case PERIPH_ID_RESERVED93:
+ case PERIPH_ID_RESERVED94:
+ case PERIPH_ID_RESERVED95:
+ return PERIPH_ID_NONE;
+ default:
+ return clk_id;
+ }
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+
+ /*
+ * PLLP output frequency set to 408Mhz
+ * PLLC output frequency set to 600Mhz
+ * PLLD output frequency set to 925Mhz
+ */
+ switch (clock_get_osc_freq()) {
+ case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
+ break;
+
+ case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
+ break;
+
+ case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+ clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
+ break;
+ case CLOCK_OSC_FREQ_19_2:
+ default:
+ /*
+ * These are not supported. It is too early to print a
+ * message and the UART likely won't work anyway due to the
+ * oscillator being wrong.
+ */
+ break;
+ }
+
+ /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
+ writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
+
+ /* PLLC_MISC: Set LOCK_ENABLE */
+ writel(0x01000000, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc);
+ udelay(2);
+
+ /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1 */
+ writel(0x40000C10, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
+ udelay(2);
+}
diff --git a/arch/arm/cpu/tegra114-common/funcmux.c b/arch/arm/cpu/tegra114-common/funcmux.c
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+ int bad_config = config != FUNCMUX_DEFAULT;
+
+ switch (id) {
+ case PERIPH_ID_UART4:
+ switch (config) {
+ case FUNCMUX_UART4_GMI:
+ pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD);
+ pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD);
+ pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD);
+ pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD);
+
+ pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT);
+ pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT);
+ pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT);
+ pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT);
+
+ pinmux_tristate_disable(PINGRP_GMI_A16);
+ pinmux_tristate_disable(PINGRP_GMI_A17);
+ pinmux_tristate_disable(PINGRP_GMI_A18);
+ pinmux_tristate_disable(PINGRP_GMI_A19);
+ break;
+ }
+ break;
+
+ /* Add other periph IDs here as needed */
+
+ default:
+ debug("%s: invalid periph_id %d", __func__, id);
+ return -1;
+ }
+
+ if (bad_config) {
+ debug("%s: invalid config %d for periph_id %d", __func__,
+ config, id);
+ return -1;
+ }
+ return 0;
+}
diff --git a/arch/arm/cpu/tegra114-common/pinmux.c b/arch/arm/cpu/tegra114-common/pinmux.c
--- /dev/null
@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 pin multiplexing functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+
+struct tegra_pingroup_desc {
+ const char *name;
+ enum pmux_func funcs[4];
+ enum pmux_func func_safe;
+ enum pmux_vddio vddio;
+ enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT 0
+#define PMUX_PULL_SHIFT 2
+#define PMUX_TRISTATE_SHIFT 4
+#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT 5
+#define PMUX_OD_SHIFT 6
+#define PMUX_LOCK_SHIFT 7
+#define PMUX_IO_RESET_SHIFT 8
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
+ { \
+ .vddio = PMUX_VDDIO_ ## vdd, \
+ .funcs = { \
+ PMUX_FUNC_ ## f0, \
+ PMUX_FUNC_ ## f1, \
+ PMUX_FUNC_ ## f2, \
+ PMUX_FUNC_ ## f3, \
+ }, \
+ .func_safe = PMUX_FUNC_RSVD1, \
+ .io = PMUX_PIN_ ## iod, \
+ }
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+ PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+ PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+ /* NAME VDD f0 f1 f2 f3 */
+ PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
+ PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
+ PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
+ PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
+ PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
+ PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
+ PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
+ PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
+ PINI(GPIO_PV2, BB, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PV3, BB, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_PWR1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_PWR2, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_SDIN, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_SDOUT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_WR_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_CS0_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_DC0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_SCK, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_PWR0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_PCLK, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_DE, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_HSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_VSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D0, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D2, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D3, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D4, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D5, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D6, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D7, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D8, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D9, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D10, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D11, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D12, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D13, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D14, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D15, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D16, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D17, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D18, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D19, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D20, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D21, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D22, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_D23, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_CS1_N, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_M1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_DC1, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
+ PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
+ PINI(CRT_HSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(CRT_VSYNC, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D0, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D1, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D2, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D3, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D4, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D5, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D6, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D7, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D8, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D9, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D10, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D11, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_PCLK, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_MCLK, VI, RSVD1, RSVD3, RSVD3, RSVD4),
+ PINI(VI_VSYNC, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(VI_HSYNC, VI, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
+ PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
+ PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
+ PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
+ PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
+ PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
+ PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
+ PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
+ PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
+ PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
+ PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
+ PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
+ PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
+ PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
+ PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
+ PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
+ PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
+ PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
+ PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
+ PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
+ PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
+ PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
+ PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
+ PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
+ PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
+ PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
+ PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
+ PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
+ PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
+ PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
+ PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
+ PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
+ PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
+ PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
+ PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
+ PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
+ PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
+ PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
+ PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
+ PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
+ PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
+ PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
+ PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
+ PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
+ PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
+ PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
+ PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
+ PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
+ PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
+ PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
+ PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
+ PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
+ PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
+ PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
+ PINI(SDMMC4_RST_N, SDMMC4, RSVD1, RSVD2, RSVD3, SDMMC4),
+ PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT2, RSVD4),
+ PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
+ PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
+ PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
+ PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
+ PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
+ PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
+ PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
+ PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
+ PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
+ PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
+ PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
+ PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
+ PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
+ PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
+ PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
+ PINI(KB_ROW11, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(KB_ROW12, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(KB_ROW13, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(KB_ROW14, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(KB_ROW15, SYS, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
+ PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
+ PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
+ PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
+ PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
+ PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
+ PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
+ PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
+ PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
+ PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
+ PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
+ PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
+ PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
+ PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
+ PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
+ PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
+ PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
+ PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
+ PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
+ PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
+ PINI(SPI2_MOSI, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
+ PINI(SPI2_MISO, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
+ PINI(SPI2_CS0_N, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
+ PINI(SPI2_SCK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
+ PINI(SPI1_MOSI, AUDIO, RSVD1, SPI1, SPI2, DAP2),
+ PINI(SPI1_SCK, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
+ PINI(SPI1_CS0_N, AUDIO, SPI6, SPI1, SPI2, RSVD4),
+ PINI(SPI1_MISO, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
+ PINI(SPI2_CS1_N, AUDIO, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(SPI2_CS2_N, AUDIO, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
+ PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
+ PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
+ PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
+ PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
+ PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
+ PINI(SDMMC3_DAT4, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC3_DAT5, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC3_DAT6, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC3_DAT7, SDMMC3, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
+ PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
+ PINI(SDMMC3_CD_N, SDMMC3, SDMMC3, OWR, RSVD3, RSVD4),
+ PINI(SPI1_CS1_N, AUDIO, SPI6, RSVD2, SPI2, I2C1),
+ PINI(SPI1_CS2_N, AUDIO, SPI6, SPI1, SPI2, I2C1),
+ PINI(USB_VBUS_EN0, SYS, USB, RSVD2, RSVD3, RSVD4),
+ PINI(USB_VBUS_EN1, SYS, USB, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PINO(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
+ PINO(NAND_GMI_CLK_LB, GMI, SDMMC2, NAND, GMI, RSVD4),
+ PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *tri = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin */
+ assert(pmux_pingrp_isvalid(pin));
+
+ reg = readl(tri);
+ if (enable)
+ reg |= PMUX_TRISTATE_MASK;
+ else
+ reg &= ~PMUX_TRISTATE_MASK;
+ writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pull = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and pupd */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_pupd_isvalid(pupd));
+
+ reg = readl(pull);
+ reg &= ~(0x3 << PMUX_PULL_SHIFT);
+ reg |= (pupd << PMUX_PULL_SHIFT);
+ writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *muxctl = &pmt->pmt_ctl[pin];
+ int i, mux = -1;
+ u32 reg;
+
+ /* Error check on pin and func */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_func_isvalid(func));
+
+ /* Handle special values */
+ if (func == PMUX_FUNC_SAFE)
+ func = tegra_soc_pingroups[pin].func_safe;
+
+ if (func & PMUX_FUNC_RSVD1) {
+ mux = func & 0x3;
+ } else {
+ /* Search for the appropriate function */
+ for (i = 0; i < 4; i++) {
+ if (tegra_soc_pingroups[pin].funcs[i] == func) {
+ mux = i;
+ break;
+ }
+ }
+ }
+ assert(mux != -1);
+
+ reg = readl(muxctl);
+ reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+ reg |= (mux << PMUX_MUXCTL_SHIFT);
+ writel(reg, muxctl);
+
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_io = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and io */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_io_isvalid(io));
+
+ reg = readl(pin_io);
+ reg &= ~(0x1 << PMUX_IO_SHIFT);
+ reg |= (io & 0x1) << PMUX_IO_SHIFT;
+ writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_lock = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and lock */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_lock_isvalid(lock));
+
+ if (lock == PMUX_PIN_LOCK_DEFAULT)
+ return 0;
+
+ reg = readl(pin_lock);
+ reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+ if (lock == PMUX_PIN_LOCK_ENABLE)
+ reg |= (0x1 << PMUX_LOCK_SHIFT);
+ else {
+ /* lock == DISABLE, which isn't possible */
+ printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
+ __func__, lock);
+ }
+ writel(reg, pin_lock);
+
+ return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_od = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and od */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_od_isvalid(od));
+
+ if (od == PMUX_PIN_OD_DEFAULT)
+ return 0;
+
+ reg = readl(pin_od);
+ reg &= ~(0x1 << PMUX_OD_SHIFT);
+ if (od == PMUX_PIN_OD_ENABLE)
+ reg |= (0x1 << PMUX_OD_SHIFT);
+ writel(reg, pin_od);
+
+ return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+ enum pmux_pin_ioreset ioreset)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and ioreset */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_ioreset_isvalid(ioreset));
+
+ if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+ return 0;
+
+ reg = readl(pin_ioreset);
+ reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+ if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+ reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+ writel(reg, pin_ioreset);
+
+ return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+ enum pmux_pingrp pin = config->pingroup;
+
+ pinmux_set_func(pin, config->func);
+ pinmux_set_pullupdown(pin, config->pull);
+ pinmux_set_tristate(pin, config->tristate);
+ pinmux_set_io(pin, config->io);
+ pinmux_set_lock(pin, config->lock);
+ pinmux_set_od(pin, config->od);
+ pinmux_set_ioreset(pin, config->ioreset);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ pinmux_config_pingroup(&config[i]);
+}
index 12987a6893691f8646016ac1e242b71519a811da..ec93894f4868f470dabcb7ef66350a999f71d492 100644 (file)
#include <div64.h>
#include <fdtdec.h>
-/*
- * This is our record of the current clock rate of each clock. We don't
- * fill all of these in since we are only really interested in clocks which
- * we use as parents.
- */
-static unsigned pll_rate[CLOCK_ID_COUNT];
-
-/*
- * The oscillator frequency is fixed to one of four set values. Based on this
- * the other clocks are set up appropriately.
- */
-static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
- 13000000,
- 19200000,
- 12000000,
- 26000000,
-};
-
/*
* Clock types that we can use as a source. The Tegra20 has muxes for the
* peripheral clocks, and in most cases there are four options for the clock
CLOCK_TYPE_NONE = -1, /* invalid clock type */
};
-/* return 1 if a peripheral ID is in range */
-#define clock_type_id_isvalid(id) ((id) >= 0 && \
- (id) < CLOCK_TYPE_COUNT)
-
-char pllp_valid = 1; /* PLLP is set up correctly */
-
enum {
CLOCK_MAX_MUX = 4 /* number of source options for each clock */
};
PERIPHC_NONE = -1,
};
-/* return 1 if a periphc_internal_id is in range */
-#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
- (id) < PERIPHC_COUNT)
-
/*
* Clock type for each peripheral clock source. We put the name in each
* record just so it is easy to match things up
NONE(CRAM2),
};
-/* number of clock outputs of a PLL */
-static const u8 pll_num_clkouts[] = {
- 1, /* PLLC */
- 1, /* PLLM */
- 4, /* PLLP */
- 1, /* PLLA */
- 0, /* PLLU */
- 0, /* PLLD */
-};
-
/*
* Get the oscillator frequency, from the corresponding hardware configuration
- * field.
+ * field. T20 has 4 frequencies that it supports.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}
-int clock_get_osc_bypass(void)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 reg;
-
- reg = readl(&clkrst->crc_osc_ctrl);
- return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
-}
-
-/* Returns a pointer to the registers of the given pll */
-static struct clk_pll *get_pll(enum clock_id clkid)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-
- assert(clock_id_is_pll(clkid));
- return &clkrst->crc_pll[clkid];
-}
-
-int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
- u32 *divp, u32 *cpcon, u32 *lfcon)
-{
- struct clk_pll *pll = get_pll(clkid);
- u32 data;
-
- assert(clkid != CLOCK_ID_USB);
-
- /* Safety check, adds to code size but is small */
- if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
- return -1;
- data = readl(&pll->pll_base);
- *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
- *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
- *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
- data = readl(&pll->pll_misc);
- *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
- *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
-
- return 0;
-}
-
-unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
- u32 divp, u32 cpcon, u32 lfcon)
-{
- struct clk_pll *pll = get_pll(clkid);
- u32 data;
-
- /*
- * We cheat by treating all PLL (except PLLU) in the same fashion.
- * This works only because:
- * - same fields are always mapped at same offsets, except DCCON
- * - DCCON is always 0, doesn't conflict
- * - M,N, P of PLLP values are ignored for PLLP
- */
- data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
- writel(data, &pll->pll_misc);
-
- data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
- (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
-
- if (clkid == CLOCK_ID_USB)
- data |= divp << PLLU_VCO_FREQ_SHIFT;
- else
- data |= divp << PLL_DIVP_SHIFT;
- writel(data, &pll->pll_base);
-
- /* calculate the stable time */
- return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
-}
-
-/* return 1 if a peripheral ID is in range and valid */
-static int clock_periph_id_isvalid(enum periph_id id)
-{
- if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
- printf("Peripheral id %d out of range\n", id);
- else {
- switch (id) {
- case PERIPH_ID_RESERVED1:
- case PERIPH_ID_RESERVED2:
- case PERIPH_ID_RESERVED30:
- case PERIPH_ID_RESERVED35:
- case PERIPH_ID_RESERVED56:
- case PERIPH_ID_RESERVED74:
- case PERIPH_ID_RESERVED76:
- case PERIPH_ID_RESERVED77:
- case PERIPH_ID_RESERVED78:
- case PERIPH_ID_RESERVED79:
- case PERIPH_ID_RESERVED80:
- case PERIPH_ID_RESERVED81:
- case PERIPH_ID_RESERVED82:
- case PERIPH_ID_RESERVED83:
- case PERIPH_ID_RESERVED91:
- printf("Peripheral id %d is reserved\n", id);
- break;
- default:
- return 1;
- }
- }
- return 0;
-}
-
/* Returns a pointer to the clock source register for a peripheral */
-static u32 *get_periph_source_reg(enum periph_id periph_id)
+u32 *get_periph_source_reg(enum periph_id periph_id)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
return &clkrst->crc_clk_src[internal_id];
}
-void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
- unsigned divisor)
-{
- u32 *reg = get_periph_source_reg(periph_id);
- u32 value;
-
- value = readl(reg);
-
- value &= ~OUT_CLK_SOURCE_MASK;
- value |= source << OUT_CLK_SOURCE_SHIFT;
-
- value &= ~OUT_CLK_DIVISOR_MASK;
- value |= divisor << OUT_CLK_DIVISOR_SHIFT;
-
- writel(value, reg);
-}
-
-void clock_ll_set_source(enum periph_id periph_id, unsigned source)
-{
- u32 *reg = get_periph_source_reg(periph_id);
-
- clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
- source << OUT_CLK_SOURCE_SHIFT);
-}
-
-/**
- * Given the parent's rate and the required rate for the children, this works
- * out the peripheral clock divider to use, in 7.1 binary format.
- *
- * @param divider_bits number of divider bits (8 or 16)
- * @param parent_rate clock rate of parent clock in Hz
- * @param rate required clock rate for this clock
- * @return divider which should be used
- */
-static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
- unsigned long rate)
-{
- u64 divider = parent_rate * 2;
- unsigned max_divider = 1 << divider_bits;
-
- divider += rate - 1;
- do_div(divider, rate);
-
- if ((s64)divider - 2 < 0)
- return 0;
-
- if ((s64)divider - 2 >= max_divider)
- return -1;
-
- return divider - 2;
-}
-
-/**
- * Given the parent's rate and the divider in 7.1 format, this works out the
- * resulting peripheral clock rate.
- *
- * @param parent_rate clock rate of parent clock in Hz
- * @param divider which should be used in 7.1 format
- * @return effective clock rate of peripheral
- */
-static unsigned long get_rate_from_divider(unsigned long parent_rate,
- int divider)
-{
- u64 rate;
-
- rate = (u64)parent_rate * 2;
- do_div(rate, divider + 2);
- return rate;
-}
-
-unsigned long clock_get_periph_rate(enum periph_id periph_id,
- enum clock_id parent)
-{
- u32 *reg = get_periph_source_reg(periph_id);
-
- return get_rate_from_divider(pll_rate[parent],
- (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
-}
-
-int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
-{
- struct clk_pll *pll = get_pll(clkid);
- int data = 0, div = 0, offset = 0;
-
- if (!clock_id_is_pll(clkid))
- return -1;
-
- if (pllout + 1 > pll_num_clkouts[clkid])
- return -1;
-
- div = clk_get_divider(8, pll_rate[clkid], rate);
-
- if (div < 0)
- return -1;
-
- /* out2 and out4 are in the high part of the register */
- if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
- offset = 16;
-
- data = (div << PLL_OUT_RATIO_SHIFT) |
- PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
- clrsetbits_le32(&pll->pll_out[pllout >> 1],
- PLL_OUT_RATIO_MASK << offset, data << offset);
-
- return 0;
-}
-
-/**
- * Find the best available 7.1 format divisor given a parent clock rate and
- * required child clock rate. This function assumes that a second-stage
- * divisor is available which can divide by powers of 2 from 1 to 256.
- *
- * @param divider_bits number of divider bits (8 or 16)
- * @param parent_rate clock rate of parent clock in Hz
- * @param rate required clock rate for this clock
- * @param extra_div value for the second-stage divisor (not set if this
- * function returns -1.
- * @return divider which should be used, or -1 if nothing is valid
- *
- */
-static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
- unsigned long rate, int *extra_div)
-{
- int shift;
- int best_divider = -1;
- int best_error = rate;
-
- /* try dividers from 1 to 256 and find closest match */
- for (shift = 0; shift <= 8 && best_error > 0; shift++) {
- unsigned divided_parent = parent_rate >> shift;
- int divider = clk_get_divider(divider_bits, divided_parent,
- rate);
- unsigned effective_rate = get_rate_from_divider(divided_parent,
- divider);
- int error = rate - effective_rate;
-
- /* Given a valid divider, look for the lowest error */
- if (divider != -1 && error < best_error) {
- best_error = error;
- *extra_div = 1 << shift;
- best_divider = divider;
- }
- }
-
- /* return what we found - *extra_div will already be set */
- return best_divider;
-}
-
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
* @param divider_bits Set to number of divider bits (8 or 16)
* @return mux value (0-4, or -1 if not found)
*/
-static int get_periph_clock_source(enum periph_id periph_id,
+int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits)
{
enum clock_type_id type;
return -1;
}
-/**
- * Adjust peripheral PLL to use the given divider and source.
- *
- * @param periph_id peripheral to adjust
- * @param source Source number (0-3 or 0-7)
- * @param mux_bits Number of mux bits (2 or 4)
- * @param divider Required divider in 7.1 or 15.1 format
- * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
- * for this peripheral)
- */
-static int adjust_periph_pll(enum periph_id periph_id, int source,
- int mux_bits, unsigned divider)
-{
- u32 *reg = get_periph_source_reg(periph_id);
-
- clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
- divider << OUT_CLK_DIVISOR_SHIFT);
- udelay(1);
-
- /* work out the source clock and set it */
- if (source < 0)
- return -1;
- if (mux_bits == 4) {
- clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
- source << OUT_CLK_SOURCE4_SHIFT);
- } else {
- clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
- source << OUT_CLK_SOURCE_SHIFT);
- }
- udelay(2);
- return 0;
-}
-
-unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
- enum clock_id parent, unsigned rate, int *extra_div)
-{
- unsigned effective_rate;
- int mux_bits, divider_bits, source;
- int divider;
-
- /* work out the source clock and set it */
- source = get_periph_clock_source(periph_id, parent, &mux_bits,
- ÷r_bits);
-
- if (extra_div)
- divider = find_best_divider(divider_bits, pll_rate[parent],
- rate, extra_div);
- else
- divider = clk_get_divider(divider_bits, pll_rate[parent],
- rate);
- assert(divider >= 0);
- if (adjust_periph_pll(periph_id, source, mux_bits, divider))
- return -1U;
- debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
- get_periph_source_reg(periph_id),
- readl(get_periph_source_reg(periph_id)));
-
- /* Check what we ended up with. This shouldn't matter though */
- effective_rate = clock_get_periph_rate(periph_id, parent);
- if (extra_div)
- effective_rate /= *extra_div;
- if (rate != effective_rate)
- debug("Requested clock rate %u not honored (got %u)\n",
- rate, effective_rate);
- return effective_rate;
-}
-
-unsigned clock_start_periph_pll(enum periph_id periph_id,
- enum clock_id parent, unsigned rate)
-{
- unsigned effective_rate;
-
- reset_set_enable(periph_id, 1);
- clock_enable(periph_id);
-
- effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
- NULL);
-
- reset_set_enable(periph_id, 0);
- return effective_rate;
-}
-
void clock_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
writel(reg, clk);
}
-void clock_enable(enum periph_id clkid)
-{
- clock_set_enable(clkid, 1);
-}
-
-void clock_disable(enum periph_id clkid)
-{
- clock_set_enable(clkid, 0);
-}
-
void reset_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
writel(reg, reset);
}
-void reset_periph(enum periph_id periph_id, int us_delay)
-{
- /* Put peripheral into reset */
- reset_set_enable(periph_id, 1);
- udelay(us_delay);
-
- /* Remove reset */
- reset_set_enable(periph_id, 0);
-
- udelay(us_delay);
-}
-
-void reset_cmplx_set_enable(int cpu, int which, int reset)
-{
- struct clk_rst_ctlr *clkrst =
- (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
- u32 mask;
-
- /* Form the mask, which depends on the cpu chosen. Tegra20 has 2 */
- assert(cpu >= 0 && cpu < 2);
- mask = which << cpu;
-
- /* either enable or disable those reset for that CPU */
- if (reset)
- writel(mask, &clkrst->crc_cpu_cmplx_set);
- else
- writel(mask, &clkrst->crc_cpu_cmplx_clr);
-}
-
-unsigned clock_get_rate(enum clock_id clkid)
-{
- struct clk_pll *pll;
- u32 base;
- u32 divm;
- u64 parent_rate;
- u64 rate;
-
- parent_rate = osc_freq[clock_get_osc_freq()];
- if (clkid == CLOCK_ID_OSC)
- return parent_rate;
-
- pll = get_pll(clkid);
- base = readl(&pll->pll_base);
-
- /* Oh for bf_unpack()... */
- rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
- divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
- if (clkid == CLOCK_ID_USB)
- divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
- else
- divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
- do_div(rate, divm);
- return rate;
-}
-
-/**
- * Set the output frequency you want for each PLL clock.
- * PLL output frequencies are programmed by setting their N, M and P values.
- * The governing equations are:
- * VCO = (Fi / m) * n, Fo = VCO / (2^p)
- * where Fo is the output frequency from the PLL.
- * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
- * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
- * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
- *
- * @param n PLL feedback divider(DIVN)
- * @param m PLL input divider(DIVN)
- * @param p post divider(DIVP)
- * @param cpcon base PLL charge pump(CPCON)
- * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
- * be overriden), 1 if PLL is already correct
- */
-static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
-{
- u32 base_reg;
- u32 misc_reg;
- struct clk_pll *pll;
-
- pll = get_pll(clkid);
-
- base_reg = readl(&pll->pll_base);
-
- /* Set BYPASS, m, n and p to PLL_BASE */
- base_reg &= ~PLL_DIVM_MASK;
- base_reg |= m << PLL_DIVM_SHIFT;
-
- base_reg &= ~PLL_DIVN_MASK;
- base_reg |= n << PLL_DIVN_SHIFT;
-
- base_reg &= ~PLL_DIVP_MASK;
- base_reg |= p << PLL_DIVP_SHIFT;
-
- if (clkid == CLOCK_ID_PERIPH) {
- /*
- * If the PLL is already set up, check that it is correct
- * and record this info for clock_verify() to check.
- */
- if (base_reg & PLL_BASE_OVRRIDE_MASK) {
- base_reg |= PLL_ENABLE_MASK;
- if (base_reg != readl(&pll->pll_base))
- pllp_valid = 0;
- return pllp_valid ? 1 : -1;
- }
- base_reg |= PLL_BASE_OVRRIDE_MASK;
- }
-
- base_reg |= PLL_BYPASS_MASK;
- writel(base_reg, &pll->pll_base);
-
- /* Set cpcon to PLL_MISC */
- misc_reg = readl(&pll->pll_misc);
- misc_reg &= ~PLL_CPCON_MASK;
- misc_reg |= cpcon << PLL_CPCON_SHIFT;
- writel(misc_reg, &pll->pll_misc);
-
- /* Enable PLL */
- base_reg |= PLL_ENABLE_MASK;
- writel(base_reg, &pll->pll_base);
-
- /* Disable BYPASS */
- base_reg &= ~PLL_BYPASS_MASK;
- writel(base_reg, &pll->pll_base);
-
- return 0;
-}
-
-void clock_ll_start_uart(enum periph_id periph_id)
-{
- /* Assert UART reset and enable clock */
- reset_set_enable(periph_id, 1);
- clock_enable(periph_id);
- clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
-
- /* wait for 2us */
- udelay(2);
-
- /* De-assert reset to UART */
- reset_set_enable(periph_id, 0);
-}
-
#ifdef CONFIG_OF_CONTROL
/*
* Convert a device tree clock ID to our peripheral ID. They are mostly
* @param clk_id Clock ID according to tegra20 device tree binding
* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
*/
-static enum periph_id clk_id_to_periph_id(int clk_id)
+enum periph_id clk_id_to_periph_id(int clk_id)
{
- if (clk_id > 95)
+ if (clk_id > PERIPH_ID_COUNT)
return PERIPH_ID_NONE;
switch (clk_id) {
- case 1:
- case 2:
- case 7:
- case 10:
- case 20:
- case 30:
- case 35:
- case 49:
- case 56:
- case 74:
- case 76:
- case 77:
- case 78:
- case 79:
- case 80:
- case 81:
- case 82:
- case 83:
- case 91:
- case 95:
+ case PERIPH_ID_RESERVED1:
+ case PERIPH_ID_RESERVED2:
+ case PERIPH_ID_RESERVED30:
+ case PERIPH_ID_RESERVED35:
+ case PERIPH_ID_RESERVED56:
+ case PERIPH_ID_RESERVED74:
+ case PERIPH_ID_RESERVED76:
+ case PERIPH_ID_RESERVED77:
+ case PERIPH_ID_RESERVED78:
+ case PERIPH_ID_RESERVED79:
+ case PERIPH_ID_RESERVED80:
+ case PERIPH_ID_RESERVED81:
+ case PERIPH_ID_RESERVED82:
+ case PERIPH_ID_RESERVED83:
+ case PERIPH_ID_RESERVED91:
return PERIPH_ID_NONE;
default:
return clk_id;
}
}
-
-int clock_decode_periph_id(const void *blob, int node)
-{
- enum periph_id id;
- u32 cell[2];
- int err;
-
- err = fdtdec_get_int_array(blob, node, "clocks", cell,
- ARRAY_SIZE(cell));
- if (err)
- return -1;
- id = clk_id_to_periph_id(cell[1]);
- assert(clock_periph_id_isvalid(id));
- return id;
-}
#endif /* CONFIG_OF_CONTROL */
-int clock_verify(void)
-{
- struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
- u32 reg = readl(&pll->pll_base);
-
- if (!pllp_valid) {
- printf("Warning: PLLP %x is not correct\n", reg);
- return -1;
- }
- debug("PLLX %x is correct\n", reg);
- return 0;
-}
-
void clock_early_init(void)
{
/*
break;
}
}
-
-void clock_init(void)
-{
- pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
- pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
- pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
- pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
- pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
- debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
- debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
- debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
-}
index ece7ad9ec954333a9bc9a85769adc97d82b2fe08..80a9bd9e28463edf774a783387769371ff341f15 100644 (file)
break;
case PERIPH_ID_UART2:
- if (config == FUNCMUX_UART2_IRDA) {
- pinmux_set_func(PINGRP_UAD, PMUX_FUNC_IRDA);
+ if (config == FUNCMUX_UART2_UAD) {
+ pinmux_set_func(PINGRP_UAD, PMUX_FUNC_UARTB);
pinmux_tristate_disable(PINGRP_UAD);
}
break;
index a2a09169e54bc46acbdc0b2bc5f89478a775b2be..5ad2121c5d08753759064c04385696d95c7a156e 100644 (file)
PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
- PIN(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF),
+ PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF),
PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
index 157b9abc4597b1fbaebb788dc2732e35dbfee3ef..0d472cfe33c7f1ae246071f200531117b1b495a7 100644 (file)
* This is the place in SRAM where the SDRAM parameters are stored. There
* are 4 blocks, one for each RAM code
*/
-#define SDRAM_PARAMS_BASE (AP20_BASE_PA_SRAM + 0x188)
+#define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
/* TODO: If we later add support for the Misc GP controller, refactor this */
union xm2cfga_reg {
diff --git a/arch/arm/cpu/tegra30-common/Makefile b/arch/arm/cpu/tegra30-common/Makefile
--- /dev/null
@@ -0,0 +1,44 @@
+#
+# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+# The AVP is ARMv4T architecture so we must use special compiler
+# flags for any startup files it might use.
+
+LIB = $(obj)lib$(SOC)-common.o
+
+COBJS-y += clock.o funcmux.o pinmux.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/tegra30-common/clock.c b/arch/arm/cpu/tegra30-common/clock.c
--- /dev/null
@@ -0,0 +1,618 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra30 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+ CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
+ CLOCK_TYPE_MCPA, /* and so on */
+ CLOCK_TYPE_MCPT,
+ CLOCK_TYPE_PCM,
+ CLOCK_TYPE_PCMT,
+ CLOCK_TYPE_PCMT16,
+ CLOCK_TYPE_PDCT,
+ CLOCK_TYPE_ACPT,
+ CLOCK_TYPE_ASPTE,
+ CLOCK_TYPE_PMDACD2T,
+ CLOCK_TYPE_PCST,
+
+ CLOCK_TYPE_COUNT,
+ CLOCK_TYPE_NONE = -1, /* invalid clock type */
+};
+
+enum {
+ CLOCK_MAX_MUX = 8 /* number of source options for each clock */
+};
+
+enum {
+ MASK_BITS_31_30 = 2, /* num of bits used to specify clock source */
+ MASK_BITS_31_29,
+ MASK_BITS_29_28,
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ * The extra column in each clock source array is used to store the mask
+ * bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+ { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_30},
+ { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
+ CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
+ CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
+ MASK_BITS_31_29},
+ { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_29_28}
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+ /* 0x00 */
+ TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
+ TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
+
+ /* 0x08 */
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
+
+ /* 0x10 */
+ TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
+
+ /* 0x18 */
+ TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
+ TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
+
+ /* 0x20 */
+ TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
+ TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
+ TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
+
+ /* 0x28 */
+ TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
+
+ /* 0x30 */
+ TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+
+ /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
+ TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
+ TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
+ TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
+ TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
+ TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
+
+ /* 0x40 */
+ TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
+ TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
+ TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
+
+ /* 0x48 */
+ TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
+ TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
+ TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+
+ /* 0x50 */
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
+ TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
+ TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
+};
+
+/*
+ * This array translates a periph_id to a periphc_internal_id
+ *
+ * Not present/matched up:
+ * uint vi_sensor; _VI_SENSOR_0, 0x1A8
+ * SPDIF - which is both 0x08 and 0x0c
+ *
+ */
+#define NONE(name) (-1)
+#define OFFSET(name, value) PERIPHC_ ## name
+static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
+ /* Low word: 31:0 */
+ NONE(CPU),
+ NONE(COP),
+ NONE(TRIGSYS),
+ NONE(RESERVED3),
+ NONE(RESERVED4),
+ NONE(TMR),
+ PERIPHC_UART1,
+ PERIPHC_UART2, /* and vfir 0x68 */
+
+ /* 8 */
+ NONE(GPIO),
+ PERIPHC_SDMMC2,
+ NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
+ PERIPHC_I2S1,
+ PERIPHC_I2C1,
+ PERIPHC_NDFLASH,
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC4,
+
+ /* 16 */
+ NONE(RESERVED16),
+ PERIPHC_PWM,
+ PERIPHC_I2S2,
+ PERIPHC_EPP,
+ PERIPHC_VI,
+ PERIPHC_G2D,
+ NONE(USBD),
+ NONE(ISP),
+
+ /* 24 */
+ PERIPHC_G3D,
+ NONE(RESERVED25),
+ PERIPHC_DISP2,
+ PERIPHC_DISP1,
+ PERIPHC_HOST1X,
+ NONE(VCP),
+ PERIPHC_I2S0,
+ NONE(CACHE2),
+
+ /* Middle word: 63:32 */
+ NONE(MEM),
+ NONE(AHBDMA),
+ NONE(APBDMA),
+ NONE(RESERVED35),
+ NONE(RESERVED36),
+ NONE(STAT_MON),
+ NONE(RESERVED38),
+ NONE(RESERVED39),
+
+ /* 40 */
+ NONE(KFUSE),
+ PERIPHC_SBC1,
+ PERIPHC_NOR,
+ NONE(RESERVED43),
+ PERIPHC_SBC2,
+ NONE(RESERVED45),
+ PERIPHC_SBC3,
+ PERIPHC_DVC_I2C,
+
+ /* 48 */
+ NONE(DSI),
+ PERIPHC_TVO, /* also CVE 0x40 */
+ PERIPHC_MIPI,
+ PERIPHC_HDMI,
+ NONE(CSI),
+ PERIPHC_TVDAC,
+ PERIPHC_I2C2,
+ PERIPHC_UART3,
+
+ /* 56 */
+ NONE(RESERVED56),
+ PERIPHC_EMC,
+ NONE(USB2),
+ NONE(USB3),
+ PERIPHC_MPE,
+ PERIPHC_VDE,
+ NONE(BSEA),
+ NONE(BSEV),
+
+ /* Upper word 95:64 */
+ PERIPHC_SPEEDO,
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_I2C3,
+ PERIPHC_SBC4,
+ PERIPHC_SDMMC3,
+ NONE(PCIE),
+ PERIPHC_OWR,
+
+ /* 72 */
+ NONE(AFI),
+ PERIPHC_CSITE,
+ NONE(PCIEXCLK),
+ NONE(AVPUCQ),
+ NONE(RESERVED76),
+ NONE(RESERVED77),
+ NONE(RESERVED78),
+ NONE(DTV),
+
+ /* 80 */
+ PERIPHC_NANDSPEED,
+ PERIPHC_I2CSLOW,
+ NONE(DSIB),
+ NONE(RESERVED83),
+ NONE(IRAMA),
+ NONE(IRAMB),
+ NONE(IRAMC),
+ NONE(IRAMD),
+
+ /* 88 */
+ NONE(CRAM2),
+ NONE(RESERVED89),
+ NONE(MDOUBLER),
+ NONE(RESERVED91),
+ NONE(SUSOUT),
+ NONE(RESERVED93),
+ NONE(RESERVED94),
+ NONE(RESERVED95),
+
+ /* V word: 31:0 */
+ NONE(CPUG),
+ NONE(CPULP),
+ PERIPHC_G3D2,
+ PERIPHC_MSELECT,
+ PERIPHC_TSENSOR,
+ PERIPHC_I2S3,
+ PERIPHC_I2S4,
+ PERIPHC_I2C4,
+
+ /* 08 */
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+ PERIPHC_AUDIO,
+ NONE(APBIF),
+ PERIPHC_DAM0,
+ PERIPHC_DAM1,
+ PERIPHC_DAM2,
+ PERIPHC_HDA2CODEC2X,
+
+ /* 16 */
+ NONE(ATOMICS),
+ NONE(RESERVED17),
+ NONE(RESERVED18),
+ NONE(RESERVED19),
+ NONE(RESERVED20),
+ NONE(RESERVED21),
+ NONE(RESERVED22),
+ PERIPHC_ACTMON,
+
+ /* 24 */
+ NONE(RESERVED24),
+ NONE(RESERVED25),
+ NONE(RESERVED26),
+ NONE(RESERVED27),
+ PERIPHC_SATA,
+ PERIPHC_HDA,
+ NONE(RESERVED30),
+ NONE(RESERVED31),
+
+ /* W word: 31:0 */
+ NONE(HDA2HDMICODEC),
+ NONE(SATACOLD),
+ NONE(RESERVED0_PCIERX0),
+ NONE(RESERVED1_PCIERX1),
+ NONE(RESERVED2_PCIERX2),
+ NONE(RESERVED3_PCIERX3),
+ NONE(RESERVED4_PCIERX4),
+ NONE(RESERVED5_PCIERX5),
+
+ /* 40 */
+ NONE(CEC),
+ NONE(RESERVED6_PCIE2),
+ NONE(RESERVED7_EMC),
+ NONE(RESERVED8_HDMI),
+ NONE(RESERVED9_SATA),
+ NONE(RESERVED10_MIPI),
+ NONE(EX_RESERVED46),
+ NONE(EX_RESERVED47),
+};
+
+/*
+ * Get the oscillator frequency, from the corresponding hardware configuration
+ * field. Note that T30 supports 3 new higher freqs, but we map back
+ * to the old T20 freqs. Support for the higher oscillators is TBD.
+ */
+enum clock_osc_freq clock_get_osc_freq(void)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 reg;
+
+ reg = readl(&clkrst->crc_osc_ctrl);
+ reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
+
+ if (reg & 1) /* one of the newer freqs */
+ printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
+
+ return reg >> 2; /* Map to most common (T20) freqs */
+}
+
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ enum periphc_internal_id internal_id;
+
+ /* Coresight is a special case */
+ if (periph_id == PERIPH_ID_CSI)
+ return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
+
+ assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
+ internal_id = periph_id_to_internal_id[periph_id];
+ assert(internal_id != -1);
+ if (internal_id >= PERIPHC_VW_FIRST) {
+ internal_id -= PERIPHC_VW_FIRST;
+ return &clkrst->crc_clk_src_vw[internal_id];
+ } else
+ return &clkrst->crc_clk_src[internal_id];
+}
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id peripheral to start
+ * @param source PLL id of required parent clock
+ * @param mux_bits Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+ enum clock_id parent, int *mux_bits, int *divider_bits)
+{
+ enum clock_type_id type;
+ enum periphc_internal_id internal_id;
+ int mux;
+
+ assert(clock_periph_id_isvalid(periph_id));
+
+ internal_id = periph_id_to_internal_id[periph_id];
+ assert(periphc_internal_id_isvalid(internal_id));
+
+ type = clock_periph_type[internal_id];
+ assert(clock_type_id_isvalid(type));
+
+ *mux_bits = clock_source[type][CLOCK_MAX_MUX];
+
+ if (type == CLOCK_TYPE_PCMT16)
+ *divider_bits = 16;
+ else
+ *divider_bits = 8;
+
+ for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
+ if (clock_source[type][mux] == parent)
+ return mux;
+
+ /* if we get here, either us or the caller has made a mistake */
+ printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
+ parent);
+ return -1;
+}
+
+void clock_set_enable(enum periph_id periph_id, int enable)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 *clk;
+ u32 reg;
+
+ /* Enable/disable the clock to this peripheral */
+ assert(clock_periph_id_isvalid(periph_id));
+ if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
+ clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
+ else
+ clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+ reg = readl(clk);
+ if (enable)
+ reg |= PERIPH_MASK(periph_id);
+ else
+ reg &= ~PERIPH_MASK(periph_id);
+ writel(reg, clk);
+}
+
+void reset_set_enable(enum periph_id periph_id, int enable)
+{
+ struct clk_rst_ctlr *clkrst =
+ (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 *reset;
+ u32 reg;
+
+ /* Enable/disable reset to the peripheral */
+ assert(clock_periph_id_isvalid(periph_id));
+ if (periph_id < PERIPH_ID_VW_FIRST)
+ reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
+ else
+ reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+ reg = readl(reset);
+ if (enable)
+ reg |= PERIPH_MASK(periph_id);
+ else
+ reg &= ~PERIPH_MASK(periph_id);
+ writel(reg, reset);
+}
+
+#ifdef CONFIG_OF_CONTROL
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id Clock ID according to tegra30 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id)
+{
+ if (clk_id > PERIPH_ID_COUNT)
+ return PERIPH_ID_NONE;
+
+ switch (clk_id) {
+ case PERIPH_ID_RESERVED3:
+ case PERIPH_ID_RESERVED4:
+ case PERIPH_ID_RESERVED16:
+ case PERIPH_ID_RESERVED24:
+ case PERIPH_ID_RESERVED35:
+ case PERIPH_ID_RESERVED43:
+ case PERIPH_ID_RESERVED45:
+ case PERIPH_ID_RESERVED56:
+ case PERIPH_ID_RESERVED76:
+ case PERIPH_ID_RESERVED77:
+ case PERIPH_ID_RESERVED78:
+ case PERIPH_ID_RESERVED83:
+ case PERIPH_ID_RESERVED89:
+ case PERIPH_ID_RESERVED91:
+ case PERIPH_ID_RESERVED93:
+ case PERIPH_ID_RESERVED94:
+ case PERIPH_ID_RESERVED95:
+ return PERIPH_ID_NONE;
+ default:
+ return clk_id;
+ }
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void clock_early_init(void)
+{
+ /*
+ * PLLP output frequency set to 408Mhz
+ * PLLC output frequency set to 228Mhz
+ */
+ switch (clock_get_osc_freq()) {
+ case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
+ break;
+
+ case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+ break;
+
+ case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+ clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
+ clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+ break;
+ case CLOCK_OSC_FREQ_19_2:
+ default:
+ /*
+ * These are not supported. It is too early to print a
+ * message and the UART likely won't work anyway due to the
+ * oscillator being wrong.
+ */
+ break;
+ }
+}
diff --git a/arch/arm/cpu/tegra30-common/funcmux.c b/arch/arm/cpu/tegra30-common/funcmux.c
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 high-level function multiplexing */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+ int bad_config = config != FUNCMUX_DEFAULT;
+
+ switch (id) {
+ case PERIPH_ID_UART1:
+ switch (config) {
+ case FUNCMUX_UART1_ULPI:
+ pinmux_set_func(PINGRP_ULPI_DATA0, PMUX_FUNC_UARTA);
+ pinmux_set_func(PINGRP_ULPI_DATA1, PMUX_FUNC_UARTA);
+ pinmux_set_func(PINGRP_ULPI_DATA2, PMUX_FUNC_UARTA);
+ pinmux_set_func(PINGRP_ULPI_DATA3, PMUX_FUNC_UARTA);
+ pinmux_tristate_disable(PINGRP_ULPI_DATA0);
+ pinmux_tristate_disable(PINGRP_ULPI_DATA1);
+ pinmux_tristate_disable(PINGRP_ULPI_DATA2);
+ pinmux_tristate_disable(PINGRP_ULPI_DATA3);
+ break;
+ }
+ break;
+
+ /* Add other periph IDs here as needed */
+
+ default:
+ debug("%s: invalid periph_id %d", __func__, id);
+ return -1;
+ }
+
+ if (bad_config) {
+ debug("%s: invalid config %d for periph_id %d", __func__,
+ config, id);
+ return -1;
+ }
+ return 0;
+}
diff --git a/arch/arm/cpu/tegra30-common/pinmux.c b/arch/arm/cpu/tegra30-common/pinmux.c
--- /dev/null
@@ -0,0 +1,506 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 pin multiplexing functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/pinmux.h>
+
+struct tegra_pingroup_desc {
+ const char *name;
+ enum pmux_func funcs[4];
+ enum pmux_func func_safe;
+ enum pmux_vddio vddio;
+ enum pmux_pin_io io;
+};
+
+#define PMUX_MUXCTL_SHIFT 0
+#define PMUX_PULL_SHIFT 2
+#define PMUX_TRISTATE_SHIFT 4
+#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
+#define PMUX_IO_SHIFT 5
+#define PMUX_OD_SHIFT 6
+#define PMUX_LOCK_SHIFT 7
+#define PMUX_IO_RESET_SHIFT 8
+
+/* Convenient macro for defining pin group properties */
+#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
+ { \
+ .vddio = PMUX_VDDIO_ ## vdd, \
+ .funcs = { \
+ PMUX_FUNC_ ## f0, \
+ PMUX_FUNC_ ## f1, \
+ PMUX_FUNC_ ## f2, \
+ PMUX_FUNC_ ## f3, \
+ }, \
+ .func_safe = PMUX_FUNC_RSVD1, \
+ .io = PMUX_PIN_ ## iod, \
+ }
+
+/* Input and output pins */
+#define PINI(pg_name, vdd, f0, f1, f2, f3) \
+ PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
+#define PINO(pg_name, vdd, f0, f1, f2, f3) \
+ PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
+
+const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
+ /* NAME VDD f0 f1 f2 f3 */
+ PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
+ PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),
+ PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),
+ PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),
+ PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),
+ PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),
+ PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),
+ PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),
+ PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),
+ PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
+ PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
+ PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
+ PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
+ PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
+ PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
+ PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
+ PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),
+ PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
+ PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
+ PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
+ PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),
+ PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),
+ PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),
+ PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),
+ PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),
+ PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),
+ PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),
+ PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),
+ PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),
+ PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),
+ PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
+ PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
+ PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
+ PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
+ PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),
+ PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),
+ PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),
+ PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),
+ PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),
+ PINI(VI_MCLK, VI, VI, VI, VI, VI),
+ PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),
+ PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),
+ PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
+ PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
+ PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),
+ PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),
+ PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),
+ PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),
+ PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),
+ PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),
+ PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),
+ PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),
+ PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
+ PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
+ PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),
+ PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),
+ PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),
+ PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),
+ PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
+ PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
+ PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
+ PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),
+ PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),
+ PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
+ PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),
+ PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),
+ PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),
+ PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),
+ PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),
+ PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),
+ PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),
+ PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),
+ PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),
+ PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),
+ PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),
+ PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
+ PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),
+ PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),
+ PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),
+ PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),
+ PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
+ PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
+ PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
+ PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
+ PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),
+ PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),
+ PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),
+ PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),
+ PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),
+ PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),
+ PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
+ PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
+ PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),
+ PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),
+ PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),
+ PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),
+ PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),
+ PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),
+ PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
+ PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
+ PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
+ PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),
+ PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),
+ PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),
+ PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),
+ PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),
+ PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),
+ PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),
+ PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),
+ PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),
+ PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),
+ PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),
+ PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),
+ PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),
+ PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),
+ PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),
+ PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),
+ PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
+ PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
+ PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
+ PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),
+ PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
+ PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),
+ PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),
+ PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),
+ PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),
+ PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),
+ PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),
+ PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
+ PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),
+ PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),
+ PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),
+ PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),
+ PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),
+ PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),
+ PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),
+ PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),
+ PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),
+ PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),
+ PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
+ PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
+ PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
+ PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),
+ PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
+ PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
+ PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),
+ PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),
+ PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
+ PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
+ PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),
+ PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),
+ PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),
+ PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),
+ PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
+ PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
+ PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
+ PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
+};
+
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *tri = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin */
+ assert(pmux_pingrp_isvalid(pin));
+
+ reg = readl(tri);
+ if (enable)
+ reg |= PMUX_TRISTATE_MASK;
+ else
+ reg &= ~PMUX_TRISTATE_MASK;
+ writel(reg, tri);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, 1);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+ pinmux_set_tristate(pin, 0);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pull = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and pupd */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_pupd_isvalid(pupd));
+
+ reg = readl(pull);
+ reg &= ~(0x3 << PMUX_PULL_SHIFT);
+ reg |= (pupd << PMUX_PULL_SHIFT);
+ writel(reg, pull);
+}
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *muxctl = &pmt->pmt_ctl[pin];
+ int i, mux = -1;
+ u32 reg;
+
+ /* Error check on pin and func */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_func_isvalid(func));
+
+ /* Handle special values */
+ if (func == PMUX_FUNC_SAFE)
+ func = tegra_soc_pingroups[pin].func_safe;
+
+ if (func & PMUX_FUNC_RSVD1) {
+ mux = func & 0x3;
+ } else {
+ /* Search for the appropriate function */
+ for (i = 0; i < 4; i++) {
+ if (tegra_soc_pingroups[pin].funcs[i] == func) {
+ mux = i;
+ break;
+ }
+ }
+ }
+ assert(mux != -1);
+
+ reg = readl(muxctl);
+ reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
+ reg |= (mux << PMUX_MUXCTL_SHIFT);
+ writel(reg, muxctl);
+
+}
+
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_io = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and io */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_io_isvalid(io));
+
+ reg = readl(pin_io);
+ reg &= ~(0x1 << PMUX_IO_SHIFT);
+ reg |= (io & 0x1) << PMUX_IO_SHIFT;
+ writel(reg, pin_io);
+}
+
+static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_lock = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and lock */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_lock_isvalid(lock));
+
+ if (lock == PMUX_PIN_LOCK_DEFAULT)
+ return 0;
+
+ reg = readl(pin_lock);
+ reg &= ~(0x1 << PMUX_LOCK_SHIFT);
+ if (lock == PMUX_PIN_LOCK_ENABLE)
+ reg |= (0x1 << PMUX_LOCK_SHIFT);
+ else {
+ /* lock == DISABLE, which isn't possible */
+ printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
+ __func__, lock);
+ }
+ writel(reg, pin_lock);
+
+ return 0;
+}
+
+static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_od = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and od */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_od_isvalid(od));
+
+ if (od == PMUX_PIN_OD_DEFAULT)
+ return 0;
+
+ reg = readl(pin_od);
+ reg &= ~(0x1 << PMUX_OD_SHIFT);
+ if (od == PMUX_PIN_OD_ENABLE)
+ reg |= (0x1 << PMUX_OD_SHIFT);
+ writel(reg, pin_od);
+
+ return 0;
+}
+
+static int pinmux_set_ioreset(enum pmux_pingrp pin,
+ enum pmux_pin_ioreset ioreset)
+{
+ struct pmux_tri_ctlr *pmt =
+ (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+ u32 *pin_ioreset = &pmt->pmt_ctl[pin];
+ u32 reg;
+
+ /* Error check on pin and ioreset */
+ assert(pmux_pingrp_isvalid(pin));
+ assert(pmux_pin_ioreset_isvalid(ioreset));
+
+ if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+ return 0;
+
+ reg = readl(pin_ioreset);
+ reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
+ if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+ reg |= (0x1 << PMUX_IO_RESET_SHIFT);
+ writel(reg, pin_ioreset);
+
+ return 0;
+}
+
+void pinmux_config_pingroup(struct pingroup_config *config)
+{
+ enum pmux_pingrp pin = config->pingroup;
+
+ pinmux_set_func(pin, config->func);
+ pinmux_set_pullupdown(pin, config->pull);
+ pinmux_set_tristate(pin, config->tristate);
+ pinmux_set_io(pin, config->io);
+ pinmux_set_lock(pin, config->lock);
+ pinmux_set_od(pin, config->od);
+ pinmux_set_ioreset(pin, config->ioreset);
+}
+
+void pinmux_config_table(struct pingroup_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ pinmux_config_pingroup(&config[i]);
+}
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
--- /dev/null
@@ -0,0 +1,5 @@
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "nvidia,tegra114";
+};
index 636ec2c1fe7da999c29542bee5b0089f5e6081ba..9a8968522e47702f3736b1f38f65dbf021943161 100644 (file)
compatible = "nvidia,tegra20";
interrupt-parent = <&intc>;
- tegra_car: clock@60006000 {
- compatible = "nvidia,tegra20-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- };
+ host1x {
+ compatible = "nvidia,tegra20-host1x", "simple-bus";
+ reg = <0x50000000 0x00024000>;
+ interrupts = <0 65 0x04 /* mpcore syncpt */
+ 0 67 0x04>; /* mpcore general */
+ status = "disabled";
- clocks {
#address-cells = <1>;
- #size-cells = <0>;
+ #size-cells = <1>;
+
+ ranges = <0x54000000 0x54000000 0x04000000>;
+
+ /* video-encoding/decoding */
+ mpe {
+ reg = <0x54040000 0x00040000>;
+ interrupts = <0 68 0x04>;
+ status = "disabled";
+ };
+
+ /* video input */
+ vi {
+ reg = <0x54080000 0x00040000>;
+ interrupts = <0 69 0x04>;
+ status = "disabled";
+ };
+
+ /* EPP */
+ epp {
+ reg = <0x540c0000 0x00040000>;
+ interrupts = <0 70 0x04>;
+ status = "disabled";
+ };
+
+ /* ISP */
+ isp {
+ reg = <0x54100000 0x00040000>;
+ interrupts = <0 71 0x04>;
+ status = "disabled";
+ };
+
+ /* 2D engine */
+ gr2d {
+ reg = <0x54140000 0x00040000>;
+ interrupts = <0 72 0x04>;
+ status = "disabled";
+ };
+
+ /* 3D engine */
+ gr3d {
+ reg = <0x54180000 0x00040000>;
+ status = "disabled";
+ };
+
+ /* display controllers */
+ dc@54200000 {
+ compatible = "nvidia,tegra20-dc";
+ reg = <0x54200000 0x00040000>;
+ interrupts = <0 73 0x04>;
+ status = "disabled";
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ dc@54240000 {
+ compatible = "nvidia,tegra20-dc";
+ reg = <0x54240000 0x00040000>;
+ interrupts = <0 74 0x04>;
+ status = "disabled";
+
+ rgb {
+ status = "disabled";
+ };
+ };
+
+ /* outputs */
+ hdmi {
+ compatible = "nvidia,tegra20-hdmi";
+ reg = <0x54280000 0x00040000>;
+ interrupts = <0 75 0x04>;
+ status = "disabled";
+ };
- osc: clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
+ tvo {
+ compatible = "nvidia,tegra20-tvo";
+ reg = <0x542c0000 0x00040000>;
+ interrupts = <0 76 0x04>;
+ status = "disabled";
+ };
+
+ dsi {
+ compatible = "nvidia,tegra20-dsi";
+ reg = <0x54300000 0x00040000>;
+ status = "disabled";
};
};
< 0x50040100 0x0100 >;
};
- i2c@7000c000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nvidia,tegra20-i2c";
- reg = <0x7000C000 0x100>;
- interrupts = < 70 >;
- /* PERIPH_ID_I2C1, PLL_P_OUT3 */
- clocks = <&tegra_car 12>, <&tegra_car 124>;
+ tegra_car: clock@60006000 {
+ compatible = "nvidia,tegra20-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
};
- i2c@7000c400 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nvidia,tegra20-i2c";
- reg = <0x7000C400 0x100>;
- interrupts = < 116 >;
- /* PERIPH_ID_I2C2, PLL_P_OUT3 */
- clocks = <&tegra_car 54>, <&tegra_car 124>;
+ apbdma: dma {
+ compatible = "nvidia,tegra20-apbdma";
+ reg = <0x6000a000 0x1200>;
+ interrupts = <0 104 0x04
+ 0 105 0x04
+ 0 106 0x04
+ 0 107 0x04
+ 0 108 0x04
+ 0 109 0x04
+ 0 110 0x04
+ 0 111 0x04
+ 0 112 0x04
+ 0 113 0x04
+ 0 114 0x04
+ 0 115 0x04
+ 0 116 0x04
+ 0 117 0x04
+ 0 118 0x04
+ 0 119 0x04>;
};
- i2c@7000c500 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nvidia,tegra20-i2c";
- reg = <0x7000C500 0x100>;
- interrupts = < 124 >;
- /* PERIPH_ID_I2C3, PLL_P_OUT3 */
- clocks = <&tegra_car 67>, <&tegra_car 124>;
+ gpio: gpio@6000d000 {
+ compatible = "nvidia,tegra20-gpio";
+ reg = < 0x6000d000 0x1000 >;
+ interrupts = < 64 65 66 67 87 119 121 >;
+ #gpio-cells = <2>;
+ gpio-controller;
};
- i2c@7000d000 {
+ pinmux: pinmux@70000000 {
+ compatible = "nvidia,tegra20-pinmux";
+ reg = < 0x70000014 0x10 /* Tri-state registers */
+ 0x70000080 0x20 /* Mux registers */
+ 0x700000a0 0x14 /* Pull-up/down registers */
+ 0x70000868 0xa8 >; /* Pad control registers */
+ };
+
+ das@70000c00 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "nvidia,tegra20-i2c-dvc";
- reg = <0x7000D000 0x200>;
- interrupts = < 85 >;
- /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
- clocks = <&tegra_car 47>, <&tegra_car 124>;
+ compatible = "nvidia,tegra20-das";
+ reg = <0x70000c00 0x80>;
};
i2s@70002800 {
dma-channel = < 1 >;
};
- das@70000c00 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nvidia,tegra20-das";
- reg = <0x70000c00 0x80>;
- };
-
- gpio: gpio@6000d000 {
- compatible = "nvidia,tegra20-gpio";
- reg = < 0x6000d000 0x1000 >;
- interrupts = < 64 65 66 67 87 119 121 >;
- #gpio-cells = <2>;
- gpio-controller;
- };
-
- pinmux: pinmux@70000000 {
- compatible = "nvidia,tegra20-pinmux";
- reg = < 0x70000014 0x10 /* Tri-state registers */
- 0x70000080 0x20 /* Mux registers */
- 0x700000a0 0x14 /* Pull-up/down registers */
- 0x70000868 0xa8 >; /* Pad control registers */
- };
-
serial@70006000 {
compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
interrupts = < 123 >;
};
- sdhci@c8000000 {
- compatible = "nvidia,tegra20-sdhci";
- reg = <0xc8000000 0x200>;
- interrupts = < 46 >;
+ nand: nand-controller@70008000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-nand";
+ reg = <0x70008000 0x100>;
};
- sdhci@c8000200 {
- compatible = "nvidia,tegra20-sdhci";
- reg = <0xc8000200 0x200>;
- interrupts = < 47 >;
+ pwm: pwm@7000a000 {
+ compatible = "nvidia,tegra20-pwm";
+ reg = <0x7000a000 0x100>;
+ #pwm-cells = <2>;
};
- sdhci@c8000400 {
- compatible = "nvidia,tegra20-sdhci";
- reg = <0xc8000400 0x200>;
- interrupts = < 51 >;
+ i2c@7000c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2c";
+ reg = <0x7000C000 0x100>;
+ interrupts = < 70 >;
+ /* PERIPH_ID_I2C1, PLL_P_OUT3 */
+ clocks = <&tegra_car 12>, <&tegra_car 124>;
};
- sdhci@c8000600 {
- compatible = "nvidia,tegra20-sdhci";
- reg = <0xc8000600 0x200>;
- interrupts = < 63 >;
+ spi@7000c380 {
+ compatible = "nvidia,tegra20-sflash";
+ reg = <0x7000c380 0x80>;
+ interrupts = <0 39 0x04>;
+ nvidia,dma-request-selector = <&apbdma 11>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ /* PERIPH_ID_SPI1, PLLP_OUT0 */
+ clocks = <&tegra_car 43>;
+ };
+
+ i2c@7000c400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2c";
+ reg = <0x7000C400 0x100>;
+ interrupts = < 116 >;
+ /* PERIPH_ID_I2C2, PLL_P_OUT3 */
+ clocks = <&tegra_car 54>, <&tegra_car 124>;
+ };
+
+ i2c@7000c500 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2c";
+ reg = <0x7000C500 0x100>;
+ interrupts = < 124 >;
+ /* PERIPH_ID_I2C3, PLL_P_OUT3 */
+ clocks = <&tegra_car 67>, <&tegra_car 124>;
+ };
+
+ i2c@7000d000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra20-i2c-dvc";
+ reg = <0x7000D000 0x200>;
+ interrupts = < 85 >;
+ /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
+ clocks = <&tegra_car 47>, <&tegra_car 124>;
+ };
+
+ kbc@7000e200 {
+ compatible = "nvidia,tegra20-kbc";
+ reg = <0x7000e200 0x0078>;
+ };
+
+ emc@7000f400 {
+ #address-cells = < 1 >;
+ #size-cells = < 0 >;
+ compatible = "nvidia,tegra20-emc";
+ reg = <0x7000f400 0x200>;
};
usb@c5000000 {
clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
};
- emc@7000f400 {
- #address-cells = < 1 >;
- #size-cells = < 0 >;
- compatible = "nvidia,tegra20-emc";
- reg = <0x7000f400 0x200>;
- };
-
- kbc@7000e200 {
- compatible = "nvidia,tegra20-kbc";
- reg = <0x7000e200 0x0078>;
+ sdhci@c8000000 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000000 0x200>;
+ interrupts = < 46 >;
};
- nand: nand-controller@70008000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nvidia,tegra20-nand";
- reg = <0x70008000 0x100>;
+ sdhci@c8000200 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000200 0x200>;
+ interrupts = < 47 >;
};
- pwm: pwm@7000a000 {
- compatible = "nvidia,tegra20-pwm";
- reg = <0x7000a000 0x100>;
- #pwm-cells = <2>;
+ sdhci@c8000400 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000400 0x200>;
+ interrupts = < 51 >;
};
- host1x {
- compatible = "nvidia,tegra20-host1x", "simple-bus";
- reg = <0x50000000 0x00024000>;
- interrupts = <0 65 0x04 /* mpcore syncpt */
- 0 67 0x04>; /* mpcore general */
- status = "disabled";
-
- #address-cells = <1>;
- #size-cells = <1>;
-
- ranges = <0x54000000 0x54000000 0x04000000>;
-
- /* video-encoding/decoding */
- mpe {
- reg = <0x54040000 0x00040000>;
- interrupts = <0 68 0x04>;
- status = "disabled";
- };
-
- /* video input */
- vi {
- reg = <0x54080000 0x00040000>;
- interrupts = <0 69 0x04>;
- status = "disabled";
- };
-
- /* EPP */
- epp {
- reg = <0x540c0000 0x00040000>;
- interrupts = <0 70 0x04>;
- status = "disabled";
- };
-
- /* ISP */
- isp {
- reg = <0x54100000 0x00040000>;
- interrupts = <0 71 0x04>;
- status = "disabled";
- };
-
- /* 2D engine */
- gr2d {
- reg = <0x54140000 0x00040000>;
- interrupts = <0 72 0x04>;
- status = "disabled";
- };
-
- /* 3D engine */
- gr3d {
- reg = <0x54180000 0x00040000>;
- status = "disabled";
- };
-
- /* display controllers */
- dc@54200000 {
- compatible = "nvidia,tegra20-dc";
- reg = <0x54200000 0x00040000>;
- interrupts = <0 73 0x04>;
- status = "disabled";
-
- rgb {
- status = "disabled";
- };
- };
-
- dc@54240000 {
- compatible = "nvidia,tegra20-dc";
- reg = <0x54240000 0x00040000>;
- interrupts = <0 74 0x04>;
- status = "disabled";
-
- rgb {
- status = "disabled";
- };
- };
-
- /* outputs */
- hdmi {
- compatible = "nvidia,tegra20-hdmi";
- reg = <0x54280000 0x00040000>;
- interrupts = <0 75 0x04>;
- status = "disabled";
- };
-
- tvo {
- compatible = "nvidia,tegra20-tvo";
- reg = <0x542c0000 0x00040000>;
- interrupts = <0 76 0x04>;
- status = "disabled";
- };
-
- dsi {
- compatible = "nvidia,tegra20-dsi";
- reg = <0x54300000 0x00040000>;
- status = "disabled";
- };
+ sdhci@c8000600 {
+ compatible = "nvidia,tegra20-sdhci";
+ reg = <0xc8000600 0x200>;
+ interrupts = < 63 >;
};
-
};
diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
--- /dev/null
@@ -0,0 +1,165 @@
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "nvidia,tegra30";
+
+ tegra_car: clock@60006000 {
+ compatible = "nvidia,tegra30-car", "nvidia,tegra20-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apbdma: dma {
+ compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
+ reg = <0x6000a000 0x1400>;
+ interrupts = <0 104 0x04
+ 0 105 0x04
+ 0 106 0x04
+ 0 107 0x04
+ 0 108 0x04
+ 0 109 0x04
+ 0 110 0x04
+ 0 111 0x04
+ 0 112 0x04
+ 0 113 0x04
+ 0 114 0x04
+ 0 115 0x04
+ 0 116 0x04
+ 0 117 0x04
+ 0 118 0x04
+ 0 119 0x04
+ 0 128 0x04
+ 0 129 0x04
+ 0 130 0x04
+ 0 131 0x04
+ 0 132 0x04
+ 0 133 0x04
+ 0 134 0x04
+ 0 135 0x04
+ 0 136 0x04
+ 0 137 0x04
+ 0 138 0x04
+ 0 139 0x04
+ 0 140 0x04
+ 0 141 0x04
+ 0 142 0x04
+ 0 143 0x04>;
+ };
+
+ i2c@7000c000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000C000 0x100>;
+ /* PERIPH_ID_I2C1, CLK_M */
+ clocks = <&tegra_car 12>;
+ };
+
+ i2c@7000c400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000C400 0x100>;
+ /* PERIPH_ID_I2C2, CLK_M */
+ clocks = <&tegra_car 54>;
+ };
+
+ i2c@7000c500 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000C500 0x100>;
+ /* PERIPH_ID_I2C3, CLK_M */
+ clocks = <&tegra_car 67>;
+ };
+
+ i2c@7000c700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000C700 0x100>;
+ /* PERIPH_ID_I2C4, CLK_M */
+ clocks = <&tegra_car 103>;
+ };
+
+ i2c@7000d000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+ reg = <0x7000D000 0x100>;
+ /* PERIPH_ID_I2C_DVC, CLK_M */
+ clocks = <&tegra_car 47>;
+ };
+
+ spi@7000d400 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d400 0x200>;
+ interrupts = <0 59 0x04>;
+ nvidia,dma-request-selector = <&apbdma 15>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ /* PERIPH_ID_SBC1, PLLP_OUT0 */
+ clocks = <&tegra_car 41>;
+ };
+
+ spi@7000d600 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d600 0x200>;
+ interrupts = <0 82 0x04>;
+ nvidia,dma-request-selector = <&apbdma 16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ /* PERIPH_ID_SBC2, PLLP_OUT0 */
+ clocks = <&tegra_car 44>;
+ };
+
+ spi@7000d800 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000d480 0x200>;
+ interrupts = <0 83 0x04>;
+ nvidia,dma-request-selector = <&apbdma 17>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ /* PERIPH_ID_SBC3, PLLP_OUT0 */
+ clocks = <&tegra_car 46>;
+ };
+
+ spi@7000da00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000da00 0x200>;
+ interrupts = <0 93 0x04>;
+ nvidia,dma-request-selector = <&apbdma 18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ /* PERIPH_ID_SBC4, PLLP_OUT0 */
+ clocks = <&tegra_car 68>;
+ };
+
+ spi@7000dc00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000dc00 0x200>;
+ interrupts = <0 94 0x04>;
+ nvidia,dma-request-selector = <&apbdma 27>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ /* PERIPH_ID_SBC5, PLLP_OUT0 */
+ clocks = <&tegra_car 104>;
+ };
+
+ spi@7000de00 {
+ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
+ reg = <0x7000de00 0x200>;
+ interrupts = <0 79 0x04>;
+ nvidia,dma-request-selector = <&apbdma 28>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ /* PERIPH_ID_SBC6, PLLP_OUT0 */
+ clocks = <&tegra_car 105>;
+ };
+};
index fbf4de3b30042d0e5d2f608681888555e41add06..638ee1aa75cbcb81ab2b26572cae6dd48f236108 100644 (file)
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_USDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
#else
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
#endif
#endif
index b021903d9b443bca0d74202d8997ed94b1509adf..ab37d641ece97c82f230ad9e6a89511fea8fddff 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
-#define timestamp (gd->tbl)
-#define lastinc (gd->lastinc)
+#define timestamp (gd->arch.tbl)
+#define lastinc (gd->arch.lastinc)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 8e69fb67b14bf53b85b263a551862c3cf434507a..ae43ef8778580aba42f8784d6eaa55e35be2073a 100644 (file)
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
+/* Micron MT41J256M8HX-15E */
+#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
+#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
+#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
+#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
+#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
+#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
+#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
+#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
+#define MT41J256M8HX15E_RATIO 0x40
+#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
+#define MT41J256M8HX15E_RD_DQS 0x3B
+#define MT41J256M8HX15E_WR_DQS 0x85
+#define MT41J256M8HX15E_PHY_WR_DATA 0xC1
+#define MT41J256M8HX15E_PHY_FIFO_WE 0x100
+#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
+
+/* Micron MT41J512M8RH-125 on EVM v1.5 */
+#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
+#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
+#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
+#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
+#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
+#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
+#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
+#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
+#define MT41J512M8RH125_RATIO 0x80
+#define MT41J512M8RH125_INVERT_CLKOUT 0x0
+#define MT41J512M8RH125_RD_DQS 0x3B
+#define MT41J512M8RH125_WR_DQS 0x3C
+#define MT41J512M8RH125_PHY_FIFO_WE 0xA5
+#define MT41J512M8RH125_PHY_WR_DATA 0x74
+#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
+
/**
* Configure SDRAM
*/
index aed6b00cc683c9dff7cdcd4790402b8d2698fe54..460ac1c02dc6db3ee5ae5dab8b4b13623d329acc 100644 (file)
/* PAD Control Fields */
#define SLEWCTRL (0x1 << 6)
#define RXACTIVE (0x1 << 5)
-#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
+#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */
+#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
#define MODE(val) val /* used for Readability */
index 644ff353febdfea316bc6d0978995367743faa82..e961ce0578a8e7839bc7c1ba9c3899c00e4241c2 100644 (file)
#define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */
#define BOOT_DEVICE_SPI 11
#define BOOT_DEVICE_UART 65
+#define BOOT_DEVICE_USBETH 68
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
#endif
index 1e8522b83980a4eb32e94133e19777d3c52f796d..d4852a38c19c3eb25b960626f03eaad9d55fc39f 100644 (file)
static inline unsigned long get_cpu_clk_rate(void)
{
DECLARE_GLOBAL_DATA_PTR;
- return gd->cpu_clk_rate_hz;
+ return gd->arch.cpu_clk_rate_hz;
}
static inline unsigned long get_main_clk_rate(void)
{
DECLARE_GLOBAL_DATA_PTR;
- return gd->main_clk_rate_hz;
+ return gd->arch.main_clk_rate_hz;
}
static inline unsigned long get_mck_clk_rate(void)
{
DECLARE_GLOBAL_DATA_PTR;
- return gd->mck_rate_hz;
+ return gd->arch.mck_rate_hz;
}
static inline unsigned long get_plla_clk_rate(void)
{
DECLARE_GLOBAL_DATA_PTR;
- return gd->plla_rate_hz;
+ return gd->arch.plla_rate_hz;
}
static inline unsigned long get_pllb_clk_rate(void)
{
DECLARE_GLOBAL_DATA_PTR;
- return gd->pllb_rate_hz;
+ return gd->arch.pllb_rate_hz;
}
static inline u32 get_pllb_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
- return gd->at91_pllb_usb_init;
+ return gd->arch.at91_pllb_usb_init;
}
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
index ef65ffbb9f739286d1da482f7ce4bb7202013c5a..fbbb1f33c3c9427b9710ad6aa1142e70261476d7 100644 (file)
#define gpio_status() gpio_info()
#define GPIO_NAME_SIZE 20
+#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
+#define MAX_NUM_GPIOS 128
+#else
#define MAX_NUM_GPIOS 144
+#endif
#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
#define GPIO_BIT(gp) ((gp) & 0x1F)
index 70d94c50417390c6ad8705c0c3d480edb89c27ec..73dfd394d8284a66f0f378f2795bb1656c24ea98 100644 (file)
#include <asm/types.h>
/* Stabilization delays, in usec */
-#define PLL_STABILIZATION_DELAY (300)
+#define PLL_STABILIZATION_DELAY (300)
#define IO_STABILIZATION_DELAY (1000)
-#define NVBL_PLLP_KHZ (216000)
-
#define PLLX_ENABLED (1 << 30)
#define CCLK_BURST_POLICY 0x20008888
#define SUPER_CCLK_DIVIDER 0x80000000
/* Calculate clock fractional divider value from ref and target frequencies */
-#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
+#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
/* Calculate clock frequency value from reference and clock divider value */
-#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
+#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
/* AVP/CPU ID */
#define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
-#define PG_UP_TAG_0 0x0
+#define PG_UP_TAG_0 0x0
#define CORESIGHT_UNLOCK 0xC5ACCE55;
-/* AP20-Specific Base Addresses */
-
-/* AP20 Base physical address of SDRAM. */
-#define AP20_BASE_PA_SDRAM 0x00000000
-/* AP20 Base physical address of internal SRAM. */
-#define AP20_BASE_PA_SRAM 0x40000000
-/* AP20 Size of internal SRAM (256KB). */
-#define AP20_BASE_PA_SRAM_SIZE 0x00040000
-/* AP20 Base physical address of flash. */
-#define AP20_BASE_PA_NOR_FLASH 0xD0000000
-/* AP20 Base physical address of boot information table. */
-#define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM
-
-/*
- * Super-temporary stacks for EXTREMELY early startup. The values chosen for
- * these addresses must be valid on ALL SOCs because this value is used before
- * we are able to differentiate between the SOC types.
- *
- * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
- * stack is placed below the AVP stack. Once the CPU stack has been moved,
- * the AVP is free to use the IRAM the CPU stack previously occupied if
- * it should need to do so.
- *
- * NOTE: In multi-processor CPU complex configurations, each processor will have
- * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
- * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
- * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
- * CPU.
- */
-
-/* Common AVP early boot stack limit */
-#define AVP_EARLY_BOOT_STACK_LIMIT \
- (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
-/* Common AVP early boot stack size */
-#define AVP_EARLY_BOOT_STACK_SIZE 0x1000
-/* Common CPU early boot stack limit */
-#define CPU_EARLY_BOOT_STACK_LIMIT \
- (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
-/* Common CPU early boot stack size */
-#define CPU_EARLY_BOOT_STACK_SIZE 0x1000
+/* AP base physical address of internal SRAM */
+#define NV_PA_BASE_SRAM 0x40000000
#define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
#define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
index be6bf25f0bfc8e78162fcf8d6eb7060e986544cf..3db0d93b89a31dd60ac0464f0fea6d7fd7fe67c6 100644 (file)
* an empty stub function will be called.
*/
-void pin_mux_usb(void); /* overrideable USB pinmux setup */
-void pin_mux_spi(void); /* overrideable SPI pinmux setup */
-void pin_mux_nand(void); /* overrideable NAND pinmux setup */
+void pin_mux_usb(void); /* overrideable USB pinmux setup */
+void pin_mux_spi(void); /* overrideable SPI pinmux setup */
+void pin_mux_nand(void); /* overrideable NAND pinmux setup */
+void pin_mux_display(void); /* overrideable DISPLAY pinmux setup */
#endif
index 7b548c2298d351872d37d3c24158993bb6463c23..c754ec753b0196ac49da8ce48fa5f14cae0fed96 100644 (file)
* MA 02111-1307 USA
*/
-#ifndef _CLK_RST_H_
-#define _CLK_RST_H_
+#ifndef _TEGRA_CLK_RST_H_
+#define _TEGRA_CLK_RST_H_
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
uint pll_misc; /* other misc things */
};
+/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
+struct clk_set_clr {
+ uint set;
+ uint clr;
+};
+
/*
* Most PLLs use the clk_pll structure, but some have a simpler two-member
* structure for which we use clk_pll_simple. The reason for this non-
enum {
TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
- TEGRA_CLK_REGS = 3, /* Number of clock enable registers */
- TEGRA_CLK_SOURCES = 64, /* Number of peripheral clock sources */
+ TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */
+ TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */
+ TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
+ TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W*/
};
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
uint crc_reserved11; /* _reserved_11, 0xFC */
uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
- uint crc_reserved20[80]; /* 0x200-33C */
- uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */
- uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
+
+ uint crc_reserved20[64]; /* _reserved_20, 0x200-2fc */
+
+ /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
+ struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
+
+ uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */
+
+ /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
+ struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
+
+ uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */
+
+ uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
+ uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
+
+ /* Additional (T30) registers */
+ uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
+ uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
+
+ uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */
+
+ uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
+ uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
+ uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
+ uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */
+ uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
+ uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
+ uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
+ uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
+ uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
+ uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTR1L_0, 0x384 */
+ uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
+ uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */
+ uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */
+ /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
+ struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
+ /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
+ struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
+ /* Additional (T114) registers */
+ uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
+ uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
+ uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
+ uint crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */
+ uint crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */
+ uint crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */
+ uint crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
+ uint crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
+ uint crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */
+ uint crc_reserved40[1]; /* _reserved_40, 0x474 */
+ uint crc_intstatus; /* __INTSTATUS_0, 0x478 */
+ uint crc_intmask; /* __INTMASK_0, 0x47C */
+ uint crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */
+ uint crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */
+ uint crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */
+
+ uint crc_plle_aux; /* _PLLE_AUX_0, 0x48C */
+ uint crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */
+ uint crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */
+ uint crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */
+
+ uint crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */
+ uint crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
+ uint crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
+ uint crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
+ uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
+ uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
+ uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
};
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
+#define CPU3_CLK_STP_SHIFT 11
+#define CPU2_CLK_STP_SHIFT 10
#define CPU1_CLK_STP_SHIFT 9
-
#define CPU0_CLK_STP_SHIFT 8
#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
+#define PLL_DCCON_SHIFT 20
+#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT)
+
+#define PLL_LOCK_ENABLE_SHIFT 18
+#define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT)
+
#define PLL_CPCON_SHIFT 8
#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
#define PLLU_VCO_FREQ_SHIFT 20
#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
+#define PLLP_OUT1_OVR (1 << 2)
+#define PLLP_OUT2_OVR (1 << 18)
+#define PLLP_OUT3_OVR (1 << 2)
+#define PLLP_OUT4_OVR (1 << 18)
+#define PLLP_OUT1_RATIO 8
+#define PLLP_OUT2_RATIO 24
+#define PLLP_OUT3_RATIO 8
+#define PLLP_OUT4_RATIO 24
+
+enum {
+ IN_408_OUT_204_DIVISOR = 2,
+ IN_408_OUT_102_DIVISOR = 6,
+ IN_408_OUT_48_DIVISOR = 15,
+ IN_408_OUT_9_6_DIVISOR = 83,
+};
+
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_FREQ_SHIFT 30
-#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
#define OSC_XOBP_SHIFT 1
#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
#define OUT_CLK_SOURCE4_SHIFT 28
#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT)
-#endif /* CLK_RST_H */
+/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
+#define SCLK_SYS_STATE_SHIFT 28U
+#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT)
+enum {
+ SCLK_SYS_STATE_STDBY,
+ SCLK_SYS_STATE_IDLE,
+ SCLK_SYS_STATE_RUN,
+ SCLK_SYS_STATE_IRQ = 4U,
+ SCLK_SYS_STATE_FIQ = 8U,
+};
+#define SCLK_COP_FIQ_MASK (1 << 27)
+#define SCLK_CPU_FIQ_MASK (1 << 26)
+#define SCLK_COP_IRQ_MASK (1 << 25)
+#define SCLK_CPU_IRQ_MASK (1 << 24)
+
+#define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12
+#define SCLK_SWAKEUP_FIQ_SOURCE_MASK \
+ (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8
+#define SCLK_SWAKEUP_IRQ_SOURCE_MASK \
+ (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4
+#define SCLK_SWAKEUP_RUN_SOURCE_MASK \
+ (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0
+
+#define SCLK_SWAKEUP_IDLE_SOURCE_MASK \
+ (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
+enum {
+ SCLK_SOURCE_CLKM,
+ SCLK_SOURCE_PLLC_OUT1,
+ SCLK_SOURCE_PLLP_OUT4,
+ SCLK_SOURCE_PLLP_OUT3,
+ SCLK_SOURCE_PLLP_OUT2,
+ SCLK_SOURCE_CLKD,
+ SCLK_SOURCE_CLKS,
+ SCLK_SOURCE_PLLM_OUT1,
+};
+#define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12)
+#define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8)
+#define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4)
+#define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0)
+
+/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
+#define SUPER_SCLK_ENB_SHIFT 31U
+#define SUPER_SCLK_ENB_MASK (1U << 31)
+#define SUPER_SCLK_DIVIDEND_SHIFT 8
+#define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT)
+#define SUPER_SCLK_DIVISOR_SHIFT 0
+#define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT)
+
+/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */
+#define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
+#define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
+#define CLK_SYS_RATE_AHB_RATE_SHIFT 4
+#define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
+#define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
+#define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
+#define CLK_SYS_RATE_APB_RATE_SHIFT 0
+#define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
+
+/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */
+#define CLR_CPURESET0 (1 << 0)
+#define CLR_CPURESET1 (1 << 1)
+#define CLR_CPURESET2 (1 << 2)
+#define CLR_CPURESET3 (1 << 3)
+#define CLR_DBGRESET0 (1 << 12)
+#define CLR_DBGRESET1 (1 << 13)
+#define CLR_DBGRESET2 (1 << 14)
+#define CLR_DBGRESET3 (1 << 15)
+#define CLR_CORERESET0 (1 << 16)
+#define CLR_CORERESET1 (1 << 17)
+#define CLR_CORERESET2 (1 << 18)
+#define CLR_CORERESET3 (1 << 19)
+#define CLR_CXRESET0 (1 << 20)
+#define CLR_CXRESET1 (1 << 21)
+#define CLR_CXRESET2 (1 << 22)
+#define CLR_CXRESET3 (1 << 23)
+#define CLR_NONCPURESET (1 << 29)
+
+#endif /* _TEGRA_CLK_RST_H_ */
index eac1dc2662000219430cc43779690c48dfa13588..c8677bdd76f833e3fdd512a62b0dca9561c9c59c 100644 (file)
/* Tegra clock control functions */
-#ifndef _CLOCK_H
-#define _CLOCK_H
+#ifndef _TEGRA_CLOCK_H_
+#define _TEGRA_CLOCK_H_
/* Set of oscillator frequencies supported in the internal API. */
enum clock_osc_freq {
* @returns 0 if ok, -1 on error (invalid clock id)
*/
int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
- u32 *divp, u32 *cpcon, u32 *lfcon);
+ u32 *divp, u32 *cpcon, u32 *lfcon);
/*
* Enable a clock
/**
* Put parts of the CPU complex into or out of reset.\
*
- * @param cpu cpu number (0 or 1 on Tegra2)
+ * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
* @param which which parts of the complex to affect (OR of crc_reset_id)
* @param reset 1 to assert reset, 0 to de-assert
*/
/* Initialize the PLLs */
void clock_early_init(void);
-#endif /* _CLOCK_H_ */
+/* Returns a pointer to the clock source register for a peripheral */
+u32 *get_periph_source_reg(enum periph_id periph_id);
+
+/**
+ * Given a peripheral ID and the required source clock, this returns which
+ * value should be programmed into the source mux for that peripheral.
+ *
+ * There is special code here to handle the one source type with 5 sources.
+ *
+ * @param periph_id peripheral to start
+ * @param source PLL id of required parent clock
+ * @param mux_bits Set to number of bits in mux register: 2 or 4
+ * @param divider_bits Set to number of divider bits (8 or 16)
+ * @return mux value (0-4, or -1 if not found)
+ */
+int get_periph_clock_source(enum periph_id periph_id,
+ enum clock_id parent, int *mux_bits, int *divider_bits);
+
+/*
+ * Convert a device tree clock ID to our peripheral ID. They are mostly
+ * the same but we are very cautious so we check that a valid clock ID is
+ * provided.
+ *
+ * @param clk_id Clock ID according to tegra30 device tree binding
+ * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
+ */
+enum periph_id clk_id_to_periph_id(int clk_id);
+
+/**
+ * Set the output frequency you want for each PLL clock.
+ * PLL output frequencies are programmed by setting their N, M and P values.
+ * The governing equations are:
+ * VCO = (Fi / m) * n, Fo = VCO / (2^p)
+ * where Fo is the output frequency from the PLL.
+ * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
+ * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
+ * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
+ *
+ * @param n PLL feedback divider(DIVN)
+ * @param m PLL input divider(DIVN)
+ * @param p post divider(DIVP)
+ * @param cpcon base PLL charge pump(CPCON)
+ * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
+ * be overriden), 1 if PLL is already correct
+ */
+int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
+
+/* return 1 if a peripheral ID is in range */
+#define clock_type_id_isvalid(id) ((id) >= 0 && \
+ (id) < CLOCK_TYPE_COUNT)
+
+/* return 1 if a periphc_internal_id is in range */
+#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
+ (id) < PERIPHC_COUNT)
+
+#endif /* _TEGRA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/funcmux.h b/arch/arm/include/asm/arch-tegra/funcmux.h
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra high-level function multiplexing */
+
+#ifndef _TEGRA_FUNCMUX_H_
+#define _TEGRA_FUNCMUX_H_
+
+/**
+ * Select a config for a particular peripheral.
+ *
+ * Each peripheral can operate through a number of configurations,
+ * which are sets of pins that it uses to bring out its signals.
+ * The basic config is 0, and higher numbers indicate different
+ * pinmux settings to bring the peripheral out on other pins,
+ *
+ * This function also disables tristate for the function's pins,
+ * so that they operate in normal mode.
+ *
+ * @param id Peripheral id
+ * @param config Configuration to use (FUNCMUX_...), 0 for default
+ * @return 0 if ok, -1 on error (e.g. incorrect id or config)
+ */
+int funcmux_select(enum periph_id id, int config);
+
+#endif /* _TEGRA_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_GP_PADCTRL_H_
+#define _TEGRA_GP_PADCTRL_H_
+
+#define GP_HIDREV 0x804
+
+/* bit fields definitions for APB_MISC_GP_HIDREV register */
+#define HIDREV_CHIPID_SHIFT 8
+#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
+#define HIDREV_MAJORPREV_SHIFT 4
+#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
+
+/* CHIPID field returned from APB_MISC_GP_HIDREV register */
+#define CHIPID_TEGRA20 0x20
+#define CHIPID_TEGRA30 0x30
+#define CHIPID_TEGRA114 0x35
+
+#endif /* _TEGRA_GP_PADCTRL_H_ */
index b1d47cd2e3ef24949ce9f475bd2618a992056e99..1bcdcf8eec7257efa7ab7839f9ecaa8bf7f29bb8 100644 (file)
#define START_CP (1 << 8)
#define CPUPWRREQ_OE (1 << 16)
+#define CPUPWRREQ_POL (1 << 15)
+
+#define CRAILID (0)
+#define CE0ID (14)
+#define C0NCID (15)
+#define CRAIL (1 << CRAILID)
+#define CE0 (1 << CE0ID)
+#define C0NC (1 << C0NCID)
#endif /* PMC_H */
index 6d2e62f5594a4ae4ab72eddad8f4bdcf3196b0a7..bf7229d8ace9fbc09461342d916dd04498a018b8 100644 (file)
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400)
+#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600)
+#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800)
+#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00)
+#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
+#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
SKU_ID_T25 = 0x18,
SKU_ID_AP25E = 0x1b,
SKU_ID_T25E = 0x1c,
+ SKU_ID_T30 = 0x81, /* Cardhu value */
+ SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
};
-/* These are the SOC categories that affect clocking */
+/*
+ * These are used to distinguish SOC types for setting up clocks. Mostly
+ * we can tell the clocking required by looking at the SOC sku_id, but
+ * for T30 it is a user option as to whether to run PLLP in fast or slow
+ * mode, so we have two options there.
+ */
enum {
TEGRA_SOC_T20,
TEGRA_SOC_T25,
+ TEGRA_SOC_T30,
+ TEGRA_SOC_T114,
- TEGRA_SOC_COUNT,
+ TEGRA_SOC_CNT,
TEGRA_SOC_UNKNOWN = -1,
};
diff --git a/arch/arm/include/asm/arch-tegra/tegra_slink.h b/arch/arm/include/asm/arch-tegra/tegra_slink.h
--- /dev/null
@@ -0,0 +1,84 @@
+/*
+ * NVIDIA Tegra SPI-SLINK controller
+ *
+ * Copyright 2010-2013 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_SLINK_H_
+#define _TEGRA_SLINK_H_
+
+#include <asm/types.h>
+
+struct slink_tegra {
+ u32 command; /* SLINK_COMMAND_0 register */
+ u32 command2; /* SLINK_COMMAND2_0 reg */
+ u32 status; /* SLINK_STATUS_0 register */
+ u32 reserved; /* Reserved offset 0C */
+ u32 mas_data; /* SLINK_MAS_DATA_0 reg */
+ u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */
+ u32 dma_ctl; /* SLINK_DMA_CTL_0 register */
+ u32 status2; /* SLINK_STATUS2_0 reg */
+ u32 rsvd[56]; /* 0x20 to 0xFF reserved */
+ u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */
+ u32 rsvd2[31]; /* 0x104 to 0x17F reserved */
+ u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */
+};
+
+/* COMMAND */
+#define SLINK_CMD_ENB (1 << 31)
+#define SLINK_CMD_GO (1 << 30)
+#define SLINK_CMD_M_S (1 << 28)
+#define SLINK_CMD_CK_SDA (1 << 21)
+#define SLINK_CMD_CS_POL (1 << 13)
+#define SLINK_CMD_CS_VAL (1 << 12)
+#define SLINK_CMD_CS_SOFT (1 << 11)
+#define SLINK_CMD_BIT_LENGTH (1 << 4)
+#define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F
+/* COMMAND2 */
+#define SLINK_CMD2_TXEN (1 << 30)
+#define SLINK_CMD2_RXEN (1 << 31)
+#define SLINK_CMD2_SS_EN (1 << 18)
+#define SLINK_CMD2_SS_EN_SHIFT 18
+#define SLINK_CMD2_SS_EN_MASK 0x000C0000
+#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17)
+/* STATUS */
+#define SLINK_STAT_BSY (1 << 31)
+#define SLINK_STAT_RDY (1 << 30)
+#define SLINK_STAT_ERR (1 << 29)
+#define SLINK_STAT_RXF_FLUSH (1 << 27)
+#define SLINK_STAT_TXF_FLUSH (1 << 26)
+#define SLINK_STAT_RXF_OVF (1 << 25)
+#define SLINK_STAT_TXF_UNR (1 << 24)
+#define SLINK_STAT_RXF_EMPTY (1 << 23)
+#define SLINK_STAT_RXF_FULL (1 << 22)
+#define SLINK_STAT_TXF_EMPTY (1 << 21)
+#define SLINK_STAT_TXF_FULL (1 << 20)
+#define SLINK_STAT_TXF_OVF (1 << 19)
+#define SLINK_STAT_RXF_UNR (1 << 18)
+#define SLINK_STAT_CUR_BLKCNT (1 << 15)
+/* STATUS2 */
+#define SLINK_STAT2_RXF_FULL_CNT (1 << 16)
+#define SLINK_STAT2_TXF_FULL_CNT (1 << 0)
+
+#define SPI_TIMEOUT 1000
+#define TEGRA_SPI_MAX_FREQ 52000000
+
+#endif /* _TEGRA_SLINK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h
--- /dev/null
@@ -0,0 +1,402 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 clock PLL tables */
+
+#ifndef _TEGRA114_CLOCK_TABLES_H_
+#define _TEGRA114_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+ CLOCK_ID_FIRST,
+ CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+ CLOCK_ID_MEMORY,
+ CLOCK_ID_PERIPH,
+ CLOCK_ID_AUDIO,
+ CLOCK_ID_USB,
+ CLOCK_ID_DISPLAY,
+
+ /* now the simple ones */
+ CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_EPCI,
+ CLOCK_ID_SFROM32KHZ,
+
+ /* These are the base clocks (inputs to the Tegra SOC) */
+ CLOCK_ID_32KHZ,
+ CLOCK_ID_OSC,
+
+ CLOCK_ID_COUNT, /* number of PLLs */
+ CLOCK_ID_DISPLAY2, /* placeholder */
+ CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+ PERIPH_ID_FIRST,
+
+ /* Low word: 31:0 (DEVICES_L) */
+ PERIPH_ID_CPU = PERIPH_ID_FIRST,
+ PERIPH_ID_COP,
+ PERIPH_ID_TRIGSYS,
+ PERIPH_ID_RESERVED3,
+ PERIPH_ID_RTC,
+ PERIPH_ID_TMR,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+
+ /* 8 */
+ PERIPH_ID_GPIO,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_NDFLASH,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC4,
+
+ /* 16 */
+ PERIPH_ID_RESERVED16,
+ PERIPH_ID_PWM,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_EPP,
+ PERIPH_ID_VI,
+ PERIPH_ID_2D,
+ PERIPH_ID_USBD,
+ PERIPH_ID_ISP,
+
+ /* 24 */
+ PERIPH_ID_3D,
+ PERIPH_ID_RESERVED24,
+ PERIPH_ID_DISP2,
+ PERIPH_ID_DISP1,
+ PERIPH_ID_HOST1X,
+ PERIPH_ID_VCP,
+ PERIPH_ID_I2S0,
+ PERIPH_ID_CACHE2,
+
+ /* Middle word: 63:32 (DEVICES_H) */
+ PERIPH_ID_MEM,
+ PERIPH_ID_AHBDMA,
+ PERIPH_ID_APBDMA,
+ PERIPH_ID_RESERVED35,
+ PERIPH_ID_KBC,
+ PERIPH_ID_STAT_MON,
+ PERIPH_ID_PMC,
+ PERIPH_ID_FUSE,
+
+ /* 40 */
+ PERIPH_ID_KFUSE,
+ PERIPH_ID_SBC1,
+ PERIPH_ID_SNOR,
+ PERIPH_ID_RESERVED43,
+ PERIPH_ID_SBC2,
+ PERIPH_ID_RESERVED45,
+ PERIPH_ID_SBC3,
+ PERIPH_ID_I2C5,
+
+ /* 48 */
+ PERIPH_ID_DSI,
+ PERIPH_ID_TVO,
+ PERIPH_ID_MIPI,
+ PERIPH_ID_HDMI,
+ PERIPH_ID_CSI,
+ PERIPH_ID_TVDAC,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_UART3,
+
+ /* 56 */
+ PERIPH_ID_RESERVED56,
+ PERIPH_ID_EMC,
+ PERIPH_ID_USB2,
+ PERIPH_ID_USB3,
+ PERIPH_ID_MPE,
+ PERIPH_ID_VDE,
+ PERIPH_ID_BSEA,
+ PERIPH_ID_BSEV,
+
+ /* Upper word 95:64 (DEVICES_U) */
+ PERIPH_ID_SPEEDO,
+ PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_SBC4,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_PCIE,
+ PERIPH_ID_OWR,
+
+ /* 72 */
+ PERIPH_ID_AFI,
+ PERIPH_ID_CORESIGHT,
+ PERIPH_ID_PCIEXCLK,
+ PERIPH_ID_AVPUCQ,
+ PERIPH_ID_RESERVED76,
+ PERIPH_ID_RESERVED77,
+ PERIPH_ID_RESERVED78,
+ PERIPH_ID_DTV,
+
+ /* 80 */
+ PERIPH_ID_NANDSPEED,
+ PERIPH_ID_I2CSLOW,
+ PERIPH_ID_DSIB,
+ PERIPH_ID_RESERVED83,
+ PERIPH_ID_IRAMA,
+ PERIPH_ID_IRAMB,
+ PERIPH_ID_IRAMC,
+ PERIPH_ID_IRAMD,
+
+ /* 88 */
+ PERIPH_ID_CRAM2,
+ PERIPH_ID_RESERVED89,
+ PERIPH_ID_MDOUBLER,
+ PERIPH_ID_RESERVED91,
+ PERIPH_ID_SUSOUT,
+ PERIPH_ID_RESERVED93,
+ PERIPH_ID_RESERVED94,
+ PERIPH_ID_RESERVED95,
+
+ PERIPH_ID_VW_FIRST,
+ /* V word: 31:0 */
+ PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+ PERIPH_ID_CPULP,
+ PERIPH_ID_3D2,
+ PERIPH_ID_MSELECT,
+ PERIPH_ID_TSENSOR,
+ PERIPH_ID_I2S3,
+ PERIPH_ID_I2S4,
+ PERIPH_ID_I2C4,
+
+ /* 104 */
+ PERIPH_ID_SBC5,
+ PERIPH_ID_SBC6,
+ PERIPH_ID_AUDIO,
+ PERIPH_ID_APBIF,
+ PERIPH_ID_DAM0,
+ PERIPH_ID_DAM1,
+ PERIPH_ID_DAM2,
+ PERIPH_ID_HDA2CODEC2X,
+
+ /* 112 */
+ PERIPH_ID_ATOMICS,
+ PERIPH_ID_EX_RESERVED17,
+ PERIPH_ID_EX_RESERVED18,
+ PERIPH_ID_EX_RESERVED19,
+ PERIPH_ID_EX_RESERVED20,
+ PERIPH_ID_EX_RESERVED21,
+ PERIPH_ID_EX_RESERVED22,
+ PERIPH_ID_ACTMON,
+
+ /* 120 */
+ PERIPH_ID_EX_RESERVED24,
+ PERIPH_ID_EX_RESERVED25,
+ PERIPH_ID_EX_RESERVED26,
+ PERIPH_ID_EX_RESERVED27,
+ PERIPH_ID_SATA,
+ PERIPH_ID_HDA,
+ PERIPH_ID_EX_RESERVED30,
+ PERIPH_ID_EX_RESERVED31,
+
+ /* W word: 31:0 */
+ PERIPH_ID_HDA2HDMICODEC,
+ PERIPH_ID_RESERVED1_SATACOLD,
+ PERIPH_ID_RESERVED2_PCIERX0,
+ PERIPH_ID_RESERVED3_PCIERX1,
+ PERIPH_ID_RESERVED4_PCIERX2,
+ PERIPH_ID_RESERVED5_PCIERX3,
+ PERIPH_ID_RESERVED6_PCIERX4,
+ PERIPH_ID_RESERVED7_PCIERX5,
+
+ /* 136 */
+ PERIPH_ID_CEC,
+ PERIPH_ID_PCIE2_IOBIST,
+ PERIPH_ID_EMC_IOBIST,
+ PERIPH_ID_HDMI_IOBIST,
+ PERIPH_ID_SATA_IOBIST,
+ PERIPH_ID_MIPI_IOBIST,
+ PERIPH_ID_EMC1_IOBIST,
+ PERIPH_ID_XUSB,
+
+ /* 144 */
+ PERIPH_ID_CILAB,
+ PERIPH_ID_CILCD,
+ PERIPH_ID_CILE,
+ PERIPH_ID_DSIA_LP,
+ PERIPH_ID_DSIB_LP,
+ PERIPH_ID_RESERVED21_ENTROPY,
+ PERIPH_ID_RESERVED22_W,
+ PERIPH_ID_RESERVED23_W,
+
+ /* 152 */
+ PERIPH_ID_RESERVED24_W,
+ PERIPH_ID_AMX0,
+ PERIPH_ID_ADX0,
+ PERIPH_ID_DVFS,
+ PERIPH_ID_XUSB_SS,
+ PERIPH_ID_EMC_DLL,
+ PERIPH_ID_MC1,
+ PERIPH_ID_EMC1,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+ PLL_OUT1,
+ PLL_OUT2,
+ PLL_OUT3,
+ PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+ /* 0x00 */
+ PERIPHC_I2S1,
+ PERIPHC_I2S2,
+ PERIPHC_SPDIF_OUT,
+ PERIPHC_SPDIF_IN,
+ PERIPHC_PWM,
+ PERIPHC_05h,
+ PERIPHC_SBC2,
+ PERIPHC_SBC3,
+
+ /* 0x08 */
+ PERIPHC_08h,
+ PERIPHC_I2C1,
+ PERIPHC_I2C5,
+ PERIPHC_0bh,
+ PERIPHC_0ch,
+ PERIPHC_SBC1,
+ PERIPHC_DISP1,
+ PERIPHC_DISP2,
+
+ /* 0x10 */
+ PERIPHC_CVE,
+ PERIPHC_11h,
+ PERIPHC_VI,
+ PERIPHC_13h,
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC2,
+ PERIPHC_G3D,
+ PERIPHC_G2D,
+
+ /* 0x18 */
+ PERIPHC_NDFLASH,
+ PERIPHC_SDMMC4,
+ PERIPHC_VFIR,
+ PERIPHC_EPP,
+ PERIPHC_MPE,
+ PERIPHC_MIPI,
+ PERIPHC_UART1,
+ PERIPHC_UART2,
+
+ /* 0x20 */
+ PERIPHC_HOST1X,
+ PERIPHC_21h,
+ PERIPHC_TVO,
+ PERIPHC_HDMI,
+ PERIPHC_24h,
+ PERIPHC_TVDAC,
+ PERIPHC_I2C2,
+ PERIPHC_EMC,
+
+ /* 0x28 */
+ PERIPHC_UART3,
+ PERIPHC_29h,
+ PERIPHC_VI_SENSOR,
+ PERIPHC_2bh,
+ PERIPHC_2ch,
+ PERIPHC_SBC4,
+ PERIPHC_I2C3,
+ PERIPHC_SDMMC3,
+
+ /* 0x30 */
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_VDE,
+ PERIPHC_OWR,
+ PERIPHC_NOR,
+ PERIPHC_CSITE,
+ PERIPHC_I2S0,
+ PERIPHC_37h,
+
+ PERIPHC_VW_FIRST,
+ /* 0x38 */
+ PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+ PERIPHC_MSELECT,
+ PERIPHC_TSENSOR,
+ PERIPHC_I2S3,
+ PERIPHC_I2S4,
+ PERIPHC_I2C4,
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+
+ /* 0x40 */
+ PERIPHC_AUDIO,
+ PERIPHC_41h,
+ PERIPHC_DAM0,
+ PERIPHC_DAM1,
+ PERIPHC_DAM2,
+ PERIPHC_HDA2CODEC2X,
+ PERIPHC_ACTMON,
+ PERIPHC_EXTPERIPH1,
+
+ /* 0x48 */
+ PERIPHC_EXTPERIPH2,
+ PERIPHC_EXTPERIPH3,
+ PERIPHC_NANDSPEED,
+ PERIPHC_I2CSLOW,
+ PERIPHC_SYS,
+ PERIPHC_SPEEDO,
+ PERIPHC_4eh,
+ PERIPHC_4fh,
+
+ /* 0x50 */
+ PERIPHC_50h,
+ PERIPHC_51h,
+ PERIPHC_52h,
+ PERIPHC_53h,
+ PERIPHC_SATAOOB,
+ PERIPHC_SATA,
+ PERIPHC_HDA,
+
+ PERIPHC_COUNT,
+
+ PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+ (id < PERIPH_ID_VW_FIRST) ? \
+ ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+ (id) < PERIPH_ID_COUNT)
+
+#endif /* _TEGRA114_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 clock control functions */
+
+#ifndef _TEGRA114_CLOCK_H_
+#define _TEGRA114_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT 28
+#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+
+#endif /* _TEGRA114_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/flow.h b/arch/arm/include/asm/arch-tegra114/flow.h
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_FLOW_H_
+#define _TEGRA114_FLOW_H_
+
+struct flow_ctlr {
+ u32 halt_cpu_events;
+ u32 halt_cop_events;
+ u32 cpu_csr;
+ u32 cop_csr;
+ u32 xrq_events;
+ u32 halt_cpu1_events;
+ u32 cpu1_csr;
+ u32 halt_cpu2_events;
+ u32 cpu2_csr;
+ u32 halt_cpu3_events;
+ u32 cpu3_csr;
+ u32 cluster_control;
+};
+
+#endif /* _TEGRA114_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/funcmux.h b/arch/arm/include/asm/arch-tegra114/funcmux.h
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra114 high-level function multiplexing */
+
+#ifndef _TEGRA114_FUNCMUX_H_
+#define _TEGRA114_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+ FUNCMUX_DEFAULT = 0, /* default config */
+
+ /* UART configs */
+ FUNCMUX_UART4_GMI = 0,
+};
+#endif /* _TEGRA114_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h
--- /dev/null
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_GP_PADCTRL_H_
+#define _TEGRA114_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+ u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
+ u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
+ u32 reserved0[22]; /* 0x08 - 0x5C: */
+ u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
+ u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+ u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+ u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+ u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+ u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+ u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+ u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+ u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+ u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+ u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+ u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
+ u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+ u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+ u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+ u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+ u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+ u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
+ u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
+ u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
+ u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+ u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+ u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+ u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+ u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+ u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+ u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
+ u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
+ u32 reserved1[7]; /* 0xD0-0xE8: */
+ u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+};
+
+#endif /* _TEGRA114_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/gpio.h b/arch/arm/include/asm/arch-tegra114/gpio.h
--- /dev/null
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_GPIO_H_
+#define _TEGRA114_GPIO_H_
+
+/*
+ * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+#include <asm/arch-tegra30/gpio.h>
+
+#endif /* _TEGRA114_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/hardware.h b/arch/arm/include/asm/arch-tegra114/hardware.h
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_HARDWARE_H_
+#define _TEGRA114_HARDWARE_H_
+
+/* include tegra specific hardware definitions */
+
+#endif /* _TEGRA114_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
--- /dev/null
@@ -0,0 +1,618 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_PINMUX_H_
+#define _TEGRA114_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ * - function
+ * - pullup / pulldown
+ * - tristate or normal
+ */
+enum pmux_pingrp {
+ PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
+ PINGRP_ULPI_DATA1,
+ PINGRP_ULPI_DATA2,
+ PINGRP_ULPI_DATA3,
+ PINGRP_ULPI_DATA4,
+ PINGRP_ULPI_DATA5,
+ PINGRP_ULPI_DATA6,
+ PINGRP_ULPI_DATA7,
+ PINGRP_ULPI_CLK,
+ PINGRP_ULPI_DIR,
+ PINGRP_ULPI_NXT,
+ PINGRP_ULPI_STP,
+ PINGRP_DAP3_FS,
+ PINGRP_DAP3_DIN,
+ PINGRP_DAP3_DOUT,
+ PINGRP_DAP3_SCLK,
+ PINGRP_GPIO_PV0,
+ PINGRP_GPIO_PV1,
+ PINGRP_SDMMC1_CLK,
+ PINGRP_SDMMC1_CMD,
+ PINGRP_SDMMC1_DAT3,
+ PINGRP_SDMMC1_DAT2,
+ PINGRP_SDMMC1_DAT1,
+ PINGRP_SDMMC1_DAT0,
+ PINGRP_GPIO_PV2,
+ PINGRP_GPIO_PV3,
+ PINGRP_CLK2_OUT,
+ PINGRP_CLK2_REQ,
+ PINGRP_LCD_PWR1,
+ PINGRP_LCD_PWR2,
+ PINGRP_LCD_SDIN,
+ PINGRP_LCD_SDOUT,
+ PINGRP_LCD_WR_N,
+ PINGRP_LCD_CS0_N,
+ PINGRP_LCD_DC0,
+ PINGRP_LCD_SCK,
+ PINGRP_LCD_PWR0,
+ PINGRP_LCD_PCLK,
+ PINGRP_LCD_DE,
+ PINGRP_LCD_HSYNC,
+ PINGRP_LCD_VSYNC,
+ PINGRP_LCD_D0,
+ PINGRP_LCD_D1,
+ PINGRP_LCD_D2,
+ PINGRP_LCD_D3,
+ PINGRP_LCD_D4,
+ PINGRP_LCD_D5,
+ PINGRP_LCD_D6,
+ PINGRP_LCD_D7,
+ PINGRP_LCD_D8,
+ PINGRP_LCD_D9,
+ PINGRP_LCD_D10,
+ PINGRP_LCD_D11,
+ PINGRP_LCD_D12,
+ PINGRP_LCD_D13,
+ PINGRP_LCD_D14,
+ PINGRP_LCD_D15,
+ PINGRP_LCD_D16,
+ PINGRP_LCD_D17,
+ PINGRP_LCD_D18,
+ PINGRP_LCD_D19,
+ PINGRP_LCD_D20,
+ PINGRP_LCD_D21,
+ PINGRP_LCD_D22,
+ PINGRP_LCD_D23,
+ PINGRP_LCD_CS1_N,
+ PINGRP_LCD_M1,
+ PINGRP_LCD_DC1,
+ PINGRP_HDMI_INT,
+ PINGRP_DDC_SCL,
+ PINGRP_DDC_SDA,
+ PINGRP_CRT_HSYNC,
+ PINGRP_CRT_VSYNC,
+ PINGRP_VI_D0,
+ PINGRP_VI_D1,
+ PINGRP_VI_D2,
+ PINGRP_VI_D3,
+ PINGRP_VI_D4,
+ PINGRP_VI_D5,
+ PINGRP_VI_D6,
+ PINGRP_VI_D7,
+ PINGRP_VI_D8,
+ PINGRP_VI_D9,
+ PINGRP_VI_D10,
+ PINGRP_VI_D11,
+ PINGRP_VI_PCLK,
+ PINGRP_VI_MCLK,
+ PINGRP_VI_VSYNC,
+ PINGRP_VI_HSYNC,
+ PINGRP_UART2_RXD,
+ PINGRP_UART2_TXD,
+ PINGRP_UART2_RTS_N,
+ PINGRP_UART2_CTS_N,
+ PINGRP_UART3_TXD,
+ PINGRP_UART3_RXD,
+ PINGRP_UART3_CTS_N,
+ PINGRP_UART3_RTS_N,
+ PINGRP_GPIO_PU0,
+ PINGRP_GPIO_PU1,
+ PINGRP_GPIO_PU2,
+ PINGRP_GPIO_PU3,
+ PINGRP_GPIO_PU4,
+ PINGRP_GPIO_PU5,
+ PINGRP_GPIO_PU6,
+ PINGRP_GEN1_I2C_SDA,
+ PINGRP_GEN1_I2C_SCL,
+ PINGRP_DAP4_FS,
+ PINGRP_DAP4_DIN,
+ PINGRP_DAP4_DOUT,
+ PINGRP_DAP4_SCLK,
+ PINGRP_CLK3_OUT,
+ PINGRP_CLK3_REQ,
+ PINGRP_GMI_WP_N,
+ PINGRP_GMI_IORDY,
+ PINGRP_GMI_WAIT,
+ PINGRP_GMI_ADV_N,
+ PINGRP_GMI_CLK,
+ PINGRP_GMI_CS0_N,
+ PINGRP_GMI_CS1_N,
+ PINGRP_GMI_CS2_N,
+ PINGRP_GMI_CS3_N,
+ PINGRP_GMI_CS4_N,
+ PINGRP_GMI_CS6_N,
+ PINGRP_GMI_CS7_N,
+ PINGRP_GMI_AD0,
+ PINGRP_GMI_AD1,
+ PINGRP_GMI_AD2,
+ PINGRP_GMI_AD3,
+ PINGRP_GMI_AD4,
+ PINGRP_GMI_AD5,
+ PINGRP_GMI_AD6,
+ PINGRP_GMI_AD7,
+ PINGRP_GMI_AD8,
+ PINGRP_GMI_AD9,
+ PINGRP_GMI_AD10,
+ PINGRP_GMI_AD11,
+ PINGRP_GMI_AD12,
+ PINGRP_GMI_AD13,
+ PINGRP_GMI_AD14,
+ PINGRP_GMI_AD15,
+ PINGRP_GMI_A16,
+ PINGRP_GMI_A17,
+ PINGRP_GMI_A18,
+ PINGRP_GMI_A19,
+ PINGRP_GMI_WR_N,
+ PINGRP_GMI_OE_N,
+ PINGRP_GMI_DQS,
+ PINGRP_GMI_RST_N,
+ PINGRP_GEN2_I2C_SCL,
+ PINGRP_GEN2_I2C_SDA,
+ PINGRP_SDMMC4_CLK,
+ PINGRP_SDMMC4_CMD,
+ PINGRP_SDMMC4_DAT0,
+ PINGRP_SDMMC4_DAT1,
+ PINGRP_SDMMC4_DAT2,
+ PINGRP_SDMMC4_DAT3,
+ PINGRP_SDMMC4_DAT4,
+ PINGRP_SDMMC4_DAT5,
+ PINGRP_SDMMC4_DAT6,
+ PINGRP_SDMMC4_DAT7,
+ PINGRP_SDMMC4_RST_N,
+ PINGRP_CAM_MCLK,
+ PINGRP_GPIO_PCC1,
+ PINGRP_GPIO_PBB0,
+ PINGRP_CAM_I2C_SCL,
+ PINGRP_CAM_I2C_SDA,
+ PINGRP_GPIO_PBB3,
+ PINGRP_GPIO_PBB4,
+ PINGRP_GPIO_PBB5,
+ PINGRP_GPIO_PBB6,
+ PINGRP_GPIO_PBB7,
+ PINGRP_GPIO_PCC2,
+ PINGRP_JTAG_RTCK,
+ PINGRP_PWR_I2C_SCL,
+ PINGRP_PWR_I2C_SDA,
+ PINGRP_KB_ROW0,
+ PINGRP_KB_ROW1,
+ PINGRP_KB_ROW2,
+ PINGRP_KB_ROW3,
+ PINGRP_KB_ROW4,
+ PINGRP_KB_ROW5,
+ PINGRP_KB_ROW6,
+ PINGRP_KB_ROW7,
+ PINGRP_KB_ROW8,
+ PINGRP_KB_ROW9,
+ PINGRP_KB_ROW10,
+ PINGRP_KB_ROW11,
+ PINGRP_KB_ROW12,
+ PINGRP_KB_ROW13,
+ PINGRP_KB_ROW14,
+ PINGRP_KB_ROW15,
+ PINGRP_KB_COL0,
+ PINGRP_KB_COL1,
+ PINGRP_KB_COL2,
+ PINGRP_KB_COL3,
+ PINGRP_KB_COL4,
+ PINGRP_KB_COL5,
+ PINGRP_KB_COL6,
+ PINGRP_KB_COL7,
+ PINGRP_CLK_32K_OUT,
+ PINGRP_SYS_CLK_REQ,
+ PINGRP_CORE_PWR_REQ,
+ PINGRP_CPU_PWR_REQ,
+ PINGRP_PWR_INT_N,
+ PINGRP_CLK_32K_IN,
+ PINGRP_OWR,
+ PINGRP_DAP1_FS,
+ PINGRP_DAP1_DIN,
+ PINGRP_DAP1_DOUT,
+ PINGRP_DAP1_SCLK,
+ PINGRP_CLK1_REQ,
+ PINGRP_CLK1_OUT,
+ PINGRP_SPDIF_IN,
+ PINGRP_SPDIF_OUT,
+ PINGRP_DAP2_FS,
+ PINGRP_DAP2_DIN,
+ PINGRP_DAP2_DOUT,
+ PINGRP_DAP2_SCLK,
+ PINGRP_SPI2_MOSI,
+ PINGRP_SPI2_MISO,
+ PINGRP_SPI2_CS0_N,
+ PINGRP_SPI2_SCK,
+ PINGRP_SPI1_MOSI,
+ PINGRP_SPI1_SCK,
+ PINGRP_SPI1_CS0_N,
+ PINGRP_SPI1_MISO,
+ PINGRP_SPI2_CS1_N,
+ PINGRP_SPI2_CS2_N,
+ PINGRP_SDMMC3_CLK,
+ PINGRP_SDMMC3_CMD,
+ PINGRP_SDMMC3_DAT0,
+ PINGRP_SDMMC3_DAT1,
+ PINGRP_SDMMC3_DAT2,
+ PINGRP_SDMMC3_DAT3,
+ PINGRP_SDMMC3_DAT4,
+ PINGRP_SDMMC3_DAT5,
+ PINGRP_SDMMC3_DAT6,
+ PINGRP_SDMMC3_DAT7,
+ PINGRP_PEX_L0_PRSNT_N,
+ PINGRP_PEX_L0_RST_N,
+ PINGRP_PEX_L0_CLKREQ_N,
+ PINGRP_PEX_WAKE_N,
+ PINGRP_PEX_L1_PRSNT_N,
+ PINGRP_PEX_L1_RST_N,
+ PINGRP_PEX_L1_CLKREQ_N,
+ PINGRP_PEX_L2_PRSNT_N,
+ PINGRP_PEX_L2_RST_N,
+ PINGRP_PEX_L2_CLKREQ_N,
+ PINGRP_HDMI_CEC, /* offset 0x33e0 */
+ PINGRP_SDMMC1_WP_N,
+ PINGRP_SDMMC3_CD_N,
+ PINGRP_SPI1_CS1_N,
+ PINGRP_SPI1_CS2_N,
+ PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
+ PINGRP_USB_VBUS_EN1,
+ PINGRP_SDMMC3_CLK_LB_IN,
+ PINGRP_SDMMC3_CLK_LB_OUT,
+ PINGRP_NAND_GMI_CLK_LB,
+ PINGRP_RESET_OUT_N,
+ PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+ PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+ PDRIVE_PINGROUP_AO2,
+ PDRIVE_PINGROUP_AT1,
+ PDRIVE_PINGROUP_AT2,
+ PDRIVE_PINGROUP_AT3,
+ PDRIVE_PINGROUP_AT4,
+ PDRIVE_PINGROUP_AT5,
+ PDRIVE_PINGROUP_CDEV1,
+ PDRIVE_PINGROUP_CDEV2,
+ PDRIVE_PINGROUP_CSUS,
+ PDRIVE_PINGROUP_DAP1,
+ PDRIVE_PINGROUP_DAP2,
+ PDRIVE_PINGROUP_DAP3,
+ PDRIVE_PINGROUP_DAP4,
+ PDRIVE_PINGROUP_DBG,
+ PDRIVE_PINGROUP_LCD1,
+ PDRIVE_PINGROUP_LCD2,
+ PDRIVE_PINGROUP_SDIO2,
+ PDRIVE_PINGROUP_SDIO3,
+ PDRIVE_PINGROUP_SPI,
+ PDRIVE_PINGROUP_UAA,
+ PDRIVE_PINGROUP_UAB,
+ PDRIVE_PINGROUP_UART2,
+ PDRIVE_PINGROUP_UART3,
+ PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
+ PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
+ PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
+ PDRIVE_PINGROUP_DDC,
+ PDRIVE_PINGROUP_GMA,
+ PDRIVE_PINGROUP_GMB,
+ PDRIVE_PINGROUP_GMC,
+ PDRIVE_PINGROUP_GMD,
+ PDRIVE_PINGROUP_GME,
+ PDRIVE_PINGROUP_GMF,
+ PDRIVE_PINGROUP_GMG,
+ PDRIVE_PINGROUP_GMH,
+ PDRIVE_PINGROUP_OWR,
+ PDRIVE_PINGROUP_UAD,
+ PDRIVE_PINGROUP_GPV,
+ PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
+ PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
+ PDRIVE_PINGROUP_AT6,
+ PDRIVE_PINGROUP_DAP5,
+ PDRIVE_PINGROUP_VBUS,
+ PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+ PMUX_FUNC_AHB_CLK,
+ PMUX_FUNC_APB_CLK,
+ PMUX_FUNC_AUDIO_SYNC,
+ PMUX_FUNC_CRT,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
+ PMUX_FUNC_DAP3,
+ PMUX_FUNC_DAP4,
+ PMUX_FUNC_DAP5,
+ PMUX_FUNC_DISPA,
+ PMUX_FUNC_DISPB,
+ PMUX_FUNC_EMC_TEST0_DLL,
+ PMUX_FUNC_EMC_TEST1_DLL,
+ PMUX_FUNC_GMI,
+ PMUX_FUNC_GMI_INT,
+ PMUX_FUNC_HDMI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
+ PMUX_FUNC_IDE,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_MIO,
+ PMUX_FUNC_MIPI_HS,
+ PMUX_FUNC_NAND,
+ PMUX_FUNC_OSC,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PCIE,
+ PMUX_FUNC_PLLA_OUT,
+ PMUX_FUNC_PLLC_OUT1,
+ PMUX_FUNC_PLLM_OUT1,
+ PMUX_FUNC_PLLP_OUT2,
+ PMUX_FUNC_PLLP_OUT3,
+ PMUX_FUNC_PLLP_OUT4,
+ PMUX_FUNC_PWM,
+ PMUX_FUNC_PWR_INTR,
+ PMUX_FUNC_PWR_ON,
+ PMUX_FUNC_RTCK,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SFLASH,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI2_ALT,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_TWC,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_UARTE,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_SENSOR_CLK,
+ PMUX_FUNC_XIO,
+ PMUX_FUNC_BLINK,
+ PMUX_FUNC_CEC,
+ PMUX_FUNC_CLK12,
+ PMUX_FUNC_DAP,
+ PMUX_FUNC_DAPSDMMC2,
+ PMUX_FUNC_DDR,
+ PMUX_FUNC_DEV3,
+ PMUX_FUNC_DTV,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT2,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_EMC_DLL,
+ PMUX_FUNC_EXTPERIPH1,
+ PMUX_FUNC_EXTPERIPH2,
+ PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI_ALT,
+ PMUX_FUNC_HDA,
+ PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C4,
+ PMUX_FUNC_I2C5,
+ PMUX_FUNC_I2CPWR,
+ PMUX_FUNC_I2S0,
+ PMUX_FUNC_I2S1,
+ PMUX_FUNC_I2S2,
+ PMUX_FUNC_I2S3,
+ PMUX_FUNC_I2S4,
+ PMUX_FUNC_NAND_ALT,
+ PMUX_FUNC_POPSDIO4,
+ PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_PWM0,
+ PMUX_FUNC_PWM1,
+ PMUX_FUNC_PWM2,
+ PMUX_FUNC_PWM3,
+ PMUX_FUNC_SATA,
+ PMUX_FUNC_SPI5,
+ PMUX_FUNC_SPI6,
+ PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_VGP1,
+ PMUX_FUNC_VGP2,
+ PMUX_FUNC_VGP3,
+ PMUX_FUNC_VGP4,
+ PMUX_FUNC_VGP5,
+ PMUX_FUNC_VGP6,
+
+ PMUX_FUNC_USB,
+ PMUX_FUNC_SOC,
+ PMUX_FUNC_CPU,
+ PMUX_FUNC_CLK,
+ PMUX_FUNC_PWRON,
+ PMUX_FUNC_PMI,
+ PMUX_FUNC_CLDVFS,
+ PMUX_FUNC_RESET_OUT_N,
+
+ PMUX_FUNC_SAFE,
+ PMUX_FUNC_MAX,
+
+ PMUX_FUNC_RSVD1 = 0x8000,
+ PMUX_FUNC_RSVD2 = 0x8001,
+ PMUX_FUNC_RSVD3 = 0x8002,
+ PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
+ || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+ PMUX_PULL_NORMAL = 0,
+ PMUX_PULL_DOWN,
+ PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+ ((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+ PMUX_TRI_NORMAL = 0,
+ PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
+ && ((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+ PMUX_PIN_OUTPUT = 0,
+ PMUX_PIN_INPUT = 1,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+ ((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+ PMUX_PIN_LOCK_DEFAULT = 0,
+ PMUX_PIN_LOCK_DISABLE,
+ PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+ ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+ PMUX_PIN_OD_DEFAULT = 0,
+ PMUX_PIN_OD_DISABLE,
+ PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+ ((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+ PMUX_PIN_IO_RESET_DEFAULT = 0,
+ PMUX_PIN_IO_RESET_DISABLE,
+ PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+ (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+ ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+ PMUX_VDDIO_BB = 0,
+ PMUX_VDDIO_LCD,
+ PMUX_VDDIO_VI,
+ PMUX_VDDIO_UART,
+ PMUX_VDDIO_DDR,
+ PMUX_VDDIO_NAND,
+ PMUX_VDDIO_SYS,
+ PMUX_VDDIO_AUDIO,
+ PMUX_VDDIO_SD,
+ PMUX_VDDIO_CAM,
+ PMUX_VDDIO_GMI,
+ PMUX_VDDIO_PEXCTL,
+ PMUX_VDDIO_SDMMC1,
+ PMUX_VDDIO_SDMMC3,
+ PMUX_VDDIO_SDMMC4,
+
+ PMUX_VDDIO_NONE
+};
+
+/* T114 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
+#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+ PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+ uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
+ uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
+ uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
+ uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
+ uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
+ uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
+ uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
+
+ uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
+
+ uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
+ uint pmt_reserved5[PMUX_OFFSET];
+ uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+ enum pmux_pingrp pingroup; /* pin group PINGRP_... */
+ enum pmux_func func; /* function to assign FUNC_... */
+ enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
+ enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
+ enum pmux_pin_io io; /* input or output PMUX_PIN_... */
+ enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
+ enum pmux_pin_od od; /* open-drain or push-pull driver */
+ enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+#endif /* _TEGRA114_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/pmu.h b/arch/arm/include/asm/arch-tegra114/pmu.h
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_PMU_H_
+#define _TEGRA114_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _TEGRA114_PMU_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/spl.h b/arch/arm/include/asm/arch-tegra114/spl.h
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM 1
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_H_
+#define _TEGRA114_H_
+
+#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET 1752 /* offset to ODMDATA word */
+
+#undef NVBOOTINFOTABLE_BCTSIZE
+#undef NVBOOTINFOTABLE_BCTPTR
+#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
+#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
+
+#define MAX_NUM_CPU 4
+
+#endif /* TEGRA114_H */
diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h
index 53708e04772b45df860b137bab89d7473a5b735c..6ec5ccb9363925beec3b5beaf0a45ff3f046ab41 100644 (file)
#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
(id) < CLOCK_ID_FIRST_SIMPLE)
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+ (id) < PERIPH_ID_COUNT)
+
#endif /* _CLOCK_TABLES_H_ */
index f592b9550e02c257862613834e16b78e8fd548e4..491c02c026d05cb6f0f6b554d61403bd11513669 100644 (file)
#include <asm/arch-tegra/clock.h>
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT 30
+#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
+
#endif /* _TEGRA20_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h
index c986b93b40a03ebacdb54f968d313f020038a3a9..7f15bceafaa74840a92736c9a63b18e4f0bf1488 100644 (file)
/* Tegra20 high-level function multiplexing */
-#ifndef __FUNCMUX_H
-#define __FUNCMUX_H
+#ifndef _TEGRA20_FUNCMUX_H_
+#define _TEGRA20_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
/* Configs supported by the func mux */
enum {
FUNCMUX_UART1_UAA_UAB,
FUNCMUX_UART1_GPU,
FUNCMUX_UART1_SDIO1,
- FUNCMUX_UART2_IRDA = 0,
+ FUNCMUX_UART2_UAD = 0,
FUNCMUX_UART4_GMC = 0,
/* I2C configs */
FUNCMUX_NDFLASH_ATC = 0,
FUNCMUX_NDFLASH_KBC_8_BIT,
};
-
-/**
- * Select a config for a particular peripheral.
- *
- * Each peripheral can operate through a number of configurations,
- * which are sets of pins that it uses to bring out its signals.
- * The basic config is 0, and higher numbers indicate different
- * pinmux settings to bring the peripheral out on other pins,
- *
- * This function also disables tristate for the function's pins,
- * so that they operate in normal mode.
- *
- * @param id Peripheral id
- * @param config Configuration to use (FUNCMUX_...), 0 for default
- * @return 0 if ok, -1 on error (e.g. incorrect id or config)
- */
-int funcmux_select(enum periph_id id, int config);
-
-#endif
+#endif /* _TEGRA20_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/gp_padctrl.h b/arch/arm/include/asm/arch-tegra20/gp_padctrl.h
index 865af5bc79f1adb06a837fee14b4f566f8e0d0b2..eaaf903bf9fd9f30ed03d9364612f64b1cd8ee21 100644 (file)
* MA 02111-1307 USA
*/
-#ifndef _GP_PADCTRL_H_
-#define _GP_PADCTRL_H_
+#ifndef _TEGRA20_GP_PADCTRL_H_
+#define _TEGRA20_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
/* APB_MISC_GP and padctrl registers */
struct apb_misc_gp_ctlr {
u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */
};
-/* bit fields definitions for APB_MISC_GP_HIDREV register */
-#define HIDREV_CHIPID_SHIFT 8
-#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
-#define HIDREV_MAJORPREV_SHIFT 4
-#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
-
-/* CHIPID field returned from APB_MISC_GP_HIDREV register */
-#define CHIPID_TEGRA20 0x20
-
-#endif
+#endif /* _TEGRA20_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 797e158e68ae49b14cf646a76add1d5098eff8da..a9b4edaf261b63e3ddb33e0825e2c7da5c8426f7 100644 (file)
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
PMUX_FUNC_IDE,
- PMUX_FUNC_IRDA,
PMUX_FUNC_KBC,
PMUX_FUNC_MIO,
PMUX_FUNC_MIPI_HS,
index ca98733262ca6f8ab6cc395eb1ed433a1031d7c5..e1de0447ff6b28c1dcd060f2f32c1643a9e244d8 100644 (file)
#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
+#define MAX_NUM_CPU 2
+
#endif /* TEGRA20_H */
diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h
--- /dev/null
@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 clock PLL tables */
+
+#ifndef _TEGRA30_CLOCK_TABLES_H_
+#define _TEGRA30_CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+ CLOCK_ID_FIRST,
+ CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+ CLOCK_ID_MEMORY,
+ CLOCK_ID_PERIPH,
+ CLOCK_ID_AUDIO,
+ CLOCK_ID_USB,
+ CLOCK_ID_DISPLAY,
+
+ /* now the simple ones */
+ CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_EPCI,
+ CLOCK_ID_SFROM32KHZ,
+
+ /* These are the base clocks (inputs to the Tegra SOC) */
+ CLOCK_ID_32KHZ,
+ CLOCK_ID_OSC,
+
+ CLOCK_ID_COUNT, /* number of PLLs */
+ CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
+ CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+ PERIPH_ID_FIRST,
+
+ /* Low word: 31:0 */
+ PERIPH_ID_CPU = PERIPH_ID_FIRST,
+ PERIPH_ID_COP,
+ PERIPH_ID_TRIGSYS,
+ PERIPH_ID_RESERVED3,
+ PERIPH_ID_RESERVED4,
+ PERIPH_ID_TMR,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+
+ /* 8 */
+ PERIPH_ID_GPIO,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_NDFLASH,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC4,
+
+ /* 16 */
+ PERIPH_ID_RESERVED16,
+ PERIPH_ID_PWM,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_EPP,
+ PERIPH_ID_VI,
+ PERIPH_ID_2D,
+ PERIPH_ID_USBD,
+ PERIPH_ID_ISP,
+
+ /* 24 */
+ PERIPH_ID_3D,
+ PERIPH_ID_RESERVED24,
+ PERIPH_ID_DISP2,
+ PERIPH_ID_DISP1,
+ PERIPH_ID_HOST1X,
+ PERIPH_ID_VCP,
+ PERIPH_ID_I2S0,
+ PERIPH_ID_CACHE2,
+
+ /* Middle word: 63:32 */
+ PERIPH_ID_MEM,
+ PERIPH_ID_AHBDMA,
+ PERIPH_ID_APBDMA,
+ PERIPH_ID_RESERVED35,
+ PERIPH_ID_KBC,
+ PERIPH_ID_STAT_MON,
+ PERIPH_ID_PMC,
+ PERIPH_ID_FUSE,
+
+ /* 40 */
+ PERIPH_ID_KFUSE,
+ PERIPH_ID_SBC1,
+ PERIPH_ID_SNOR,
+ PERIPH_ID_RESERVED43,
+ PERIPH_ID_SBC2,
+ PERIPH_ID_RESERVED45,
+ PERIPH_ID_SBC3,
+ PERIPH_ID_DVC_I2C,
+
+ /* 48 */
+ PERIPH_ID_DSI,
+ PERIPH_ID_TVO,
+ PERIPH_ID_MIPI,
+ PERIPH_ID_HDMI,
+ PERIPH_ID_CSI,
+ PERIPH_ID_TVDAC,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_UART3,
+
+ /* 56 */
+ PERIPH_ID_RESERVED56,
+ PERIPH_ID_EMC,
+ PERIPH_ID_USB2,
+ PERIPH_ID_USB3,
+ PERIPH_ID_MPE,
+ PERIPH_ID_VDE,
+ PERIPH_ID_BSEA,
+ PERIPH_ID_BSEV,
+
+ /* Upper word 95:64 */
+ PERIPH_ID_SPEEDO,
+ PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_SBC4,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_PCIE,
+ PERIPH_ID_OWR,
+
+ /* 72 */
+ PERIPH_ID_AFI,
+ PERIPH_ID_CORESIGHT,
+ PERIPH_ID_PCIEXCLK,
+ PERIPH_ID_AVPUCQ,
+ PERIPH_ID_RESERVED76,
+ PERIPH_ID_RESERVED77,
+ PERIPH_ID_RESERVED78,
+ PERIPH_ID_DTV,
+
+ /* 80 */
+ PERIPH_ID_NANDSPEED,
+ PERIPH_ID_I2CSLOW,
+ PERIPH_ID_DSIB,
+ PERIPH_ID_RESERVED83,
+ PERIPH_ID_IRAMA,
+ PERIPH_ID_IRAMB,
+ PERIPH_ID_IRAMC,
+ PERIPH_ID_IRAMD,
+
+ /* 88 */
+ PERIPH_ID_CRAM2,
+ PERIPH_ID_RESERVED89,
+ PERIPH_ID_MDOUBLER,
+ PERIPH_ID_RESERVED91,
+ PERIPH_ID_SUSOUT,
+ PERIPH_ID_RESERVED93,
+ PERIPH_ID_RESERVED94,
+ PERIPH_ID_RESERVED95,
+
+ PERIPH_ID_VW_FIRST,
+ /* V word: 31:0 */
+ PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
+ PERIPH_ID_CPULP,
+ PERIPH_ID_3D2,
+ PERIPH_ID_MSELECT,
+ PERIPH_ID_TSENSOR,
+ PERIPH_ID_I2S3,
+ PERIPH_ID_I2S4,
+ PERIPH_ID_I2C4,
+
+ /* 08 */
+ PERIPH_ID_SBC5,
+ PERIPH_ID_SBC6,
+ PERIPH_ID_AUDIO,
+ PERIPH_ID_APBIF,
+ PERIPH_ID_DAM0,
+ PERIPH_ID_DAM1,
+ PERIPH_ID_DAM2,
+ PERIPH_ID_HDA2CODEC2X,
+
+ /* 16 */
+ PERIPH_ID_ATOMICS,
+ PERIPH_ID_EX_RESERVED17,
+ PERIPH_ID_EX_RESERVED18,
+ PERIPH_ID_EX_RESERVED19,
+ PERIPH_ID_EX_RESERVED20,
+ PERIPH_ID_EX_RESERVED21,
+ PERIPH_ID_EX_RESERVED22,
+ PERIPH_ID_ACTMON,
+
+ /* 24 */
+ PERIPH_ID_EX_RESERVED24,
+ PERIPH_ID_EX_RESERVED25,
+ PERIPH_ID_EX_RESERVED26,
+ PERIPH_ID_EX_RESERVED27,
+ PERIPH_ID_SATA,
+ PERIPH_ID_HDA,
+ PERIPH_ID_EX_RESERVED30,
+ PERIPH_ID_EX_RESERVED31,
+
+ /* W word: 31:0 */
+ PERIPH_ID_HDA2HDMICODEC,
+ PERIPH_ID_SATACOLD,
+ PERIPH_ID_RESERVED0_PCIERX0,
+ PERIPH_ID_RESERVED1_PCIERX1,
+ PERIPH_ID_RESERVED2_PCIERX2,
+ PERIPH_ID_RESERVED3_PCIERX3,
+ PERIPH_ID_RESERVED4_PCIERX4,
+ PERIPH_ID_RESERVED5_PCIERX5,
+
+ /* 40 */
+ PERIPH_ID_CEC,
+ PERIPH_ID_RESERVED6_PCIE2,
+ PERIPH_ID_RESERVED7_EMC,
+ PERIPH_ID_RESERVED8_HDMI,
+ PERIPH_ID_RESERVED9_SATA,
+ PERIPH_ID_RESERVED10_MIPI,
+ PERIPH_ID_EX_RESERVED46,
+ PERIPH_ID_EX_RESERVED47,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+ PLL_OUT1,
+ PLL_OUT2,
+ PLL_OUT3,
+ PLL_OUT4
+};
+
+/*
+ * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
+ * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
+ * confusion bewteen PERIPH_ID_... and PERIPHC_...
+ *
+ * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
+ * confusing.
+ */
+enum periphc_internal_id {
+ /* 0x00 */
+ PERIPHC_I2S1,
+ PERIPHC_I2S2,
+ PERIPHC_SPDIF_OUT,
+ PERIPHC_SPDIF_IN,
+ PERIPHC_PWM,
+ PERIPHC_05h,
+ PERIPHC_SBC2,
+ PERIPHC_SBC3,
+
+ /* 0x08 */
+ PERIPHC_08h,
+ PERIPHC_I2C1,
+ PERIPHC_DVC_I2C,
+ PERIPHC_0bh,
+ PERIPHC_0ch,
+ PERIPHC_SBC1,
+ PERIPHC_DISP1,
+ PERIPHC_DISP2,
+
+ /* 0x10 */
+ PERIPHC_CVE,
+ PERIPHC_11h,
+ PERIPHC_VI,
+ PERIPHC_13h,
+ PERIPHC_SDMMC1,
+ PERIPHC_SDMMC2,
+ PERIPHC_G3D,
+ PERIPHC_G2D,
+
+ /* 0x18 */
+ PERIPHC_NDFLASH,
+ PERIPHC_SDMMC4,
+ PERIPHC_VFIR,
+ PERIPHC_EPP,
+ PERIPHC_MPE,
+ PERIPHC_MIPI,
+ PERIPHC_UART1,
+ PERIPHC_UART2,
+
+ /* 0x20 */
+ PERIPHC_HOST1X,
+ PERIPHC_21h,
+ PERIPHC_TVO,
+ PERIPHC_HDMI,
+ PERIPHC_24h,
+ PERIPHC_TVDAC,
+ PERIPHC_I2C2,
+ PERIPHC_EMC,
+
+ /* 0x28 */
+ PERIPHC_UART3,
+ PERIPHC_29h,
+ PERIPHC_VI_SENSOR,
+ PERIPHC_2bh,
+ PERIPHC_2ch,
+ PERIPHC_SBC4,
+ PERIPHC_I2C3,
+ PERIPHC_SDMMC3,
+
+ /* 0x30 */
+ PERIPHC_UART4,
+ PERIPHC_UART5,
+ PERIPHC_VDE,
+ PERIPHC_OWR,
+ PERIPHC_NOR,
+ PERIPHC_CSITE,
+ PERIPHC_I2S0,
+ PERIPHC_37h,
+
+ PERIPHC_VW_FIRST,
+ /* 0x38 */
+ PERIPHC_G3D2 = PERIPHC_VW_FIRST,
+ PERIPHC_MSELECT,
+ PERIPHC_TSENSOR,
+ PERIPHC_I2S3,
+ PERIPHC_I2S4,
+ PERIPHC_I2C4,
+ PERIPHC_SBC5,
+ PERIPHC_SBC6,
+
+ /* 0x40 */
+ PERIPHC_AUDIO,
+ PERIPHC_41h,
+ PERIPHC_DAM0,
+ PERIPHC_DAM1,
+ PERIPHC_DAM2,
+ PERIPHC_HDA2CODEC2X,
+ PERIPHC_ACTMON,
+ PERIPHC_EXTPERIPH1,
+
+ /* 0x48 */
+ PERIPHC_EXTPERIPH2,
+ PERIPHC_EXTPERIPH3,
+ PERIPHC_NANDSPEED,
+ PERIPHC_I2CSLOW,
+ PERIPHC_SYS,
+ PERIPHC_SPEEDO,
+ PERIPHC_4eh,
+ PERIPHC_4fh,
+
+ /* 0x50 */
+ PERIPHC_50h,
+ PERIPHC_51h,
+ PERIPHC_52h,
+ PERIPHC_53h,
+ PERIPHC_SATAOOB,
+ PERIPHC_SATA,
+ PERIPHC_HDA,
+
+ PERIPHC_COUNT,
+
+ PERIPHC_NONE = -1,
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
+#define PERIPH_REG(id) \
+ (id < PERIPH_ID_VW_FIRST) ? \
+ ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
+
+/* return 1 if a peripheral ID is in range */
+#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
+ (id) < PERIPH_ID_COUNT)
+
+#endif /* _TEGRA30_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/clock.h b/arch/arm/include/asm/arch-tegra30/clock.h
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 clock control functions */
+
+#ifndef _TEGRA30_CLOCK_H_
+#define _TEGRA30_CLOCK_H_
+
+#include <asm/arch-tegra/clock.h>
+
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT 28
+#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+
+#endif /* _TEGRA30_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/flow.h b/arch/arm/include/asm/arch-tegra30/flow.h
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_FLOW_H_
+#define _TEGRA30_FLOW_H_
+
+struct flow_ctlr {
+ u32 halt_cpu_events;
+ u32 halt_cop_events;
+ u32 cpu_csr;
+ u32 cop_csr;
+ u32 xrq_events;
+ u32 halt_cpu1_events;
+ u32 cpu1_csr;
+ u32 halt_cpu2_events;
+ u32 cpu2_csr;
+ u32 halt_cpu3_events;
+ u32 cpu3_csr;
+ u32 cluster_control;
+};
+
+#endif /* _TEGRA30_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/funcmux.h b/arch/arm/include/asm/arch-tegra30/funcmux.h
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Tegra30 high-level function multiplexing */
+
+#ifndef _TEGRA30_FUNCMUX_H_
+#define _TEGRA30_FUNCMUX_H_
+
+#include <asm/arch-tegra/funcmux.h>
+
+/* Configs supported by the func mux */
+enum {
+ FUNCMUX_DEFAULT = 0, /* default config */
+
+ /* UART configs */
+ FUNCMUX_UART1_ULPI = 0,
+};
+#endif /* _TEGRA30_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gp_padctrl.h b/arch/arm/include/asm/arch-tegra30/gp_padctrl.h
--- /dev/null
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_GP_PADCTRL_H_
+#define _TEGRA30_GP_PADCTRL_H_
+
+#include <asm/arch-tegra/gp_padctrl.h>
+
+/* APB_MISC_GP and padctrl registers */
+struct apb_misc_gp_ctlr {
+ u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
+ u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
+ u32 reserved0[22]; /* 0x08 - 0x5C: */
+ u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
+ u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
+ u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
+ u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+ u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
+ u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
+ u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
+ u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
+ u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
+ u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
+ u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
+ u32 csuscfg; /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
+ u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
+ u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
+ u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
+ u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
+ u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
+ u32 lcdcfg1; /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
+ u32 lcdcfg2; /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
+ u32 sdio2cfg; /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
+ u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
+ u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
+ u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
+ u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
+ u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
+ u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
+ u32 vicfg1; /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
+ u32 vivttgen; /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
+ u32 reserved1[7]; /* 0xD0-0xE8: */
+ u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+};
+
+#endif /* _TEGRA30_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h
--- /dev/null
@@ -0,0 +1,304 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_GPIO_H_
+#define _TEGRA30_GPIO_H_
+
+/*
+ * The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
+ * each with 8 GPIOs.
+ */
+#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
+#define TEGRA_GPIO_BANKS 8 /* number of banks */
+
+#include <asm/arch-tegra/gpio.h>
+
+/* GPIO Controller registers for a single bank */
+struct gpio_ctlr_bank {
+ uint gpio_config[TEGRA_GPIO_PORTS];
+ uint gpio_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_out[TEGRA_GPIO_PORTS];
+ uint gpio_in[TEGRA_GPIO_PORTS];
+ uint gpio_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_int_clear[TEGRA_GPIO_PORTS];
+ uint gpio_masked_config[TEGRA_GPIO_PORTS];
+ uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
+ uint gpio_masked_out[TEGRA_GPIO_PORTS];
+ uint gpio_masked_in[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
+ uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
+};
+
+struct gpio_ctlr {
+ struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
+};
+
+enum gpio_pin {
+ GPIO_PA0 = 0, /* pin 0 */
+ GPIO_PA1,
+ GPIO_PA2,
+ GPIO_PA3,
+ GPIO_PA4,
+ GPIO_PA5,
+ GPIO_PA6,
+ GPIO_PA7,
+ GPIO_PB0, /* pin 8 */
+ GPIO_PB1,
+ GPIO_PB2,
+ GPIO_PB3,
+ GPIO_PB4,
+ GPIO_PB5,
+ GPIO_PB6,
+ GPIO_PB7,
+ GPIO_PC0, /* pin 16 */
+ GPIO_PC1,
+ GPIO_PC2,
+ GPIO_PC3,
+ GPIO_PC4,
+ GPIO_PC5,
+ GPIO_PC6,
+ GPIO_PC7,
+ GPIO_PD0, /* pin 24 */
+ GPIO_PD1,
+ GPIO_PD2,
+ GPIO_PD3,
+ GPIO_PD4,
+ GPIO_PD5,
+ GPIO_PD6,
+ GPIO_PD7,
+ GPIO_PE0, /* pin 32 */
+ GPIO_PE1,
+ GPIO_PE2,
+ GPIO_PE3,
+ GPIO_PE4,
+ GPIO_PE5,
+ GPIO_PE6,
+ GPIO_PE7,
+ GPIO_PF0, /* pin 40 */
+ GPIO_PF1,
+ GPIO_PF2,
+ GPIO_PF3,
+ GPIO_PF4,
+ GPIO_PF5,
+ GPIO_PF6,
+ GPIO_PF7,
+ GPIO_PG0, /* pin 48 */
+ GPIO_PG1,
+ GPIO_PG2,
+ GPIO_PG3,
+ GPIO_PG4,
+ GPIO_PG5,
+ GPIO_PG6,
+ GPIO_PG7,
+ GPIO_PH0, /* pin 56 */
+ GPIO_PH1,
+ GPIO_PH2,
+ GPIO_PH3,
+ GPIO_PH4,
+ GPIO_PH5,
+ GPIO_PH6,
+ GPIO_PH7,
+ GPIO_PI0, /* pin 64 */
+ GPIO_PI1,
+ GPIO_PI2,
+ GPIO_PI3,
+ GPIO_PI4,
+ GPIO_PI5,
+ GPIO_PI6,
+ GPIO_PI7,
+ GPIO_PJ0, /* pin 72 */
+ GPIO_PJ1,
+ GPIO_PJ2,
+ GPIO_PJ3,
+ GPIO_PJ4,
+ GPIO_PJ5,
+ GPIO_PJ6,
+ GPIO_PJ7,
+ GPIO_PK0, /* pin 80 */
+ GPIO_PK1,
+ GPIO_PK2,
+ GPIO_PK3,
+ GPIO_PK4,
+ GPIO_PK5,
+ GPIO_PK6,
+ GPIO_PK7,
+ GPIO_PL0, /* pin 88 */
+ GPIO_PL1,
+ GPIO_PL2,
+ GPIO_PL3,
+ GPIO_PL4,
+ GPIO_PL5,
+ GPIO_PL6,
+ GPIO_PL7,
+ GPIO_PM0, /* pin 96 */
+ GPIO_PM1,
+ GPIO_PM2,
+ GPIO_PM3,
+ GPIO_PM4,
+ GPIO_PM5,
+ GPIO_PM6,
+ GPIO_PM7,
+ GPIO_PN0, /* pin 104 */
+ GPIO_PN1,
+ GPIO_PN2,
+ GPIO_PN3,
+ GPIO_PN4,
+ GPIO_PN5,
+ GPIO_PN6,
+ GPIO_PN7,
+ GPIO_PO0, /* pin 112 */
+ GPIO_PO1,
+ GPIO_PO2,
+ GPIO_PO3,
+ GPIO_PO4,
+ GPIO_PO5,
+ GPIO_PO6,
+ GPIO_PO7,
+ GPIO_PP0, /* pin 120 */
+ GPIO_PP1,
+ GPIO_PP2,
+ GPIO_PP3,
+ GPIO_PP4,
+ GPIO_PP5,
+ GPIO_PP6,
+ GPIO_PP7,
+ GPIO_PQ0, /* pin 128 */
+ GPIO_PQ1,
+ GPIO_PQ2,
+ GPIO_PQ3,
+ GPIO_PQ4,
+ GPIO_PQ5,
+ GPIO_PQ6,
+ GPIO_PQ7,
+ GPIO_PR0, /* pin 136 */
+ GPIO_PR1,
+ GPIO_PR2,
+ GPIO_PR3,
+ GPIO_PR4,
+ GPIO_PR5,
+ GPIO_PR6,
+ GPIO_PR7,
+ GPIO_PS0, /* pin 144 */
+ GPIO_PS1,
+ GPIO_PS2,
+ GPIO_PS3,
+ GPIO_PS4,
+ GPIO_PS5,
+ GPIO_PS6,
+ GPIO_PS7,
+ GPIO_PT0, /* pin 152 */
+ GPIO_PT1,
+ GPIO_PT2,
+ GPIO_PT3,
+ GPIO_PT4,
+ GPIO_PT5,
+ GPIO_PT6,
+ GPIO_PT7,
+ GPIO_PU0, /* pin 160 */
+ GPIO_PU1,
+ GPIO_PU2,
+ GPIO_PU3,
+ GPIO_PU4,
+ GPIO_PU5,
+ GPIO_PU6,
+ GPIO_PU7,
+ GPIO_PV0, /* pin 168 */
+ GPIO_PV1,
+ GPIO_PV2,
+ GPIO_PV3,
+ GPIO_PV4,
+ GPIO_PV5,
+ GPIO_PV6,
+ GPIO_PV7,
+ GPIO_PW0, /* pin 176 */
+ GPIO_PW1,
+ GPIO_PW2,
+ GPIO_PW3,
+ GPIO_PW4,
+ GPIO_PW5,
+ GPIO_PW6,
+ GPIO_PW7,
+ GPIO_PX0, /* pin 184 */
+ GPIO_PX1,
+ GPIO_PX2,
+ GPIO_PX3,
+ GPIO_PX4,
+ GPIO_PX5,
+ GPIO_PX6,
+ GPIO_PX7,
+ GPIO_PY0, /* pin 192 */
+ GPIO_PY1,
+ GPIO_PY2,
+ GPIO_PY3,
+ GPIO_PY4,
+ GPIO_PY5,
+ GPIO_PY6,
+ GPIO_PY7,
+ GPIO_PZ0, /* pin 200 */
+ GPIO_PZ1,
+ GPIO_PZ2,
+ GPIO_PZ3,
+ GPIO_PZ4,
+ GPIO_PZ5,
+ GPIO_PZ6,
+ GPIO_PZ7,
+ GPIO_PAA0, /* pin 208 */
+ GPIO_PAA1,
+ GPIO_PAA2,
+ GPIO_PAA3,
+ GPIO_PAA4,
+ GPIO_PAA5,
+ GPIO_PAA6,
+ GPIO_PAA7,
+ GPIO_PBB0, /* pin 216 */
+ GPIO_PBB1,
+ GPIO_PBB2,
+ GPIO_PBB3,
+ GPIO_PBB4,
+ GPIO_PBB5,
+ GPIO_PBB6,
+ GPIO_PBB7,
+ GPIO_PCC0, /* pin 224 */
+ GPIO_PCC1,
+ GPIO_PCC2,
+ GPIO_PCC3,
+ GPIO_PCC4,
+ GPIO_PCC5,
+ GPIO_PCC6,
+ GPIO_PCC7,
+ GPIO_PDD0, /* pin 232 */
+ GPIO_PDD1,
+ GPIO_PDD2,
+ GPIO_PDD3,
+ GPIO_PDD4,
+ GPIO_PDD5,
+ GPIO_PDD6,
+ GPIO_PDD7,
+ GPIO_PEE0, /* pin 240 */
+ GPIO_PEE1,
+ GPIO_PEE2,
+ GPIO_PEE3,
+ GPIO_PEE4,
+ GPIO_PEE5,
+ GPIO_PEE6,
+ GPIO_PEE7, /* pin 247 */
+};
+
+#endif /* _TEGRA30_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/hardware.h b/arch/arm/include/asm/arch-tegra30/hardware.h
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_HARDWARE_H_
+#define _TEGRA30_HARDWARE_H_
+
+/* include tegra specific hardware definitions */
+
+#endif /* _TEGRA30-HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
--- /dev/null
@@ -0,0 +1,603 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_PINMUX_H_
+#define _TEGRA30_PINMUX_H_
+
+/*
+ * Pin groups which we adjust. There are three basic attributes of each pin
+ * group which use this enum:
+ *
+ * - function
+ * - pullup / pulldown
+ * - tristate or normal
+ */
+enum pmux_pingrp {
+ PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
+ PINGRP_ULPI_DATA1,
+ PINGRP_ULPI_DATA2,
+ PINGRP_ULPI_DATA3,
+ PINGRP_ULPI_DATA4,
+ PINGRP_ULPI_DATA5,
+ PINGRP_ULPI_DATA6,
+ PINGRP_ULPI_DATA7,
+ PINGRP_ULPI_CLK,
+ PINGRP_ULPI_DIR,
+ PINGRP_ULPI_NXT,
+ PINGRP_ULPI_STP,
+ PINGRP_DAP3_FS,
+ PINGRP_DAP3_DIN,
+ PINGRP_DAP3_DOUT,
+ PINGRP_DAP3_SCLK,
+ PINGRP_GPIO_PV0,
+ PINGRP_GPIO_PV1,
+ PINGRP_SDMMC1_CLK,
+ PINGRP_SDMMC1_CMD,
+ PINGRP_SDMMC1_DAT3,
+ PINGRP_SDMMC1_DAT2,
+ PINGRP_SDMMC1_DAT1,
+ PINGRP_SDMMC1_DAT0,
+ PINGRP_GPIO_PV2,
+ PINGRP_GPIO_PV3,
+ PINGRP_CLK2_OUT,
+ PINGRP_CLK2_REQ,
+ PINGRP_LCD_PWR1,
+ PINGRP_LCD_PWR2,
+ PINGRP_LCD_SDIN,
+ PINGRP_LCD_SDOUT,
+ PINGRP_LCD_WR_N,
+ PINGRP_LCD_CS0_N,
+ PINGRP_LCD_DC0,
+ PINGRP_LCD_SCK,
+ PINGRP_LCD_PWR0,
+ PINGRP_LCD_PCLK,
+ PINGRP_LCD_DE,
+ PINGRP_LCD_HSYNC,
+ PINGRP_LCD_VSYNC,
+ PINGRP_LCD_D0,
+ PINGRP_LCD_D1,
+ PINGRP_LCD_D2,
+ PINGRP_LCD_D3,
+ PINGRP_LCD_D4,
+ PINGRP_LCD_D5,
+ PINGRP_LCD_D6,
+ PINGRP_LCD_D7,
+ PINGRP_LCD_D8,
+ PINGRP_LCD_D9,
+ PINGRP_LCD_D10,
+ PINGRP_LCD_D11,
+ PINGRP_LCD_D12,
+ PINGRP_LCD_D13,
+ PINGRP_LCD_D14,
+ PINGRP_LCD_D15,
+ PINGRP_LCD_D16,
+ PINGRP_LCD_D17,
+ PINGRP_LCD_D18,
+ PINGRP_LCD_D19,
+ PINGRP_LCD_D20,
+ PINGRP_LCD_D21,
+ PINGRP_LCD_D22,
+ PINGRP_LCD_D23,
+ PINGRP_LCD_CS1_N,
+ PINGRP_LCD_M1,
+ PINGRP_LCD_DC1,
+ PINGRP_HDMI_INT,
+ PINGRP_DDC_SCL,
+ PINGRP_DDC_SDA,
+ PINGRP_CRT_HSYNC,
+ PINGRP_CRT_VSYNC,
+ PINGRP_VI_D0,
+ PINGRP_VI_D1,
+ PINGRP_VI_D2,
+ PINGRP_VI_D3,
+ PINGRP_VI_D4,
+ PINGRP_VI_D5,
+ PINGRP_VI_D6,
+ PINGRP_VI_D7,
+ PINGRP_VI_D8,
+ PINGRP_VI_D9,
+ PINGRP_VI_D10,
+ PINGRP_VI_D11,
+ PINGRP_VI_PCLK,
+ PINGRP_VI_MCLK,
+ PINGRP_VI_VSYNC,
+ PINGRP_VI_HSYNC,
+ PINGRP_UART2_RXD,
+ PINGRP_UART2_TXD,
+ PINGRP_UART2_RTS_N,
+ PINGRP_UART2_CTS_N,
+ PINGRP_UART3_TXD,
+ PINGRP_UART3_RXD,
+ PINGRP_UART3_CTS_N,
+ PINGRP_UART3_RTS_N,
+ PINGRP_GPIO_PU0,
+ PINGRP_GPIO_PU1,
+ PINGRP_GPIO_PU2,
+ PINGRP_GPIO_PU3,
+ PINGRP_GPIO_PU4,
+ PINGRP_GPIO_PU5,
+ PINGRP_GPIO_PU6,
+ PINGRP_GEN1_I2C_SDA,
+ PINGRP_GEN1_I2C_SCL,
+ PINGRP_DAP4_FS,
+ PINGRP_DAP4_DIN,
+ PINGRP_DAP4_DOUT,
+ PINGRP_DAP4_SCLK,
+ PINGRP_CLK3_OUT,
+ PINGRP_CLK3_REQ,
+ PINGRP_GMI_WP_N,
+ PINGRP_GMI_IORDY,
+ PINGRP_GMI_WAIT,
+ PINGRP_GMI_ADV_N,
+ PINGRP_GMI_CLK,
+ PINGRP_GMI_CS0_N,
+ PINGRP_GMI_CS1_N,
+ PINGRP_GMI_CS2_N,
+ PINGRP_GMI_CS3_N,
+ PINGRP_GMI_CS4_N,
+ PINGRP_GMI_CS6_N,
+ PINGRP_GMI_CS7_N,
+ PINGRP_GMI_AD0,
+ PINGRP_GMI_AD1,
+ PINGRP_GMI_AD2,
+ PINGRP_GMI_AD3,
+ PINGRP_GMI_AD4,
+ PINGRP_GMI_AD5,
+ PINGRP_GMI_AD6,
+ PINGRP_GMI_AD7,
+ PINGRP_GMI_AD8,
+ PINGRP_GMI_AD9,
+ PINGRP_GMI_AD10,
+ PINGRP_GMI_AD11,
+ PINGRP_GMI_AD12,
+ PINGRP_GMI_AD13,
+ PINGRP_GMI_AD14,
+ PINGRP_GMI_AD15,
+ PINGRP_GMI_A16,
+ PINGRP_GMI_A17,
+ PINGRP_GMI_A18,
+ PINGRP_GMI_A19,
+ PINGRP_GMI_WR_N,
+ PINGRP_GMI_OE_N,
+ PINGRP_GMI_DQS,
+ PINGRP_GMI_RST_N,
+ PINGRP_GEN2_I2C_SCL,
+ PINGRP_GEN2_I2C_SDA,
+ PINGRP_SDMMC4_CLK,
+ PINGRP_SDMMC4_CMD,
+ PINGRP_SDMMC4_DAT0,
+ PINGRP_SDMMC4_DAT1,
+ PINGRP_SDMMC4_DAT2,
+ PINGRP_SDMMC4_DAT3,
+ PINGRP_SDMMC4_DAT4,
+ PINGRP_SDMMC4_DAT5,
+ PINGRP_SDMMC4_DAT6,
+ PINGRP_SDMMC4_DAT7,
+ PINGRP_SDMMC4_RST_N,
+ PINGRP_CAM_MCLK,
+ PINGRP_GPIO_PCC1,
+ PINGRP_GPIO_PBB0,
+ PINGRP_CAM_I2C_SCL,
+ PINGRP_CAM_I2C_SDA,
+ PINGRP_GPIO_PBB3,
+ PINGRP_GPIO_PBB4,
+ PINGRP_GPIO_PBB5,
+ PINGRP_GPIO_PBB6,
+ PINGRP_GPIO_PBB7,
+ PINGRP_GPIO_PCC2,
+ PINGRP_JTAG_RTCK,
+ PINGRP_PWR_I2C_SCL,
+ PINGRP_PWR_I2C_SDA,
+ PINGRP_KB_ROW0,
+ PINGRP_KB_ROW1,
+ PINGRP_KB_ROW2,
+ PINGRP_KB_ROW3,
+ PINGRP_KB_ROW4,
+ PINGRP_KB_ROW5,
+ PINGRP_KB_ROW6,
+ PINGRP_KB_ROW7,
+ PINGRP_KB_ROW8,
+ PINGRP_KB_ROW9,
+ PINGRP_KB_ROW10,
+ PINGRP_KB_ROW11,
+ PINGRP_KB_ROW12,
+ PINGRP_KB_ROW13,
+ PINGRP_KB_ROW14,
+ PINGRP_KB_ROW15,
+ PINGRP_KB_COL0,
+ PINGRP_KB_COL1,
+ PINGRP_KB_COL2,
+ PINGRP_KB_COL3,
+ PINGRP_KB_COL4,
+ PINGRP_KB_COL5,
+ PINGRP_KB_COL6,
+ PINGRP_KB_COL7,
+ PINGRP_CLK_32K_OUT,
+ PINGRP_SYS_CLK_REQ,
+ PINGRP_CORE_PWR_REQ,
+ PINGRP_CPU_PWR_REQ,
+ PINGRP_PWR_INT_N,
+ PINGRP_CLK_32K_IN,
+ PINGRP_OWR,
+ PINGRP_DAP1_FS,
+ PINGRP_DAP1_DIN,
+ PINGRP_DAP1_DOUT,
+ PINGRP_DAP1_SCLK,
+ PINGRP_CLK1_REQ,
+ PINGRP_CLK1_OUT,
+ PINGRP_SPDIF_IN,
+ PINGRP_SPDIF_OUT,
+ PINGRP_DAP2_FS,
+ PINGRP_DAP2_DIN,
+ PINGRP_DAP2_DOUT,
+ PINGRP_DAP2_SCLK,
+ PINGRP_SPI2_MOSI,
+ PINGRP_SPI2_MISO,
+ PINGRP_SPI2_CS0_N,
+ PINGRP_SPI2_SCK,
+ PINGRP_SPI1_MOSI,
+ PINGRP_SPI1_SCK,
+ PINGRP_SPI1_CS0_N,
+ PINGRP_SPI1_MISO,
+ PINGRP_SPI2_CS1_N,
+ PINGRP_SPI2_CS2_N,
+ PINGRP_SDMMC3_CLK,
+ PINGRP_SDMMC3_CMD,
+ PINGRP_SDMMC3_DAT0,
+ PINGRP_SDMMC3_DAT1,
+ PINGRP_SDMMC3_DAT2,
+ PINGRP_SDMMC3_DAT3,
+ PINGRP_SDMMC3_DAT4,
+ PINGRP_SDMMC3_DAT5,
+ PINGRP_SDMMC3_DAT6,
+ PINGRP_SDMMC3_DAT7,
+ PINGRP_PEX_L0_PRSNT_N,
+ PINGRP_PEX_L0_RST_N,
+ PINGRP_PEX_L0_CLKREQ_N,
+ PINGRP_PEX_WAKE_N,
+ PINGRP_PEX_L1_PRSNT_N,
+ PINGRP_PEX_L1_RST_N,
+ PINGRP_PEX_L1_CLKREQ_N,
+ PINGRP_PEX_L2_PRSNT_N,
+ PINGRP_PEX_L2_RST_N,
+ PINGRP_PEX_L2_CLKREQ_N,
+ PINGRP_HDMI_CEC, /* offset 0x33e0 */
+ PINGRP_COUNT,
+};
+
+enum pdrive_pingrp {
+ PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
+ PDRIVE_PINGROUP_AO2,
+ PDRIVE_PINGROUP_AT1,
+ PDRIVE_PINGROUP_AT2,
+ PDRIVE_PINGROUP_AT3,
+ PDRIVE_PINGROUP_AT4,
+ PDRIVE_PINGROUP_AT5,
+ PDRIVE_PINGROUP_CDEV1,
+ PDRIVE_PINGROUP_CDEV2,
+ PDRIVE_PINGROUP_CSUS,
+ PDRIVE_PINGROUP_DAP1,
+ PDRIVE_PINGROUP_DAP2,
+ PDRIVE_PINGROUP_DAP3,
+ PDRIVE_PINGROUP_DAP4,
+ PDRIVE_PINGROUP_DBG,
+ PDRIVE_PINGROUP_LCD1,
+ PDRIVE_PINGROUP_LCD2,
+ PDRIVE_PINGROUP_SDIO2,
+ PDRIVE_PINGROUP_SDIO3,
+ PDRIVE_PINGROUP_SPI,
+ PDRIVE_PINGROUP_UAA,
+ PDRIVE_PINGROUP_UAB,
+ PDRIVE_PINGROUP_UART2,
+ PDRIVE_PINGROUP_UART3,
+ PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
+ PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
+ PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
+ PDRIVE_PINGROUP_DDC,
+ PDRIVE_PINGROUP_GMA,
+ PDRIVE_PINGROUP_GMB,
+ PDRIVE_PINGROUP_GMC,
+ PDRIVE_PINGROUP_GMD,
+ PDRIVE_PINGROUP_GME,
+ PDRIVE_PINGROUP_GMF,
+ PDRIVE_PINGROUP_GMG,
+ PDRIVE_PINGROUP_GMH,
+ PDRIVE_PINGROUP_OWR,
+ PDRIVE_PINGROUP_UAD,
+ PDRIVE_PINGROUP_GPV,
+ PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
+ PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
+ PDRIVE_PINGROUP_COUNT,
+};
+
+/*
+ * Functions which can be assigned to each of the pin groups. The values here
+ * bear no relation to the values programmed into pinmux registers and are
+ * purely a convenience. The translation is done through a table search.
+ */
+enum pmux_func {
+ PMUX_FUNC_AHB_CLK,
+ PMUX_FUNC_APB_CLK,
+ PMUX_FUNC_AUDIO_SYNC,
+ PMUX_FUNC_CRT,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
+ PMUX_FUNC_DAP3,
+ PMUX_FUNC_DAP4,
+ PMUX_FUNC_DAP5,
+ PMUX_FUNC_DISPA,
+ PMUX_FUNC_DISPB,
+ PMUX_FUNC_EMC_TEST0_DLL,
+ PMUX_FUNC_EMC_TEST1_DLL,
+ PMUX_FUNC_GMI,
+ PMUX_FUNC_GMI_INT,
+ PMUX_FUNC_HDMI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
+ PMUX_FUNC_IDE,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_MIO,
+ PMUX_FUNC_MIPI_HS,
+ PMUX_FUNC_NAND,
+ PMUX_FUNC_OSC,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PCIE,
+ PMUX_FUNC_PLLA_OUT,
+ PMUX_FUNC_PLLC_OUT1,
+ PMUX_FUNC_PLLM_OUT1,
+ PMUX_FUNC_PLLP_OUT2,
+ PMUX_FUNC_PLLP_OUT3,
+ PMUX_FUNC_PLLP_OUT4,
+ PMUX_FUNC_PWM,
+ PMUX_FUNC_PWR_INTR,
+ PMUX_FUNC_PWR_ON,
+ PMUX_FUNC_RTCK,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SFLASH,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI2_ALT,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_TWC,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_UARTE,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_SENSOR_CLK,
+ PMUX_FUNC_XIO,
+ PMUX_FUNC_BLINK,
+ PMUX_FUNC_CEC,
+ PMUX_FUNC_CLK12,
+ PMUX_FUNC_DAP,
+ PMUX_FUNC_DAPSDMMC2,
+ PMUX_FUNC_DDR,
+ PMUX_FUNC_DEV3,
+ PMUX_FUNC_DTV,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT2,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_EMC_DLL,
+ PMUX_FUNC_EXTPERIPH1,
+ PMUX_FUNC_EXTPERIPH2,
+ PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI_ALT,
+ PMUX_FUNC_HDA,
+ PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C4,
+ PMUX_FUNC_I2C5,
+ PMUX_FUNC_I2CPWR,
+ PMUX_FUNC_I2S0,
+ PMUX_FUNC_I2S1,
+ PMUX_FUNC_I2S2,
+ PMUX_FUNC_I2S3,
+ PMUX_FUNC_I2S4,
+ PMUX_FUNC_NAND_ALT,
+ PMUX_FUNC_POPSDIO4,
+ PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_PWM0,
+ PMUX_FUNC_PWM1,
+ PMUX_FUNC_PWM2,
+ PMUX_FUNC_PWM3,
+ PMUX_FUNC_SATA,
+ PMUX_FUNC_SPI5,
+ PMUX_FUNC_SPI6,
+ PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_VGP1,
+ PMUX_FUNC_VGP2,
+ PMUX_FUNC_VGP3,
+ PMUX_FUNC_VGP4,
+ PMUX_FUNC_VGP5,
+ PMUX_FUNC_VGP6,
+ PMUX_FUNC_CLK_12M_OUT,
+ PMUX_FUNC_HDCP,
+ PMUX_FUNC_TEST,
+ PMUX_FUNC_CORE_PWR_REQ,
+ PMUX_FUNC_CPU_PWR_REQ,
+ PMUX_FUNC_PWR_INT_N,
+ PMUX_FUNC_CLK_32K_IN,
+ PMUX_FUNC_SAFE,
+
+ PMUX_FUNC_MAX,
+
+ PMUX_FUNC_RSVD1 = 0x8000,
+ PMUX_FUNC_RSVD2 = 0x8001,
+ PMUX_FUNC_RSVD3 = 0x8002,
+ PMUX_FUNC_RSVD4 = 0x8003,
+};
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
+ || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+ PMUX_PULL_NORMAL = 0,
+ PMUX_PULL_DOWN,
+ PMUX_PULL_UP,
+};
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
+ ((pupd) <= PMUX_PULL_UP))
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+ PMUX_TRI_NORMAL = 0,
+ PMUX_TRI_TRISTATE = 1,
+};
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
+ && ((tristate) <= PMUX_TRI_TRISTATE))
+
+enum pmux_pin_io {
+ PMUX_PIN_OUTPUT = 0,
+ PMUX_PIN_INPUT = 1,
+};
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
+ ((io) <= PMUX_PIN_INPUT))
+
+enum pmux_pin_lock {
+ PMUX_PIN_LOCK_DEFAULT = 0,
+ PMUX_PIN_LOCK_DISABLE,
+ PMUX_PIN_LOCK_ENABLE,
+};
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
+ ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+enum pmux_pin_od {
+ PMUX_PIN_OD_DEFAULT = 0,
+ PMUX_PIN_OD_DISABLE,
+ PMUX_PIN_OD_ENABLE,
+};
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
+ ((od) <= PMUX_PIN_OD_ENABLE))
+
+enum pmux_pin_ioreset {
+ PMUX_PIN_IO_RESET_DEFAULT = 0,
+ PMUX_PIN_IO_RESET_DISABLE,
+ PMUX_PIN_IO_RESET_ENABLE,
+};
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+ (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
+ ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+/* Available power domains used by pin groups */
+enum pmux_vddio {
+ PMUX_VDDIO_BB = 0,
+ PMUX_VDDIO_LCD,
+ PMUX_VDDIO_VI,
+ PMUX_VDDIO_UART,
+ PMUX_VDDIO_DDR,
+ PMUX_VDDIO_NAND,
+ PMUX_VDDIO_SYS,
+ PMUX_VDDIO_AUDIO,
+ PMUX_VDDIO_SD,
+ PMUX_VDDIO_CAM,
+ PMUX_VDDIO_GMI,
+ PMUX_VDDIO_PEXCTL,
+ PMUX_VDDIO_SDMMC1,
+ PMUX_VDDIO_SDMMC3,
+ PMUX_VDDIO_SDMMC4,
+
+ PMUX_VDDIO_NONE
+};
+
+/* t30 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
+#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+ PDRIVE_PINGROUP_COUNT)
+struct pmux_tri_ctlr {
+ uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
+ uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
+ uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
+ uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
+ uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
+ uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
+ uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
+
+ uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
+
+ uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
+ uint pmt_reserved5[PMUX_OFFSET];
+ uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
+};
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pingroup_config {
+ enum pmux_pingrp pingroup; /* pin group PINGRP_... */
+ enum pmux_func func; /* function to assign FUNC_... */
+ enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
+ enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
+ enum pmux_pin_io io; /* input or output PMUX_PIN_... */
+ enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
+ enum pmux_pin_od od; /* open-drain or push-pull driver */
+ enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
+};
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the complete configuration for a pin group */
+void pinmux_config_pingroup(struct pingroup_config *config);
+
+/* Set a pin group to tristate or normal */
+void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
+
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void pinmux_config_table(struct pingroup_config *config, int len);
+
+/* Set a group of pins from a table */
+void pinmux_init(void);
+
+#endif /* _TEGRA30_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pmu.h b/arch/arm/include/asm/arch-tegra30/pmu.h
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_PMU_H_
+#define _TEGRA30_PMU_H_
+
+/* Set core and CPU voltages to nominal levels */
+int pmu_set_nominal(void);
+
+#endif /* _TEGRA30_PMU_H_ */
similarity index 63%
rename from board/eNET/hardware.h
rename to arch/arm/include/asm/arch-tegra30/spl.h
index dec2cd8040683d673bae05b72de149be8ada5e19..5e453c5cc7c4381951ec2498b0ece6840d86f898 100644 (file)
rename from board/eNET/hardware.h
rename to arch/arm/include/asm/arch-tegra30/spl.h
index dec2cd8040683d673bae05b72de149be8ada5e19..5e453c5cc7c4381951ec2498b0ece6840d86f898 100644 (file)
--- a/board/eNET/hardware.h
/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
+ * (C) Copyright 2012
+ * NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_ARCH_SPL_H_
-#ifndef HARDWARE_H_
-#define HARDWARE_H_
+#define BOOT_DEVICE_RAM 1
-#define LED_LATCH_ADDRESS 0x1002
-#define LED_RUN_BITMASK 0x01
-#define LED_1_BITMASK 0x02
-#define LED_2_BITMASK 0x04
-#define LED_RX_BITMASK 0x08
-#define LED_TX_BITMASK 0x10
-#define LED_ERR_BITMASK 0x20
-#define WATCHDOG_PIO_BIT 0x8000
-
-#endif /* HARDWARE_H_ */
+#endif
diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA30_H_
+#define _TEGRA30_H_
+
+#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
+
+#include <asm/arch-tegra/tegra.h>
+
+#define BCT_ODMDATA_OFFSET 6116 /* 12 bytes from end of BCT */
+
+#define MAX_NUM_CPU 4
+
+#endif /* TEGRA30_H */
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
--- /dev/null
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2013 Xilinx Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
+#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
+#define XPSS_SCU_BASEADDR 0xF8F00000
+
+/* Reflect slcr offsets */
+struct slcr_regs {
+ u32 scl; /* 0x0 */
+ u32 slcr_lock; /* 0x4 */
+ u32 slcr_unlock; /* 0x8 */
+ u32 reserved1[125];
+ u32 pss_rst_ctrl; /* 0x200 */
+ u32 reserved2[15];
+ u32 fpga_rst_ctrl; /* 0x240 */
+ u32 reserved3[5];
+ u32 reboot_status; /* 0x258 */
+ u32 boot_mode; /* 0x25c */
+ u32 reserved4[116];
+ u32 trust_zone; /* 0x430 */ /* FIXME */
+ u32 reserved5[115];
+ u32 ddr_urgent; /* 0x600 */
+ u32 reserved6[6];
+ u32 ddr_urgent_sel; /* 0x61c */
+ u32 reserved7[188];
+ u32 ocm_cfg; /* 0x910 */
+};
+
+#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
+
+struct devcfg_regs {
+ u32 ctrl; /* 0x0 */
+ u32 lock; /* 0x4 */
+ u32 cfg; /* 0x8 */
+ u32 int_sts; /* 0xc */
+ u32 int_mask; /* 0x10 */
+ u32 status; /* 0x14 */
+ u32 dma_src_addr; /* 0x18 */
+ u32 dma_dst_addr; /* 0x1c */
+ u32 dma_src_len; /* 0x20 */
+ u32 dma_dst_len; /* 0x24 */
+ u32 rom_shadow; /* 0x28 */
+ u32 reserved1[2];
+ u32 unlock; /* 0x34 */
+ u32 reserved2[18];
+ u32 mctrl; /* 0x80 */
+ u32 reserved3;
+ u32 write_count; /* 0x88 */
+ u32 read_count; /* 0x8c */
+};
+
+#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
+
+struct scu_regs {
+ u32 reserved1[16];
+ u32 filter_start; /* 0x40 */
+ u32 filter_end; /* 0x44 */
+};
+
+#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
+
+#endif /* _ASM_ARCH_HARDWARE_H */
similarity index 71%
rename from board/eNET/eNET_start.S
rename to arch/arm/include/asm/arch-zynq/sys_proto.h
index 0dec7ea09bf940b6d246d3a7bc6237fcae249546..e78890011a8421be7ccdaad03a831e1e4572d694 100644 (file)
rename from board/eNET/eNET_start.S
rename to arch/arm/include/asm/arch-zynq/sys_proto.h
index 0dec7ea09bf940b6d246d3a7bc6237fcae249546..e78890011a8421be7ccdaad03a831e1e4572d694 100644 (file)
--- a/board/eNET/eNET_start.S
/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
+ * Copyright (c) 2013 Xilinx Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#include "hardware.h"
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
-/* board early intialization */
-.globl early_board_init
-early_board_init:
- /* No 32-bit board specific initialisation */
- jmp early_board_init_ret
+extern void zynq_slcr_lock(void);
+extern void zynq_slcr_unlock(void);
+extern void zynq_slcr_cpu_reset(void);
+
+#endif /* _SYS_PROTO_H_ */
index 41a26edfb54d597d905d591a565053f8b70b0966..37ac0daa70b05c1aedfcaf6a6251117e28ab6ead 100644 (file)
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory which is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
-#endif
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- unsigned long fb_base; /* base address of frame buffer */
-#ifdef CONFIG_FSL_ESDHC
- unsigned long sdhc_clk;
+/* Architecture-specific global data */
+struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC)
+ u32 sdhc_clk;
#endif
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long pllb_rate_hz;
unsigned long at91_pllb_usb_init;
#endif
-#ifdef CONFIG_ARM
/* "static data" needed by most of timer.c on ARM platforms */
- unsigned long timer_rate_hz;
- unsigned long tbl;
- unsigned long tbu;
- unsigned long long timer_reset_value;
- unsigned long lastinc;
-#endif
+ unsigned long timer_rate_hz;
+ unsigned long tbu;
+ unsigned long tbl;
+ unsigned long lastinc;
+ unsigned long long timer_reset_value;
#ifdef CONFIG_IXP425
- unsigned long timestamp;
+ unsigned long timestamp;
#endif
- unsigned long relocaddr; /* Start address of U-Boot in RAM */
- phys_size_t ram_size; /* RAM size */
- unsigned long mon_len; /* monitor len */
- unsigned long irq_sp; /* irq stack pointer */
- unsigned long start_addr_sp; /* start_addr_stackpointer */
- unsigned long reloc_off;
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- unsigned long tlb_addr;
- unsigned long tlb_size;
-#endif
- const void *fdt_blob; /* Our device tree, NULL if none */
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
- unsigned long post_log_word; /* Record POST activities */
- unsigned long post_log_res; /* success of POST test */
- unsigned long post_init_f_time; /* When post_init_f started */
+ unsigned long tlb_addr;
+ unsigned long tlb_size;
#endif
-} gd_t;
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8")
index 78ca8e0a6dc10741469753edff8d73cc96b61d29..1918492eaed7e6f19845a283d78ab6341446b038 100644 (file)
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
+#ifdef __ARM_ARCH_7A__
+#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
+#else
+#define wfi()
+#endif
+
static inline unsigned int get_cr(void)
{
unsigned int val;
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index cfe32cc926d502e470d23ec092f827e29c91cf0f..162e2cc86385df0f7489eef0ae2ac00c3be12fc9 100644 (file)
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
/* reserve TLB table */
- gd->tlb_size = 4096 * 4;
- addr -= gd->tlb_size;
+ gd->arch.tlb_size = 4096 * 4;
+ addr -= gd->arch.tlb_size;
/* round down to next 64 kB limit */
addr &= ~(0x10000 - 1);
- gd->tlb_addr = addr;
- debug("TLB table from %08lx to %08lx\n", addr, addr + gd->tlb_size);
+ gd->arch.tlb_addr = addr;
+ debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);
#endif
/* round down to next 4 kB limit */
static int should_load_env(void)
{
#ifdef CONFIG_OF_CONTROL
- return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 0);
+ return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
#elif defined CONFIG_DELAY_ENVIRONMENT
return 0;
#else
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 1bd273085685ba9c4d424e7ac761a6b8bde5828d..f3b30c57a37cd03b0c368dcd73aff49fc0b29478 100644 (file)
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
-#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/bootm.h>
index 1cab27c22629fe5bd034d8278efa8d09e36f7378..b6e5e95530b3793f0be70289eb53ed7207cb305b 100644 (file)
void set_section_dcache(int section, enum dcache_option option)
{
- u32 *page_table = (u32 *)gd->tlb_addr;
+ u32 *page_table = (u32 *)gd->arch.tlb_addr;
u32 value;
value = (section << MMU_SECTION_SHIFT) | (3 << 10);
void mmu_set_region_dcache_behaviour(u32 start, int size,
enum dcache_option option)
{
- u32 *page_table = (u32 *)gd->tlb_addr;
+ u32 *page_table = (u32 *)gd->arch.tlb_addr;
u32 upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"
- : : "r" (gd->tlb_addr) : "memory");
+ : : "r" (gd->arch.tlb_addr) : "memory");
/* Set the access control to all-supervisor */
asm volatile("mcr p15, 0, %0, c3, c0, 0"
: : "r" (~0));
diff --git a/arch/avr32/cpu/cpu.c b/arch/avr32/cpu/cpu.c
index 790783767f12a4430c1a1707e17620095ad4850a..9d82ca4ad231bce6a22c905b4c58206834959a5c 100644 (file)
--- a/arch/avr32/cpu/cpu.c
+++ b/arch/avr32/cpu/cpu.c
{
extern void _evba(void);
- gd->cpu_hz = CONFIG_SYS_OSC0_HZ;
+ gd->arch.cpu_hz = CONFIG_SYS_OSC0_HZ;
/* TODO: Move somewhere else, but needs to be run before we
* increase the clock frequency. */
clk_init();
/* Update the CPU speed according to the PLL configuration */
- gd->cpu_hz = get_cpu_clk_rate();
+ gd->arch.cpu_hz = get_cpu_clk_rate();
/* Set up the exception handler table and enable exceptions */
sysreg_write(EVBA, (unsigned long)&_evba);
index b21ef1f928daaf891d8d749ee158b44fd33bb359..828fc00a49d3b5af488e9cd20ce709c39f4bef03 100644 (file)
printf("CPU Mode: %s\n", cpu_modes[mode]);
/* Avoid exception loops */
- if (regs->sp < (gd->stack_end - CONFIG_STACKSIZE)
- || regs->sp >= gd->stack_end)
+ if (regs->sp < (gd->arch.stack_end - CONFIG_STACKSIZE)
+ || regs->sp >= gd->arch.stack_end)
printf("\nStack pointer seems bogus, won't do stack dump\n");
else
- dump_mem("\nStack: ", regs->sp, gd->stack_end);
+ dump_mem("\nStack: ", regs->sp, gd->arch.stack_end);
panic("Unhandled exception\n");
}
index 49a00f1c8ca7e4b6e57edb32844dc1f348c0dac1..d87c6e11665daa9ffe0a486a03ec769e7ff77f38 100644 (file)
unsigned long get_tbclk(void)
{
- return gd->cpu_hz;
+ return gd->arch.cpu_hz;
}
unsigned long long get_ticks(void)
sysreg_write(COUNT, 0);
tmp = (u64)CONFIG_SYS_HZ << 32;
- tmp += gd->cpu_hz / 2;
- do_div(tmp, gd->cpu_hz);
+ tmp += gd->arch.cpu_hz / 2;
+ do_div(tmp, gd->arch.cpu_hz);
tb_factor = (u32)tmp;
if (set_interrupt_handler(0, &timer_interrupt_handler, 3))
index bf661e23be93d9384f03618aa34e1e3c1a279504..a71f199b750f45f1ba4025d8a9c9838f094bbc1f 100644 (file)
#ifndef __ASM_GLOBAL_DATA_H__
#define __ASM_GLOBAL_DATA_H__
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long stack_end; /* highest stack address */
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
-#endif
- unsigned long reloc_off; /* Relocation Offset */
- unsigned long env_addr; /* Address of env struct */
- unsigned long env_valid; /* Checksum of env valid? */
- unsigned long cpu_hz; /* cpu core clock frequency */
-#if defined(CONFIG_LCD)
- void *fb_base; /* framebuffer address */
-#endif
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+ unsigned long stack_end; /* highest stack address */
+ unsigned long cpu_hz; /* cpu core clock frequency */
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5")
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index e3287c486b1b985d462e1085b20cb09b8db781b7..d3c8cb76dde081661ad0916641da1cd5fc6d363a 100644 (file)
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
/* And finally, a new, bigger stack. */
new_sp = (unsigned long *)addr;
- gd->stack_end = addr;
+ gd->arch.stack_end = addr;
*(--new_sp) = 0;
*(--new_sp) = 0;
diff --git a/arch/avr32/lib/bootm.c b/arch/avr32/lib/bootm.c
index 74ebeca058a7ed3f3a268a95cd0625f4da9388cd..87f3f9c35d3b966c5366351c60d06ebc1b72c825 100644 (file)
--- a/arch/avr32/lib/bootm.c
+++ b/arch/avr32/lib/bootm.c
params->hdr.size = tag_size(tag_clock);
params->u.clock.clock_id = ACLOCK_BOOTCPU;
params->u.clock.clock_flags = 0;
- params->u.clock.clock_hz = gd->cpu_hz;
+ params->u.clock.clock_hz = gd->arch.cpu_hz;
#ifdef CONFIG_AT32AP7000
/*
index d91e5a40d314f2dd96b8cf28739bf798e7a7a30b..c2c4d4d41dfd7d699e5f1a3c7e8789ef6c30bec8 100644 (file)
#include <asm/u-boot.h>
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned long board_type;
- unsigned int baudrate;
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
-#endif
- phys_size_t ram_size; /* RAM size */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
- unsigned long post_log_word; /* Record POST activities */
- unsigned long post_log_res; /* success of POST test */
- unsigned long post_init_f_time; /* When post_init_f started */
-#endif
-
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P3")
index 3a0ab9746b457215b6bcab033993e3a4d7e61ba9..705bd4428cb7be5366522d7618727caadc6e58b3 100644 (file)
printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
strmhz(buf1, gd->cpu_clk),
strmhz(buf2, gd->bus_clk),
- strmhz(buf3, gd->flb_clk));
+ strmhz(buf3, gd->arch.flb_clk));
printf(" INP CLK %s MHz VCO CLK %s MHz\n",
- strmhz(buf1, gd->inp_clk),
- strmhz(buf2, gd->vco_clk));
+ strmhz(buf1, gd->arch.inp_clk),
+ strmhz(buf2, gd->arch.vco_clk));
}
return 0;
index b94a9eda48266e30e6d4bab3bcb9a81bd589ac27..98f554aa7f5099d409271b18cac05deec43dc361 100644 (file)
((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
CONFIG_SYS_INPUT_CLKSRC;
}
- gd->vco_clk = vco; /* Vco clock */
+ gd->arch.vco_clk = vco; /* Vco clock */
} else if (bootmode == 3) {
/* serial mode */
vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
- gd->vco_clk = vco; /* Vco clock */
+ gd->arch.vco_clk = vco; /* Vco clock */
}
if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
- gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
+ gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
- gd->flb_clk = vco / temp; /* flexbus clock */
- gd->bus_clk = gd->flb_clk;
+ gd->arch.flb_clk = vco / temp; /* flexbus clock */
+ gd->bus_clk = gd->arch.flb_clk;
}
#ifdef CONFIG_FSL_I2C
- gd->i2c1_clk = gd->bus_clk;
+ gd->arch.i2c1_clk = gd->bus_clk;
#endif
return (0);
index e2a6ae3a58fd5a9a0ce96b5afaba8a07aa490ad6..ae462579e27d61d147d9d18eb6995794b817a721 100644 (file)
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_FSL_I2C
- gd->i2c1_clk = gd->bus_clk;
+ gd->arch.i2c1_clk = gd->bus_clk;
#endif
return (0);
index 70abed25c4171fa4f7eae52bfed05eb007a39d1a..ba7dbaa1cfc34a1cd4bb3dad218d1deec893e6e2 100644 (file)
#endif
#ifdef CONFIG_FSL_I2C
- gd->i2c1_clk = gd->bus_clk;
+ gd->arch.i2c1_clk = gd->bus_clk;
#ifdef CONFIG_SYS_I2C2_OFFSET
- gd->i2c2_clk = gd->bus_clk;
+ gd->arch.i2c2_clk = gd->bus_clk;
#endif
#endif
index cfdcc8b80770d1062d3282e4334531ab2d40886d..8efb451dc133b8659873cc84d3f4b7324e90eec9 100644 (file)
gd->cpu_clk = (gd->bus_clk * 3);
#ifdef CONFIG_FSL_I2C
- gd->i2c1_clk = gd->bus_clk;
+ gd->arch.i2c1_clk = gd->bus_clk;
#endif
return (0);
index b612cdaea1ac28975184fbb090c79c40f69d7ab6..08930f48d7be4d0dc8605a4b962cfb4471cc7fab 100644 (file)
printf(" CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
strmhz(buf1, gd->cpu_clk),
strmhz(buf2, gd->bus_clk),
- strmhz(buf3, gd->flb_clk));
+ strmhz(buf3, gd->arch.flb_clk));
#ifdef CONFIG_PCI
printf(" PCI CLK %s MHz INP CLK %s MHz VCO CLK %s MHz\n",
strmhz(buf1, gd->pci_clk),
- strmhz(buf2, gd->inp_clk),
- strmhz(buf3, gd->vco_clk));
+ strmhz(buf2, gd->arch.inp_clk),
+ strmhz(buf3, gd->arch.vco_clk));
#else
printf(" INP CLK %s MHz VCO CLK %s MHz\n",
- strmhz(buf1, gd->inp_clk),
- strmhz(buf2, gd->vco_clk));
+ strmhz(buf1, gd->arch.inp_clk),
+ strmhz(buf2, gd->arch.vco_clk));
#endif
}
index 55d1c488a317f5e11e803fb2a2a2f7901062c93d..aa73e1f0252e33f1b9b9d95b7cf0e35fb06f15b7 100644 (file)
out_be32(&pll->pcr, pcrvalue);
}
- gd->vco_clk = vco; /* Vco clock */
+ gd->arch.vco_clk = vco; /* Vco clock */
} else if (bootmode == 2) {
/* Normal mode */
vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
out_be32(&pll->pcr, pcrvalue);
vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
}
- gd->vco_clk = vco; /* Vco clock */
+ gd->arch.vco_clk = vco; /* Vco clock */
} else if (bootmode == 3) {
/* serial mode */
vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
- gd->vco_clk = vco; /* Vco clock */
+ gd->arch.vco_clk = vco; /* Vco clock */
}
if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */
} else {
- gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
+ gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
gd->cpu_clk = vco / temp; /* cpu clock */
gd->bus_clk = vco / temp; /* bus clock */
temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
- gd->flb_clk = vco / temp; /* FlexBus clock */
+ gd->arch.flb_clk = vco / temp; /* FlexBus clock */
#ifdef CONFIG_PCI
if (bPci) {
}
#ifdef CONFIG_FSL_I2C
- gd->i2c1_clk = gd->bus_clk;
+ gd->arch.i2c1_clk = gd->bus_clk;
#endif
}
#endif
#endif
#ifdef CONFIG_FSL_I2C
- gd->i2c1_clk = gd->bus_clk;
+ gd->arch.i2c1_clk = gd->bus_clk;
#endif
return (0);
index 31130b54115203dfc262aafba2948ed8275934a3..41aae9d9eb27c51ed3da1629683a8df2a6e89868 100644 (file)
gd->cpu_clk = (gd->bus_clk * 2);
#ifdef CONFIG_FSL_I2C
- gd->i2c1_clk = gd->bus_clk;
+ gd->arch.i2c1_clk = gd->bus_clk;
#endif
return (0);
index 0cdb11cf99eeccce75df5d9482c3e4a066a4b3af..3ec298ff4a2be56d41cee406abfc7273d16c4fd6 100644 (file)
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long cpu_clk; /* CPU clock in Hz! */
- unsigned long bus_clk;
-#ifdef CONFIG_PCI
- unsigned long pci_clk;
-#endif
-#ifdef CONFIG_EXTRA_CLOCK
- unsigned long inp_clk;
- unsigned long vco_clk;
- unsigned long flb_clk;
-#endif
+/* Architecture-specific global data */
+struct arch_global_data {
#ifdef CONFIG_FSL_I2C
unsigned long i2c1_clk;
unsigned long i2c2_clk;
#endif
- phys_size_t ram_size; /* RAM size */
- unsigned long reloc_off; /* Relocation Offset */
- unsigned long reset_status; /* reset status register at boot */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
-#endif
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
- unsigned long fb_base; /* Base addr of framebuffer memory */
-#endif
-#ifdef CONFIG_BOARD_TYPES
- unsigned long board_type;
+#ifdef CONFIG_EXTRA_CLOCK
+ unsigned long inp_clk;
+ unsigned long vco_clk;
+ unsigned long flb_clk;
#endif
- void **jt; /* Standalone app jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#if 0
extern gd_t *global_data;
diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c
index e934cb6c25f5d49eebcb50b8535d1e74ae6f7e92..c372ae228b5572c2208daa6a07973ffc48c73e9d 100644 (file)
--- a/arch/m68k/lib/board.c
+++ b/arch/m68k/lib/board.c
bd->bi_pcifreq = gd->pci_clk; /* PCI Freq in Hz */
#endif
#ifdef CONFIG_EXTRA_CLOCK
- bd->bi_inpfreq = gd->inp_clk; /* input Freq in Hz */
- bd->bi_vcofreq = gd->vco_clk; /* vco Freq in Hz */
- bd->bi_flbfreq = gd->flb_clk; /* flexbus Freq in Hz */
+ bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
+ bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
+ bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
#endif
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
index 2111c7cba27fb7a1e3e65e82c1e8cd7091f774aa..89dcef7c7e7d7b3149308194fa75591985b56e53 100644 (file)
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
-#endif
- unsigned long env_addr; /* Address of Environment struct */
- const void *fdt_blob; /* Our device tree, NULL if none */
- unsigned long env_valid; /* Checksum of Environment valid? */
- unsigned long fb_base; /* base address of frame buffer */
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31")
index 7730695be4d725322cf870a17cd853127b5c54c3..8d7febd47826a3ff3b78f9e00f8170e77ec87e12 100644 (file)
COBJS-y += board.o
COBJS-y += bootm.o
+COBJS-y += muldi3.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/microblaze/lib/muldi3.c b/arch/microblaze/lib/muldi3.c
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * U-boot - muldi3.c contains routines for mult and div
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Generic function got from GNU gcc package, libgcc2.c */
+#ifndef SI_TYPE_SIZE
+#define SI_TYPE_SIZE 32
+#endif
+#define __ll_B (1L << (SI_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
+#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+#define BITS_PER_UNIT 8
+
+#if !defined(umul_ppmm)
+#define umul_ppmm(w1, w0, u, v) \
+ do { \
+ USItype __x0, __x1, __x2, __x3; \
+ USItype __ul, __vl, __uh, __vh; \
+ \
+ __ul = __ll_lowpart(u); \
+ __uh = __ll_highpart(u); \
+ __vl = __ll_lowpart(v); \
+ __vh = __ll_highpart(v); \
+ \
+ __x0 = (USItype) __ul * __vl; \
+ __x1 = (USItype) __ul * __vh; \
+ __x2 = (USItype) __uh * __vl; \
+ __x3 = (USItype) __uh * __vh; \
+ \
+ __x1 += __ll_highpart(__x0); /* this can't give carry */\
+ __x1 += __x2; /* but this indeed can */ \
+ if (__x1 < __x2) /* did we get it? */ \
+ __x3 += __ll_B; /* yes, add it in the proper pos. */ \
+ \
+ (w1) = __x3 + __ll_highpart(__x1); \
+ (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0);\
+ } while (0)
+#endif
+
+#if !defined(__umulsidi3)
+#define __umulsidi3(u, v) \
+ ({DIunion __w; \
+ umul_ppmm(__w.s.high, __w.s.low, u, v); \
+ __w.ll; })
+#endif
+
+typedef unsigned int USItype __attribute__ ((mode(SI)));
+typedef int SItype __attribute__ ((mode(SI)));
+typedef int DItype __attribute__ ((mode(DI)));
+typedef int word_type __attribute__ ((mode(__word__)));
+
+struct DIstruct {
+ SItype low, high;
+};
+typedef union {
+ struct DIstruct s;
+ DItype ll;
+} DIunion;
+
+DItype __muldi3(DItype u, DItype v)
+{
+ DIunion w;
+ DIunion uu, vv;
+
+ uu.ll = u, vv.ll = v;
+ /* panic("kernel panic for __muldi3"); */
+ w.ll = __umulsidi3(uu.s.low, vv.s.low);
+ w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+ + (USItype) uu.s.high * (USItype) vv.s.low);
+
+ return w.ll;
+}
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index de9140b67b5258b9a4511bc0dbbdd913c00c525a..aaa94e8be203f7e1c0a1da17a240f0b7decc20cd 100644 (file)
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
PLATFORM_CPPFLAGS += -msoft-float
PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-LDFLAGS_FINAL += --gc-sections
+LDFLAGS_FINAL += --gc-sections -pie
+OBJCFLAGS += --remove-section=.dynsym
index 481e9844db232474da43344bac63b6f226924a97..7399701fe9656d9ef5e7e49d99f1d7974030ee11 100644 (file)
MIPSFLAGS := -march=mips32r2
PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS += -m elf32btsmip
+else
+PLATFORM_LDFLAGS += -m elf32ltsmip
+endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
index 9c1b2f76d09bcff61c4d617da0795b7f35b9085c..76abbaa27368d5b14ebea23aeccd00d63004de52 100644 (file)
.set pop
.endm
- .macro setup_c0_status_reset
-#ifdef CONFIG_64BIT
- setup_c0_status ST0_KX 0
-#else
- setup_c0_status 0 0
-#endif
- .endm
-
-#define RVECENT(f,n) \
- b f; nop
-#define XVECENT(f,bev) \
- b f ; \
- li k0,bev
-
.set noreorder
.globl _start
.text
_start:
- RVECENT(reset,0) # U-boot entry point
- RVECENT(reset,1) # software reboot
+ /* U-boot entry point */
+ b reset
+ nop
+
+ .org 0x10
#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
/*
* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
* device with correct parameters. This config option is board-specific.
*/
.word CONFIG_SYS_XWAY_EBU_BOOTCFG
- .word 0x00000000
-#else
- RVECENT(romReserved,2)
+ .word 0x0
#endif
- RVECENT(romReserved,3)
- RVECENT(romReserved,4)
- RVECENT(romReserved,5)
- RVECENT(romReserved,6)
- RVECENT(romReserved,7)
- RVECENT(romReserved,8)
- RVECENT(romReserved,9)
- RVECENT(romReserved,10)
- RVECENT(romReserved,11)
- RVECENT(romReserved,12)
- RVECENT(romReserved,13)
- RVECENT(romReserved,14)
- RVECENT(romReserved,15)
- RVECENT(romReserved,16)
- RVECENT(romReserved,17)
- RVECENT(romReserved,18)
- RVECENT(romReserved,19)
- RVECENT(romReserved,20)
- RVECENT(romReserved,21)
- RVECENT(romReserved,22)
- RVECENT(romReserved,23)
- RVECENT(romReserved,24)
- RVECENT(romReserved,25)
- RVECENT(romReserved,26)
- RVECENT(romReserved,27)
- RVECENT(romReserved,28)
- RVECENT(romReserved,29)
- RVECENT(romReserved,30)
- RVECENT(romReserved,31)
- RVECENT(romReserved,32)
- RVECENT(romReserved,33)
- RVECENT(romReserved,34)
- RVECENT(romReserved,35)
- RVECENT(romReserved,36)
- RVECENT(romReserved,37)
- RVECENT(romReserved,38)
- RVECENT(romReserved,39)
- RVECENT(romReserved,40)
- RVECENT(romReserved,41)
- RVECENT(romReserved,42)
- RVECENT(romReserved,43)
- RVECENT(romReserved,44)
- RVECENT(romReserved,45)
- RVECENT(romReserved,46)
- RVECENT(romReserved,47)
- RVECENT(romReserved,48)
- RVECENT(romReserved,49)
- RVECENT(romReserved,50)
- RVECENT(romReserved,51)
- RVECENT(romReserved,52)
- RVECENT(romReserved,53)
- RVECENT(romReserved,54)
- RVECENT(romReserved,55)
- RVECENT(romReserved,56)
- RVECENT(romReserved,57)
- RVECENT(romReserved,58)
- RVECENT(romReserved,59)
- RVECENT(romReserved,60)
- RVECENT(romReserved,61)
- RVECENT(romReserved,62)
- RVECENT(romReserved,63)
- XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector
- RVECENT(romReserved,65)
- RVECENT(romReserved,66)
- RVECENT(romReserved,67)
- RVECENT(romReserved,68)
- RVECENT(romReserved,69)
- RVECENT(romReserved,70)
- RVECENT(romReserved,71)
- RVECENT(romReserved,72)
- RVECENT(romReserved,73)
- RVECENT(romReserved,74)
- RVECENT(romReserved,75)
- RVECENT(romReserved,76)
- RVECENT(romReserved,77)
- RVECENT(romReserved,78)
- RVECENT(romReserved,79)
- XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector
- RVECENT(romReserved,81)
- RVECENT(romReserved,82)
- RVECENT(romReserved,83)
- RVECENT(romReserved,84)
- RVECENT(romReserved,85)
- RVECENT(romReserved,86)
- RVECENT(romReserved,87)
- RVECENT(romReserved,88)
- RVECENT(romReserved,89)
- RVECENT(romReserved,90)
- RVECENT(romReserved,91)
- RVECENT(romReserved,92)
- RVECENT(romReserved,93)
- RVECENT(romReserved,94)
- RVECENT(romReserved,95)
- XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector
- RVECENT(romReserved,97)
- RVECENT(romReserved,98)
- RVECENT(romReserved,99)
- RVECENT(romReserved,100)
- RVECENT(romReserved,101)
- RVECENT(romReserved,102)
- RVECENT(romReserved,103)
- RVECENT(romReserved,104)
- RVECENT(romReserved,105)
- RVECENT(romReserved,106)
- RVECENT(romReserved,107)
- RVECENT(romReserved,108)
- RVECENT(romReserved,109)
- RVECENT(romReserved,110)
- RVECENT(romReserved,111)
- XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector
- RVECENT(romReserved,113)
- RVECENT(romReserved,114)
- RVECENT(romReserved,115)
- RVECENT(romReserved,116)
- RVECENT(romReserved,116)
- RVECENT(romReserved,118)
- RVECENT(romReserved,119)
- RVECENT(romReserved,120)
- RVECENT(romReserved,121)
- RVECENT(romReserved,122)
- RVECENT(romReserved,123)
- RVECENT(romReserved,124)
- RVECENT(romReserved,125)
- RVECENT(romReserved,126)
- RVECENT(romReserved,127)
- /*
- * We hope there are no more reserved vectors!
- * 128 * 8 == 1024 == 0x400
- * so this is address R_VEC+0x400 == 0xbfc00400
- */
+ .org 0x200
+ /* TLB refill, 32 bit task */
+1: b 1b
+ nop
+
+ .org 0x280
+ /* XTLB refill, 64 bit task */
+1: b 1b
+ nop
+
+ .org 0x300
+ /* Cache error exception */
+1: b 1b
+ nop
+
+ .org 0x380
+ /* General exception */
+1: b 1b
+ nop
+
+ .org 0x400
+ /* Catch interrupt exceptions */
+1: b 1b
+ nop
+
+ .org 0x480
+ /* EJTAG debug exception */
+1: b 1b
+ nop
+
.align 4
reset:
/* WP(Watch Pending), SW0/1 should be cleared */
mtc0 zero, CP0_CAUSE
- setup_c0_status_reset
+ setup_c0_status 0 0
/* Init Timer */
mtc0 zero, CP0_COUNT
#endif
/* Set up temporary stack */
- li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
- la sp, 0(t0)
+ li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
la t9, board_init_f
jr t9
relocate_code:
move sp, a0 # set new stack pointer
+ move s0, a1 # save gd in s0
+ move s2, a2 # save destination address in s2
+
li t0, CONFIG_SYS_MONITOR_BASE
+ sub s1, s2, t0 # s1 <-- relocation offset
+
la t3, in_ram
- lw t2, -12(t3) # t2 <-- uboot_end_data
+ lw t2, -12(t3) # t2 <-- __image_copy_end
move t1, a2
- move s2, a2 # s2 <-- destination address
- /*
- * Fix $gp:
- *
- * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
- */
- move t6, gp
- sub gp, CONFIG_SYS_MONITOR_BASE
- add gp, a2 # gp now adjusted
- sub s1, gp, t6 # s1 <-- relocation offset
+ add gp, s1 # adjust gp
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
-
- /*
- * Save destination address and size for later usage in flush_cache()
- */
- move s0, a1 # save gd in s0
- move a0, t1 # a0 <-- destination addr
- sub a1, t2, t0 # a1 <-- size
-
1:
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
- ble t0, t2, 1b
+ blt t0, t2, 1b
addu t1, 4
/* If caches were enabled, we would have to flush them here. */
-
- /* a0 & a1 are already set up for flush_cache(start, size) */
+ sub a1, t1, s2 # a1 <-- size
la t9, flush_cache
jalr t9
- nop
+ move a0, s2 # a0 <-- destination address
/* Jump to where we've relocated ourselves */
addi t0, s2, in_ram - _start
jr t0
nop
- .word _gp
+ .word __rel_dyn_end
+ .word __rel_dyn_start
+ .word __image_copy_end
.word _GLOBAL_OFFSET_TABLE_
- .word uboot_end_data
- .word uboot_end
.word num_got_entries
in_ram:
* generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) # t3 <-- num_got_entries
- lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
- lw t5, -20(t0) # t5 <-- _gp
- sub t4, t5 # compute offset
- add t4, t4, gp # t4 now holds relocated _G_O_T_
+ lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
+ add t4, s1 # t4 now holds relocated _G_O_T_
addi t4, t4, 8 # skipping first two entries
li t2, 2
1:
blt t2, t3, 1b
addi t4, 4
- /* Clear BSS */
- lw t1, -12(t0) # t1 <-- uboot_end_data
- lw t2, -8(t0) # t2 <-- uboot_end
- add t1, s1 # adjust pointers
- add t2, s1
+ /* Update dynamic relocations */
+ lw t1, -16(t0) # t1 <-- __rel_dyn_start
+ lw t2, -20(t0) # t2 <-- __rel_dyn_end
+
+ b 2f # skip first reserved entry
+ addi t1, 8
+
+1:
+ lw t3, -4(t1) # t3 <-- relocation info
+
+ sub t3, 3
+ bnez t3, 2f # skip non R_MIPS_REL32 entries
+ nop
+
+ lw t3, -8(t1) # t3 <-- location to fix up in FLASH
+
+ lw t4, 0(t3) # t4 <-- original pointer
+ add t4, s1 # t4 <-- adjusted pointer
+
+ add t3, s1 # t3 <-- location to fix up in RAM
+ sw t4, 0(t3)
+
+2:
+ blt t1, t2, 1b
+ addi t1, 8 # each rel.dyn entry is 8 bytes
+
+ /*
+ * Clear BSS
+ *
+ * GOT is now relocated. Thus __bss_start and __bss_end can be
+ * accessed directly via $gp.
+ */
+ la t1, __bss_start # t1 <-- __bss_start
+ la t2, __bss_end # t2 <-- __bss_end
- sub t1, 4
1:
- addi t1, 4
- bltl t1, t2, 1b
- sw zero, 0(t1)
+ sw zero, 0(t1)
+ blt t1, t2, 1b
+ addi t1, 4
move a0, s0 # a0 <-- gd
la t9, board_init_r
move a1, s2
.end relocate_code
-
- /* Exception handlers */
-romReserved:
- b romReserved
-
-romExcHandle:
- b romExcHandle
index 2b8d531e73b84ef9d2e0280165ed1668dad9d318..dc7ce07ce78c8e416e8a7d359ef724c46592c517 100644 (file)
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
+#ifdef CONFIG_SYS_LITTLE_ENDIAN
+#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
+ (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
+#else
+#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
+ ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
+#endif
+
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
.globl _start
.text
_start:
- .org 0x000
+ /* U-boot entry point */
b reset
nop
- .org 0x080
- b romReserved
- nop
- .org 0x100
- b romReserved
- nop
- .org 0x180
- b romReserved
- nop
+
.org 0x200
- b romReserved
+ /* TLB refill, 32 bit task */
+1: b 1b
nop
+
.org 0x280
- b romReserved
+ /* XTLB refill, 64 bit task */
+1: b 1b
nop
+
.org 0x300
- b romReserved
+ /* Cache error exception */
+1: b 1b
nop
+
.org 0x380
- b romReserved
+ /* General exception */
+1: b 1b
+ nop
+
+ .org 0x400
+ /* Catch interrupt exceptions */
+1: b 1b
nop
+
.org 0x480
- b romReserved
+ /* EJTAG debug exception */
+1: b 1b
nop
- /*
- * We hope there are no more reserved vectors!
- * 128 * 8 == 1024 == 0x400
- * so this is address R_VEC+0x400 == 0xbfc00400
- */
- .org 0x500
.align 4
reset:
#endif
/* Set up temporary stack */
- dli t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
- dla sp, 0(t0)
+ dli sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
dla t9, board_init_f
jr t9
relocate_code:
move sp, a0 # set new stack pointer
+ move s0, a1 # save gd in s0
+ move s2, a2 # save destination address in s2
+
dli t0, CONFIG_SYS_MONITOR_BASE
+ dsub s1, s2, t0 # s1 <-- relocation offset
+
dla t3, in_ram
- ld t2, -24(t3) # t2 <-- uboot_end_data
+ ld t2, -24(t3) # t2 <-- __image_copy_end
move t1, a2
- move s2, a2 # s2 <-- destination address
- /*
- * Fix $gp:
- *
- * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
- */
- move t8, gp
- dsub gp, CONFIG_SYS_MONITOR_BASE
- dadd gp, a2 # gp now adjusted
- dsub s1, gp, t8 # s1 <-- relocation offset
+ dadd gp, s1 # adjust gp
/*
* t0 = source address
* t1 = target address
* t2 = source end address
*/
-
- /*
- * Save destination address and size for dlater usage in flush_cache()
- */
- move s0, a1 # save gd in s0
- move a0, t1 # a0 <-- destination addr
- dsub a1, t2, t0 # a1 <-- size
-
1:
lw t3, 0(t0)
sw t3, 0(t1)
daddu t0, 4
- ble t0, t2, 1b
+ blt t0, t2, 1b
daddu t1, 4
/* If caches were enabled, we would have to flush them here. */
-
- /* a0 & a1 are already set up for flush_cache(start, size) */
+ dsub a1, t1, s2 # a1 <-- size
dla t9, flush_cache
jalr t9
- nop
+ move a0, s2 # a0 <-- destination address
/* Jump to where we've relocated ourselves */
daddi t0, s2, in_ram - _start
jr t0
nop
- .dword _gp
+ .dword __rel_dyn_end
+ .dword __rel_dyn_start
+ .dword __image_copy_end
.dword _GLOBAL_OFFSET_TABLE_
- .dword uboot_end_data
- .dword uboot_end
.dword num_got_entries
in_ram:
* generated by GNU ld. Skip these reserved entries from relocation.
*/
ld t3, -8(t0) # t3 <-- num_got_entries
- ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
- ld t9, -40(t0) # t9 <-- _gp
- dsub t8, t9 # compute offset
- dadd t8, t8, gp # t8 now holds relocated _G_O_T_
+ ld t8, -16(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ dadd t8, s1 # t8 now holds relocated _G_O_T_
daddi t8, t8, 16 # skipping first two entries
dli t2, 2
1:
blt t2, t3, 1b
daddi t8, 8
- /* Clear BSS */
- ld t1, -24(t0) # t1 <-- uboot_end_data
- ld t2, -16(t0) # t2 <-- uboot_end
- dadd t1, s1 # adjust pointers
- dadd t2, s1
+ /* Update dynamic relocations */
+ ld t1, -32(t0) # t1 <-- __rel_dyn_start
+ ld t2, -40(t0) # t2 <-- __rel_dyn_end
+
+ b 2f # skip first reserved entry
+ daddi t1, 16
- dsub t1, 8
1:
- daddi t1, 8
- bltl t1, t2, 1b
- sd zero, 0(t1)
+ lw t8, -4(t1) # t8 <-- relocation info
+
+ dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
+ bne t8, t3, 2f # skip non R_MIPS_REL32 entries
+ nop
+
+ ld t3, -16(t1) # t3 <-- location to fix up in FLASH
+
+ ld t8, 0(t3) # t8 <-- original pointer
+ dadd t8, s1 # t8 <-- adjusted pointer
+
+ dadd t3, s1 # t3 <-- location to fix up in RAM
+ sd t8, 0(t3)
+
+2:
+ blt t1, t2, 1b
+ daddi t1, 16 # each rel.dyn entry is 16 bytes
+
+ /*
+ * Clear BSS
+ *
+ * GOT is now relocated. Thus __bss_start and __bss_end can be
+ * accessed directly via $gp.
+ */
+ dla t1, __bss_start # t1 <-- __bss_start
+ dla t2, __bss_end # t2 <-- __bss_end
+
+1:
+ sd zero, 0(t1)
+ blt t1, t2, 1b
+ daddi t1, 8
move a0, s0 # a0 <-- gd
dla t9, board_init_r
move a1, s2
.end relocate_code
-
- /* Exception handlers */
-romReserved:
- b romReserved
diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds
--- /dev/null
+++ b/arch/mips/cpu/u-boot.lds
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if defined(CONFIG_64BIT)
+#define PTR_COUNT_SHIFT 3
+#else
+#define PTR_COUNT_SHIFT 2
+#endif
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text : {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
+
+ .got : {
+ *(.got)
+ }
+
+ num_got_entries = SIZEOF(.got) >> PTR_COUNT_SHIFT;
+
+ . = ALIGN(4);
+ .sdata : {
+ *(.sdata*)
+ }
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel.dyn)
+ __rel_dyn_end = .;
+ }
+
+ .deadcode : {
+ /*
+ * Workaround for a binutils feature (or bug?).
+ *
+ * The GNU ld from binutils puts the dynamic relocation
+ * entries into the .rel.dyn section. Sometimes it
+ * allocates more dynamic relocation entries than it needs
+ * and the unused slots are set to R_MIPS_NONE entries.
+ *
+ * However the size of the .rel.dyn section in the ELF
+ * section header does not cover the unused entries, so
+ * objcopy removes those during stripping.
+ *
+ * Create a small section here to avoid that.
+ */
+ LONG(0xffffffff);
+ }
+
+ .dynsym : {
+ *(.dynsym)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.sbss.*)
+ *(.bss.*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end = .;
+ }
+
+ /DISCARD/ : {
+ *(.dynbss)
+ *(.dynstr)
+ *(.dynamic)
+ *(.interp)
+ *(.hash)
+ *(.gnu.*)
+ *(.plt)
+ *(.got.plt)
+ *(.rel.plt)
+ }
+}
index 1536746c974b4cf4ae7294e18096b9101a2e5761..cf5fa6ab6bd5b29e2a0d629563d21a77ae12752a 100644 (file)
#
PLATFORM_CPPFLAGS += -march=mips32
+PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS += -m elf32btsmip
+else
+PLATFORM_LDFLAGS += -m elf32ltsmip
+endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds
index c0b9817ab9765d8e73cb8f27d1e273b347b4fb21..b2d8f4d20dcb50e4b3eae53dcf4ed7e2202ce2ce 100644 (file)
pllout = __cpm_get_pllout();
gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
- gd->sys_clk = pllout / div[__cpm_get_hdiv()];
- gd->per_clk = pllout / div[__cpm_get_pdiv()];
+ gd->arch.sys_clk = pllout / div[__cpm_get_hdiv()];
+ gd->arch.per_clk = pllout / div[__cpm_get_pdiv()];
gd->mem_clk = pllout / div[__cpm_get_mdiv()];
- gd->dev_clk = CONFIG_SYS_EXTAL;
+ gd->arch.dev_clk = CONFIG_SYS_EXTAL;
}
void rtc_init(void)
index 3a8280cb0ab850deaf36731e4c705f449a832866..d2c064b0175b0c5368e5a7d183c9192bc6340b8e 100644 (file)
move sp, a0 # set new stack pointer
li t0, CONFIG_SYS_MONITOR_BASE
+ sub t6, a2, t0 # t6 <-- relocation offset
+
la t3, in_ram
- lw t2, -12(t3) # t2 <-- uboot_end_data
+ lw t2, -12(t3) # t2 <-- __image_copy_end
move t1, a2
- /*
- * Fix $gp:
- *
- * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
- */
- move t6, gp
- sub gp, CONFIG_SYS_MONITOR_BASE
- add gp, a2 # gp now adjusted
- sub t6, gp, t6 # t6 <-- relocation offset
+ add gp, t6 # adjust gp
/*
* t0 = source address
lw t3, 0(t0)
sw t3, 0(t1)
addu t0, 4
- ble t0, t2, 1b
+ blt t0, t2, 1b
addu t1, 4
/* If caches were enabled, we would have to flush them here. */
jr t0
nop
- .word _gp
+ .word __rel_dyn_end
+ .word __rel_dyn_start
+ .word __image_copy_end
.word _GLOBAL_OFFSET_TABLE_
- .word uboot_end_data
- .word uboot_end
.word num_got_entries
in_ram:
* generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) # t3 <-- num_got_entries
- lw t4, -16(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
- lw t5, -20(t0) # t5 <-- _gp
- sub t4, t5 # compute offset
- add t4, t4, gp # t4 now holds relocated _G_O_T_
+ lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
+ add t4, t6 # t4 now holds relocated _G_O_T_
addi t4, t4, 8 # skipping first two entries
li t2, 2
1:
blt t2, t3, 1b
addi t4, 4
- /* Clear BSS */
- lw t1, -12(t0) # t1 <-- uboot_end_data
- lw t2, -8(t0) # t2 <-- uboot_end
- add t1, t6 # adjust pointers
- add t2, t6
+ /* Update dynamic relocations */
+ lw t1, -16(t0) # t1 <-- __rel_dyn_start
+ lw t2, -20(t0) # t2 <-- __rel_dyn_end
+
+ b 2f # skip first reserved entry
+ addi t1, 8
+
+1:
+ lw t3, -4(t1) # t3 <-- relocation info
+
+ sub t3, 3
+ bnez t3, 2f # skip non R_MIPS_REL32 entries
+ nop
+
+ lw t3, -8(t1) # t3 <-- location to fix up in FLASH
+
+ lw t4, 0(t3) # t4 <-- original pointer
+ add t4, t6 # t4 <-- adjusted pointer
+
+ add t3, t6 # t3 <-- location to fix up in RAM
+ sw t4, 0(t3)
+
+2:
+ blt t1, t2, 1b
+ addi t1, 8 # each rel.dyn entry is 8 bytes
+
+ /*
+ * Clear BSS
+ *
+ * GOT is now relocated. Thus __bss_start and __bss_end can be
+ * accessed directly via $gp.
+ */
+ la t1, __bss_start # t1 <-- __bss_start
+ la t2, __bss_end # t2 <-- __bss_end
- sub t1, 4
-1: addi t1, 4
- bltl t1, t2, 1b
- sw zero, 0(t1)
+1:
+ sw zero, 0(t1)
+ blt t1, t2, 1b
+ addi t1, 4
move a0, a1 # a0 <-- gd
la t9, board_init_r
index b6b3855ea193a6e7ecd2747da749b2d5058f9704..8c33d3ca3c339266743e53fc9bbf39c812150848 100644 (file)
void reset_timer_masked(void)
{
/* reset time */
- gd->lastinc = readl(&tcu->tcnt0);
- gd->tbl = 0;
+ gd->arch.lastinc = readl(&tcu->tcnt0);
+ gd->arch.tbl = 0;
}
ulong get_timer_masked(void)
{
ulong now = readl(&tcu->tcnt0);
- if (gd->lastinc <= now)
- gd->tbl += now - gd->lastinc; /* normal mode */
+ if (gd->arch.lastinc <= now)
+ gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */
else {
/* we have an overflow ... */
- gd->tbl += TIMER_FDATA + now - gd->lastinc;
+ gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc;
}
- gd->lastinc = now;
+ gd->arch.lastinc = now;
- return gd->tbl;
+ return gd->arch.tbl;
}
void udelay_masked(unsigned long usec)
writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */
- gd->lastinc = 0;
- gd->tbl = 0;
+ gd->arch.lastinc = 0;
+ gd->arch.tbl = 0;
return 0;
}
void set_timer(ulong t)
{
- gd->tbl = t;
+ gd->arch.tbl = t;
}
void __udelay(unsigned long usec)
index 02fbfb3abfea8ae55e4aef175d3e4e525cef5a79..049c44eaf84de0ce67d86afcf0cd016d4bd6c407 100644 (file)
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
-#define CONFIG_NEEDS_MANUAL_RELOC
-
#endif
index a735a8a2c76d0cc3986dc705fd8f2e709d214008..f912428caecaa2b1a0907205c020b72a31ad1370 100644 (file)
#include <asm/regdef.h>
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
+/* Architecture-specific global data */
+struct arch_global_data {
#ifdef CONFIG_JZSOC
/* There are other clocks in the jz4740 */
- unsigned long cpu_clk; /* CPU core clock */
- unsigned long sys_clk; /* System bus clock */
- unsigned long per_clk; /* Peripheral bus clock */
- unsigned long mem_clk; /* Memory bus clock */
- unsigned long dev_clk; /* Device clock */
- /* "static data" needed by most of timer.c */
- unsigned long tbl;
- unsigned long lastinc;
-#endif
- unsigned int baudrate;
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
+ unsigned long per_clk; /* Peripheral bus clock */
+ unsigned long dev_clk; /* Device clock */
+ unsigned long sys_clk;
+ unsigned long tbl;
+ unsigned long lastinc;
#endif
- phys_size_t ram_size; /* RAM size */
- unsigned long reloc_off; /* Relocation Offset */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0")
index 80eab75e153afdfff91beeea87152291edf54426..3864c804c0500b2322fe25fb0ca296f728130fee 100644 (file)
*/
#define __OUT1(s) \
-extern inline void __out##s(unsigned int value, unsigned int port) {
+static inline void __out##s(unsigned int value, unsigned int port) {
#define __OUT2(m) \
__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
@@ -268,7 +268,7 @@ __OUT1(s##c_p) __OUT2(m) : : "r" (__ioswab##w(value)), "ir" (port), "r" (mips_io
SLOW_DOWN_IO; }
#define __IN1(t,s) \
-extern __inline__ t __in##s(unsigned int port) { t _v;
+static inline t __in##s(unsigned int port) { t _v;
/*
* Required nops will be inserted by the assembler
@@ -283,7 +283,7 @@ __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SL
__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return __ioswab##w(_v); }
#define __INS1(s) \
-extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
+static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
#define __INS2(m) \
if (count) \
: "$1");}
#define __OUTS1(s) \
-extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
+static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
#define __OUTS2(m) \
if (count) \
index 6f26dfac56cd90be16687edbf0f64205e35aaa23..a483166a9c992eeca804fa03f3b31f226b2c803c 100644 (file)
* Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de
*/
-extern ulong uboot_end_data;
-extern ulong uboot_end;
+static inline unsigned long bss_start(void)
+{
+ extern ulong __bss_start;
+ return (unsigned long) &__bss_start;
+}
+
+static inline unsigned long bss_end(void)
+{
+ extern ulong __bss_end;
+ return (unsigned long) &__bss_end;
+}
+
+static inline unsigned long image_copy_end(void)
+{
+ extern ulong __image_copy_end;
+ return (unsigned long) &__image_copy_end;
+}
extern int incaip_set_cpuclk(void);
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index d79e1837d9a37c21c07556618a22dc9c60e173e7..f19f198ae98eab8f4069727d94cdc8141eb0c201 100644 (file)
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
gd_t gd_data, *id;
bd_t *bd;
init_fnc_t **init_fnc_ptr;
- ulong addr, addr_sp, len = (ulong)&uboot_end - CONFIG_SYS_MONITOR_BASE;
+ ulong addr, addr_sp, len;
ulong *s;
/* Pointer is writable since we allocated a register for it.
/* Reserve memory for U-Boot code, data & bss
* round down to next 16 kB limit
*/
+ len = bss_end() - CONFIG_SYS_MONITOR_BASE;
addr -= len;
addr &= ~(16 * 1024 - 1);
{
#ifndef CONFIG_SYS_NO_FLASH
ulong size;
-#endif
-#ifndef CONFIG_ENV_IS_NOWHERE
- extern char *env_name_spec;
#endif
bd_t *bd;
gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
- monitor_flash_len = (ulong)&uboot_end_data - dest_addr;
+ monitor_flash_len = image_copy_end() - dest_addr;
serial_initialize();
-#if defined(CONFIG_NEEDS_MANUAL_RELOC)
- /*
- * We have to relocate the command table manually
- */
- fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
- ll_entry_count(cmd_tbl_t, cmd));
-#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
-
- /* there are some other pointer constants we must deal with */
-#ifndef CONFIG_ENV_IS_NOWHERE
- env_name_spec += gd->reloc_off;
-#endif
-
bd = gd->bd;
/* The Malloc area is immediately below the monitor copy in DRAM */
mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN);
- malloc_bin_reloc();
#ifndef CONFIG_SYS_NO_FLASH
/* configure available FLASH banks */
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index 608c1a78db895fd2f9432788712126d2976be3cf..a36154a892c1ea687b5148772d1d384da664712d 100644 (file)
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
static void linux_params_init(ulong start, char *commandline);
static void linux_env_set(char *env_name, char *env_val);
-int do_bootm_linux(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
+static void boot_prep_linux(bootm_headers_t *images)
{
- void (*theKernel) (int, char **, char **, int *);
char *commandline = getenv("bootargs");
char env_buf[12];
char *cp;
- if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
- return 1;
-
- /* find kernel entry point */
- theKernel = (void (*)(int, char **, char **, int *))images->ep;
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
-#ifdef DEBUG
- printf("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong) theKernel);
-#endif
-
linux_params_init(UNCACHED_SDRAM(gd->bd->bi_boot_params), commandline);
#ifdef CONFIG_MEMSIZE_IN_BYTES
cp = getenv("eth1addr");
if (cp)
linux_env_set("eth1addr", cp);
+}
+
+static void boot_jump_linux(bootm_headers_t *images)
+{
+ void (*theKernel) (int, char **, char **, int *);
+
+ /* find kernel entry point */
+ theKernel = (void (*)(int, char **, char **, int *))images->ep;
+
+ debug("## Transferring control to Linux (at address %08lx) ...\n",
+ (ulong) theKernel);
+
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
/* we assume that the kernel is in place */
printf("\nStarting kernel ...\n\n");
theKernel(linux_argc, linux_argv, linux_env, 0);
+}
+
+int do_bootm_linux(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ /* No need for those on MIPS */
+ if (flag & BOOTM_STATE_OS_BD_T || flag & BOOTM_STATE_OS_CMDLINE)
+ return -1;
+
+ if (flag & BOOTM_STATE_OS_PREP) {
+ boot_prep_linux(images);
+ return 0;
+ }
+
+ if (flag & BOOTM_STATE_OS_GO) {
+ boot_jump_linux(images);
+ return 0;
+ }
+
+ boot_prep_linux(images);
+ boot_jump_linux(images);
/* does not return */
return 1;
index b1feb2c0d0fc05558c9cb69a7ad00e3637a5d564..4927d5254b65682b4d007ea9afbebd43906343cd 100644 (file)
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long have_console; /* serial_init() was called */
-
- unsigned long reloc_off; /* Relocation Offset */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- unsigned long fb_base; /* base address of frame buffer */
-
- unsigned long relocaddr; /* Start address of U-Boot in RAM */
- phys_size_t ram_size; /* RAM size */
- unsigned long mon_len; /* monitor len */
- unsigned long irq_sp; /* irq stack pointer */
- unsigned long start_addr_sp; /* start_addr_stackpointer */
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- unsigned long tlb_addr;
-#endif
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
extern volatile gd_t g_gd;
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
index 91395cabf35dde2bbbc70c58a910270c1e407bf3..09feaf3733057ce1b30ffef87aa1214943c57b04 100644 (file)
--- a/arch/nds32/lib/board.c
+++ b/arch/nds32/lib/board.c
addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size;
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- /* reserve TLB table */
- addr -= (4096 * 4);
-
- /* round down to next 64 kB limit */
- addr &= ~(0x10000 - 1);
-
- gd->tlb_addr = addr;
- debug("TLB table at: %08lx\n", addr);
-#endif
-
/* round down to next 4 kB limit */
addr &= ~(4096 - 1);
debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c
index b1ed9e17f2db8ed7799c808a1319955029ea759b..f238665915343946f2d31a13b663750101600417 100644 (file)
--- a/arch/nios2/cpu/fdt.c
+++ b/arch/nios2/cpu/fdt.c
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
#include <libfdt.h>
-#include <libfdt_env.h>
#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
index 413b485b61bc72af1a85c2091774a6e158313dd4..39c570023bcfd5eed776a6aaf6fa2909fc4275ac 100644 (file)
#ifndef __ASM_NIOS2_GLOBALDATA_H_
#define __ASM_NIOS2_GLOBALDATA_H_
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long cpu_clk; /* CPU clock in Hz! */
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
-#endif
- phys_size_t ram_size; /* RAM size */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid */
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
- unsigned long post_log_word; /* Record POST activities */
- unsigned long post_log_res; /* success of POST test */
- unsigned long post_init_f_time; /* When post_init_f started */
-#endif
- void **jt; /* Standalone app jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
index 96f3f1cdbbd6d27436d8555ceeb7128feab354ae..d267ccd652fcc92a1af8d9d039bf87bce6e98fe0 100644 (file)
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long cpu_clk; /* CPU clock in Hz! */
- unsigned long have_console; /* serial_init() was called */
- phys_size_t ram_size; /* RAM size */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- unsigned long fb_base; /* base address of frame buffer */
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
/* OR32 GCC already has r10 set as fixed-use */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r10")
index a1a3bd4adf156ae0f125284aef658109f6b82a8a..bb03c6d88575445e865443f0c34bbc1e4658c998 100644 (file)
}
printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
strmhz(buf1, clock),
- strmhz(buf2, gd->csb_clk),
- gd->reset_status & 0xffff);
+ strmhz(buf2, gd->arch.csb_clk),
+ gd->arch.reset_status & 0xffff);
return 0;
}
index fe6beaf84d28843edf9043a2b088b63af29c3557..32ade1b0b9215eff9a66ff65a026acdde4ca8811 100644 (file)
#endif
/* RSR - Reset Status Register - clear all status */
- gd->reset_status = im->reset.rsr;
+ gd->arch.reset_status = im->reset.rsr;
out_be32(&im->reset.rsr, ~RSR_RES);
/*
index 0ea12806b92c718648d8677bd9b5f61a12e13d10..59040f83c9251b87b5b91a277ac077079ed2160b 100644 (file)
{126, 128}
};
- ips = gd->ips_clk;
+ ips = gd->arch.ips_clk;
for (i = 7; i >= 0; i--) {
for (j = 7; j >= 0; j--) {
scl = 2 * (scltap[j].scl2tap +
index dd6b2f4673d70ddb4274a580af9e6e1756e98643..7a496734e7c6b683f2ad3c6bfd8455f084a9f4e5 100644 (file)
ide_set_reset(0);
/* Init timings : we use PIO mode 0 timings */
- t = 1000000000 / gd->ips_clk; /* period in ns */
+ t = 1000000000 / gd->arch.ips_clk; /* period in ns */
cfg.bytes.field1 = 3;
cfg.bytes.field2 = 3;
cfg.bytes.field3 = (pio_specs.t1 + t) / t;
index 58587fd5bcf59c78446a5a52f89e055ededdff39..3afbe810184500784afe0c0bcaebc0fb21806f0a 100644 (file)
}
/* calculate divisor for setting PSC CTUR and CTLR registers */
- baseclk = (gd->ips_clk + 8) / 16;
+ baseclk = (gd->arch.ips_clk + 8) / 16;
div = (baseclk + (baudrate / 2)) / baudrate;
out_8(&psc->ctur, (div >> 8) & 0xff);
index 9d749f22e4d6abc6d471e0f6cddac4ed483045a9..9a8f315d8255325e7fd81ea2ce834737a30564f4 100644 (file)
pci_clk = 333333;
}
- gd->ips_clk = ips_clk;
+ gd->arch.ips_clk = ips_clk;
gd->pci_clk = pci_clk;
- gd->csb_clk = csb_clk;
+ gd->arch.csb_clk = csb_clk;
gd->cpu_clk = core_clk;
gd->bus_clk = csb_clk;
return 0;
*********************************************/
ulong get_bus_freq (ulong dummy)
{
- return gd->csb_clk;
+ return gd->arch.csb_clk;
}
int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
printf("Clock configuration:\n");
printf(" CPU: %-4s MHz\n", strmhz(buf, gd->cpu_clk));
- printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
- printf(" IPS Bus: %-4s MHz\n", strmhz(buf, gd->ips_clk));
+ printf(" Coherent System Bus: %-4s MHz\n",
+ strmhz(buf, gd->arch.csb_clk));
+ printf(" IPS Bus: %-4s MHz\n",
+ strmhz(buf, gd->arch.ips_clk));
printf(" PCI: %-4s MHz\n", strmhz(buf, gd->pci_clk));
- printf(" DDR: %-4s MHz\n", strmhz(buf, 2*gd->csb_clk));
+ printf(" DDR: %-4s MHz\n",
+ strmhz(buf, 2 * gd->arch.csb_clk));
return 0;
}
index 0c1eebd4ee1ec983ac99ef8c2a9ac6eef2a43974..dc021e35f55c4ba055045a45d210757ea512a885 100644 (file)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
-#include <libfdt_env.h>
#include <fdt_support.h>
#endif
index b423d2fe3416a0bfde16ccb9b33f54330f0e9b36..8d5f47b1bba78eaed2125bed82ba4e07693890fd 100644 (file)
{126, 128}
};
- ipb = gd->ipb_clk;
+ ipb = gd->arch.ipb_clk;
for (i = 7; i >= 0; i--) {
for (j = 7; j >= 0; j--) {
scl = 2 * (scltap[j].scl2tap +
index d337abb1c9f637e723eda56f57e280f59db3ef64..094f62b6bab82a03384fee5c36d7f9c619ea9a86 100644 (file)
psdma->PtdCntrl |= 1;
/* Init timings : we use PIO mode 0 timings */
- period = 1000000000 / gd->ipb_clk; /* period in ns */
+ period = 1000000000 / gd->arch.ipb_clk; /* period in ns */
t0 = CALC_TIMING (600);
t2_8 = CALC_TIMING (290);
index eb141619b87448a8aa45c5794ddb8db1d54047d0..1ccb4e35def93f5083e44203956cf9b96edf21ae 100644 (file)
/* select clock sources */
psc->psc_clock_select = 0;
- baseclk = (gd->ipb_clk + 16) / 32;
+ baseclk = (gd->arch.ipb_clk + 16) / 32;
/* switch to UART mode */
psc->sicr = 0;
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
unsigned long baseclk, div;
- baseclk = (gd->ipb_clk + 16) / 32;
+ baseclk = (gd->arch.ipb_clk + 16) / 32;
/* set up UART divisor */
div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
index 8027d3e08a2c8054a97bbcd00d0200389fccdfa0..5353e3d535071718ac18b1dffcc82f31eecd7456 100644 (file)
val = *(vu_long *)MPC5XXX_CDM_CFG;
if (val & (1 << 8)) {
- gd->ipb_clk = gd->bus_clk / 2;
+ gd->arch.ipb_clk = gd->bus_clk / 2;
} else {
- gd->ipb_clk = gd->bus_clk;
+ gd->arch.ipb_clk = gd->bus_clk;
}
switch (val & 3) {
- case 0: gd->pci_clk = gd->ipb_clk; break;
- case 1: gd->pci_clk = gd->ipb_clk / 2; break;
- default: gd->pci_clk = gd->bus_clk / 4; break;
+ case 0:
+ gd->pci_clk = gd->arch.ipb_clk;
+ break;
+ case 1:
+ gd->pci_clk = gd->arch.ipb_clk / 2;
+ break;
+ default:
+ gd->pci_clk = gd->bus_clk / 4;
+ break;
}
return (0);
printf (" Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
strmhz(buf1, gd->bus_clk),
- strmhz(buf2, gd->ipb_clk),
+ strmhz(buf2, gd->arch.ipb_clk),
strmhz(buf3, gd->pci_clk)
);
return (0);
index aaf9be107af83fbdd7c1b6963b84ab2c76c7452b..43fa802ca96db0a5a4e6f0542fb5873877d3ecd5 100644 (file)
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
- /* tbd - rtm */
- /*fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); */
- /* No MII for 7-wire mode */
+ /*
+ * tbd - rtm
+ * fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
+ * No MII for 7-wire mode
+ */
fec->eth->mii_speed = 0x00000030;
}
index 62ac845b7ae8f1aacfae45e623faa404eded5dbf..bb72e5ce126a642ac55327f54a0a55689038bd97 100644 (file)
#error clock measuring not implemented yet - define CONFIG_SYS_MPC8220_CLKIN
#endif
- gd->inp_clk = CONFIG_SYS_MPC8220_CLKIN;
+ gd->arch.inp_clk = CONFIG_SYS_MPC8220_CLKIN;
/* Read XLB to PCI(INP) clock multiplier */
pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
/* FlexBus is temporary set as the same as input clock */
/* will do dynamic in the future */
- gd->flb_clk = CONFIG_SYS_MPC8220_CLKIN;
+ gd->arch.flb_clk = CONFIG_SYS_MPC8220_CLKIN;
/* CPU Clock - Read HID1 */
asm volatile ("mfspr %0, 1009":"=r" (hid1):);
for (i = 0; i < size; i++)
if (hid1 == bus2core[i].hid1) {
gd->cpu_clk = (bus2core[i].multi * gd->bus_clk) >> 1;
- gd->vco_clk = CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER * (gd->pci_clk * bus2core[i].vco_div)/2;
+ gd->arch.vco_clk =
+ CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER *
+ (gd->pci_clk * bus2core[i].vco_div) / 2;
break;
}
/* hardcoded 81MHz for now */
- gd->pev_clk = 81000000;
+ gd->arch.pev_clk = 81000000;
return (0);
}
strmhz(buf1, gd->bus_clk),
strmhz(buf2, gd->cpu_clk),
strmhz(buf3, gd->pci_clk),
- strmhz(buf4, gd->vco_clk)
+ strmhz(buf4, gd->arch.vco_clk)
);
return (0);
}
index 082957ee08e3755142dbf6dd9abed19ce4aede20..22cef3e9839e96101b9bba3212e7068bb6d93acc 100644 (file)
/* Reclaim the DP memory for our use.
*/
- gd->dp_alloc_base = CPM_DATAONLY_BASE;
- gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
+ gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+ gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
/*
* Reset CPM
uint savebase;
align_mask = align - 1;
- savebase = gd->dp_alloc_base;
+ savebase = gd->arch.dp_alloc_base;
- if ((off = (gd->dp_alloc_base & align_mask)) != 0)
- gd->dp_alloc_base += (align - off);
+ off = gd->arch.dp_alloc_base & align_mask;
+ if (off != 0)
+ gd->arch.dp_alloc_base += (align - off);
if ((off = size & align_mask) != 0)
size += align - off;
- if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
- gd->dp_alloc_base = savebase;
+ if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
+ gd->arch.dp_alloc_base = savebase;
panic("m8260_cpm_dpalloc: ran out of dual port ram!");
}
- retloc = gd->dp_alloc_base;
- gd->dp_alloc_base += size;
+ retloc = gd->arch.dp_alloc_base;
+ gd->arch.dp_alloc_base += size;
memset((void *)&immr->im_dprambase[retloc], 0, size);
* Baud rate clocks are zero-based in the driver code (as that maps
* to port numbers). Documentation uses 1-based numbering.
*/
-#define BRG_INT_CLK gd->brg_clk
+#define BRG_INT_CLK gd->arch.brg_clk
#define BRG_UART_CLK (BRG_INT_CLK / 16)
/* This function is used by UARTs, or anything else that uses a 16x
index 220c1e24b1037bdee849fd7b11ca81a412a1ddec..f8bc5a9834b861b54e25f9391ddea6d08cd8949c 100644 (file)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
-#include <libfdt_env.h>
#include <fdt_support.h>
#endif
index acd48a9f553def27b6ab70bd3948c4dca0dffc1d..3964e607d0514ffa2d906906618d6ca6ed102b86 100644 (file)
memset ((void *) gd, 0, sizeof (gd_t));
/* RSR - Reset Status Register - clear all status (5-4) */
- gd->reset_status = immr->im_clkrst.car_rsr;
+ gd->arch.reset_status = immr->im_clkrst.car_rsr;
immr->im_clkrst.car_rsr = RSR_ALLBITS;
/* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
RSR_EHRS, "External Hard"}
};
static int n = sizeof bits / sizeof bits[0];
- ulong rsr = gd->reset_status;
+ ulong rsr = gd->arch.reset_status;
int i;
char *sep;
index 7382cbadc7eebb2a38f9f9263240deec5df9b3e8..b720b1fb882b1b4261939a18479a08e2b2243a2d 100644 (file)
* divide BRGCLK by 1)
*/
debug("[I2C] Setting rate...\n");
- i2c_setrate(gd->brg_clk, CONFIG_SYS_I2C_SPEED);
+ i2c_setrate(gd->arch.brg_clk, CONFIG_SYS_I2C_SPEED);
/* Set I2C controller in master mode */
i2c->i2c_i2com = 0x01;
index bb50dee9602de8bfb535df38c68cdf1b3d7d76c6..7841e8a898c8e64229aada14afd9c8b682230f74 100644 (file)
(get_pvr () == PVR_8260_HIP7R1) ||
(get_pvr () == PVR_8260_HIP7RA)) {
pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
- gd->vco_out = clkin * (pllmf + 1);
+ gd->arch.vco_out = clkin * (pllmf + 1);
} else { /* HiP3, HiP4 */
pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
- gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
+ gd->arch.vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
}
- gd->cpm_clk = gd->vco_out / 2;
+ gd->arch.cpm_clk = gd->arch.vco_out / 2;
gd->bus_clk = clkin;
- gd->scc_clk = gd->vco_out / 4;
- gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+ gd->arch.scc_clk = gd->arch.vco_out / 4;
+ gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
if (cp->b2c_mult > 0) {
gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
pci_div = pcidf + 1;
}
- gd->pci_clk = (gd->cpm_clk * 2) / pci_div;
+ gd->pci_clk = (gd->arch.cpm_clk * 2) / pci_div;
}
#endif
plldf, pllmf, pcidf);
printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
- gd->vco_out, gd->scc_clk, gd->brg_clk);
+ gd->arch.vco_out, gd->arch.scc_clk, gd->arch.brg_clk);
printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
- gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
+ gd->cpu_clk, gd->arch.cpm_clk, gd->bus_clk);
#ifdef CONFIG_PCI
printf (" - pci_clk %10ld\n", gd->pci_clk);
#endif
index 687f5e90a4d5f6dcdce3236db3a7a779cba5ba96..8a470b84b84ca3f04c30aaca351316aed74cc10a 100644 (file)
LIB = $(obj)lib$(CPU).o
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
START = start.o
+ifdef MINIMAL
+
+COBJS-y += spl_minimal.o
+
+else
+
COBJS-y += traps.o
COBJS-y += cpu.o
COBJS-y += cpu_init.o
endif
COBJS-$(CONFIG_FSL_DDR2) += law.o
+endif # not minimal
+
COBJS := $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y))
index e64b0c3411827dd1a06ec9bdb72c8cf9abefce1b..cc2023429828b0cf44b1152e4b8e435139f2009a 100644 (file)
printf(" at %s MHz, ", strmhz(buf, clock));
- printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
+ printf("CSB: %s MHz\n", strmhz(buf, gd->arch.csb_clk));
return 0;
}
index 20d06003e57794cd7633906a34beac4e3b52a5bd..51533519626576bc608ea1f73f7b3487d25e880a 100644 (file)
clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
/* RSR - Reset Status Register - clear all status (4.6.1.3) */
- gd->reset_status = __raw_readl(&im->reset.rsr);
+ gd->arch.reset_status = __raw_readl(&im->reset.rsr);
__raw_writel(~(RSR_RES), &im->reset.rsr);
/* AER - Arbiter Event Register - store status */
- gd->arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
- gd->arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
+ gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
+ gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
/*
* RMR - Reset Mode Register
"reserved"
};
- int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
+ int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
>> AEATR_EVENT_SHIFT;
- int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
+ int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
>> AEATR_MSTR_ID_SHIFT;
- int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
+ int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
>> AEATR_TBST_SHIFT;
- int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
+ int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
>> AEATR_TSIZE_SHIFT;
- int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
+ int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
>> AEATR_TTYPE_SHIFT;
- if (!force && !gd->arbiter_event_address)
+ if (!force && !gd->arch.arbiter_event_address)
return 0;
puts("Arbiter Event Status:\n");
- printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
+ printf(" Event Address: 0x%08lX\n",
+ gd->arch.arbiter_event_address);
printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
- return gd->arbiter_event_address;
+ return gd->arch.arbiter_event_address;
}
#elif defined(CONFIG_DISPLAY_AER_BRIEF)
static int print_83xx_arb_event(int force)
{
- if (!force && !gd->arbiter_event_address)
+ if (!force && !gd->arch.arbiter_event_address)
return 0;
printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
- gd->arbiter_event_attributes, gd->arbiter_event_address);
+ gd->arch.arbiter_event_attributes,
+ gd->arch.arbiter_event_address);
- return gd->arbiter_event_address;
+ return gd->arch.arbiter_event_address;
}
#endif /* CONFIG_DISPLAY_AER_xxxx */
RSR_HRS, "External/Internal Hard"}
};
static int n = sizeof bits / sizeof bits[0];
- ulong rsr = gd->reset_status;
+ ulong rsr = gd->arch.reset_status;
int i;
char *sep;
index 1f54781b7e2d3b7e8e1e58e1dce64b727b21e9ba..fe553a74f001e465250a2ffd67d96203e892ca0e 100644 (file)
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "clock-frequency", gd->core_clk, 1);
+ "clock-frequency", gd->arch.core_clk, 1);
do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_compat_u32(blob, "fsl,soc",
index 52d446175aa5992e1e1c3a36c550d61d22bd818e..609b133215c44d958e74d56b3c1d6bd6bd103938 100644 (file)
get_clocks();
/* Configure the PCIE controller core clock ratio */
out_le32(hose_cfg_base + PEX_GCLK_RATIO,
- (((bus ? gd->pciexp2_clk : gd->pciexp1_clk) / 1000000) * 16)
- / 333);
+ (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk)
+ / 1000000) * 16) / 333);
udelay(1000000);
/* Do Type 1 bridge configuration */
index b8c05d15929ce33800e9848a5419a50560633f17..6be0e3a2ee41c7f36258cf0550d651a349ab1696 100644 (file)
brg_clk = qe_clk / 2;
#endif
- gd->csb_clk = csb_clk;
+ gd->arch.csb_clk = csb_clk;
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
- gd->tsec1_clk = tsec1_clk;
- gd->tsec2_clk = tsec2_clk;
- gd->usbdr_clk = usbdr_clk;
+ gd->arch.tsec1_clk = tsec1_clk;
+ gd->arch.tsec2_clk = tsec2_clk;
+ gd->arch.usbdr_clk = usbdr_clk;
#elif defined(CONFIG_MPC8309)
- gd->usbdr_clk = usbdr_clk;
+ gd->arch.usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_MPC834x)
- gd->usbmph_clk = usbmph_clk;
+ gd->arch.usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_MPC8315)
- gd->tdm_clk = tdm_clk;
+ gd->arch.tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
- gd->sdhc_clk = sdhc_clk;
+ gd->arch.sdhc_clk = sdhc_clk;
#endif
- gd->core_clk = core_clk;
- gd->i2c1_clk = i2c1_clk;
+ gd->arch.core_clk = core_clk;
+ gd->arch.i2c1_clk = i2c1_clk;
#if !defined(CONFIG_MPC832x)
- gd->i2c2_clk = i2c2_clk;
+ gd->arch.i2c2_clk = i2c2_clk;
#endif
#if !defined(CONFIG_MPC8309)
- gd->enc_clk = enc_clk;
+ gd->arch.enc_clk = enc_clk;
#endif
- gd->lbiu_clk = lbiu_clk;
- gd->lclk_clk = lclk_clk;
+ gd->arch.lbiu_clk = lbiu_clk;
+ gd->arch.lclk_clk = lclk_clk;
gd->mem_clk = mem_clk;
#if defined(CONFIG_MPC8360)
- gd->mem_sec_clk = mem_sec_clk;
+ gd->arch.mem_sec_clk = mem_sec_clk;
#endif
#if defined(CONFIG_QE)
- gd->qe_clk = qe_clk;
- gd->brg_clk = brg_clk;
+ gd->arch.qe_clk = qe_clk;
+ gd->arch.brg_clk = brg_clk;
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
- gd->pciexp1_clk = pciexp1_clk;
- gd->pciexp2_clk = pciexp2_clk;
+ gd->arch.pciexp1_clk = pciexp1_clk;
+ gd->arch.pciexp2_clk = pciexp2_clk;
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
- gd->sata_clk = sata_clk;
+ gd->arch.sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
- gd->cpu_clk = gd->core_clk;
- gd->bus_clk = gd->csb_clk;
+ gd->cpu_clk = gd->arch.core_clk;
+ gd->bus_clk = gd->arch.csb_clk;
return 0;
}
*********************************************/
ulong get_bus_freq(ulong dummy)
{
- return gd->csb_clk;
+ return gd->arch.csb_clk;
}
/********************************************
@@ -536,49 +536,69 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
char buf[32];
printf("Clock configuration:\n");
- printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
- printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
+ printf(" Core: %-4s MHz\n",
+ strmhz(buf, gd->arch.core_clk));
+ printf(" Coherent System Bus: %-4s MHz\n",
+ strmhz(buf, gd->arch.csb_clk));
#if defined(CONFIG_QE)
- printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
- printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk));
-#endif
- printf(" Local Bus Controller:%-4s MHz\n", strmhz(buf, gd->lbiu_clk));
- printf(" Local Bus: %-4s MHz\n", strmhz(buf, gd->lclk_clk));
+ printf(" QE: %-4s MHz\n",
+ strmhz(buf, gd->arch.qe_clk));
+ printf(" BRG: %-4s MHz\n",
+ strmhz(buf, gd->arch.brg_clk));
+#endif
+ printf(" Local Bus Controller:%-4s MHz\n",
+ strmhz(buf, gd->arch.lbiu_clk));
+ printf(" Local Bus: %-4s MHz\n",
+ strmhz(buf, gd->arch.lclk_clk));
printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
#if defined(CONFIG_MPC8360)
- printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
+ printf(" DDR Secondary: %-4s MHz\n",
+ strmhz(buf, gd->arch.mem_sec_clk));
#endif
#if !defined(CONFIG_MPC8309)
- printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
+ printf(" SEC: %-4s MHz\n",
+ strmhz(buf, gd->arch.enc_clk));
#endif
- printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
+ printf(" I2C1: %-4s MHz\n",
+ strmhz(buf, gd->arch.i2c1_clk));
#if !defined(CONFIG_MPC832x)
- printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
+ printf(" I2C2: %-4s MHz\n",
+ strmhz(buf, gd->arch.i2c2_clk));
#endif
#if defined(CONFIG_MPC8315)
- printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk));
+ printf(" TDM: %-4s MHz\n",
+ strmhz(buf, gd->arch.tdm_clk));
#endif
#if defined(CONFIG_FSL_ESDHC)
- printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
+ printf(" SDHC: %-4s MHz\n",
+ strmhz(buf, gd->arch.sdhc_clk));
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
- printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
- printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
- printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+ printf(" TSEC1: %-4s MHz\n",
+ strmhz(buf, gd->arch.tsec1_clk));
+ printf(" TSEC2: %-4s MHz\n",
+ strmhz(buf, gd->arch.tsec2_clk));
+ printf(" USB DR: %-4s MHz\n",
+ strmhz(buf, gd->arch.usbdr_clk));
#elif defined(CONFIG_MPC8309)
- printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+ printf(" USB DR: %-4s MHz\n",
+ strmhz(buf, gd->arch.usbdr_clk));
#endif
#if defined(CONFIG_MPC834x)
- printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
+ printf(" USB MPH: %-4s MHz\n",
+ strmhz(buf, gd->arch.usbmph_clk));
#endif
#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
- printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
- printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
+ printf(" PCIEXP1: %-4s MHz\n",
+ strmhz(buf, gd->arch.pciexp1_clk));
+ printf(" PCIEXP2: %-4s MHz\n",
+ strmhz(buf, gd->arch.pciexp2_clk));
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
- printf(" SATA: %-4s MHz\n", strmhz(buf, gd->sata_clk));
+ printf(" SATA: %-4s MHz\n",
+ strmhz(buf, gd->arch.sata_clk));
#endif
return 0;
}
similarity index 100%
rename from arch/powerpc/cpu/mpc83xx/nand_init.c
rename to arch/powerpc/cpu/mpc83xx/spl_minimal.c
rename from arch/powerpc/cpu/mpc83xx/nand_init.c
rename to arch/powerpc/cpu/mpc83xx/spl_minimal.c
index b70b4ca12cea1540a4697654b1e41a527eb1078c..44a64b7acd9cda4ea674ce250e55f960b0551f4f 100644 (file)
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_NAND_SPL) || \
+ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
+#define MINIMAL_SPL
+#endif
+
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
+ !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_SYS_FLASHBOOT
#endif
GOT_ENTRY(__bss_start)
GOT_ENTRY(__bss_end__)
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
GOT_ENTRY(_FIXUP_TABLE_)
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
/* Initialise the E300 processor core */
/*------------------------------------------*/
-#ifdef CONFIG_NAND_SPL
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
+ defined(CONFIG_NAND_SPL)
/* The FCM begins execution after only the first page
* is loaded. Wait for the rest before branching
* to another flash page.
/* NOTREACHED - board_init_f() does not return */
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
/*
* Vector Table
*/
lwz r1,GPR1(r1)
SYNC
rfi
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
/*
* This code initialises the E300 processor core
* Note: requires that all cache bits in
* HID0 are in the low half word.
*/
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
.globl icache_enable
icache_enable:
mfspr r3, HID0
mfspr r3, HID0
rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
.globl dcache_enable
dcache_enable:
stw r0,0(r3)
2: bdnz 1b
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
/*
* Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
mr r4, r10 /* Destination Address */
bl board_init_r
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
/*
* Copy exception vector code to low memory
*
mtlr r4 /* restore link register */
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
#ifdef CONFIG_SYS_INIT_RAM_LOCK
lock_ram_in_cache:
sync
blr
-#ifndef CONFIG_NAND_SPL
+#ifndef MINIMAL_SPL
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
sync
mtspr HID0, r3 /* no invalidate, unlock */
blr
-#endif /* !CONFIG_NAND_SPL */
+#endif /* !MINIMAL_SPL */
#endif /* CONFIG_SYS_INIT_RAM_LOCK */
#ifdef CONFIG_SYS_FLASHBOOT
diff --git a/nand_spl/board/freescale/mpc8313erdb/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
similarity index 100%
rename from nand_spl/board/freescale/mpc8313erdb/u-boot.lds
rename to arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
rename from nand_spl/board/freescale/mpc8313erdb/u-boot.lds
rename to arch/powerpc/cpu/mpc83xx/u-boot-spl.lds
index 4c2b1040d4613317b2365ddce77bdf23ffc21493..6776c85e4998b5db946ef3d9bc9511aea49e0edc 100644 (file)
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o
COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
+COBJS-$(CONFIG_BSC9132) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o
COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
+COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
COBJS-y += cpu.o
COBJS-y += cpu_init.o
index 7d33731a7ba455615b1cb21c1143d48c9e585467..0f4e82e05b3a185e4755469f8927b78f437ac22a 100644 (file)
};
#endif
+#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_1(1, 307),
SET_SRIO_LIODN_1(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
SET_DMA_LIODN(1, 147),
SET_DMA_LIODN(2, 227),
+#ifndef CONFIG_PPC_B4420
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+#endif
/* SET_NEXUS_LIODN(557), -- not yet implemented */
};
SET_FMAN_RX_1G_LIODN(1, 3, 91),
SET_FMAN_RX_1G_LIODN(1, 4, 92),
SET_FMAN_RX_1G_LIODN(1, 5, 93),
+#ifndef CONFIG_PPC_B4420
SET_FMAN_RX_10G_LIODN(1, 0, 94),
SET_FMAN_RX_10G_LIODN(1, 1, 95),
+#endif
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#endif
index 9990202f421af77c459f2810b340af4bfb8c879d..bd3234271a1da1f1b644c827e7c9ad70e2f59565 100644 (file)
u8 lanes[SRDS_MAX_LANES];
};
+#ifdef CONFIG_PPC_B4860
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1}},
{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
{0x30, {AURORA, AURORA,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
CPRI4, CPRI3, CPRI2, CPRI1}},
{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SRIO2, SRIO2, AURORA, AURORA,
XFI_FM1_MAC9, XFI_FM1_MAC10}},
SRIO2, SRIO2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XFI_FM1_MAC9, XFI_FM1_MAC10}},
{0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
XAUI_FM1_MAC10, XAUI_FM1_MAC10,
{0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
XAUI_FM1_MAC9, XAUI_FM1_MAC9,
SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
{}
};
+#endif
+
+#ifdef CONFIG_PPC_B4420
+static struct serdes_config serdes1_cfg_tbl[] = {
+ {0x0D, {NONE, NONE, CPRI6, CPRI5,
+ CPRI4, CPRI3, NONE, NONE} },
+ {0x0E, {NONE, NONE, CPRI8, CPRI5,
+ CPRI4, CPRI3, NONE, NONE} },
+ {0x0F, {NONE, NONE, CPRI6, CPRI5,
+ CPRI4, CPRI3, NONE, NONE} },
+ {0x18, {NONE, NONE,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
+ {0x1B, {NONE, NONE,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
+ {0x1E, {NONE, NONE, AURORA, AURORA,
+ NONE, NONE, NONE, NONE} },
+ {0x21, {NONE, NONE, AURORA, AURORA,
+ NONE, NONE, NONE, NONE} },
+ {0x3E, {NONE, NONE, CPRI6, CPRI5,
+ CPRI4, CPRI3, NONE, NONE} },
+ {}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+ {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ NONE, NONE, NONE, NONE} },
+ {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ NONE, NONE, NONE, NONE} },
+ {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ AURORA, AURORA, NONE, NONE, NONE, NONE} },
+ {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ AURORA, AURORA, NONE, NONE, NONE, NONE} },
+ {0x9A, {PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
+ {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
+ NONE, NONE, NONE, NONE} },
+ {}
+};
+#endif
+
static struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
serdes2_cfg_tbl,
diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
--- /dev/null
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES 4
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+ [0] = {NONE, NONE, NONE, NONE},
+ [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
+ [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
+ [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
+ [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
+ [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
+ [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+ [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+ [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+ [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+ [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+ [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
+ [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+ [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+ [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+ [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+ [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+ [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+ [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+ [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+ [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+ [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+ [22] = {PCIE1, PCIE2, CPRI2, CPRI1},
+ [23] = {PCIE1, PCIE2, CPRI2, CPRI1},
+ [24] = {PCIE1, PCIE2, CPRI2, CPRI1},
+ [25] = {PCIE1, PCIE2, CPRI2, CPRI1},
+ [26] = {PCIE1, PCIE2, CPRI2, CPRI1},
+ [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+ [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+ [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+ [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+ [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+ [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
+ [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+ [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+ [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+ [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+ [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+ [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+ [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+ [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+ [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+ [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+ [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+ [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+ [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+ [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+ [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+ return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+ int lane;
+
+ debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+ if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
+ printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+ return;
+ }
+
+ for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+ serdes1_prtcl_map |= (1 << lane_prtcl);
+ }
+}
index e5ecf5dae59d2384cdf671a58fc49a4a66a7e457..5d72f4c342d36dcb9462b67ed71e35e72426aec4 100644 (file)
@@ -240,6 +240,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
puts("Work-around for Erratum A004934 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
+ if (IS_SVR_REV(svr, 1, 0))
+ puts("Work-around for Erratum A005871 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4849(svr);
index 292b723dcddf00178b757cc03ae02ddbe5e1f6f5..37e706238b6fc92607c7729699afccdb4edef1e6 100644 (file)
/* Reclaim the DP memory for our use.
*/
- gd->dp_alloc_base = CPM_DATAONLY_BASE;
- gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
+ gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+ gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
/*
* Reset CPM
uint savebase;
align_mask = align - 1;
- savebase = gd->dp_alloc_base;
+ savebase = gd->arch.dp_alloc_base;
- if ((off = (gd->dp_alloc_base & align_mask)) != 0)
- gd->dp_alloc_base += (align - off);
+ off = gd->arch.dp_alloc_base & align_mask;
+ if (off != 0)
+ gd->arch.dp_alloc_base += (align - off);
if ((off = size & align_mask) != 0)
size += align - off;
- if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
- gd->dp_alloc_base = savebase;
+ if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
+ gd->arch.dp_alloc_base = savebase;
panic("m8560_cpm_dpalloc: ran out of dual port ram!");
}
- retloc = gd->dp_alloc_base;
- gd->dp_alloc_base += size;
+ retloc = gd->arch.dp_alloc_base;
+ gd->arch.dp_alloc_base += size;
memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
* Baud rate clocks are zero-based in the driver code (as that maps
* to port numbers). Documentation uses 1-based numbering.
*/
-#define BRG_INT_CLK gd->brg_clk
+#define BRG_INT_CLK gd->arch.brg_clk
#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
/* This function is used by UARTS, or anything else that uses a 16x
index 9b9832cfc3363b71d53893f85a7e90b8fbd46895..df2ab6d73cbd73a3872c5263233483f3a277da41 100644 (file)
puts("CPU: ");
}
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
puts(cpu->name);
if (IS_E_PROCESSOR(svr))
index d1155e81263e8d948144cb1d84a3098e3c41f161..de9d9161115d1713fb02ee90c22845b04f7e58bd 100644 (file)
/* Look through the remaining clusters, and set up their caches */
do {
+ int j, cluster_valid = 0;
+
l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+
cluster = in_be32(&gur->tp_cluster[i].lower);
- /* set stash ID to (cluster) * 2 + 32 + 1 */
- clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+ /* check that at least one core/accel is enabled in cluster */
+ for (j = 0; j < 4; j++) {
+ u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
+ u32 type = in_be32(&gur->tp_ityp[idx]);
+
+ if (type & TP_ITYP_AV)
+ cluster_valid = 1;
+ }
- printf("enable l2 for cluster %d %p\n", i, l2cache);
+ if (cluster_valid) {
+ /* set stash ID to (cluster) * 2 + 32 + 1 */
+ clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
- out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
- while ((in_be32(&l2cache->l2csr0) &
- (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
- ;
- out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+ printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+ out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+ while ((in_be32(&l2cache->l2csr0)
+ & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+ ;
+ out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+ }
i++;
} while (!(cluster & TP_CLUSTER_EOC));
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
+ if (IS_SVR_REV(svr, 1, 0)) {
+ int i;
+ __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
+
+ for (i = 0; i < 12; i++) {
+ p += i + (i > 5 ? 11 : 0);
+ out_be32(p, 0x2);
+ }
+ p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
+ out_be32(p, 0x34);
+ }
+#endif
+
#ifdef CONFIG_SYS_SRIO
srio_init();
#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
index ab0933076df9352b7ecb401686941c9cf7cbc1c1..24eb9789be9708cd5ffca1d7c4c8d47ad85e29d4 100644 (file)
printf("Failed to reserve memory for bootpg: %s\n",
fdt_strerror(off));
}
+
+#ifndef CONFIG_MPC8xxx_DISABLE_BPTR
+ /*
+ * Reserve the default boot page so OSes dont use it.
+ * The default boot page is always mapped to bootpg above using
+ * boot page translation.
+ */
+ if (0xfffff000ull < memory_limit) {
+ off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
+ if (off < 0) {
+ printf("Failed to reserve memory for 0xfffff000: %s\n",
+ fdt_strerror(off));
+ }
+ }
+#endif
+
/* Reserve spin table page */
if (spin_tbl_addr < memory_limit) {
off = fdt_add_mem_rsv(blob,
/* delete crypto node if not on an E-processor */
if (!IS_E_PROCESSOR(get_svr()))
fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+ else {
+ ccsr_sec_t __iomem *sec;
+
+ sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ fdt_fixup_crypto_node(blob, in_be32(&sec->secvid_ms));
+ }
+#endif
fdt_fixup_ethernet(blob);
"bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
- "bus-frequency", gd->lbc_clk, 1);
+ "bus-frequency", gd->arch.lbc_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,elbc",
- "bus-frequency", gd->lbc_clk, 1);
+ "bus-frequency", gd->arch.lbc_clk, 1);
#ifdef CONFIG_QE
ft_qe_setup(blob);
ft_fixup_qe_snum(blob);
#ifdef CONFIG_SYS_LBC_ADDR
off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
if (off > 0) {
- const u32 *reg = fdt_getprop(fdt, off, "reg", NULL);
+ const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
if (reg) {
uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
index 801ee078c088c135dfe110aea276ca11a73a045e..297f2ed4739f2080e35207cb9521511c98ee27f8 100644 (file)
gd->cpu_clk = sys_info.freqProcessor[0];
gd->bus_clk = sys_info.freqSystemBus;
gd->mem_clk = sys_info.freqDDRBus;
- gd->lbc_clk = sys_info.freqLocalBus;
+ gd->arch.lbc_clk = sys_info.freqLocalBus;
#ifdef CONFIG_QE
- gd->qe_clk = sys_info.freqQE;
- gd->brg_clk = gd->qe_clk / 2;
+ gd->arch.qe_clk = sys_info.freqQE;
+ gd->arch.brg_clk = gd->arch.qe_clk / 2;
#endif
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
*/
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
- gd->i2c1_clk = sys_info.freqSystemBus;
+ gd->arch.i2c1_clk = sys_info.freqSystemBus;
#elif defined(CONFIG_MPC8544)
/*
* On the 8544, the I2C clock is the same as the SEC clock. This can be
* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
*/
if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
- gd->i2c1_clk = sys_info.freqSystemBus / 3;
+ gd->arch.i2c1_clk = sys_info.freqSystemBus / 3;
else
- gd->i2c1_clk = sys_info.freqSystemBus / 2;
+ gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
#else
/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
- gd->i2c1_clk = sys_info.freqSystemBus / 2;
+ gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
#endif
- gd->i2c2_clk = gd->i2c1_clk;
+ gd->arch.i2c2_clk = gd->arch.i2c1_clk;
#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
defined(CONFIG_P1014)
- gd->sdhc_clk = gd->bus_clk;
+ gd->arch.sdhc_clk = gd->bus_clk;
#else
- gd->sdhc_clk = gd->bus_clk / 2;
+ gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */
#if defined(CONFIG_CPM2)
- gd->vco_out = 2*sys_info.freqSystemBus;
- gd->cpm_clk = gd->vco_out / 2;
- gd->scc_clk = gd->vco_out / 4;
- gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+ gd->arch.vco_out = 2*sys_info.freqSystemBus;
+ gd->arch.cpm_clk = gd->arch.vco_out / 2;
+ gd->arch.scc_clk = gd->arch.vco_out / 4;
+ gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
#endif
if(gd->cpu_clk != 0) return (0);
index bb0dc1a653e193fb1f141e13ede0980f0c075198..fb674694e4363bdc14c8e73f0db377f8cb46843d 100644 (file)
/* Set the size of the TLB to 4KB */
mfspr r3, MAS1
- li r2, 0xF00
+ li r2, 0xF80
andc r3, r3, r2 /* Clear the TSIZE bits */
ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
oris r3, r3, MAS1_IPROT@h
index f44fadcffd80599143faca65b6f38c278e34e097..0dff37f77cd20c26b75c5ff28bd65856a0fc7afa 100644 (file)
_mas1 = mfspr(MAS1);
*valid = (_mas1 & MAS1_VALID);
- *tsize = (_mas1 >> 8) & 0xf;
+ *tsize = (_mas1 >> 7) & 0x1f;
*epn = mfspr(MAS2) & MAS2_EPN;
*rpn = mfspr(MAS3) & MAS3_RPN;
#ifdef CONFIG_ENABLE_36BIT_PHYS
int i = idx / 32;
int bit = idx % 32;
- gd->used_tlb_cams[i] |= (1 << bit);
+ gd->arch.used_tlb_cams[i] |= (1 << bit);
}
static inline void free_tlb_cam(u8 idx)
int i = idx / 32;
int bit = idx % 32;
- gd->used_tlb_cams[i] &= ~(1 << bit);
+ gd->arch.used_tlb_cams[i] &= ~(1 << bit);
}
void init_used_tlb_cams(void)
unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
- gd->used_tlb_cams[i] = 0;
+ gd->arch.used_tlb_cams[i] = 0;
/* walk all the entries */
for (i = 0; i < num_cam; i++) {
u32 idx;
for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
- idx = ffz(gd->used_tlb_cams[i]);
+ idx = ffz(gd->arch.used_tlb_cams[i]);
if (idx != 32)
break;
if (tlb == 1)
use_tlb_cam(esel);
+ if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
+ tsize & 1) {
+ printf("%s: bad tsize %d on entry %d at 0x%08x\n",
+ __func__, tsize, tlb, epn);
+ return;
+ }
+
_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
_mas2 = FSL_BOOKE_MAS2(epn, wimge);
unsigned int tlb_size;
unsigned int wimge = MAS2_M;
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
- unsigned int max_cam;
+ unsigned int max_cam, tsize_mask;
u64 size, memsize = (u64)memsize_in_meg << 20;
#ifdef CONFIG_SYS_PPC_DDR_WIMGE
if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
/* Convert (4^max) kB to (2^max) bytes */
max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+ tsize_mask = ~1U;
} else {
/* Convert (2^max) kB to (2^max) bytes */
max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+ tsize_mask = ~0U;
}
for (i = 0; size && i < 8; i++) {
int ram_tlb_index = find_free_tlbcam();
- u32 camsize = __ilog2_u64(size) & ~1U;
- u32 align = __ilog2(ram_tlb_address) & ~1U;
+ u32 camsize = __ilog2_u64(size) & tsize_mask;
+ u32 align = __ilog2(ram_tlb_address) & tsize_mask;
if (ram_tlb_index == -1)
break;
if (camsize > max_cam)
camsize = max_cam;
- tlb_size = (camsize - 10) / 2;
+ tlb_size = camsize - 10;
set_tlb(1, ram_tlb_address, p_addr,
MAS3_SX|MAS3_SW|MAS3_SR, wimge,
index d2c8c78e864b279d88cc9b86e0fbb153b329141d..c553415b555a5a122b5f4966d97c9915ad2efc1e 100644 (file)
}
puts("CPU: ");
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
puts(cpu->name);
index 2f955fe9309220fcc8af6b6803b30e2624bed76b..26a65c586d5da49ca1f3437594e2ee9a7489f7d2 100644 (file)
#if defined(CONFIG_MPC8641)
do_fixup_by_compat_u32(blob, "fsl,mpc8641-localbus",
- "bus-frequency", gd->lbc_clk, 1);
+ "bus-frequency", gd->arch.lbc_clk, 1);
#endif
do_fixup_by_compat_u32(blob, "fsl,elbc",
- "bus-frequency", gd->lbc_clk, 1);
+ "bus-frequency", gd->arch.lbc_clk, 1);
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
index a2d0a8ac6ebdf6f75b3661e002318e4ba0651c4c..18c1eea0c1ae1b7242051da35170a26e3044eac5 100644 (file)
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqSystemBus;
- gd->lbc_clk = sys_info.freqLocalBus;
+ gd->arch.lbc_clk = sys_info.freqLocalBus;
/*
* The base clock for I2C depends on the actual SOC. Unfortunately,
* AN2919.
*/
#ifdef CONFIG_MPC8610
- gd->i2c1_clk = sys_info.freqSystemBus;
+ gd->arch.i2c1_clk = sys_info.freqSystemBus;
#else
- gd->i2c1_clk = sys_info.freqSystemBus / 2;
+ gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
#endif
- gd->i2c2_clk = gd->i2c1_clk;
+ gd->arch.i2c2_clk = gd->arch.i2c1_clk;
if (gd->cpu_clk != 0)
return 0;
index 5fe01fffae26f8e4538ea379fafff75ed2aa8935..a364782096778de7dfb1221cb8712de9c595cd30 100644 (file)
int dpram_init (void)
{
/* Reclaim the DP memory for our use. */
- gd->dp_alloc_base = CPM_DATAONLY_BASE;
- gd->dp_alloc_top = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE;
+ gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
+ gd->arch.dp_alloc_top = CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE;
return (0);
}
*/
uint dpram_alloc (uint size)
{
- uint addr = gd->dp_alloc_base;
+ uint addr = gd->arch.dp_alloc_base;
- if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top)
+ if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top)
return (CPM_DP_NOSPACE);
- gd->dp_alloc_base += size;
+ gd->arch.dp_alloc_base += size;
return addr;
}
uint dpram_base (void)
{
- return gd->dp_alloc_base;
+ return gd->arch.dp_alloc_base;
}
/* Allocate some memory from the dual ported ram. We may want to
{
uint addr, mask = align - 1;
- addr = (gd->dp_alloc_base + mask) & ~mask;
+ addr = (gd->arch.dp_alloc_base + mask) & ~mask;
- if ((addr + size) >= gd->dp_alloc_top)
+ if ((addr + size) >= gd->arch.dp_alloc_top)
return (CPM_DP_NOSPACE);
- gd->dp_alloc_base = addr + size;
+ gd->arch.dp_alloc_base = addr + size;
return addr;
}
{
uint mask = align - 1;
- return (gd->dp_alloc_base + mask) & ~mask;
+ return (gd->arch.dp_alloc_base + mask) & ~mask;
}
#endif /* CONFIG_SYS_ALLOC_DPRAM */
index b3fcfe5626a5e1cb5aadfa16e1acd39c64726a1f..b6b733d77fd356b6231c958f2da326c3468c3855 100644 (file)
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
-#include <libfdt_env.h>
#include <fdt_support.h>
#endif
index 7130983ff222f19e17d59c395af6fc5fe3a72ac1..7edd7e4204e20e894b11de7ac028edbcc95256bd 100644 (file)
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
- gd->brg_clk, 1);
+ gd->arch.brg_clk, 1);
/* Fixup ethernet MAC addresses */
fdt_fixup_ethernet(blob);
index 6e13e5de028b800a4bb2721938aba056cc5b97ee..091b49f24a9f628abaf95ef6b3a0cb8d7ca4eda5 100644 (file)
divider = 64;
break;
}
- gd->brg_clk = gd->cpu_clk/divider;
+ gd->arch.brg_clk = gd->cpu_clk/divider;
}
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
index e8613be39310ced159744d8115ac2f198c791742..39525fb29d55ed6163a2c748b594a7160b959117 100644 (file)
CPU_TYPE_ENTRY(B4220, B4220, 0),
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
+ CPU_TYPE_ENTRY(BSC9132, 9132, 2),
+ CPU_TYPE_ENTRY(BSC9232, 9232, 2),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),
u32 cpu_mask(void)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
- struct cpu_type *cpu = gd->cpu;
+ struct cpu_type *cpu = gd->arch.cpu;
/* better to query feature reporting register than just assume 1 */
if (cpu == &cpu_type_unknown)
*/
int cpu_numcores(void)
{
- struct cpu_type *cpu = gd->cpu;
+ struct cpu_type *cpu = gd->arch.cpu;
/*
* Report # of cores in terms of the cpu_mask if we haven't
svr = get_svr();
ver = SVR_SOC_VER(svr);
- gd->cpu = identify_cpu(ver);
+ gd->arch.cpu = identify_cpu(ver);
return 0;
}
/* Once in memory, compute mask & # cores once and save them off */
int fixup_cpu(void)
{
- struct cpu_type *cpu = gd->cpu;
+ struct cpu_type *cpu = gd->arch.cpu;
if (cpu->num_cores == 0) {
cpu->mask = cpu_mask();
index 8016bcdc22ec8b54a12ef1d7f7cf7bf4aa0d5f27..26c42f7039033d82a8829e7b48396e6105c2daee 100644 (file)
{
unsigned int init_value; /* Initialization value */
+#ifdef CONFIG_MEM_INIT_VALUE
+ init_value = CONFIG_MEM_INIT_VALUE;
+#else
init_value = 0xDEADBEEF;
+#endif
ddr->ddr_data_init = init_value;
}
index c8b0f916763340a0fead834dbce1a5fb4411401d..4dd55fc4c3f923ea3bf942346cf41380edc1b8d6 100644 (file)
unsigned int memctl_interleaved,
unsigned int ctrl_num);
-unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo);
+int fsl_ddr_interactive_env_var_exists(void);
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index cb71f94ba1ecd1540728892dc0bf3c72d3b1f94c..46257c9529ef924dc0c92827d0591a8231d18f48 100644 (file)
#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
-unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
-{
- unsigned long long ddrsize;
- const char *prompt = "FSL DDR>";
- char buffer[CONFIG_SYS_CBSIZE];
- char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
- int argc;
- unsigned int next_step = STEP_GET_SPD;
+static unsigned int fsl_ddr_parse_interactive_cmd(
+ char **argv,
+ int argc,
+ unsigned int *pstep_mask,
+ unsigned int *pctlr_mask,
+ unsigned int *pdimm_mask,
+ unsigned int *pdimm_number_required
+ ) {
+
static const struct data_strings options[] = {
DATA_OPTIONS(spd, STEP_GET_SPD, 1),
DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
+
+ unsigned int i, j;
+ unsigned int error = 0;
+
+ for (i = 1; i < argc; i++) {
+ unsigned int matched = 0;
+
+ for (j = 0; j < n_opts; j++) {
+ if (strcmp(options[j].data_name, argv[i]) != 0)
+ continue;
+ *pstep_mask |= options[j].step_mask;
+ *pdimm_number_required =
+ options[j].dimm_number_required;
+ matched = 1;
+ break;
+ }
+
+ if (matched)
+ continue;
+
+ if (argv[i][0] == 'c') {
+ char c = argv[i][1];
+ if (isdigit(c))
+ *pctlr_mask |= 1 << (c - '0');
+ continue;
+ }
+
+ if (argv[i][0] == 'd') {
+ char c = argv[i][1];
+ if (isdigit(c))
+ *pdimm_mask |= 1 << (c - '0');
+ continue;
+ }
+
+ printf("unknown arg %s\n", argv[i]);
+ *pstep_mask = 0;
+ error = 1;
+ break;
+ }
+
+ return error;
+}
+
+int fsl_ddr_interactive_env_var_exists(void)
+{
+ char buffer[CONFIG_SYS_CBSIZE];
+
+ if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
+ return 1;
+
+ return 0;
+}
+
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
+{
+ unsigned long long ddrsize;
+ const char *prompt = "FSL DDR>";
+ char buffer[CONFIG_SYS_CBSIZE];
+ char buffer2[CONFIG_SYS_CBSIZE];
+ char *p = NULL;
+ char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
+ int argc;
+ unsigned int next_step = STEP_GET_SPD;
const char *usage = {
"commands:\n"
"print print SPD and intermediate computed data\n"
"recompute reload SPD and options to default and recompute regs\n"
"edit modify spd, parameter, or option\n"
"compute recompute registers from current next_step to end\n"
+ "copy copy parameters\n"
"next_step shows current next_step\n"
"help this message\n"
"go program the memory controller and continue with u-boot\n"
};
+ if (var_is_set) {
+ if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) {
+ p = buffer2;
+ } else {
+ var_is_set = 0;
+ }
+ }
+
/*
* The strategy for next_step is that it points to the next
* step in the computation process that needs to be done.
*/
while (1) {
- /*
- * No need to worry for buffer overflow here in
- * this function; readline() maxes out at CFG_CBSIZE
- */
- readline_into_buffer(prompt, buffer, 0);
+ if (var_is_set) {
+ char *pend = strchr(p, ';');
+ if (pend) {
+ /* found command separator, copy sub-command */
+ *pend = '\0';
+ strcpy(buffer, p);
+ p = pend + 1;
+ } else {
+ /* separator not found, copy whole string */
+ strcpy(buffer, p);
+ p = NULL;
+ var_is_set = 0;
+ }
+ } else {
+ /*
+ * No need to worry for buffer overflow here in
+ * this function; readline() maxes out at CFG_CBSIZE
+ */
+ readline_into_buffer(prompt, buffer, 0);
+ }
argc = parse_line(buffer, argv);
if (argc == 0)
continue;
continue;
}
- if (strcmp(argv[0], "edit") == 0) {
- unsigned int i, j;
+ if (strcmp(argv[0], "copy") == 0) {
unsigned int error = 0;
unsigned int step_mask = 0;
- unsigned int ctlr_mask = 0;
- unsigned int dimm_mask = 0;
- char *p_element = NULL;
- char *p_value = NULL;
+ unsigned int src_ctlr_mask = 0;
+ unsigned int src_dimm_mask = 0;
unsigned int dimm_number_required = 0;
- unsigned int ctrl_num;
- unsigned int dimm_num;
- unsigned int matched = 0;
+ unsigned int src_ctlr_num = 0;
+ unsigned int src_dimm_num = 0;
+ unsigned int dst_ctlr_num = -1;
+ unsigned int dst_dimm_num = -1;
+ unsigned int i, num_dest_parms;
if (argc == 1) {
- /* Only the element and value must be last */
- printf("edit <c#> <d#> "
- "<spd|dimmparms|commonparms|opts|"
- "addresses|regs> <element> <value>\n");
- printf("for spd, specify byte number for "
- "element\n");
+ printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
continue;
}
- for (i = 1; i < argc - 2; i++) {
- for (j = 0; j < n_opts; j++) {
- if (strcmp(options[j].data_name,
- argv[i]) != 0)
- continue;
- step_mask |= options[j].step_mask;
- dimm_number_required =
- options[j].dimm_number_required;
- matched = 1;
- break;
+ error = fsl_ddr_parse_interactive_cmd(
+ argv, argc,
+ &step_mask,
+ &src_ctlr_mask,
+ &src_dimm_mask,
+ &dimm_number_required
+ );
+
+ /* XXX: only dimm_number_required and step_mask will
+ be used by this function. Parse the controller and
+ DIMM number separately because it is easier. */
+
+ if (error)
+ continue;
+
+ /* parse source destination controller / DIMM */
+
+ num_dest_parms = dimm_number_required ? 2 : 1;
+
+ for (i = 0; i < argc; i++) {
+ if (argv[i][0] == 'c') {
+ char c = argv[i][1];
+ if (isdigit(c)) {
+ src_ctlr_num = (c - '0');
+ break;
+ }
}
+ }
- if (matched)
- continue;
+ for (i = 0; i < argc; i++) {
+ if (argv[i][0] == 'd') {
+ char c = argv[i][1];
+ if (isdigit(c)) {
+ src_dimm_num = (c - '0');
+ break;
+ }
+ }
+ }
+
+ /* parse destination controller / DIMM */
+ for (i = argc - 1; i >= argc - num_dest_parms; i--) {
if (argv[i][0] == 'c') {
char c = argv[i][1];
- if (isdigit(c))
- ctlr_mask |= 1 << (c - '0');
- continue;
+ if (isdigit(c)) {
+ dst_ctlr_num = (c - '0');
+ break;
+ }
}
+ }
+ for (i = argc - 1; i >= argc - num_dest_parms; i--) {
if (argv[i][0] == 'd') {
char c = argv[i][1];
- if (isdigit(c))
- dimm_mask |= 1 << (c - '0');
- continue;
+ if (isdigit(c)) {
+ dst_dimm_num = (c - '0');
+ break;
+ }
}
+ }
+
+ /* TODO: validate inputs */
+
+ debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
+ src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
- printf("unknown arg %s\n", argv[i]);
- step_mask = 0;
- error = 1;
+
+ switch (step_mask) {
+
+ case STEP_GET_SPD:
+ memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
+ &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
+ sizeof(pinfo->spd_installed_dimms[0][0]));
break;
+
+ case STEP_COMPUTE_DIMM_PARMS:
+ memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
+ &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
+ sizeof(pinfo->dimm_params[0][0]));
+ break;
+
+ case STEP_COMPUTE_COMMON_PARMS:
+ memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
+ &(pinfo->common_timing_params[src_ctlr_num]),
+ sizeof(pinfo->common_timing_params[0]));
+ break;
+
+ case STEP_GATHER_OPTS:
+ memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
+ &(pinfo->memctl_opts[src_ctlr_num]),
+ sizeof(pinfo->memctl_opts[0]));
+ break;
+
+ /* someday be able to have addresses to copy addresses... */
+
+ case STEP_COMPUTE_REGS:
+ memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
+ &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
+ sizeof(pinfo->memctl_opts[0]));
+ break;
+
+ default:
+ printf("unexpected step_mask value\n");
+ }
+
+ continue;
+
+ }
+
+ if (strcmp(argv[0], "edit") == 0) {
+ unsigned int error = 0;
+ unsigned int step_mask = 0;
+ unsigned int ctlr_mask = 0;
+ unsigned int dimm_mask = 0;
+ char *p_element = NULL;
+ char *p_value = NULL;
+ unsigned int dimm_number_required = 0;
+ unsigned int ctrl_num;
+ unsigned int dimm_num;
+
+ if (argc == 1) {
+ /* Only the element and value must be last */
+ printf("edit <c#> <d#> "
+ "<spd|dimmparms|commonparms|opts|"
+ "addresses|regs> <element> <value>\n");
+ printf("for spd, specify byte number for "
+ "element\n");
+ continue;
}
+ error = fsl_ddr_parse_interactive_cmd(
+ argv, argc - 2,
+ &step_mask,
+ &ctlr_mask,
+ &dimm_mask,
+ &dimm_number_required
+ );
if (error)
continue;
}
if (strcmp(argv[0], "print") == 0) {
- unsigned int i, j;
unsigned int error = 0;
unsigned int step_mask = 0;
unsigned int ctlr_mask = 0;
unsigned int dimm_mask = 0;
- unsigned int matched = 0;
+ unsigned int dimm_number_required = 0;
if (argc == 1) {
printf("print [c<n>] [d<n>] [spd] [dimmparms] "
continue;
}
- for (i = 1; i < argc; i++) {
- for (j = 0; j < n_opts; j++) {
- if (strcmp(options[j].data_name,
- argv[i]) != 0)
- continue;
- step_mask |= options[j].step_mask;
- matched = 1;
- break;
- }
-
- if (matched)
- continue;
-
- if (argv[i][0] == 'c') {
- char c = argv[i][1];
- if (isdigit(c))
- ctlr_mask |= 1 << (c - '0');
- continue;
- }
-
- if (argv[i][0] == 'd') {
- char c = argv[i][1];
- if (isdigit(c))
- dimm_mask |= 1 << (c - '0');
- continue;
- }
-
- printf("unknown arg %s\n", argv[i]);
- step_mask = 0;
- error = 1;
- break;
- }
+ error = fsl_ddr_parse_interactive_cmd(
+ argv, argc,
+ &step_mask,
+ &ctlr_mask,
+ &dimm_mask,
+ &dimm_number_required
+ );
if (error)
continue;
index d6b73c7af166d51cbeb292af2dfb2030e2f1f5dd..5311a262a2990ef8b52386f89a03b451772f5c26 100644 (file)
/* Compute it once normally. */
#ifdef CONFIG_FSL_DDR_INTERACTIVE
- if (getenv("ddr_interactive"))
- total_memory = fsl_ddr_interactive(&info);
- else
+ if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */
+ total_memory = fsl_ddr_interactive(&info, 0);
+ } else if (fsl_ddr_interactive_env_var_exists()) {
+ total_memory = fsl_ddr_interactive(&info, 1);
+ } else
#endif
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
index 1986fea030a4eaa25ea533c838f2d9d2810df63b..284709428d9c5c6907b43ac0a8b7e8e8bb183cb0 100644 (file)
fdt_strerror(err));
}
#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */
+static u8 caam_get_era(void)
+{
+ static const struct {
+ u16 ip_id;
+ u8 maj_rev;
+ u8 era;
+ } caam_eras[] = {
+ {0x0A10, 1, 1},
+ {0x0A10, 2, 2},
+ {0x0A12, 1, 3},
+ {0x0A14, 1, 3},
+ {0x0A14, 2, 4},
+ {0x0A16, 1, 4},
+ {0x0A10, 3, 4},
+ {0x0A11, 1, 4},
+ {0x0A18, 1, 4},
+ {0x0A11, 2, 5},
+ {0x0A12, 2, 5},
+ {0x0A13, 1, 5},
+ {0x0A1C, 1, 5}
+ };
+
+ ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ u32 secvid_ms = in_be32(&sec->secvid_ms);
+ u32 ccbvid = in_be32(&sec->ccbvid);
+ u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
+ SEC_SECVID_MS_IPID_SHIFT;
+ u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
+ SEC_SECVID_MS_MAJ_REV_SHIFT;
+ u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT;
+
+ int i;
+
+ if (era) /* This is '0' prior to CAAM ERA-6 */
+ return era;
+
+ for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
+ if (caam_eras[i].ip_id == ip_id &&
+ caam_eras[i].maj_rev == maj_rev)
+ return caam_eras[i].era;
+
+ return 0;
+}
+
+static void fdt_fixup_crypto_era(void *blob, u32 era)
+{
+ int err;
+ int crypto_node;
+
+ crypto_node = fdt_path_offset(blob, "crypto");
+ if (crypto_node < 0) {
+ printf("WARNING: Missing crypto node\n");
+ return;
+ }
+
+ err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era,
+ sizeof(era));
+ if (err < 0) {
+ printf("ERROR: could not set fsl,sec-era property: %s\n",
+ fdt_strerror(err));
+ }
+}
+
void fdt_fixup_crypto_node(void *blob, int sec_rev)
{
- if (!sec_rev)
+ u8 era;
+
+ if (!sec_rev) {
fdt_del_node_and_alias(blob, "crypto");
+ return;
+ }
+
+ /* Add SEC ERA information in compatible */
+ era = caam_get_era();
+ if (era) {
+ fdt_fixup_crypto_era(blob, era);
+ } else {
+ printf("WARNING: Unable to get ERA for CAAM rev: %d\n",
+ sec_rev);
+ }
}
#endif
index ce1d71e307a02f081e8222392a5bc53b845f574b..6f9d5683a9c7ecc36ee768b742322e202c9327f0 100644 (file)
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
- gd->used_laws |= (1 << idx);
+ gd->arch.used_laws |= (1 << idx);
out_be32(LAWAR_ADDR(idx), 0);
set_law_base_addr(idx, addr);
void disable_law(u8 idx)
{
- gd->used_laws &= ~(1 << idx);
+ gd->arch.used_laws &= ~(1 << idx);
out_be32(LAWAR_ADDR(idx), 0);
set_law_base_addr(idx, 0);
int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
- u32 idx = ffz(gd->used_laws);
+ u32 idx = ffz(gd->arch.used_laws);
if (idx >= FSL_HW_NUM_LAWS)
return -1;
u32 idx;
/* we have no LAWs free */
- if (gd->used_laws == -1)
+ if (gd->arch.used_laws == -1)
return -1;
/* grab the last free law */
- idx = __ilog2(~(gd->used_laws));
+ idx = __ilog2(~(gd->arch.used_laws));
if (idx >= FSL_HW_NUM_LAWS)
return -1;
int i;
#if FSL_HW_NUM_LAWS < 32
- gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
+ gd->arch.used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
#elif FSL_HW_NUM_LAWS == 32
- gd->used_laws = 0;
+ gd->arch.used_laws = 0;
#else
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
u32 lawar = in_be32(LAWAR_ADDR(i));
if (lawar & LAW_EN)
- gd->used_laws |= (1 << i);
+ gd->arch.used_laws |= (1 << i);
}
#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
index 38ba60bb0d6b73b5d5f3aff56de3e69b9e8e8d5e..2ab185f0fd9adc5d63e3f56bb95a9a7ea584e9bf 100644 (file)
* the UART divisor is available
*/
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
- gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
+ gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
#else
get_sys_info(&sys_info);
- gd->uart_clk = sys_info.freqUART / udiv;
+ gd->arch.uart_clk = sys_info.freqUART / udiv;
#endif
return clk;
index 5ddb8802417ea373fc65d6e6ea50524fb3163d9d..3cdd5319a9b32f10a2d663010943d551f76fb116 100644 (file)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
#include <libfdt.h>
-#include <libfdt_env.h>
#include <fdt_support.h>
#include <asm/4xx_pcie.h>
/*
* Fixup all UART clocks for CPU internal UARTs
- * (only these UARTs are definitely clocked by gd->uart_clk)
+ * (only these UARTs are definitely clocked by gd->arch.uart_clk)
*
* These UARTs are direct childs of /plb/opb. This code
* does not touch any UARTs that are connected to the ebc.
(fdt_node_check_compatible(blob, off, "ns16550") == 0))
fdt_setprop(blob, off,
"clock-frequency",
- (void*)&(gd->uart_clk), 4);
+ (void *)&gd->arch.uart_clk, 4);
}
/*
index 0b9638bceef0bf565610dbaae045aa66de83d86c..d57c178f7f23d61c2a5adcb7f2aad92900a5edfa 100644 (file)
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#elif defined(CONFIG_BSC9132)
+#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
+
#elif defined(CONFIG_PPC_T4240)
#define CONFIG_SYS_PPC64 /* 64-bit core */
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_A004468
#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_FSL_ERRATUM_A005871
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+
+#elif defined(CONFIG_PPC_B4420)
+#define CONFIG_SYS_PPC64 /* 64-bit core */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 4
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#elif defined(CONFIG_PPC_B4860)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
#define CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
index cb3a80bb2bfe8c153c540130845a91871d473854..d5db8549cc93770e8d7f5d4fd7cd96fd116768a5 100644 (file)
#include "config.h"
#include "asm/types.h"
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long cpu_clk; /* CPU clock in Hz! */
- unsigned long bus_clk;
+/* Architecture-specific global data */
+struct arch_global_data {
+#if defined(CONFIG_FSL_ESDHC)
+ u32 sdhc_clk;
+#endif
#if defined(CONFIG_8xx)
- unsigned long brg_clk;
+ unsigned long brg_clk;
#endif
#if defined(CONFIG_CPM2)
/* There are many clocks on the MPC8260 - see page 9-5 */
- unsigned long vco_out;
- unsigned long cpm_clk;
- unsigned long scc_clk;
- unsigned long brg_clk;
-#ifdef CONFIG_PCI
- unsigned long pci_clk;
-#endif
+ unsigned long vco_out;
+ unsigned long cpm_clk;
+ unsigned long scc_clk;
+ unsigned long brg_clk;
#endif
- unsigned long mem_clk;
+ /* TODO: sjg@chromium.org: Should these be unslgned long? */
#if defined(CONFIG_MPC83xx)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
-#elif defined(CONFIG_MPC8309)
+# elif defined(CONFIG_MPC8309)
u32 usbdr_clk;
-#endif
-#if defined (CONFIG_MPC834x)
+# endif
+# if defined(CONFIG_MPC834x)
u32 usbmph_clk;
-#endif /* CONFIG_MPC834x */
-#if defined(CONFIG_MPC8315)
+# endif /* CONFIG_MPC834x */
+# if defined(CONFIG_MPC8315)
u32 tdm_clk;
-#endif
+# endif
u32 core_clk;
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
- u32 pci_clk;
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
defined(CONFIG_MPC837x)
u32 pciexp1_clk;
u32 pciexp2_clk;
-#endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+# endif
+# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
u32 sata_clk;
-#endif
-#if defined(CONFIG_MPC8360)
- u32 mem_sec_clk;
-#endif /* CONFIG_MPC8360 */
-#endif
-#if defined(CONFIG_FSL_ESDHC)
- u32 sdhc_clk;
+# endif
+# if defined(CONFIG_MPC8360)
+ u32 mem_sec_clk;
+# endif /* CONFIG_MPC8360 */
#endif
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
u32 lbc_clk;
void *cpu;
#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
+ defined(CONFIG_MPC86xx)
u32 i2c1_clk;
u32 i2c2_clk;
#endif
u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
#endif
#if defined(CONFIG_MPC5xxx)
- unsigned long ipb_clk;
- unsigned long pci_clk;
+ unsigned long ipb_clk;
#endif
#if defined(CONFIG_MPC512X)
u32 ips_clk;
u32 csb_clk;
- u32 pci_clk;
#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC8220)
- unsigned long bExtUart;
- unsigned long inp_clk;
- unsigned long pci_clk;
- unsigned long vco_clk;
- unsigned long pev_clk;
- unsigned long flb_clk;
-#endif
- phys_size_t ram_size; /* RAM size */
- unsigned long reset_status; /* reset status register at boot */
-#if defined(CONFIG_MPC83xx)
- unsigned long arbiter_event_attributes;
- unsigned long arbiter_event_address;
+ unsigned long inp_clk;
+ unsigned long vco_clk;
+ unsigned long pev_clk;
+ unsigned long flb_clk;
#endif
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
+ unsigned long reset_status; /* reset status register at boot */
+#if defined(CONFIG_MPC83xx)
+ unsigned long arbiter_event_attributes;
+ unsigned long arbiter_event_address;
#endif
#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
- unsigned int dp_alloc_base;
- unsigned int dp_alloc_top;
+ unsigned int dp_alloc_base;
+ unsigned int dp_alloc_top;
#endif
#if defined(CONFIG_4xx)
- u32 uart_clk;
+ u32 uart_clk;
#endif /* CONFIG_4xx */
#if defined(CONFIG_SYS_GT_6426x)
- unsigned int mirror_hack[16];
-#endif
-#if defined(CONFIG_A3000) || \
- defined(CONFIG_HIDDEN_DRAGON) || \
- defined(CONFIG_MUSENKI) || \
- defined(CONFIG_SANDPOINT)
- void * console_addr;
-#endif
- unsigned long relocaddr; /* Start address of U-Boot in RAM */
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
- unsigned long fb_base; /* Base address of framebuffer memory */
-#endif
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
- unsigned long post_log_word; /* Record POST activities */
- unsigned long post_log_res; /* success of POST test */
- unsigned long post_init_f_time; /* When post_init_f started */
-#endif
-#ifdef CONFIG_BOARD_TYPES
- unsigned long board_type;
-#endif
-#ifdef CONFIG_MODEM_SUPPORT
- unsigned long do_mdm_init;
- unsigned long be_quiet;
-#endif
-#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
- unsigned long kbd_status;
+ unsigned int mirror_hack[16];
#endif
#ifdef CONFIG_SYS_FPGA_COUNT
unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
#if defined(CONFIG_WD_MAX_RATE)
unsigned long long wdt_last; /* trace watch-dog triggering rate */
#endif
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
+ unsigned long kbd_status;
+#endif
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
index 296b5497798ee08c86e1f9fec78c899e4a4ca93a..4eb3f7923039aec0964e899b674a890a56bd794d 100644 (file)
#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
-#elif defined(CONFIG_PPC_B4860)
+#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
#else
-#ifdef CONFIG_BSC9131
+#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#else
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
u32 porbmsr; /* POR boot mode status */
#define MPC85xx_PORBMSR_HA 0x00070000
#define MPC85xx_PORBMSR_HA_SHIFT 16
+#define MPC85XX_PORBMSR_ROMLOC_SHIFT 24
+#define PORBMSR_ROMLOC_SPI 0x6
+#define PORBMSR_ROMLOC_SDHC 0x7
+#define PORBMSR_ROMLOC_NAND_2K 0x9
+#define PORBMSR_ROMLOC_NOR 0xf
u32 porimpscr; /* POR I/O impedance status & control */
u32 pordevsr; /* POR I/O device status regsiter */
#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
#if defined(CONFIG_P1010)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
+#elif defined(CONFIG_BSC9132)
+#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
#else
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
+#endif
+#ifdef CONFIG_BSC9132
+#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
+#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
#define MPC85xx_PMUXCR2_USB 0x00150000
#endif
+#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
#if defined(CONFIG_BSC9131)
#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
+#endif
u32 pmuxcr3;
-
+#if defined(CONFIG_BSC9131)
#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
+#endif
+#ifdef CONFIG_BSC9132
+#define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
+#define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
+#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
+#define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
+#endif
u32 pmuxcr4;
#else
u8 res6[8];
#define SEC_CHANUM_MS_JRNUM_SHIFT 28
#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT 24
+#define SEC_SECVID_MS_IPID_MASK 0xffff0000
+#define SEC_SECVID_MS_IPID_SHIFT 16
+#define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
+#define SEC_SECVID_MS_MAJ_REV_SHIFT 8
+#define SEC_CCBVID_ERA_MASK 0xff000000
+#define SEC_CCBVID_ERA_SHIFT 24
#endif
typedef struct ccsr_qman {
#endif
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
+#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_SNVS_OFFSET 0xE6000
index 2e0e292da05df9e8ad8c14015478c1941b55c69d..b700a3a0bec55025a7067cfbaa0d65a89ca28c7a 100644 (file)
#define MAS1_IPROT 0x40000000
#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
#define MAS1_TS 0x00001000
-#define MAS1_TSIZE(x) (((x) << 8) & 0x00000F00)
-#define TSIZE_TO_BYTES(x) (1ULL << (((x) * 2) + 10))
+#define MAS1_TSIZE(x) (((x) << 7) & 0x00000F80)
+#define TSIZE_TO_BYTES(x) (1ULL << ((x) + 10))
#define MAS2_EPN 0xFFFFF000
#define MAS2_X0 0x00000040
#define FSL_BOOKE_MAS7(rpn) \
(((u64)(rpn)) >> 32)
-#define BOOKE_PAGESZ_1K 0
-#define BOOKE_PAGESZ_4K 1
-#define BOOKE_PAGESZ_16K 2
-#define BOOKE_PAGESZ_64K 3
-#define BOOKE_PAGESZ_256K 4
-#define BOOKE_PAGESZ_1M 5
-#define BOOKE_PAGESZ_4M 6
-#define BOOKE_PAGESZ_16M 7
-#define BOOKE_PAGESZ_64M 8
-#define BOOKE_PAGESZ_256M 9
-#define BOOKE_PAGESZ_1G 10
-#define BOOKE_PAGESZ_4G 11
-#define BOOKE_PAGESZ_16GB 12
-#define BOOKE_PAGESZ_64GB 13
-#define BOOKE_PAGESZ_256GB 14
-#define BOOKE_PAGESZ_1TB 15
+#define BOOKE_PAGESZ_1K 0
+#define BOOKE_PAGESZ_2K 1
+#define BOOKE_PAGESZ_4K 2
+#define BOOKE_PAGESZ_8K 3
+#define BOOKE_PAGESZ_16K 4
+#define BOOKE_PAGESZ_32K 5
+#define BOOKE_PAGESZ_64K 6
+#define BOOKE_PAGESZ_128K 7
+#define BOOKE_PAGESZ_256K 8
+#define BOOKE_PAGESZ_512K 9
+#define BOOKE_PAGESZ_1M 10
+#define BOOKE_PAGESZ_2M 11
+#define BOOKE_PAGESZ_4M 12
+#define BOOKE_PAGESZ_8M 13
+#define BOOKE_PAGESZ_16M 14
+#define BOOKE_PAGESZ_32M 15
+#define BOOKE_PAGESZ_64M 16
+#define BOOKE_PAGESZ_128M 17
+#define BOOKE_PAGESZ_256M 18
+#define BOOKE_PAGESZ_512M 19
+#define BOOKE_PAGESZ_1G 20
+#define BOOKE_PAGESZ_2G 21
+#define BOOKE_PAGESZ_4G 22
+#define BOOKE_PAGESZ_8G 23
+#define BOOKE_PAGESZ_16GB 24
+#define BOOKE_PAGESZ_32GB 25
+#define BOOKE_PAGESZ_64GB 26
+#define BOOKE_PAGESZ_128GB 27
+#define BOOKE_PAGESZ_256GB 28
+#define BOOKE_PAGESZ_512GB 29
+#define BOOKE_PAGESZ_1TB 30
+#define BOOKE_PAGESZ_2TB 31
#define TLBIVAX_ALL 4
#define TLBIVAX_TLB0 0
index 19fe250305729f29dabeba4438e034143903d938..8c91f0849b86899c860d1d08b1640183f677d8b4 100644 (file)
#define SVR_9130 0x860001
#define SVR_9131 0x860000
+#define SVR_9132 0x861000
+#define SVR_9232 0x861400
#define SVR_Unknown 0xFFFFFF
index 844fe8636de9f2a4a92178c76a46dd4cd4ddc921..86cf02ace4147f8fc29ad727dc5e44879844b632 100644 (file)
endif
ifdef MINIMAL
-COBJS-y += cache.o
+COBJS-y += cache.o time.o
+SOBJS-y += ticks.o
else
SOBJS-y += ppcstring.o
index 6a7bf4b6c21588a02b3d3bb57ed751948e5ceb73..12270a4533a3c79de111ce64941c2ccd379ffff1 100644 (file)
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
#endif
#if defined(CONFIG_MPC8220)
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
- bd->bi_inpfreq = gd->inp_clk;
+ bd->bi_inpfreq = gd->arch.inp_clk;
bd->bi_pcifreq = gd->pci_clk;
- bd->bi_vcofreq = gd->vco_clk;
- bd->bi_pevfreq = gd->pev_clk;
- bd->bi_flbfreq = gd->flb_clk;
+ bd->bi_vcofreq = gd->arch.vco_clk;
+ bd->bi_pevfreq = gd->arch.pev_clk;
+ bd->bi_flbfreq = gd->arch.flb_clk;
/* store bootparam to sram (backward compatible), here? */
{
*sram++ = gd->ram_size;
*sram++ = gd->bus_clk;
- *sram++ = gd->inp_clk;
+ *sram++ = gd->arch.inp_clk;
*sram++ = gd->cpu_clk;
- *sram++ = gd->vco_clk;
- *sram++ = gd->flb_clk;
+ *sram++ = gd->arch.vco_clk;
+ *sram++ = gd->arch.flb_clk;
*sram++ = 0xb8c3ba11; /* boot signature */
}
#endif
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
#if defined(CONFIG_CPM2)
- bd->bi_cpmfreq = gd->cpm_clk;
- bd->bi_brgfreq = gd->brg_clk;
- bd->bi_sccfreq = gd->scc_clk;
- bd->bi_vco = gd->vco_out;
+ bd->bi_cpmfreq = gd->arch.cpm_clk;
+ bd->bi_brgfreq = gd->arch.brg_clk;
+ bd->bi_sccfreq = gd->arch.scc_clk;
+ bd->bi_vco = gd->arch.vco_out;
#endif /* CONFIG_CPM2 */
#if defined(CONFIG_MPC512X)
- bd->bi_ipsfreq = gd->ips_clk;
+ bd->bi_ipsfreq = gd->arch.ips_clk;
#endif /* CONFIG_MPC512X */
#if defined(CONFIG_MPC5xxx)
- bd->bi_ipbfreq = gd->ipb_clk;
+ bd->bi_ipbfreq = gd->arch.ipb_clk;
bd->bi_pcifreq = gd->pci_clk;
#endif /* CONFIG_MPC5xxx */
bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
/*
- * The gd->cpu pointer is set to an address in flash before relocation.
- * We need to update it to point to the same CPU entry in RAM.
+ * The gd->arch.cpu pointer is set to an address in flash before
+ * relocation. We need to update it to point to the same CPU entry
+ * in RAM.
*/
- gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
+ gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
/*
* If we didn't know the cpu mask & # cores, we can save them of
index 7088293a3647a6c249369a1e2d436497feb70c8b..0119a7b6ebf7e6c1a6edb7ce43fb14fa1bfdc389 100644 (file)
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
#include <asm/mp.h>
#if defined(CONFIG_OF_LIBFDT)
-#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
-
#endif
#ifdef CONFIG_SYS_INIT_RAM_LOCK
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index d7684d38eb7f9b35909a5ad625f063bc22ab552e..b2788d5d536280a55733d3b43a764eb05bb3c7b1 100644 (file)
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
- return (void *)(gd->ram_buf + paddr);
+ return (void *)(gd->arch.ram_buf + paddr);
}
void flush_dcache_range(unsigned long start, unsigned long stop)
index 78a751d96f76bbeb28de499bdfce2ca4c8d7eda2..3bedf77c5cbed56a291e50683865ad9f32c0c8d5 100644 (file)
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long have_console; /* serial_init() was called */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- unsigned long fb_base; /* base address of frame buffer */
+/* Architecture-specific global data */
+struct arch_global_data {
u8 *ram_buf; /* emulated RAM buffer */
- phys_size_t ram_size; /* RAM size */
- const void *fdt_blob; /* Our device tree, NULL if none */
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR extern gd_t *gd
index 83858c1ffe5ca7c738fc6fe79fd95958910fcdb9..3752fab5020223241e76719c1be81da08f9e83c6 100644 (file)
--- a/arch/sandbox/lib/board.c
+++ b/arch/sandbox/lib/board.c
mem = os_malloc(CONFIG_SYS_SDRAM_SIZE);
assert(mem);
- gd->ram_buf = mem;
+ gd->arch.ram_buf = mem;
addr = (ulong)(mem + size);
/*
#endif
/* The Malloc area is at the top of simulated DRAM */
- mem_malloc_init((ulong)gd->ram_buf + gd->ram_size - TOTAL_MALLOC_LEN,
- TOTAL_MALLOC_LEN);
+ mem_malloc_init((ulong)gd->arch.ram_buf + gd->ram_size -
+ TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN);
/* initialize environment */
env_relocate();
index 9a2c19376daed36399086f48ff7b095b39e5aef2..0360230043247004436219dc849bfb73f5790341 100644 (file)
#ifndef __ASM_SH_GLOBALDATA_H_
#define __ASM_SH_GLOBALDATA_H_
-typedef struct global_data
-{
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long cpu_clk; /* CPU clock in Hz! */
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
-#endif
- phys_size_t ram_size; /* RAM size */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid */
- void **jt; /* Standalone app jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13")
index aa63b35cab14669d98cabd409537837b8fe510db..9f019b133144d8dbcbf339198f504e9a3f490ec9 100644 (file)
#include "asm/types.h"
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
-
-typedef struct global_data {
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long cpu_clk; /* CPU clock in Hz! */
- unsigned long bus_clk;
-
- phys_size_t ram_size; /* RAM size */
- unsigned long reloc_off; /* Relocation Offset */
- unsigned long reset_status; /* reset status register at boot */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- unsigned long have_console; /* serial_init() was called */
-
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
-#endif
-#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
- unsigned long fb_base; /* Base address of framebuffer memory */
-#endif
-#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
- unsigned long post_log_word; /* Record POST activities */
- unsigned long post_log_res; /* success of POST test */
- unsigned long post_init_f_time; /* When post_init_f started */
-#endif
-#ifdef CONFIG_BOARD_TYPES
- unsigned long board_type;
-#endif
-#ifdef CONFIG_MODEM_SUPPORT
- unsigned long do_mdm_init;
- unsigned long be_quiet;
-#endif
-#ifdef CONFIG_LWMON
- unsigned long kbd_status;
-#endif
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-} gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+};
-#include <asm-generic/global_data_flags.h>
+#include <asm-generic/global_data.h>
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("%g7")
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 57324b61749edbeb3fadfe045252d3fd7a8560a5..7b520f8dca165a8c7dcaea387cf6da5f97e6f535 100644 (file)
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
LIB = $(obj)lib$(CPU).o
START-y = start.o
-RESET_OBJS-$(CONFIG_X86_NO_RESET_VECTOR) += resetvec.o start16.o
+START-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
COBJS = interrupts.o cpu.o timer.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-START := $(addprefix $(obj),$(START-y) $(RESET_OBJS-))
+START := $(addprefix $(obj),$(START-y))
all: $(obj).depend $(START) $(LIB)
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 315e87afeb2120e4dab4929f7a6eac225348cfa6..6a23974ff58f1b54bfd4a293803b23d33e7b873d 100644 (file)
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
/* FS: data, read/write, 4 GB, base (Global Data Pointer) */
- gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093, (ulong)id, 0xfffff);
+ id->arch.gd_addr = id;
+ gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
+ (ulong)&id->arch.gd_addr, 0xfffff);
/* 16-bit CS: code, read/execute, 64 kB, base 0 */
gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff);
diff --git a/arch/x86/cpu/sc520/Makefile b/arch/x86/cpu/sc520/Makefile
+++ /dev/null
@@ -1,58 +0,0 @@
-#
-# (C) Copyright 2008
-# Graeme Russ, graeme.russ@gmail.com.
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB := $(obj)lib$(SOC).o
-
-COBJS-$(CONFIG_SYS_SC520) += sc520.o
-COBJS-$(CONFIG_PCI) += sc520_pci.o
-COBJS-$(CONFIG_SYS_SC520_RESET) += sc520_reset.o
-COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o
-COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
-COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
-
-SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
-
-SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
\ No newline at end of file
diff --git a/arch/x86/cpu/sc520/asm-offsets.c b/arch/x86/cpu/sc520/asm-offsets.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <common.h>
-#include <asm/arch/sc520.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
- DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
-
- DEFINE(GENERATED_SC520_PAR0, offsetof(struct sc520_mmcr, par[0]));
- DEFINE(GENERATED_SC520_PAR1, offsetof(struct sc520_mmcr, par[1]));
- DEFINE(GENERATED_SC520_PAR2, offsetof(struct sc520_mmcr, par[2]));
- DEFINE(GENERATED_SC520_PAR3, offsetof(struct sc520_mmcr, par[3]));
- DEFINE(GENERATED_SC520_PAR4, offsetof(struct sc520_mmcr, par[4]));
- DEFINE(GENERATED_SC520_PAR5, offsetof(struct sc520_mmcr, par[5]));
- DEFINE(GENERATED_SC520_PAR6, offsetof(struct sc520_mmcr, par[6]));
- DEFINE(GENERATED_SC520_PAR7, offsetof(struct sc520_mmcr, par[7]));
- DEFINE(GENERATED_SC520_PAR8, offsetof(struct sc520_mmcr, par[8]));
- DEFINE(GENERATED_SC520_PAR9, offsetof(struct sc520_mmcr, par[9]));
- DEFINE(GENERATED_SC520_PAR10, offsetof(struct sc520_mmcr, par[10]));
- DEFINE(GENERATED_SC520_PAR11, offsetof(struct sc520_mmcr, par[11]));
- DEFINE(GENERATED_SC520_PAR12, offsetof(struct sc520_mmcr, par[12]));
- DEFINE(GENERATED_SC520_PAR13, offsetof(struct sc520_mmcr, par[13]));
- DEFINE(GENERATED_SC520_PAR14, offsetof(struct sc520_mmcr, par[14]));
- DEFINE(GENERATED_SC520_PAR15, offsetof(struct sc520_mmcr, par[15]));
-
- return 0;
-}
diff --git a/arch/x86/cpu/sc520/sc520.c b/arch/x86/cpu/sc520/sc520.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <asm/arch/sc520.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
-
-int cpu_init_f(void)
-{
- if (CONFIG_SYS_SC520_HIGH_SPEED) {
- /* set it to 133 MHz and write back */
- writeb(0x02, &sc520_mmcr->cpuctl);
- gd->cpu_clk = 133000000;
- } else {
- /* set it to 100 MHz and write back */
- writeb(0x01, &sc520_mmcr->cpuctl);
- gd->cpu_clk = 100000000;
- }
-
- /* wait at least one millisecond */
- asm("movl $0x2000, %%ecx\n"
- "0: pushl %%ecx\n"
- "popl %%ecx\n"
- "loop 0b\n" : : : "ecx");
-
- return x86_cpu_init_f();
-}
-
-int cpu_init_r(void)
-{
- /* Disable the PAR used for CAR */
- writel(0x0000000, &sc520_mmcr->par[2]);
-
- /* turn on the SDRAM write buffer */
- writeb(0x11, &sc520_mmcr->dbctl);
-
- return x86_cpu_init_r();
-}
diff --git a/arch/x86/cpu/sc520/sc520_car.S b/arch/x86/cpu/sc520/sc520_car.S
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * (C) Copyright 2010-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/processor-flags.h>
-#include <asm/arch/sc520.h>
-#include <generated/asm-offsets.h>
-
-.section .text
-
-.globl car_init
-car_init:
- /*
- * How to enable Cache-As-RAM for the AMD Elan SC520:
- * 1. Turn off the CPU Cache (may not be strictly required)
- * 2. Set code execution PAR (usually the BOOTCS region) to be
- * non-cachable
- * 3. Create a Cachable PAR Region for an area of memory which is
- * a) NOT where the code is being executed
- * b) NOT SDRAM (Controller not initialised yet)
- * c) WILL response to read requests
- * The easiest way to do this is to create a second BOOTCS
- * PAR mappnig with an address != the PAR in step 2
- * 4. Issue a wbinvd to invalidate the CPU cache
- * 5. Turn on the CPU Cache
- * 6. Read 16kB from the cached PAR region setup in step 3
- * 7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
- *
- * The following code uses PAR2 as the cached PAR (PAR0 and PAR1
- * are avoided as these are the only two PARs which can be used
- * as PCI BUS Memory regions which the board might require)
- *
- * The configuration of PAR2 must be set in the board configuration
- * file as CONFIG_SYS_SC520_CAR_PAR
- */
-
- /* Configure Cache-As-RAM PAR */
- movl $CONFIG_SYS_SC520_CAR_PAR, %eax
- movl $(SC520_MMCR_BASE + GENERATED_SC520_PAR2), %edi
- movl %eax, (%edi)
-
- /* Trash the cache then turn it on */
- wbinvd
- movl %cr0, %eax
- andl $~(X86_CR0_NW | X86_CR0_CD), %eax
- movl %eax, %cr0
-
- /*
- * The cache is now enabled and empty. Map a region of memory to
- * it by reading that region.
- */
- movl $CONFIG_SYS_CAR_ADDR, %esi
- movl $CONFIG_SYS_CAR_SIZE, %ecx
- shrl $2, %ecx /* we are reading longs */
- cld
- rep lodsl
-
- /* Turn off the cache, but don't trash it */
- movl %cr0, %eax
- orl $(X86_CR0_NW | X86_CR0_CD), %eax
- movl %eax, %cr0
-
- /* Clear the CAR region */
- xorl %eax, %eax
- movl $CONFIG_SYS_CAR_ADDR, %edi
- movl $CONFIG_SYS_CAR_SIZE, %ecx
- shrl $2, %ecx /* we are writing longs */
- rep stosl
-
- /*
- * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
- * Cache-As-RAM
- */
- jmp car_init_ret
diff --git a/arch/x86/cpu/sc520/sc520_pci.c b/arch/x86/cpu/sc520/sc520_pci.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pci.h>
-#include <asm/arch/sc520.h>
-
-static struct {
- u8 priority;
- u16 level_reg;
- u8 level_bit;
-} sc520_irq[] = {
- { SC520_IRQ0, 0, 0x01 },
- { SC520_IRQ1, 0, 0x02 },
- { SC520_IRQ2, 1, 0x02 },
- { SC520_IRQ3, 0, 0x08 },
- { SC520_IRQ4, 0, 0x10 },
- { SC520_IRQ5, 0, 0x20 },
- { SC520_IRQ6, 0, 0x40 },
- { SC520_IRQ7, 0, 0x80 },
-
- { SC520_IRQ8, 1, 0x01 },
- { SC520_IRQ9, 1, 0x02 },
- { SC520_IRQ10, 1, 0x04 },
- { SC520_IRQ11, 1, 0x08 },
- { SC520_IRQ12, 1, 0x10 },
- { SC520_IRQ13, 1, 0x20 },
- { SC520_IRQ14, 1, 0x40 },
- { SC520_IRQ15, 1, 0x80 }
-};
-
-/* The interrupt used for PCI INTA-INTD */
-int sc520_pci_ints[15] = {
- -1, -1, -1, -1, -1, -1, -1, -1,
- -1, -1, -1, -1, -1, -1, -1
-};
-
-/* utility function to configure a pci interrupt */
-int pci_sc520_set_irq(int pci_pin, int irq)
-{
- int i;
- u8 tmpb;
- u16 tmpw;
-
- debug("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
-
- if (irq < 0 || irq > 15)
- return -1; /* illegal irq */
-
- if (pci_pin < 0 || pci_pin > 15)
- return -1; /* illegal pci int pin */
-
- /* first disable any non-pci interrupt source that use
- * this level */
-
- /* PCI interrupt mapping (A through D)*/
- for (i = 0; i <= 3 ; i++) {
- tmpb = readb(&sc520_mmcr->pci_int_map[i]);
-
- if (tmpb == sc520_irq[irq].priority)
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[i]);
- }
-
- /* GP IRQ interrupt mapping */
- for (i = 0; i <= 10 ; i++) {
- tmpb = readb(&sc520_mmcr->gp_int_map[i]);
-
- if (tmpb == sc520_irq[irq].priority)
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_int_map[i]);
- }
-
- /* Set the trigger to level */
- tmpb = readb(&sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
- tmpb |= sc520_irq[irq].level_bit;
- writeb(tmpb, &sc520_mmcr->pic_mode[sc520_irq[irq].level_reg]);
-
-
- if (pci_pin < 4) {
- /* PCI INTA-INTD */
- /* route the interrupt */
- writeb(sc520_irq[irq].priority,
- &sc520_mmcr->pci_int_map[pci_pin]);
- } else {
- /* GPIRQ0-GPIRQ10 used for additional PCI INTS */
- writeb(sc520_irq[irq].priority,
- &sc520_mmcr->gp_int_map[pci_pin - 4]);
-
- /* also set the polarity in this case */
- tmpw = readw(&sc520_mmcr->intpinpol);
- tmpw |= (1 << (pci_pin-4));
- writew(tmpw, &sc520_mmcr->intpinpol);
- }
-
- /* register the pin */
- sc520_pci_ints[pci_pin] = irq;
-
-
- return 0; /* OK */
-}
-
-void pci_sc520_init(struct pci_controller *hose)
-{
- hose->first_busno = 0;
- hose->last_busno = 0xff;
- hose->region_count = pci_set_regions(hose);
-
- pci_setup_type1(hose);
-
- pci_register_hose(hose);
-
- hose->last_busno = pci_hose_scan(hose);
-
- /* enable target memory acceses on host brige */
- pci_write_config_word(0, PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-}
diff --git a/arch/x86/cpu/sc520/sc520_sdram.c b/arch/x86/cpu/sc520/sc520_sdram.c
+++ /dev/null
@@ -1,479 +0,0 @@
-/*
- * (C) Copyright 2010,2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <asm/arch/sc520.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct sc520_sdram_info {
- u8 banks;
- u8 columns;
- u8 rows;
- u8 size;
-};
-
-static void sc520_sizemem(void);
-static void sc520_set_dram_timing(void);
-static void sc520_set_dram_refresh_rate(void);
-static void sc520_enable_dram_refresh(void);
-static void sc520_enable_sdram(void);
-
-int dram_init_f(void)
-{
- sc520_sizemem();
- sc520_set_dram_timing();
- sc520_set_dram_refresh_rate();
- sc520_enable_dram_refresh();
- sc520_enable_sdram();
-
- return 0;
-}
-
-static inline void sc520_dummy_write(void)
-{
- writew(0x0000, CACHELINESZ);
-}
-static inline void sc520_issue_sdram_op_mode_select(u8 command)
-{
- writeb(command, &sc520_mmcr->drcctl);
- sc520_dummy_write();
-}
-
-static inline int check_long(u32 test_long)
-{
- u8 i;
- u8 tmp_byte = (u8)(test_long & 0x000000ff);
-
- for (i = 1; i < 4; i++) {
- if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte)
- return -1;
- }
-
- return 0;
-}
-
-static inline int write_and_test(u32 data, u32 address)
-{
- writel(data, address);
- if (readl(address) == data)
- return 0; /* Good */
- else
- return -1; /* Bad */
-}
-
-static void sc520_enable_sdram(void)
-{
- u32 par_config;
-
- /* Enable Writes, Caching and Code Execution to SDRAM */
- par_config = readl(&sc520_mmcr->par[3]);
- par_config &= ~(SC520_PAR_EXEC_DIS |
- SC520_PAR_CACHE_DIS |
- SC520_PAR_WRITE_DIS);
- writel(par_config, &sc520_mmcr->par[3]);
-
- par_config = readl(&sc520_mmcr->par[4]);
- par_config &= ~(SC520_PAR_EXEC_DIS |
- SC520_PAR_CACHE_DIS |
- SC520_PAR_WRITE_DIS);
- writel(par_config, &sc520_mmcr->par[4]);
-}
-
-static void sc520_set_dram_timing(void)
-{
- u8 drctmctl = 0x00;
-
-#if defined CONFIG_SYS_SDRAM_DRCTMCTL
- /* just have your hardware designer _GIVE_ you what you need here! */
- drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL;
-#else
- switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) {
- case 2:
- break;
- case 3:
- drctmctl |= 0x01;
- break;
- case 4:
- default:
- drctmctl |= 0x02;
- break;
- }
-
- switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) {
- case 2:
- break;
- case 3:
- drctmctl |= 0x04;
- break;
- case 4:
- default:
- drctmctl |= 0x08;
- break;
-
- case 6:
- drctmctl |= 0x0c;
- break;
- }
-
- switch (CONFIG_SYS_SDRAM_CAS_LATENCY) {
- case 2:
- break;
- case 3:
- default:
- drctmctl |= 0x10;
- break;
- }
-#endif
- writeb(drctmctl, &sc520_mmcr->drctmctl);
-
- /* Issue load mode register command */
- sc520_issue_sdram_op_mode_select(0x03);
-}
-
-static void sc520_set_dram_refresh_rate(void)
-{
- u8 drctl;
-
- drctl = readb(&sc520_mmcr->drcctl);
- drctl &= 0xcf;
-
- switch (CONFIG_SYS_SDRAM_REFRESH_RATE) {
- case 78:
- break;
- case 156:
- default:
- drctl |= 0x10;
- break;
- case 312:
- drctl |= 0x20;
- break;
- case 624:
- drctl |= 0x30;
- break;
- }
-
- writeb(drctl, &sc520_mmcr->drcctl);
-}
-
-static void sc520_enable_dram_refresh(void)
-{
- u8 drctl;
-
- drctl = readb(&sc520_mmcr->drcctl);
- drctl &= 0x30; /* keep refresh rate */
- drctl |= 0x08; /* enable refresh, normal mode */
-
- writeb(drctl, &sc520_mmcr->drcctl);
-}
-
-static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info)
-{
- u32 col_data;
- u32 row_data;
-
- u32 drcbendadr;
- u16 drccfg;
-
- u8 banks = 0x00;
- u8 columns = 0x00;
- u8 rows = 0x00;
-
- bank_info->banks = 0x00;
- bank_info->columns = 0x00;
- bank_info->rows = 0x00;
- bank_info->size = 0x00;
-
- if ((bank < 0) || (bank > 3)) {
- printf("Bad Bank ID\n");
- return;
- }
-
- /* Save configuration */
- drcbendadr = readl(&sc520_mmcr->drcbendadr);
- drccfg = readw(&sc520_mmcr->drccfg);
-
- /* Setup SDRAM Bank to largest possible size */
- writew(0x000b << (bank * 4), &sc520_mmcr->drccfg);
-
- /* Set ending address for this bank */
- writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr);
-
- /* write col 11 wrap adr */
- if (write_and_test(COL11_DATA, COL11_ADR) != 0)
- goto restore_and_exit;
-
- /* write col 10 wrap adr */
- if (write_and_test(COL10_DATA, COL10_ADR) != 0)
- goto restore_and_exit;
-
- /* write col 9 wrap adr */
- if (write_and_test(COL09_DATA, COL09_ADR) != 0)
- goto restore_and_exit;
-
- /* write col 8 wrap adr */
- if (write_and_test(COL08_DATA, COL08_ADR) != 0)
- goto restore_and_exit;
-
- col_data = readl(COL11_ADR);
-
- /* All four bytes in the read long must be the same */
- if (check_long(col_data) < 0)
- goto restore_and_exit;
-
- if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA))
- columns = (u8)(col_data & 0x000000ff);
- else
- goto restore_and_exit;
-
- /* write row 14 wrap adr */
- if (write_and_test(ROW14_DATA, ROW14_ADR) != 0)
- goto restore_and_exit;
-
- /* write row 13 wrap adr */
- if (write_and_test(ROW13_DATA, ROW13_ADR) != 0)
- goto restore_and_exit;
-
- /* write row 12 wrap adr */
- if (write_and_test(ROW12_DATA, ROW12_ADR) != 0)
- goto restore_and_exit;
-
- /* write row 11 wrap adr */
- if (write_and_test(ROW11_DATA, ROW11_ADR) != 0)
- goto restore_and_exit;
-
- if (write_and_test(ROW10_DATA, ROW10_ADR) != 0)
- goto restore_and_exit;
-
- /*
- * read data @ row 12 wrap adr to determine number of banks,
- * and read data @ row 14 wrap adr to determine number of rows.
- * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
- * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
- * if data @ row 12 wrap == 11 or 12, we have 4 banks,
- */
- row_data = readl(ROW12_ADR);
-
- /* All four bytes in the read long must be the same */
- if (check_long(row_data) != 0)
- goto restore_and_exit;
-
- switch (row_data) {
- case ROW10_DATA:
- banks = 2;
- break;
-
- case ROW11_DATA:
- case ROW12_DATA:
- banks = 4;
- break;
-
- default:
- goto restore_and_exit;
- }
-
- row_data = readl(ROW14_ADR);
-
- /* All four bytes in the read long must be the same */
- if (check_long(row_data) != 0)
- goto restore_and_exit;
-
- switch (row_data) {
- case ROW11_DATA:
- case ROW12_DATA:
- case ROW13_DATA:
- case ROW14_DATA:
- rows = (u8)(row_data & 0x000000ff);
- break;
-
- default:
- goto restore_and_exit;
- }
-
- bank_info->banks = banks;
- bank_info->columns = columns;
- bank_info->rows = rows;
-
- if ((bank_info->banks != 0) &&
- (bank_info->columns != 0) &&
- (bank_info->rows != 0)) {
- bank_info->size = bank_info->rows;
- bank_info->size >>= (11 - bank_info->columns);
- bank_info->size++;
- }
-
-restore_and_exit:
- /* Restore configuration */
- writel(drcbendadr, &sc520_mmcr->drcbendadr);
- writew(drccfg, &sc520_mmcr->drccfg);
-}
-
-static void sc520_setup_sizemem(void)
-{
- u8 i;
-
- /* Disable write buffer */
- writeb(0x00, &sc520_mmcr->dbctl);
-
- /* Disable ECC */
- writeb(0x00, &sc520_mmcr->eccctl);
-
- /* Set slowest SDRAM timing */
- writeb(0x1e, &sc520_mmcr->drctmctl);
-
- /* Issue a NOP to all SDRAM banks */
- sc520_issue_sdram_op_mode_select(0x01);
-
- /* Delay for 100 microseconds */
- udelay(100);
-
- /* Issue 'All Banks Precharge' command */
- sc520_issue_sdram_op_mode_select(0x02);
-
- /* Issue 2 'Auto Refresh Enable' command */
- sc520_issue_sdram_op_mode_select(0x04);
- sc520_dummy_write();
-
- /* Issue 'Load Mode Register' command */
- sc520_issue_sdram_op_mode_select(0x03);
-
- /* Issue 8 more 'Auto Refresh Enable' commands */
- sc520_issue_sdram_op_mode_select(0x04);
- for (i = 0; i < 7; i++)
- sc520_dummy_write();
-
- /* Set control register to 'Normal Mode' */
- writeb(0x00, &sc520_mmcr->drcctl);
-}
-
-static void sc520_sizemem(void)
-{
- struct sc520_sdram_info sdram_info[4];
- u8 bank_config = 0x00;
- u8 end_addr = 0x00;
- u16 drccfg = 0x0000;
- u32 drcbendadr = 0x00000000;
- u8 i;
-
- /* Use PARs to disable caching of maximum allowable 256MB SDRAM */
- writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[3]);
- writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[4]);
-
- sc520_setup_sizemem();
-
- gd->ram_size = 0;
-
- /* Size each SDRAM bank */
- for (i = 0; i <= 3; i++) {
- sc520_get_bank_info(i, &sdram_info[i]);
-
- if (sdram_info[i].banks != 0) {
- /* Update Configuration register */
- bank_config = sdram_info[i].columns - 8;
-
- if (sdram_info[i].banks == 4)
- bank_config |= 0x08;
-
- drccfg |= bank_config << (i * 4);
-
- /* Update End Address register */
- end_addr += sdram_info[i].size;
- drcbendadr |= (end_addr | 0x80) << (i * 8);
-
- gd->ram_size += sdram_info[i].size << 22;
- }
-
- /* Issue 'All Banks Precharge' command */
- sc520_issue_sdram_op_mode_select(0x02);
-
- /* Set control register to 'Normal Mode' */
- writeb(0x00, &sc520_mmcr->drcctl);
- }
-
- writel(drcbendadr, &sc520_mmcr->drcbendadr);
- writew(drccfg, &sc520_mmcr->drccfg);
-
- /* Clear PARs preventing caching of SDRAM */
- writel(0x00000000, &sc520_mmcr->par[3]);
- writel(0x00000000, &sc520_mmcr->par[4]);
-}
-
-int dram_init(void)
-{
- ulong dram_ctrl;
- ulong dram_present = 0x00000000;
-
- /*
- * We read-back the configuration of the dram
- * controller that the assembly code wrote
- */
- dram_ctrl = readl(&sc520_mmcr->drcbendadr);
-
- gd->bd->bi_dram[0].start = 0;
- if (dram_ctrl & 0x80) {
- /* bank 0 enabled */
- gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
- dram_present = gd->bd->bi_dram[1].start;
- gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start;
- } else {
- gd->bd->bi_dram[0].size = 0;
- gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start;
- }
-
- if (dram_ctrl & 0x8000) {
- /* bank 1 enabled */
- gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
- dram_present = gd->bd->bi_dram[2].start;
- gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start -
- gd->bd->bi_dram[1].start;
- } else {
- gd->bd->bi_dram[1].size = 0;
- gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start;
- }
-
- if (dram_ctrl & 0x800000) {
- /* bank 2 enabled */
- gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
- dram_present = gd->bd->bi_dram[3].start;
- gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start -
- gd->bd->bi_dram[2].start;
- } else {
- gd->bd->bi_dram[2].size = 0;
- gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start;
- }
-
- if (dram_ctrl & 0x80000000) {
- /* bank 3 enabled */
- dram_present = (dram_ctrl & 0x7f000000) >> 2;
- gd->bd->bi_dram[3].size = dram_present -
- gd->bd->bi_dram[3].start;
- } else {
- gd->bd->bi_dram[3].size = 0;
- }
-
- gd->ram_size = dram_present;
-
- return 0;
-}
diff --git a/arch/x86/cpu/sc520/sc520_ssi.c b/arch/x86/cpu/sc520/sc520_ssi.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ssi.h>
-#include <asm/arch/sc520.h>
-
-int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
-{
- u8 temp = 0;
-
- if (freq >= 8192)
- temp |= CTL_CLK_SEL_4;
- else if (freq >= 4096)
- temp |= CTL_CLK_SEL_8;
- else if (freq >= 2048)
- temp |= CTL_CLK_SEL_16;
- else if (freq >= 1024)
- temp |= CTL_CLK_SEL_32;
- else if (freq >= 512)
- temp |= CTL_CLK_SEL_64;
- else if (freq >= 256)
- temp |= CTL_CLK_SEL_128;
- else if (freq >= 128)
- temp |= CTL_CLK_SEL_256;
- else
- temp |= CTL_CLK_SEL_512;
-
- if (!lsb_first)
- temp |= MSBF_ENB;
-
- if (inv_clock)
- temp |= CLK_INV_ENB;
-
- if (inv_phase)
- temp |= PHS_INV_ENB;
-
- writeb(temp, &sc520_mmcr->ssictl);
-
- return 0;
-}
-
-u8 ssi_txrx_byte(u8 data)
-{
- writeb(data, &sc520_mmcr->ssixmit);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
- ;
- writeb(SSICMD_CMD_SEL_XMITRCV, &sc520_mmcr->ssicmd);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
- ;
-
- return readb(&sc520_mmcr->ssircv);
-}
-
-void ssi_tx_byte(u8 data)
-{
- writeb(data, &sc520_mmcr->ssixmit);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
- ;
- writeb(SSICMD_CMD_SEL_XMIT, &sc520_mmcr->ssicmd);
-}
-
-u8 ssi_rx_byte(void)
-{
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
- ;
- writeb(SSICMD_CMD_SEL_RCV, &sc520_mmcr->ssicmd);
- while (readb(&sc520_mmcr->ssista) & SSISTA_BSY)
- ;
-
- return readb(&sc520_mmcr->ssircv);
-}
diff --git a/arch/x86/cpu/sc520/sc520_timer.c b/arch/x86/cpu/sc520/sc520_timer.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2008-2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/interrupt.h>
-#include <asm/arch/sc520.h>
-
-void sc520_timer_isr(void)
-{
- /* Ack the GP Timer Interrupt */
- writeb(0x02, &sc520_mmcr->gptmrsta);
-}
-
-int timer_init(void)
-{
- /* Register the SC520 specific timer interrupt handler */
- register_timer_isr(sc520_timer_isr);
-
- /* Install interrupt handler for GP Timer 1 */
- irq_install_handler (0, timer_isr, NULL);
-
- /* Map GP Timer 1 to Master PIC IR0 */
- writeb(0x01, &sc520_mmcr->gp_tmr_int_map[1]);
-
- /* Disable GP Timers 1 & 2 - Allow configuration writes */
- writew(0x4000, &sc520_mmcr->gptmr1ctl);
- writew(0x4000, &sc520_mmcr->gptmr2ctl);
-
- /* Reset GP Timers 1 & 2 */
- writew(0x0000, &sc520_mmcr->gptmr1cnt);
- writew(0x0000, &sc520_mmcr->gptmr2cnt);
-
- /* Setup GP Timer 2 as a 100kHz (10us) prescaler */
- writew(83, &sc520_mmcr->gptmr2maxcmpa);
- writew(0xc001, &sc520_mmcr->gptmr2ctl);
-
- /* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
- writew(100, &sc520_mmcr->gptmr1maxcmpa);
- writew(0xe009, &sc520_mmcr->gptmr1ctl);
-
- unmask_irq(0);
-
- /* Clear the GP Timer 1 status register to get the show rolling*/
- writeb(0x02, &sc520_mmcr->gptmrsta);
-
- return 0;
-}
-
-/* Allow boards to override udelay implementation */
-void __udelay(unsigned long usec)
- __attribute__((weak, alias("sc520_udelay")));
-
-void sc520_udelay(unsigned long usec)
-{
- int m = 0;
- long u;
-
- readw(&sc520_mmcr->swtmrmilli);
- readw(&sc520_mmcr->swtmrmicro);
-
- do {
- m += readw(&sc520_mmcr->swtmrmilli);
- u = readw(&sc520_mmcr->swtmrmicro) + (m * 1000);
- } while (u < usec);
-}
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index e960e21f6e49d88979b3b502e163f646920dc41d..f389584567cf2823e64e3ed515823585d7875802 100644 (file)
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
/* Set second parameter to setup_gdt */
movl %esp, %edx
- /* gd->gd_addr = gd (Required to allow gd->xyz to work) */
- movl %eax, (%eax)
-
/* Setup global descriptor table so gd->xyz works */
call setup_gdt
/* Set second parameter to setup_gdt */
movl %esp, %edx
- /* gd->gd_addr = gd (Required to allow gd->xyz to work) */
- movl %eax, (%eax)
-
/* Setup global descriptor table so gd->xyz works */
call setup_gdt
index 0c6f0e31d8365309f0c6e19bb5cb04a9a423fdee..2313cd793a281fc2a1ac57b0794e63b70de94665 100644 (file)
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
__bios_start = LOADADDR(.bios);
__bios_size = SIZEOF(.bios);
-#ifndef CONFIG_X86_NO_RESET_VECTOR
+#ifdef CONFIG_X86_RESET_VECTOR
/*
* The following expressions place the 16-bit Real-Mode code and
diff --git a/arch/x86/include/asm/arch-coreboot/sysinfo.h b/arch/x86/include/asm/arch-coreboot/sysinfo.h
index 77ae304969ca3fa8d831b51f73e009423f3f1120..78d3a9d49ea06785871d99faf99e12cf5dad64b8 100644 (file)
#include <common.h>
#include <compiler.h>
-#include <fdt.h>
+#include <libfdt.h>
#include <asm/arch/tables.h>
/* Allow a maximum of 16 memory range definitions. */
diff --git a/arch/x86/include/asm/arch-sc520/pci.h b/arch/x86/include/asm/arch-sc520/pci.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_IC_SC520_PCI_H_
-#define _ASM_IC_SC520_PCI_H_ 1
-
-/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */
-#define SC520_REG_ADDR 0x00000cf8
-#define SC520_REG_DATA 0x00000cfc
-
-#define SC520_ISA_MEM_PHYS 0x00000000
-#define SC520_ISA_MEM_BUS 0x00000000
-#define SC520_ISA_MEM_SIZE 0x01000000
-
-#define SC520_ISA_IO_PHYS 0x00000000
-#define SC520_ISA_IO_BUS 0x00000000
-#define SC520_ISA_IO_SIZE 0x00001000
-
-/* PCI I/O space from 0x1000 to 0xdfff
- * (make 0xe000-0xfdff available for stuff like PCCard boot) */
-#define SC520_PCI_IO_PHYS 0x00001000
-#define SC520_PCI_IO_BUS 0x00001000
-#define SC520_PCI_IO_SIZE 0x0000d000
-
-/* system memory from 0x00000000 to 0x0fffffff */
-#define SC520_PCI_MEMORY_PHYS 0x00000000
-#define SC520_PCI_MEMORY_BUS 0x00000000
-#define SC520_PCI_MEMORY_SIZE 0x10000000
-
-/* PCI bus memory from 0x10000000 to 0x26ffffff
- * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
-#define SC520_PCI_MEM_PHYS 0x10000000
-#define SC520_PCI_MEM_BUS 0x10000000
-#define SC520_PCI_MEM_SIZE 0x17000000
-
-/* pin number used for PCI interrupt mappings */
-#define SC520_PCI_INTA 0
-#define SC520_PCI_INTB 1
-#define SC520_PCI_INTC 2
-#define SC520_PCI_INTD 3
-#define SC520_PCI_GPIRQ0 4
-#define SC520_PCI_GPIRQ1 5
-#define SC520_PCI_GPIRQ2 6
-#define SC520_PCI_GPIRQ3 7
-#define SC520_PCI_GPIRQ4 8
-#define SC520_PCI_GPIRQ5 9
-#define SC520_PCI_GPIRQ6 10
-#define SC520_PCI_GPIRQ7 11
-#define SC520_PCI_GPIRQ8 12
-#define SC520_PCI_GPIRQ9 13
-#define SC520_PCI_GPIRQ10 14
-
-extern int sc520_pci_ints[];
-
-void pci_sc520_init(struct pci_controller *hose);
-int pci_set_regions(struct pci_controller *hose);
-int pci_sc520_set_irq(int pci_pin, int irq);
-
-#endif
diff --git a/arch/x86/include/asm/arch-sc520/sc520.h b/arch/x86/include/asm/arch-sc520/sc520.h
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ASM_IC_SC520_H_
-#define _ASM_IC_SC520_H_ 1
-
-#ifndef __ASSEMBLY__
-
-void init_sc520(void);
-unsigned long init_sc520_dram(void);
-void sc520_udelay(unsigned long usec);
-
-/* Memory mapped configuration registers */
-typedef struct sc520_mmcr {
- u16 revid; /* ElanSC520 microcontroller revision id */
- u8 cpuctl; /* am5x86 CPU control */
-
- u8 pad_0x003[0x0d];
-
- u8 drcctl; /* SDRAM control */
- u8 pad_0x011[0x01];
- u8 drctmctl; /* SDRAM timing control */
- u8 pad_0x013[0x01];
- u16 drccfg; /* SDRAM bank configuration*/
- u8 pad_0x016[0x02];
- u32 drcbendadr; /* SDRAM bank 0-3 ending address*/
- u8 pad_0x01c[0x04];
- u8 eccctl; /* ECC control */
- u8 eccsta; /* ECC status */
- u8 eccckbpos; /* ECC check bit position */
- u8 ecccktest; /* ECC Check Code Test */
- u32 eccsbadd; /* ECC single-bit error address */
- u32 eccmbadd; /* ECC multi-bit error address */
-
- u8 pad_0x02c[0x14];
-
- u8 dbctl; /* SDRAM buffer control */
-
- u8 pad_0x041[0x0f];
-
- u16 bootcsctl; /* /BOOTCS control */
- u8 pad_0x052[0x02];
- u16 romcs1ctl; /* /ROMCS1 control */
- u16 romcs2ctl; /* /ROMCS2 control */
-
- u8 pad_0x058[0x08];
-
- u16 hbctl; /* host bridge control */
- u16 hbtgtirqctl; /* host bridge target interrupt control */
- u16 hbtgtirqsta; /* host bridge target interrupt status */
- u16 hbmstirqctl; /* host bridge target interrupt control */
- u16 hbmstirqsta; /* host bridge master interrupt status */
- u8 pad_0x06a[0x02];
- u32 mstintadd; /* host bridge master interrupt address */
-
- u8 sysarbctl; /* system arbiter control */
- u8 pciarbsta; /* PCI bus arbiter status */
- u16 sysarbmenb; /* system arbiter master enable */
- u32 arbprictl; /* arbiter priority control */
-
- u8 pad_0x078[0x08];
-
- u8 adddecctl; /* address decode control */
- u8 pad_0x081[0x01];
- u16 wpvsta; /* write-protect violation status */
- u8 pad_0x084[0x04];
- u32 par[16]; /* programmable address regions */
-
- u8 pad_0x0c8[0x0b38];
-
- u8 gpecho; /* GP echo mode */
- u8 gpcsdw; /* GP chip select data width */
- u16 gpcsqual; /* GP chip select qualification */
- u8 pad_0xc04[0x4];
- u8 gpcsrt; /* GP chip select recovery time */
- u8 gpcspw; /* GP chip select pulse width */
- u8 gpcsoff; /* GP chip select offset */
- u8 gprdw; /* GP read pulse width */
- u8 gprdoff; /* GP read offset */
- u8 gpwrw; /* GP write pulse width */
- u8 gpwroff; /* GP write offset */
- u8 gpalew; /* GP ale pulse width */
- u8 gpaleoff; /* GP ale offset */
-
- u8 pad_0xc11[0x0f];
-
- u16 piopfs15_0; /* PIO15-PIO0 pin function select */
- u16 piopfs31_16; /* PIO31-PIO16 pin function select */
- u8 cspfs; /* chip select pin function select */
- u8 pad_0xc25[0x01];
- u8 clksel; /* clock select */
- u8 pad_0xc27[0x01];
- u16 dsctl; /* drive strength control */
- u16 piodir15_0; /* PIO15-PIO0 direction */
- u16 piodir31_16; /* PIO31-PIO16 direction */
- u8 pad_0xc2e[0x02];
- u16 piodata15_0 ; /* PIO15-PIO0 data */
- u16 piodata31_16; /* PIO31-PIO16 data */
- u16 pioset15_0; /* PIO15-PIO0 set */
- u16 pioset31_16; /* PIO31-PIO16 set */
- u16 pioclr15_0; /* PIO15-PIO0 clear */
- u16 pioclr31_16; /* PIO31-PIO16 clear */
-
- u8 pad_0xc3c[0x24];
-
- u16 swtmrmilli; /* software timer millisecond count */
- u16 swtmrmicro; /* software timer microsecond count */
- u8 swtmrcfg; /* software timer configuration */
-
- u8 pad_0xc65[0x0b];
-
- u8 gptmrsta; /* GP timers status register */
- u8 pad_0xc71;
- u16 gptmr0ctl; /* GP timer 0 mode/control */
- u16 gptmr0cnt; /* GP timer 0 count */
- u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */
- u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */
- u16 gptmr1ctl; /* GP timer 1 mode/control */
- u16 gptmr1cnt; /* GP timer 1 count */
- u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */
- u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/
- u16 gptmr2ctl; /* GP timer 2 mode/control */
- u16 gptmr2cnt; /* GP timer 2 count */
- u8 pad_0xc86[0x08];
- u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */
-
- u8 pad_0xc90[0x20];
-
- u16 wdtmrctl; /* watchdog timer control */
- u16 wdtmrcntl; /* watchdog timer count low */
- u16 wdtmrcnth; /* watchdog timer count high */
-
- u8 pad_0xcb6[0x0a];
-
- u8 uart1ctl; /* UART 1 general control */
- u8 uart1sta; /* UART 1 general status */
- u8 uart1fcrshad; /* UART 1 FIFO control shadow */
- u8 pad_0xcc3[0x01];
- u8 uart2ctl; /* UART 2 general control */
- u8 uart2sta; /* UART 2 general status */
- u8 uart2fcrshad; /* UART 2 FIFO control shadow */
-
- u8 pad_0xcc7[0x09];
-
- u8 ssictl; /* SSI control */
- u8 ssixmit; /* SSI transmit */
- u8 ssicmd; /* SSI command */
- u8 ssista; /* SSI status */
- u8 ssircv; /* SSI receive */
-
- u8 pad_0xcd5[0x2b];
-
- u8 picicr; /* interrupt control */
- u8 pad_0xd01[0x01];
- u8 pic_mode[3]; /* PIC interrupt mode */
- u8 pad_0xd05[0x03];
- u16 swint16_1; /* software interrupt 16-1 control */
- u8 swint22_17; /* software interrupt 22-17/NMI control */
- u8 pad_0xd0b[0x05];
- u16 intpinpol; /* interrupt pin polarity */
- u8 pad_0xd12[0x02];
- u16 pcihostmap; /* PCI host bridge interrupt mapping */
- u8 pad_0xd16[0x02];
- u16 eccmap; /* ECC interrupt mapping */
- u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */
- u8 pad_0xd1d[0x03];
- u8 pit_int_map[3]; /* PIT interrupt mapping */
- u8 pad_0xd23[0x05];
- u8 uart_int_map[2]; /* UART interrupt mapping */
- u8 pad_0xd2a[0x06];
- u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/
- u8 pad_0xd34[0x0c];
- u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */
- u8 ssimap; /* SSI interrupt mapping register */
- u8 wdtmap; /* watchdog timer interrupt mapping */
- u8 rtcmap; /* RTC interrupt mapping register */
- u8 wpvmap; /* write-protect interrupt mapping */
- u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */
- u8 ferrmap; /* floating point error interrupt mapping */
- u8 pad_0xd47[0x09];
- u8 gp_int_map[11]; /* GP IRQ interrupt mapping */
-
- u8 pad_0xd5b[0x15];
-
- u8 sysinfo; /* system board information */
- u8 pad_0xd71[0x01];
- u8 rescfg; /* reset configuration */
- u8 pad_0xd73[0x01];
- u8 ressta; /* reset status */
-
- u8 pad_0xd75[0x0b];
-
- u8 gpdmactl; /* GP-DMA Control */
- u8 gpdmammio; /* GP-DMA memory-mapped I/O */
- u16 gpdmaextchmapa; /* GP-DMA resource channel map a */
- u16 gpdmaextchmapb; /* GP-DMA resource channel map b */
- u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */
- u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */
- u8 pad_0xd8d[0x03];
- u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */
- u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */
- u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */
- u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */
- u8 pad_0xd94[0x4];
- u8 gpdmabcctl; /* buffer chaining control */
- u8 gpdmabcsta; /* buffer chaining status */
- u8 gpdmabsintenb; /* buffer chaining interrupt enable */
- u8 gpdmabcval; /* buffer chaining valid */
- u8 pad_0xd9c[0x04];
- u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */
- u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */
- u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */
- u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */
- u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */
- u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */
- u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */
- u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */
- u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */
- u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */
- u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */
- u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */
- u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */
- u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */
- u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */
- u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */
-
- u8 pad_0xdc0[0x0240];
-} sc520_mmcr_t;
-
-extern sc520_mmcr_t *sc520_mmcr;
-
-#endif
-
-/* Memory Mapped Control Registers (MMCR) Base Address */
-#define SC520_MMCR_BASE 0xfffef000
-
-/*
- * PARs for maximum allowable 256MB of SDRAM @ 0x00000000
- * Two PARs are required due to maximum PAR size of 128MB
- * These are used in the SDRAM sizing code to disable caching
- *
- * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
- * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
- * \ / | | | | \----+----/ \-----+------/
- * | | | | | | +---------- Start at 0x00000000
- * | | | | | | 0x08000000
- * | | | | | +----------------------- 128MB Region Size
- * | | | | | ((2047 + 1) * 64kB)
- * | | | | +------------------------------ 64kB Page Size
- * | | | +-------------------------------- Writes Enabled
- * | | +---------------------------------- Caching Enabled
- * | +------------------------------------ Execution Enabled
- * +--------------------------------------- SDRAM
- */
-#define SC520_SDRAM1_PAR 0xe3ffc000
-#define SC520_SDRAM2_PAR 0xe3ffc800
-
-#define SC520_PAR_WRITE_DIS 0x04000000
-#define SC520_PAR_CACHE_DIS 0x08000000
-#define SC520_PAR_EXEC_DIS 0x10000000
-
-/*
- * Programmable Address Regions to cover 256MB SDRAM (Maximum supported)
- * required for DRAM sizing code
- */
-
-/* MMCR Register bits (not all of them :) ) */
-
-/* SSI Stuff */
-#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */
-#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */
-#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */
-#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */
-#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */
-#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */
-#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */
-#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */
-
-#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */
-#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */
-#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */
-#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */
-
-#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */
-#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */
-#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */
-#define SSISTA_BSY 0x02 /* SSI Busy */
-#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */
-
-/* BITS for SC520_ADDDECCTL: */
-#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */
-#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */
-#define RTC_DIS 0x04 /* RTC Disable */
-#define UART2_DIS 0x02 /* UART2 Disable */
-#define UART1_DIS 0x01 /* UART1 Disable */
-
-/*
- * Defines used for SDRAM Sizing (number of columns and rows)
- * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the
- * Elan SC520 Microcontroller User's Manual (Order #22004B)
- */
-#define CACHELINESZ 0x00000010
-
-#define COL11_ADR 0x0e001e00
-#define COL10_ADR 0x0e000e00
-#define COL09_ADR 0x0e000600
-#define COL08_ADR 0x0e000200
-#define COL11_DATA 0x0b0b0b0b
-#define COL10_DATA 0x0a0a0a0a
-#define COL09_DATA 0x09090909
-#define COL08_DATA 0x08080808
-
-#define ROW14_ADR 0x0f000000
-#define ROW13_ADR 0x07000000
-#define ROW12_ADR 0x03000000
-#define ROW11_ADR 0x01000000
-#define ROW10_ADR 0x00000000
-#define ROW14_DATA 0x3f3f3f3f
-#define ROW13_DATA 0x1f1f1f1f
-#define ROW12_DATA 0x0f0f0f0f
-#define ROW11_DATA 0x07070707
-#define ROW10_DATA 0xaaaaaaaa
-
-/* 0x28000000 - 0x3fffffff is used by the flash banks */
-
-/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
-
-/* priority numbers used for interrupt channel mappings */
-#define SC520_IRQ_DISABLED 0
-#define SC520_IRQ0 1
-#define SC520_IRQ1 2
-#define SC520_IRQ2 4 /* same as IRQ9 */
-#define SC520_IRQ3 11
-#define SC520_IRQ4 12
-#define SC520_IRQ5 13
-#define SC520_IRQ6 21
-#define SC520_IRQ7 22
-#define SC520_IRQ8 3
-#define SC520_IRQ9 4
-#define SC520_IRQ10 5
-#define SC520_IRQ11 6
-#define SC520_IRQ12 7
-#define SC520_IRQ13 8
-#define SC520_IRQ14 9
-#define SC520_IRQ15 10
-
-#endif
index dc6402b67dba5425a19d526749ca0d73db35806b..8a96fc96e8d760ebbbd2329d46c0a50c29fd2980 100644 (file)
#ifndef __ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
-/*
- * The following data structure is placed in some memory wich is
- * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
- * some locked parts of the data cache) to allow for a minimum set of
- * global variables during system initialization (until we have set
- * up the memory controller so that we can use RAM).
- */
#ifndef __ASSEMBLY__
-#include <asm/u-boot.h>
-
-typedef struct global_data gd_t;
+/* Architecture-specific global data */
+struct arch_global_data {
+ struct global_data *gd_addr; /* Location of Global Data */
+};
-struct global_data {
- /* NOTE: gd_addr MUST be first member of struct global_data! */
- gd_t *gd_addr; /* Location of Global Data */
- bd_t *bd;
- unsigned long flags;
- unsigned int baudrate;
- unsigned long have_console; /* serial_init() was called */
-#ifdef CONFIG_PRE_CONSOLE_BUFFER
- unsigned long precon_buf_idx; /* Pre-Console buffer index */
#endif
- unsigned long reloc_off; /* Relocation Offset */
- unsigned long load_off; /* Load Offset */
- unsigned long env_addr; /* Address of Environment struct */
- unsigned long env_valid; /* Checksum of Environment valid? */
- unsigned long cpu_clk; /* CPU clock in Hz! */
- unsigned long bus_clk;
- unsigned long relocaddr; /* Start address of U-Boot in RAM */
- unsigned long start_addr_sp; /* start_addr_stackpointer */
- unsigned long gdt_addr; /* Location of GDT */
- phys_size_t ram_size; /* RAM size */
- unsigned long reset_status; /* reset status register at boot */
- const void *fdt_blob; /* Our device tree, NULL if none */
- void **jt; /* jump table */
- char env_buf[32]; /* buffer for getenv() before reloc. */
-};
+#include <asm-generic/global_data.h>
+
+#ifndef __ASSEMBLY__
static inline gd_t *get_fs_gd_ptr(void)
{
gd_t *gd_ptr;
#endif
-#include <asm-generic/global_data_flags.h>
-
/*
* Our private Global Data Flags
*/
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 0a52cc896c6b9c36b920f7d3fc91fdd3a2c17603..9b24dc5fdf025eac7e727c84ee6eb998124c26a4 100644 (file)
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
LIB = $(obj)lib$(ARCH).o
-ifeq ($(CONFIG_X86_NO_REAL_MODE),)
-SOBJS-$(CONFIG_SYS_PC_BIOS) += bios.o
-SOBJS-$(CONFIG_SYS_PCI_BIOS) += bios_pci.o
-COBJS-y += realmode.o
-SOBJS-y += realmode_switch.o
-
-COBJS-$(CONFIG_SYS_PC_BIOS) += bios_setup.o
-COBJS-$(CONFIG_VIDEO_VGA) += video_bios.o
-endif
-
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-y += cmd_boot.o
diff --git a/arch/x86/lib/bios.S b/arch/x86/lib/bios.S
--- a/arch/x86/lib/bios.S
+++ /dev/null
@@ -1,569 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Based on msbios.c from rolo 1.6:
- *----------------------------------------------------------------------
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions GmbH
- * Klein-Winternheim, Germany
- *----------------------------------------------------------------------
- */
-
-#include "bios.h"
-
-/*
- * During it's initialization phase, before switching to protected
- * mode, the Linux Kernel makes a few BIOS calls. This won't work
- * if the board does not have a BIOS.
- *
- * This is a very minimalisic BIOS that supplies just enough
- * functionality to keep the Linux Kernel happy. It is NOT
- * a general purpose replacement for a real BIOS !!
- */
-
-.section .bios, "ax"
-.code16
-.org 0
- /* a call to f000:0 should warmboot */
- jmp realmode_reset
-
-.globl rm_int00
-.hidden rm_int00
-.type rm_int00, @function
-rm_int00:
- pushw $0
- jmp any_interrupt16
-.globl rm_int01
-.hidden rm_int01
-.type rm_int01, @function
-rm_int01:
- pushw $1
- jmp any_interrupt16
-.globl rm_int02
-.hidden rm_int02
-.type rm_int02, @function
-rm_int02:
- pushw $2
- jmp any_interrupt16
-.globl rm_int03
-.hidden rm_int03
-.type rm_int03, @function
-rm_int03:
- pushw $3
- jmp any_interrupt16
-.globl rm_int04
-.hidden rm_int04
-.type rm_int04, @function
-rm_int04:
- pushw $4
- jmp any_interrupt16
-.globl rm_int05
-.hidden rm_int05
-.type rm_int05, @function
-rm_int05:
- pushw $5
- jmp any_interrupt16
-.globl rm_int06
-.hidden rm_int06
-.type rm_int06, @function
-rm_int06:
- pushw $6
- jmp any_interrupt16
-.globl rm_int07
-.hidden rm_int07
-.type rm_int07, @function
-rm_int07:
- pushw $7
- jmp any_interrupt16
-.globl rm_int08
-.hidden rm_int08
-.type rm_int08, @function
-rm_int08:
- pushw $8
- jmp any_interrupt16
-.globl rm_int09
-.hidden rm_int09
-.type rm_int09, @function
-rm_int09:
- pushw $9
- jmp any_interrupt16
-.globl rm_int0a
-.hidden rm_int0a
-.type rm_int0a, @function
-rm_int0a:
- pushw $10
- jmp any_interrupt16
-.globl rm_int0b
-.hidden rm_int0b
-.type rm_int0b, @function
-rm_int0b:
- pushw $11
- jmp any_interrupt16
-.globl rm_int0c
-.hidden rm_int0c
-.type rm_int0c, @function
-rm_int0c:
- pushw $12
- jmp any_interrupt16
-.globl rm_int0d
-.hidden rm_int0d
-.type rm_int0d, @function
-rm_int0d:
- pushw $13
- jmp any_interrupt16
-.globl rm_int0e
-.hidden rm_int0e
-.type rm_int0e, @function
-rm_int0e:
- pushw $14
- jmp any_interrupt16
-.globl rm_int0f
-.hidden rm_int0f
-.type rm_int0f, @function
-rm_int0f:
- pushw $15
- jmp any_interrupt16
-.globl rm_int10
-.hidden rm_int10
-.type rm_int10, @function
-rm_int10:
- pushw $16
- jmp any_interrupt16
-.globl rm_int11
-.hidden rm_int11
-.type rm_int11, @function
-rm_int11:
- pushw $17
- jmp any_interrupt16
-.globl rm_int12
-.hidden rm_int12
-.type rm_int12, @function
-rm_int12:
- pushw $18
- jmp any_interrupt16
-.globl rm_int13
-.hidden rm_int13
-.type rm_int13, @function
-rm_int13:
- pushw $19
- jmp any_interrupt16
-.globl rm_int14
-.hidden rm_int14
-.type rm_int14, @function
-rm_int14:
- pushw $20
- jmp any_interrupt16
-.globl rm_int15
-.hidden rm_int15
-.type rm_int15, @function
-rm_int15:
- pushw $21
- jmp any_interrupt16
-.globl rm_int16
-.hidden rm_int16
-.type rm_int16, @function
-rm_int16:
- pushw $22
- jmp any_interrupt16
-.globl rm_int17
-.hidden rm_int17
-.type rm_int17, @function
-rm_int17:
- pushw $23
- jmp any_interrupt16
-.globl rm_int18
-.hidden rm_int18
-.type rm_int18, @function
-rm_int18:
- pushw $24
- jmp any_interrupt16
-.globl rm_int19
-.hidden rm_int19
-.type rm_int19, @function
-rm_int19:
- pushw $25
- jmp any_interrupt16
-.globl rm_int1a
-.hidden rm_int1a
-.type rm_int1a, @function
-rm_int1a:
- pushw $26
- jmp any_interrupt16
-.globl rm_int1b
-.hidden rm_int1b
-.type rm_int1b, @function
-rm_int1b:
- pushw $27
- jmp any_interrupt16
-.globl rm_int1c
-.hidden rm_int1c
-.type rm_int1c, @function
-rm_int1c:
- pushw $28
- jmp any_interrupt16
-.globl rm_int1d
-.hidden rm_int1d
-.type rm_int1d, @function
-rm_int1d:
- pushw $29
- jmp any_interrupt16
-.globl rm_int1e
-.hidden rm_int1e
-.type rm_int1e, @function
-rm_int1e:
- pushw $30
- jmp any_interrupt16
-.globl rm_int1f
-.hidden rm_int1f
-.type rm_int1f, @function
-rm_int1f:
- pushw $31
- jmp any_interrupt16
-.globl rm_def_int
-.hidden rm_def_int
-.type rm_def_int, @function
-rm_def_int:
- iret
-
- /*
- * All interrupt jumptable entries jump to here after pushing the
- * interrupt vector number onto the stack.
- */
-any_interrupt16:
- MAKE_BIOS_STACK
-
-gs movw OFFS_VECTOR(%bp), %ax
- cmpw $0x10, %ax
- je Lint_10h
- cmpw $0x11, %ax
- je Lint_11h
- cmpw $0x12, %ax
- je Lint_12h
- cmpw $0x13, %ax
- je Lint_13h
- cmpw $0x15, %ax
- je Lint_15h
- cmpw $0x16, %ax
- je Lint_16h
- cmpw $0x1a, %ax
- je Lint_1ah
- movw $0xffff, %ax
- jmp Lout
-Lint_10h:
- /* VGA BIOS services */
- call bios_10h
- jmp Lout
-Lint_11h:
- call bios_11h
- jmp Lout
-Lint_12h:
- call bios_12h
- jmp Lout
-Lint_13h:
- /* BIOS disk services */
- call bios_13h
- jmp Lout
-Lint_15h:
- /* Misc. BIOS services */
- call bios_15h
- jmp Lout
-Lint_16h:
- /* keyboard services */
- call bios_16h
- jmp Lout
-Lint_1ah:
- /* PCI bios */
- call bios_1ah
- jmp Lout
-Lout:
- cmpw $0, %ax
- je Lhandeled
-
- /*
- * Insert code for unhandeled INTs here.
- *
- * ROLO prints a message to the console we could do that but then
- * we're in 16bit mode so we'll have to get back into 32bit mode
- * to use the console I/O routines (if we do this we should make
- * int 0x10 and int 0x16 work as well)
- */
-Lhandeled:
- RESTORE_CALLERS_STACK
-
- /* dump vector number */
- addw $2,%sp
-
- /* return from interrupt */
- iret
-
-/*
- ************************************************************
- * BIOS interrupt 10h -- VGA services
- ************************************************************
- */
-bios_10h:
-gs movw OFFS_AX(%bp), %ax
- shrw $8, %ax
- cmpw $0x3, %ax
- je Lcur_pos
- cmpw $0xf, %ax
- je Lvid_state
- cmpw $0x12, %ax
- je Lvid_cfg
- movw $0xffff, %ax
- ret
-Lcur_pos:
- /* Read Cursor Position and Size */
-gs movw $0, OFFS_CX(%bp)
-gs movw $0, OFFS_DX(%bp)
- xorw %ax, %ax
- ret
-Lvid_state:
- /* Get Video State - 80 columns, 80x25, 16 colors */
-gs movw $(80 << 8|0x03), OFFS_AX(%bp)
-gs movw $0, OFFS_BX(%bp)
- xorw %ax, %ax
- ret
-Lvid_cfg:
- /* Video Subsystem Configuration (EGA/VGA) - indicate CGA/MDA/HGA */
-gs movw $0x10, OFFS_BX(%bp)
- xorw %ax, %ax
- ret
-
-/*
- ************************************************************
- * BIOS interrupt 11h -- Equipment determination
- ************************************************************
- */
-
-bios_11h:
-cs movw bios_equipment, %ax
-gs movw %ax, OFFS_AX(%bp)
- xorw %ax, %ax
- ret
-
-/*
- ************************************************************
- * BIOS interrupt 12h -- Get Memory Size
- ************************************************************
- */
-bios_12h:
-cs movw ram_in_64kb_chunks, %ax
- cmpw $0xa, %ax
- ja b12_more_than_640k
- shlw $6, %ax
- jmp b12_return
-b12_more_than_640k:
- movw $0x280, %ax
-b12_return:
- /* return number of kilobytes in ax */
-gs movw %ax, OFFS_AX(%bp)
-
-gs movw OFFS_FLAGS(%bp), %ax
-
- /* clear carry -- function succeeded */
- andw $0xfffe, %ax
-gs movw %ax, OFFS_FLAGS(%bp)
-
- xorw %ax, %ax
- ret
-
-/*
- ************************************************************
- * BIOS interrupt 13h -- Disk services
- ************************************************************
- */
-bios_13h:
-gs movw OFFS_AX(%bp), %ax
- shrw $8, %ax
- cmpw $0x15, %ax
- je Lfunc_15h
- movw $0xffff, %ax
- ret
-Lfunc_15h:
-gs movw OFFS_AX(%bp), %ax
-
- /* return AH=0->drive not present */
- andw $0x00ff, %ax
-gs movw %ax, OFFS_AX(%bp)
- xorw %ax, %ax
- ret
-
-/*
- ***********************************************************
- * BIOS interrupt 15h -- Miscellaneous services
- ***********************************************************
- */
-bios_15h:
-gs movw OFFS_AX(%bp), %ax
- shrw $8, %ax
- cmpw $0xc0, %ax
- je Lfunc_c0h
- cmpw $0xe8, %ax
- je Lfunc_e8h
- cmpw $0x88, %ax
- je Lfunc_88h
- movw $0xffff, %ax
- ret
-
-Lfunc_c0h:
- /* Return System Configuration Parameters (PS2 only) */
-gs movw OFFS_FLAGS(%bp), %ax
-
- /* return carry -- function not supported */
- orw $1, %ax
-gs movw %ax, OFFS_FLAGS(%bp)
- xorw %ax, %ax
- ret
-
-Lfunc_e8h:
-gs movw OFFS_AX(%bp), %ax
- andw $0xff, %ax
- cmpw $1, %ax
- je Lfunc_e801h
-gs movw OFFS_FLAGS(%bp), %ax
-
- /* return carry -- function not supported */
- orw $1, %ax
-gs movw %ax, OFFS_FLAGS(%bp)
- xorw %ax, %ax
- ret
-
-Lfunc_e801h:
- /* Get memory size for >64M Configurations */
-cs movw ram_in_64kb_chunks, %ax
- cmpw $0x100, %ax
- ja e801_more_than_16mb
-
- /* multiply by 64 */
- shlw $6, %ax
-
- /* 1st meg does not count */
- subw $0x400, %ax
-
- /* return memory size between 1M and 16M in 1kb chunks in AX and CX */
-gs movw %ax, OFFS_AX(%bp)
-gs movw %ax, OFFS_CX(%bp)
-
- /* set BX and DX to 0*/
-gs movw $0, OFFS_BX(%bp)
-gs movw $0, OFFS_DX(%bp)
-gs movw OFFS_FLAGS(%bp), %ax
-
- /* clear carry -- function succeeded */
- andw $0xfffe, %ax
-gs movw %ax, OFFS_FLAGS(%bp)
- xorw %ax, %ax
- ret
-
-e801_more_than_16mb:
- /* subtract 16MB */
- subw $0x100, %ax
-
- /* return 0x3c00 (16MB-1MB) in AX and CX */
-gs movw $0x3c00, OFFS_AX(%bp)
-gs movw $0x3c00, OFFS_CX(%bp)
-
- /* set BX and DX to number of 64kb chunks above 16MB */
-gs movw %ax, OFFS_BX(%bp)
-gs movw %ax, OFFS_DX(%bp)
-
-gs movw OFFS_FLAGS(%bp), %ax
-
- /* clear carry -- function succeeded */
- andw $0xfffe, %ax
-gs movw %ax, OFFS_FLAGS(%bp)
- xorw %ax, %ax
- ret
-
-Lfunc_88h:
-cs movw ram_in_64kb_chunks, %ax
- cmpw $0x100, %ax
- jna b88_not_more_than16
- movw $0x100, %ax
-b88_not_more_than16:
- shlw $6, %ax
-
- /* 1st meg does not count */
- subw $0x400, %ax
-
- /* return number of kilobytes between 16MB and 16MB in ax */
-gs movw %ax, OFFS_AX(%bp)
-
-gs movw OFFS_FLAGS(%bp), %ax
-
- /* clear carry -- function succeeded */
- andw $0xfffe, %ax
-gs movw %ax, OFFS_FLAGS(%bp)
-
- xorw %ax, %ax
- ret
-
-/*
- ************************************************************
- * BIOS interrupt 16h -- keyboard services
- ************************************************************
- */
-bios_16h:
-gs movw OFFS_AX(%bp), %ax
- shrw $8, %ax
- cmpw $0x03, %ax
- je Lfunc_03h
- movw $0xffff, %ax
- ret
-Lfunc_03h:
- /* do nothing -- function not supported */
- xorw %ax, %ax
- ret
-
-/*
- ************************************************************
- * BIOS interrupt 1ah -- PCI bios
- ************************************************************
- */
-bios_1ah:
-gs movw OFFS_AX(%bp), %ax
- cmpb $0xb1, %ah
- je Lfunc_b1h
- movw $0xffff, %ax
- ret
-Lfunc_b1h:
- call realmode_pci_bios
-
- /* do nothing -- function not supported */
- xorw %ax, %ax
- ret
-
-
-.globl ram_in_64kb_chunks
-.hidden ram_in_64kb_chunks
-.type ram_in_64kb_chunks, @function
-ram_in_64kb_chunks:
- .word 0
-
-.globl bios_equipment
-.hidden bios_equipment
-.type bios_equipment, @function
-bios_equipment:
- .word 0
diff --git a/arch/x86/lib/bios.h b/arch/x86/lib/bios.h
index a220983df134f6b50090d2701710a0ee942ff30b..96509b066e7f507861d3bbf65596b3a7f929a556 100644 (file)
--- a/arch/x86/lib/bios.h
+++ b/arch/x86/lib/bios.h
extern void *rm_int1f;
extern void *rm_def_int;
-extern void *realmode_reset;
-extern void *realmode_pci_bios_call_entry;
-
#define RELOC_16_LONG(seg, off) (*(u32 *)(seg << 4 | (u32)&off))
#define RELOC_16_WORD(seg, off) (*(u16 *)(seg << 4 | (u32)&off))
#define RELOC_16_BYTE(seg, off) (*(u8 *)(seg << 4 | (u32)&off))
diff --git a/arch/x86/lib/bios_pci.S b/arch/x86/lib/bios_pci.S
--- a/arch/x86/lib/bios_pci.S
+++ /dev/null
@@ -1,447 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * x86 realmode assembly implementation of a PCI BIOS
- * for platforms that use one PCI hose and configuration
- * access type 1. (The common case for low-end PC's)
- */
-
-#include "bios.h"
-
-#define PCI_BIOS_DEBUG
-
-.section .bios, "ax"
-.code16
-.globl realmode_pci_bios_call_entry
-.hidden realmode_pci_bios_call_entry
-.type realmode_pci_bios_call_entry, @function
-realmode_pci_bios_call_entry:
- MAKE_BIOS_STACK
- call realmode_pci_bios
- RESTORE_CALLERS_STACK
- ret
-
-
-.globl realmode_pci_bios
-realmode_pci_bios:
-gs movw OFFS_AX(%bp), %ax
- cmpb $1, %al
- je pci_bios_present
- cmpb $2, %al
- je pci_bios_find_device
- cmpb $3, %al
- je pci_bios_find_class
- cmpb $6, %al
- je pci_bios_generate_special_cycle
- cmpb $8, %al
- je pci_bios_read_cfg_byte
- cmpb $9, %al
- je pci_bios_read_cfg_word
- cmpb $10, %al
- je pci_bios_read_cfg_dword
- cmpb $11, %al
- je pci_bios_write_cfg_byte
- cmpb $12, %al
- je pci_bios_write_cfg_word
- cmpb $13, %al
- je pci_bios_write_cfg_dword
- cmpb $14, %al
- je pci_bios_get_irq_routing
- cmpb $15, %al
- je pci_bios_set_irq
- jmp unknown_function
-
-/*****************************************************************************/
-
-pci_bios_present:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_present
-#endif
- movl $0x20494350, %eax
-gs movl %eax, OFFS_EDX(%bp)
-
- /* We support cfg type 1 version 2.10 */
- movb $0x01, %al
-gs movb %al, OFFS_AL(%bp)
- movw $0x0210, %ax
-gs movw %ax, OFFS_BX(%bp)
-
- /* last bus number */
-cs movb pci_last_bus, %al
-gs movb %al, OFFS_CL(%bp)
- jmp clear_carry
-
-/*****************************************************************************/
-
-/* device 0-31, function 0-7 */
-pci_bios_find_device:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_find_device
-#endif
-gs movw OFFS_CX(%bp), %di
- shll $16, %edi
-gs movw OFFS_DX(%bp), %di
- /* edi now holds device in upper 16 bits and vendor in lower 16 bits */
-
-gs movw OFFS_SI(%bp), %si
-
- /* start at bus 0 dev 0 function 0 */
- xorw %bx, %bx
-pfd_loop:
- /* dword 0 is vendor/device */
- xorw %ax, %ax
- call __pci_bios_select_register
- movw $0xcfc, %dx
- inl %dx, %eax
-
- /* our device ? */
- cmpl %edi, %eax
- je pfd_found_one
-pfd_next_dev:
- /* check for multi function devices */
- movw %bx, %ax
- andw $3, %ax
- jnz pfd_function_not_zero
- movw $0x000c, %ax
- call __pci_bios_select_register
- movw $0xcfe, %dx
- inb %dx, %al
- andb $0x80, %al
- jz pfd_not_multi_function
-pfd_function_not_zero:
- /* next function, overflows in to device number, then bus number */
- incw %bx
- jmp pfd_check_bus
-
-pfd_not_multi_function:
- /* remove function bits */
- andw $0xfff8, %bx
-
- /* next device, overflows in to bus number */
- addw $0x0008, %bx
-pfd_check_bus:
-cs movb pci_last_bus, %ah
- cmpb %ah, %bh
- ja pfd_not_found
- jmp pfd_loop
-pfd_found_one:
- decw %si
- js pfd_done
- jmp pfd_next_dev
-
-pfd_done:
-gs movw %bx, OFFS_BX(%bp)
- jmp clear_carry
-
-pfd_not_found:
- /* device not found */
- movb $0x86, %ah
- jmp set_carry
-
-/*****************************************************************************/
-
-pci_bios_find_class:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_find_class
-#endif
-gs movl OFFS_ECX(%bp), %edi
-
- /* edi now holds class-code in lower 24 bits */
- andl $0x00ffffff, %edi
-gs movw OFFS_SI(%bp), %si
-
- /* start at bus 0 dev 0 function 0 */
- xorw %bx, %bx
-pfc_loop:
- /* dword 8 is class-code high 24bits */
- movw $8, %ax
- call __pci_bios_select_register
- movw $0xcfc, %dx
- inl %dx, %eax
- shrl $8, %eax
- andl $0x00ffffff, %eax
-
- /* our device ? */
- cmpl %edi, %eax
- je pfc_found_one
-pfc_next_dev:
- /* check for multi function devices */
- andw $3, %bx
- jnz pfc_function_not_zero
- movw $0x000c, %ax
- call __pci_bios_select_register
- movw $0xcfe, %dx
- inb %dx, %al
- andb $0x80, %al
- jz pfc_not_multi_function
-pfc_function_not_zero:
- /* next function, overflows in to device number, then bus number */
- incw %bx
- jmp pfc_check_bus
-
-pfc_not_multi_function:
- /* remove function bits */
- andw $0xfff8, %bx
-
- /* next device, overflows in to bus number */
- addw $0x0008, %bx
-pfc_check_bus:
-cs movb pci_last_bus, %ah
- cmpb %ah, %bh
- ja pfc_not_found
- jmp pfc_loop
-pfc_found_one:
- decw %si
- js pfc_done
- jmp pfc_next_dev
-
-pfc_done:
-gs movw %bx, OFFS_BX(%bp)
- jmp clear_carry
-
-pfc_not_found:
- /* device not found */
- movb $0x86, %ah
- jmp set_carry
-
-/*****************************************************************************/
-
-pci_bios_generate_special_cycle:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_generate_special_cycle
-#endif
- /* function not supported */
- movb $0x81, %ah
- jmp set_carry
-
-/*****************************************************************************/
-
-pci_bios_read_cfg_byte:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_read_cfg_byte
-#endif
- call pci_bios_select_register
-gs movw OFFS_DI(%bp), %dx
- andw $3, %dx
- addw $0xcfc, %dx
- inb %dx, %al
-gs movb %al, OFFS_CL(%bp)
- jmp clear_carry
-
-/*****************************************************************************/
-
-pci_bios_read_cfg_word:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_read_cfg_word
-#endif
- call pci_bios_select_register
-gs movw OFFS_DI(%bp), %dx
- andw $2, %dx
- addw $0xcfc, %dx
- inw %dx, %ax
-gs movw %ax, OFFS_CX(%bp)
- jmp clear_carry
-
-
-/*****************************************************************************/
-
-pci_bios_read_cfg_dword:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_read_cfg_dword
-#endif
- call pci_bios_select_register
- movw $0xcfc, %dx
- inl %dx, %eax
-gs movl %eax, OFFS_ECX(%bp)
- jmp clear_carry
-
-/*****************************************************************************/
-
-pci_bios_write_cfg_byte:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_write_cfg_byte
-#endif
- call pci_bios_select_register
-gs movw OFFS_DI(%bp), %dx
-gs movb OFFS_CL(%bp), %al
- andw $3, %dx
- addw $0xcfc, %dx
- outb %al, %dx
- jmp clear_carry
-
-/*****************************************************************************/
-
-pci_bios_write_cfg_word:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_write_cfg_word
-#endif
- call pci_bios_select_register
-gs movw OFFS_DI(%bp), %dx
-gs movw OFFS_CX(%bp), %ax
- andw $2, %dx
- addw $0xcfc, %dx
- outw %ax, %dx
- jmp clear_carry
-
-/*****************************************************************************/
-
-pci_bios_write_cfg_dword:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_write_cfg_dword
-#endif
- call pci_bios_select_register
-gs movl OFFS_ECX(%bp), %eax
- movw $0xcfc, %dx
- outl %eax, %dx
- jmp clear_carry
-
-/*****************************************************************************/
-
-pci_bios_get_irq_routing:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_get_irq_routing
-#endif
- /* function not supported */
- movb $0x81, %ah
- jmp set_carry
-
-/*****************************************************************************/
-
-pci_bios_set_irq:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_set_irq
-#endif
- /* function not supported */
- movb $0x81, %ah
- jmp set_carry
-
-/*****************************************************************************/
-
-unknown_function:
-#ifdef PCI_BIOS_DEBUG
-cs incl num_pci_bios_unknown_function
-#endif
- /* function not supported */
- movb $0x81, %ah
- jmp set_carry
-
-/*****************************************************************************/
-
-pci_bios_select_register:
-gs movw OFFS_BX(%bp), %bx
-gs movw OFFS_DI(%bp), %ax
-/* destroys eax, dx */
-__pci_bios_select_register:
- /* BX holds device id, AX holds register index */
- pushl %ebx
- andl $0xfc, %eax
- andl $0xffff, %ebx
- shll $8, %ebx
- orl %ebx, %eax
- orl $0x80000000, %eax
- movw $0xcf8, %dx
- outl %eax, %dx
- popl %ebx
- ret
-
-
-clear_carry:
-gs movw OFFS_FLAGS(%bp), %ax
-
- /* clear carry -- function succeeded */
- andw $0xfffe, %ax
-gs movw %ax, OFFS_FLAGS(%bp)
- xorw %ax, %ax
-gs movb %ah, OFFS_AH(%bp)
- ret
-
-set_carry:
-gs movb %ah, OFFS_AH(%bp)
-gs movw OFFS_FLAGS(%bp), %ax
-
- /* return carry -- function not supported */
- orw $1, %ax
-gs movw %ax, OFFS_FLAGS(%bp)
- movw $-1, %ax
- ret
-
-/*****************************************************************************/
-
-.globl pci_last_bus
-pci_last_bus:
- .byte 0
-
-#ifdef PCI_BIOS_DEBUG
-.globl num_pci_bios_present
-num_pci_bios_present:
- .long 0
-
-.globl num_pci_bios_find_device
-num_pci_bios_find_device:
- .long 0
-
-.globl num_pci_bios_find_class
-num_pci_bios_find_class:
- .long 0
-
-.globl num_pci_bios_generate_special_cycle
-num_pci_bios_generate_special_cycle:
- .long 0
-
-.globl num_pci_bios_read_cfg_byte
-num_pci_bios_read_cfg_byte:
- .long 0
-
-.globl num_pci_bios_read_cfg_word
-num_pci_bios_read_cfg_word:
- .long 0
-
-.globl num_pci_bios_read_cfg_dword
-num_pci_bios_read_cfg_dword:
- .long 0
-
-.globl num_pci_bios_write_cfg_byte
-num_pci_bios_write_cfg_byte:
- .long 0
-
-.globl num_pci_bios_write_cfg_word
-num_pci_bios_write_cfg_word:
- .long 0
-
-.globl num_pci_bios_write_cfg_dword
-num_pci_bios_write_cfg_dword:
- .long 0
-
-.globl num_pci_bios_get_irq_routing
-num_pci_bios_get_irq_routing:
- .long 0
-
-.globl num_pci_bios_set_irq
-num_pci_bios_set_irq:
- .long 0
-
-.globl num_pci_bios_unknown_function
-num_pci_bios_unknown_function:
- .long 0
-#endif
diff --git a/arch/x86/lib/bios_setup.c b/arch/x86/lib/bios_setup.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Partly based on msbios.c from rolo 1.6:
- *----------------------------------------------------------------------
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions GmbH
- * Klein-Winternheim, Germany
- *----------------------------------------------------------------------
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/realmode.h>
-#include <asm/io.h>
-#include "bios.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define NUMVECTS 256
-
-static int set_jmp_vector(int entry_point, void *target)
-{
- if (entry_point & ~0xffff)
- return -1;
-
- if (((u32)target - 0xf0000) & ~0xffff)
- return -1;
-
- printf("set_jmp_vector: 0xf000:%04x -> %p\n",
- entry_point, target);
-
- /* jmp opcode */
- writeb(0xea, 0xf0000 + entry_point);
-
- /* offset */
- writew(((u32)target-0xf0000), 0xf0000 + entry_point + 1);
-
- /* segment */
- writew(0xf000, 0xf0000 + entry_point + 3);
-
- return 0;
-}
-
-/* Install an interrupt vector */
-static void setvector(int vector, u16 segment, void *handler)
-{
- u16 *ptr = (u16 *)(vector * 4);
- ptr[0] = ((u32)handler - (segment << 4)) & 0xffff;
- ptr[1] = segment;
-
-#if 0
- printf("setvector: int%02x -> %04x:%04x\n",
- vector, ptr[1], ptr[0]);
-#endif
-}
-
-int bios_setup(void)
-{
- /* The BIOS section is not relocated and still in the ROM. */
- ulong bios_start = (ulong)&__bios_start;
- ulong bios_size = (ulong)&__bios_size;
-
- static int done;
- int vector;
-#ifdef CONFIG_PCI
- struct pci_controller *pri_hose;
-#endif
- if (done)
- return 0;
-
- done = 1;
-
- if (bios_size > 65536) {
- printf("BIOS too large (%ld bytes, max is 65536)\n",
- bios_size);
- return -1;
- }
-
- memcpy(BIOS_BASE, (void *)bios_start, bios_size);
-
- /* clear bda */
- memset(BIOS_DATA, 0, BIOS_DATA_SIZE);
-
- /* enter some values to the bda */
- writew(0x3f8, BIOS_DATA); /* com1 addr */
- writew(0x2f8, BIOS_DATA+2); /* com2 addr */
- writew(0x3e8, BIOS_DATA+4); /* com3 addr */
- writew(0x2e8, BIOS_DATA+6); /* com4 addr */
- writew(0x278, BIOS_DATA+8); /* lpt1 addr */
- /*
- * The kernel wants to read the base memory size
- * from 40:13. Put a zero there to avoid an error message
- */
- writew(0, BIOS_DATA+0x13); /* base memory size */
-
-
- /* setup realmode interrupt vectors */
- for (vector = 0; vector < NUMVECTS; vector++)
- setvector(vector, BIOS_CS, &rm_def_int);
-
- setvector(0x00, BIOS_CS, &rm_int00);
- setvector(0x01, BIOS_CS, &rm_int01);
- setvector(0x02, BIOS_CS, &rm_int02);
- setvector(0x03, BIOS_CS, &rm_int03);
- setvector(0x04, BIOS_CS, &rm_int04);
- setvector(0x05, BIOS_CS, &rm_int05);
- setvector(0x06, BIOS_CS, &rm_int06);
- setvector(0x07, BIOS_CS, &rm_int07);
- setvector(0x08, BIOS_CS, &rm_int08);
- setvector(0x09, BIOS_CS, &rm_int09);
- setvector(0x0a, BIOS_CS, &rm_int0a);
- setvector(0x0b, BIOS_CS, &rm_int0b);
- setvector(0x0c, BIOS_CS, &rm_int0c);
- setvector(0x0d, BIOS_CS, &rm_int0d);
- setvector(0x0e, BIOS_CS, &rm_int0e);
- setvector(0x0f, BIOS_CS, &rm_int0f);
- setvector(0x10, BIOS_CS, &rm_int10);
- setvector(0x11, BIOS_CS, &rm_int11);
- setvector(0x12, BIOS_CS, &rm_int12);
- setvector(0x13, BIOS_CS, &rm_int13);
- setvector(0x14, BIOS_CS, &rm_int14);
- setvector(0x15, BIOS_CS, &rm_int15);
- setvector(0x16, BIOS_CS, &rm_int16);
- setvector(0x17, BIOS_CS, &rm_int17);
- setvector(0x18, BIOS_CS, &rm_int18);
- setvector(0x19, BIOS_CS, &rm_int19);
- setvector(0x1a, BIOS_CS, &rm_int1a);
- setvector(0x1b, BIOS_CS, &rm_int1b);
- setvector(0x1c, BIOS_CS, &rm_int1c);
- setvector(0x1d, BIOS_CS, &rm_int1d);
- setvector(0x1e, BIOS_CS, &rm_int1e);
- setvector(0x1f, BIOS_CS, &rm_int1f);
-
- set_jmp_vector(0xfff0, &realmode_reset);
- set_jmp_vector(0xfe6e, &realmode_pci_bios_call_entry);
-
- /* fill in data area */
- RELOC_16_WORD(0xf000, ram_in_64kb_chunks) = gd->ram_size >> 16;
- RELOC_16_WORD(0xf000, bios_equipment) = 0; /* FixMe */
-
- /* If we assume only one PCI hose, this PCI hose
- * will own PCI bus #0, and the last PCI bus of
- * that PCI hose will be the last PCI bus in the
- * system.
- * (This, ofcause break on multi hose systems,
- * but our PCI BIOS only support one hose anyway)
- */
-#ifdef CONFIG_PCI
- pri_hose = pci_bus_to_hose(0);
- if (NULL != pri_hose) {
- /* fill in last pci bus number for use by the realmode
- * PCI BIOS */
- RELOC_16_BYTE(0xf000, pci_last_bus) = pri_hose->last_busno;
- }
-#endif
- return 0;
-}
diff --git a/arch/x86/lib/realmode.c b/arch/x86/lib/realmode.c
--- a/arch/x86/lib/realmode.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/ptrace.h>
-#include <asm/realmode.h>
-
-#define REALMODE_MAILBOX ((char *)0xe00)
-
-int realmode_setup(void)
-{
- /* The realmode section is not relocated and still in the ROM. */
- ulong realmode_start = (ulong)&__realmode_start;
- ulong realmode_size = (ulong)&__realmode_size;
-
- /* copy the realmode switch code */
- if (realmode_size > (REALMODE_MAILBOX - (char *)REALMODE_BASE)) {
- printf("realmode switch too large (%ld bytes, max is %d)\n",
- realmode_size,
- (int)(REALMODE_MAILBOX - (char *)REALMODE_BASE));
- return -1;
- }
-
- memcpy((char *)REALMODE_BASE, (void *)realmode_start, realmode_size);
- asm("wbinvd\n");
-
- return 0;
-}
-
-int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out)
-{
-
- /* setup out thin bios emulation */
- if (bios_setup())
- return -1;
-
- if (realmode_setup())
- return -1;
-
- in->eip = off;
- in->xcs = seg;
- if ((in->esp & 0xffff) < 4)
- printf("Warning: entering realmode with sp < 4 will fail\n");
-
- memcpy(REALMODE_MAILBOX, in, sizeof(struct pt_regs));
- asm("wbinvd\n");
-
- __asm__ volatile (
- "lcall $0x20,%0\n" : : "i" (&realmode_enter));
-
- asm("wbinvd\n");
- memcpy(out, REALMODE_MAILBOX, sizeof(struct pt_regs));
-
- return out->eax;
-}
-
-/*
- * This code is supposed to access a realmode interrupt
- * it does currently not work for me
- */
-int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out)
-{
- /* place two instructions at 0x700 */
- writeb(0xcd, 0x700); /* int $lvl */
- writeb(lvl, 0x701);
- writeb(0xcb, 0x702); /* lret */
- asm("wbinvd\n");
-
- enter_realmode(0x00, 0x700, in, out);
-
- return out->eflags & 0x00000001;
-}
diff --git a/arch/x86/lib/realmode_switch.S b/arch/x86/lib/realmode_switch.S
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* 32bit -> 16bit -> 32bit mode switch code */
-
-/*
- * Stack frame at 0xe00
- * e00 ebx;
- * e04 ecx;
- * e08 edx;
- * e0c esi;
- * e10 edi;
- * e14 ebp;
- * e18 eax;
- * e1c ds;
- * e20 es;
- * e24 fs;
- * e28 gs;
- * e2c orig_eax;
- * e30 eip;
- * e34 cs;
- * e38 eflags;
- * e3c esp;
- * e40 ss;
- */
-
-#define a32 .byte 0x67; /* address size prefix 32 */
-#define o32 .byte 0x66; /* operand size prefix 32 */
-
-.section .realmode, "ax"
-.code16
-
- /* 16bit protected mode code here */
-.globl realmode_enter
-realmode_enter:
-o32 pusha
-o32 pushf
- cli
- sidt saved_idt
- sgdt saved_gdt
- movl %esp, %eax
- movl %eax, saved_protected_mode_esp
-
- movl $0x10, %eax
- movl %eax, %esp
- movw $0x28, %ax
- movw %ax, %ds
- movw %ax, %es
- movw %ax, %fs
- movw %ax, %gs
-
- lidt realmode_idt_ptr
- /* Go back into real mode by clearing PE to 0 */
- movl %cr0, %eax
- andl $0x7ffffffe, %eax
- movl %eax, %cr0
-
- /* switch to real mode */
- ljmp $0x0,$do_realmode
-
-do_realmode:
- /* realmode code from here */
- movw %cs,%ax
- movw %ax,%ds
- movw %ax,%es
- movw %ax,%fs
- movw %ax,%gs
-
- /* create a temporary stack */
- movw $0xc0, %ax
- movw %ax, %ss
- movw $0x200, %ax
- movw %ax, %sp
-
- popl %ebx
- popl %ecx
- popl %edx
- popl %esi
- popl %edi
- popl %ebp
- popl %eax
- movl %eax, temp_eax
- popl %eax
- movw %ax, %ds
- popl %eax
- movw %ax, %es
- popl %eax
- movw %ax, %fs
- popl %eax
- movw %ax, %gs
- popl %eax /* orig_eax */
- popl %eax
-cs movw %ax, temp_ip
- popl %eax
-cs movw %ax, temp_cs
-o32 popf
- popl %eax
- popw %ss
- movl %eax, %esp
-cs movl temp_eax, %eax
-
- /* self-modifying code, better flush the cache */
- wbinvd
-
- .byte 0x9a /* lcall */
-temp_ip:
- .word 0 /* new ip */
-temp_cs:
- .word 0 /* new cs */
-
-realmode_ret:
- /* save eax, esp and ss */
-cs movl %eax, saved_eax
- movl %esp, %eax
-cs movl %eax, saved_esp
- movw %ss, %ax
-cs movw %ax, saved_ss
-
- /*
- * restore the stack, note that we set sp to 0x244;
- * pt_regs is 0x44 bytes long and we push the structure
- * backwards on to the stack, bottom first
- */
- movw $0xc0, %ax
- movw %ax, %ss
- movw $0x244, %ax
- movw %ax, %sp
-
- xorl %eax,%eax
-cs movw saved_ss, %ax
- pushl %eax
-cs movl saved_esp, %eax
- pushl %eax
-o32 pushf
- xorl %eax,%eax
-cs movw temp_cs, %ax
- pushl %eax
-cs movw temp_ip, %ax
- pushl %eax
- pushl $0
- movw %gs, %ax
- pushl %eax
- movw %fs, %ax
- pushl %eax
- movw %es, %ax
- pushl %eax
- movw %ds, %ax
- pushl %eax
- movl saved_eax, %eax
- pushl %eax
- pushl %ebp
- pushl %edi
- pushl %esi
- pushl %edx
- pushl %ecx
- pushl %ebx
-
-o32 cs lidt saved_idt
-o32 cs lgdt saved_gdt
-
- /* Go back into protected mode reset PE to 1 */
- movl %cr0, %eax
- orl $1,%eax
- movl %eax, %cr0
-
- /* flush prefetch queue */
- jmp next_line
-next_line:
- movw $return_ptr, %ax
- movw %ax,%bp
-o32 cs ljmp *(%bp)
-
-.code32
-protected_mode:
- /* Reload segment registers */
- movl $0x18, %eax
- movw %ax, %fs
- movw %ax, %ds
- movw %ax, %gs
- movw %ax, %es
- movw %ax, %ss
- movl saved_protected_mode_esp, %eax
- movl %eax, %esp
- popf
- popa
- ret
-
-temp_eax:
- .long 0
-
-saved_ss:
- .word 0
-saved_esp:
- .long 0
-saved_eax:
- .long 0
-
-realmode_idt_ptr:
- .word 0x400
- .word 0x0, 0x0
-
-saved_gdt:
- .word 0, 0, 0, 0
-saved_idt:
- .word 0, 0, 0, 0
-
-saved_protected_mode_esp:
- .long 0
-
-return_ptr:
- .long protected_mode
- .word 0x10
diff --git a/arch/x86/lib/video.c b/arch/x86/lib/video.c
index 20e2416ae16f31f3ae8e441b8ec7b640e3dc00c4..81824f314457f859a6f1aebfed6ef6ab61941edc 100644 (file)
--- a/arch/x86/lib/video.c
+++ b/arch/x86/lib/video.c
#include <stdio_dev.h>
#include <i8042.h>
#include <asm/ptrace.h>
-#include <asm/realmode.h>
#include <asm/io.h>
#include <asm/pci.h>
int drv_video_init(void)
{
-#ifndef CONFIG_X86_NO_REAL_MODE
- if (video_bios_init())
- return 1;
-#endif
-
return video_init();
}
diff --git a/arch/x86/lib/video_bios.c b/arch/x86/lib/video_bios.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <malloc.h>
-#include <asm/ptrace.h>
-#include <asm/realmode.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include "bios.h"
-
-#undef PCI_BIOS_DEBUG
-#undef VGA_BIOS_DEBUG
-
-#ifdef VGA_BIOS_DEBUG
-#define PRINTF(fmt, args...) printf(fmt, ##args)
-#else
-#define PRINTF(fmt, args...)
-#endif
-
-#define PCI_CLASS_VIDEO 3
-#define PCI_CLASS_VIDEO_STD 0
-#define PCI_CLASS_VIDEO_PROG_IF_VGA 0
-
-DEFINE_PCI_DEVICE_TABLE(supported) = {
- {PCI_VIDEO_VENDOR_ID, PCI_VIDEO_DEVICE_ID},
- {}
-};
-
-static u32 probe_pci_video(void)
-{
- struct pci_controller *hose;
- pci_dev_t devbusfn = pci_find_devices(supported, 0);
-
- if ((devbusfn != -1)) {
- u32 old;
- u32 addr;
-
- /* PCI video device detected */
- printf("Found PCI VGA device at %02x.%02x.%x\n",
- PCI_BUS(devbusfn),
- PCI_DEV(devbusfn),
- PCI_FUNC(devbusfn));
-
- /* Enable I/O decoding as well, PCI viudeo boards
- * support I/O accesses, but they provide no
- * bar register for this since the ports are fixed.
- */
- pci_write_config_word(devbusfn,
- PCI_COMMAND,
- PCI_COMMAND_MEMORY |
- PCI_COMMAND_IO |
- PCI_COMMAND_MASTER);
-
- /* Test the ROM decoder, do the device support a rom? */
- pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old);
- pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS,
- (u32)PCI_ROM_ADDRESS_MASK);
- pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr);
- pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old);
-
- if (!addr) {
- printf("PCI VGA have no ROM?\n");
- return 0;
- }
-
- /* device have a rom */
- if (pci_shadow_rom(devbusfn, (void *)0xc0000)) {
- printf("Shadowing of PCI VGA BIOS failed\n");
- return 0;
- }
-
- /* Now enable lagacy VGA port access */
- hose = pci_bus_to_hose(PCI_BUS(devbusfn));
- if (pci_enable_legacy_video_ports(hose)) {
- printf("PCI VGA enable failed\n");
- return 0;
- }
-
-
- /* return the pci device info, that we'll need later */
- return PCI_BUS(devbusfn) << 8 |
- PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn) & 7);
- }
-
- return 0;
-}
-
-static int probe_isa_video(void)
-{
- u32 ptr;
- char *buf;
-
- ptr = isa_map_rom(0xc0000, 0x8000);
-
- if (!ptr)
- return -1;
-
- buf = malloc(0x8000);
- if (!buf) {
- isa_unmap_rom(ptr);
- return -1;
- }
-
- if (readw(ptr) != 0xaa55) {
- free(buf);
- isa_unmap_rom(ptr);
- return -1;
- }
-
- /* shadow the rom */
- memcpy(buf, (void *)ptr, 0x8000);
- isa_unmap_rom(ptr);
- memcpy((void *)0xc0000, buf, 0x8000);
-
- free(buf);
-
- return 0;
-}
-
-int video_bios_init(void)
-{
- struct pt_regs regs;
- int size;
- int i;
- u8 sum;
-
- /* clear the video bios area in case we warmbooted */
- memset((void *)0xc0000, 0, 0x8000);
- memset(®s, 0, sizeof(struct pt_regs));
-
- if (probe_isa_video())
- /* No ISA board found, try the PCI bus */
- regs.eax = probe_pci_video();
-
- /* Did we succeed in mapping any video bios */
- if (readw(0xc0000) == 0xaa55) {
- PRINTF("Found video bios signature\n");
- size = readb(0xc0002) * 512;
- PRINTF("size %d\n", size);
- sum = 0;
-
- for (i = 0; i < size; i++)
- sum += readb(0xc0000 + i);
-
- PRINTF("Checksum is %sOK\n", sum ? "NOT " : "");
-
- if (sum)
- return 1;
-
- /*
- * Some video bioses (ATI Mach64) seem to think that
- * the original int 10 handler is always at
- * 0xf000:0xf065 , place an iret instruction there
- */
- writeb(0xcf, 0xff065);
-
- regs.esp = 0x8000;
- regs.xss = 0x2000;
- enter_realmode(0xc000, 3, ®s, ®s);
-
- PRINTF("INT 0x10 vector after: %04x:%04x\n",
- readw(0x42), readw(0x40));
- PRINTF("BIOS returned %scarry\n",
- regs.eflags & 0x00000001 ? "" : "NOT ");
-#ifdef PCI_BIOS_DEBUG
- print_bios_bios_stat();
-#endif
- return regs.eflags & 0x00000001;
-
- }
-
- return 1;
-
-}
diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c
index 46af391f29f2a82baebd91acf6e55d638dc7524b..4e9e1f77e5ac35bda83ff2fe8b23c0e9970c9859 100644 (file)
--- a/arch/x86/lib/zimage.c
+++ b/arch/x86/lib/zimage.c
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/zimage.h>
-#include <asm/realmode.h>
#include <asm/byteorder.h>
#include <asm/bootparam.h>
#ifdef CONFIG_SYS_COREBOOT
else
*load_address = (void *)ZIMAGE_LOAD_ADDR;
-#if (defined CONFIG_ZBOOT_32 || defined CONFIG_X86_NO_REAL_MODE)
printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base);
memset(setup_base, 0, sizeof(*setup_base));
setup_base->hdr = params->hdr;
-#else
- /* load setup */
- printf("Moving Real-Mode Code to 0x%8.8lx (%d bytes)\n",
- (ulong)setup_base, setup_size);
- memmove(setup_base, image, setup_size);
-#endif
if (bootproto >= 0x0204)
kernel_size = hdr->syssize * 16;
@@ -241,10 +233,8 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
struct setup_header *hdr = &setup_base->hdr;
int bootproto = get_boot_protocol(hdr);
-#if (defined CONFIG_ZBOOT_32 || defined CONFIG_X86_NO_REAL_MODE)
setup_base->e820_entries = install_e820_map(
ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map);
-#endif
if (bootproto == 0x0100) {
setup_base->screen_info.cl_magic = COMMAND_LINE_MAGIC;
#ifdef CONFIG_SYS_COREBOOT
timestamp_add_now(TS_U_BOOT_START_KERNEL);
#endif
-#if defined CONFIG_ZBOOT_32
/*
* Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params
* structure, and then jump to the kernel. We assume that %cs is
"b"(0), "D"(0)
: "%ebp"
);
-#else
- struct pt_regs regs;
-
- memset(®s, 0, sizeof(struct pt_regs));
- regs.xds = (u32)setup_base >> 4;
- regs.xes = regs.xds;
- regs.xss = regs.xds;
- regs.esp = 0x9000;
- regs.eflags = 0;
- enter_realmode(((u32)setup_base + SETUP_START_OFFSET) >> 4, 0,
- ®s, ®s);
-#endif
}
void setup_pcat_compatibility(void)
index 744b927f1e2effdad6d8e6d61415c0f5b787ca13..c280029a36fee47c35aaa02f559457b746c1956e 100644 (file)
#
#Provide at least 16MB spacing between us and the Linux Kernel image
-PAD_TO := 12320
+CONFIG_SPL_PAD_TO := 12320
UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg
ifndef CONFIG_SPL_BUILD
ALL-y += $(obj)u-boot.ubl
diff --git a/board/avionic-design/dts/tegra20-medcom-wide.dts b/board/avionic-design/dts/tegra20-medcom-wide.dts
index f916122421a680e0362b37636897d31581f9641a..e46afbeab38e18491a026807a824c5a1b315e024 100644 (file)
reg = <0x00000000 0x20000000>;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = <32000>;
- };
+ host1x {
+ status = "okay";
- osc {
- clock-frequency = <12000000>;
- };
- };
+ dc@54200000 {
+ status = "okay";
- clock@60006000 {
- clocks = <&clk_32k &osc>;
+ rgb {
+ nvidia,panel = <&lcd_panel>;
+ status = "okay";
+ };
+ };
};
serial@70006300 {
usb@c5004000 {
status = "disabled";
};
+
+ lcd_panel: panel {
+ clock = <61715000>;
+ xres = <1366>;
+ yres = <768>;
+ left-margin = <2>;
+ right-margin = <47>;
+ hsync-len = <136>;
+ lower-margin = <21>;
+ upper-margin = <11>;
+ vsync-len = <4>;
+
+ nvidia,bits-per-pixel = <16>;
+ nvidia,pwm = <&pwm 0 500000>;
+ nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
+ nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+ nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+ nvidia,panel-timings = <0 0 0 0>;
+ };
};
diff --git a/board/avionic-design/dts/tegra20-plutux.dts b/board/avionic-design/dts/tegra20-plutux.dts
index 78c394f935894b952dce9689ded844ee069d28cc..3e6cce013e4910bf46c7b8a8e6e52c9360369e6f 100644 (file)
reg = <0x00000000 0x20000000>;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = <32000>;
- };
-
- osc {
- clock-frequency = <12000000>;
- };
- };
-
- clock@60006000 {
- clocks = <&clk_32k &osc>;
- };
-
serial@70006300 {
clock-frequency = <216000000>;
};
index 50ea3b51e4a7a575848bf97f968da47e4ebd3f27..bf3ff1d00974f101522d2959e6fbcd596a1d27f6 100644 (file)
reg = <0x00000000 0x20000000>;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = <32000>;
- };
+ host1x {
+ status = "okay";
- osc {
- clock-frequency = <12000000>;
- };
- };
+ dc@54200000 {
+ status = "okay";
- clock@60006000 {
- clocks = <&clk_32k &osc>;
+ rgb {
+ nvidia,panel = <&lcd_panel>;
+ status = "okay";
+ };
+ };
};
serial@70006300 {
clock-frequency = <216000000>;
};
+ nand-controller@70008000 {
+ nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+ nvidia,width = <8>;
+ nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+
+ nand@0 {
+ reg = <0>;
+ compatible = "hynix,hy27uf4g2b", "nand-flash";
+ };
+ };
+
i2c@7000c000 {
status = "disabled";
};
status = "disabled";
};
- nand-controller@70008000 {
- nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
- nvidia,width = <8>;
- nvidia,timing = <26 100 20 80 20 10 12 10 70>;
-
- nand@0 {
- reg = <0>;
- compatible = "hynix,hy27uf4g2b", "nand-flash";
- };
+ lcd_panel: panel {
+ clock = <33260000>;
+ xres = <800>;
+ yres = <480>;
+ left-margin = <120>;
+ right-margin = <120>;
+ hsync-len = <16>;
+ lower-margin = <15>;
+ upper-margin = <15>;
+ vsync-len = <15>;
+
+ nvidia,bits-per-pixel = <16>;
+ nvidia,pwm = <&pwm 0 500000>;
+ nvidia,backlight-enable-gpios = <&gpio 13 0>; /* PB5 */
+ nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+ nvidia,lvds-shutdown-gpios = <&gpio 10 0>; /* PB2 */
+ nvidia,panel-timings = <0 0 0 0>;
};
};
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index b25887bcaa80f2fa0aca87f6d831245081dba9f7..c0ea1c62290ad879ae5e78d5a2084d09bd6df6ab 100644 (file)
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
#ifdef CONFIG_OF_LIBFDT
#include <libfdt.h>
-#include <libfdt_env.h>
#include <fdt_support.h>
#endif /* CONFIG_OF_LIBFDT */
index 9e3e16906965dfd0833330fd6b2caa977aecde31..31b064d41871332ae589222281c250c3bad7f130 100644 (file)
reg = <0x00000000 0x20000000>;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = <32000>;
+ host1x {
+ status = "okay";
+ dc@54200000 {
+ status = "okay";
+ rgb {
+ status = "okay";
+ nvidia,panel = <&lcd_panel>;
+ };
};
- osc {
- clock-frequency = <12000000>;
- };
- };
-
- clock@60006000 {
- clocks = <&clk_32k &osc>;
};
serial@70006000 {
usb@c5004000 {
status = "disabled";
};
+
+ lcd_panel: panel {
+ /* PAZ00 has 1024x600 */
+ clock = <54030000>;
+ xres = <1024>;
+ yres = <600>;
+ right-margin = <160>;
+ left-margin = <24>;
+ hsync-len = <136>;
+ upper-margin = <3>;
+ lower-margin = <61>;
+ vsync-len = <6>;
+ hsync-active-high;
+ nvidia,bits-per-pixel = <16>;
+ nvidia,pwm = <&pwm 0 0>;
+ nvidia,backlight-enable-gpios = <&gpio 164 0>; /* PU4 */
+ nvidia,lvds-shutdown-gpios = <&gpio 102 0>; /* PM6 */
+ nvidia,backlight-vdd-gpios = <&gpio 176 0>; /* PW0 */
+ nvidia,panel-vdd-gpios = <&gpio 4 0>; /* PA4 */
+ nvidia,panel-timings = <400 4 203 17 15>;
+ };
};
index 6492d4168e1dacc08f13b4320b062c724d23906a..1447f47605b326cf51765c3c55c21c791b83b0f9 100644 (file)
return 0;
}
#endif
+
+#ifdef CONFIG_LCD
+/* this is a weak define that we are overriding */
+void pin_mux_display(void)
+{
+ debug("init display pinmux\n");
+
+ /* EN_VDD_PANEL GPIO A4 */
+ pinmux_tristate_disable(PINGRP_DAP2);
+}
+#endif
index 4450674a75989f8f87fe763acdf0535364b3492e..7aeed670db0594478a336049b04c4e418253f754 100644 (file)
reg = <0x00000000 0x40000000>;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = <32000>;
- };
- osc {
- clock-frequency = <12000000>;
- };
- };
-
- clock@60006000 {
- clocks = <&clk_32k &osc>;
- };
-
serial@70006000 {
clock-frequency = <216000000>;
};
status = "disabled";
};
+ spi@7000c380 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+
i2c@7000c400 {
status = "disabled";
};
diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- .sdata : { *(.sdata*) }
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss*) }
- .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
--- a/board/eNET/eNET.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc520.h>
-#include <net.h>
-#include <netdev.h>
-
-#ifdef CONFIG_HW_WATCHDOG
-#include <watchdog.h>
-#endif
-
-#include "hardware.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
-static void enet_timer_isr(void);
-static void enet_toggle_run_led(void);
-static void enet_setup_pars(void);
-
-/*
- * Miscellaneous platform dependent initializations
- */
-int board_early_init_f(void)
-{
- u16 pio_out_cfg = 0x0000;
-
- /* Configure General Purpose Bus timing */
- writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
- writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
- writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
- writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
- writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
- writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
- writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
-
- /* Configure Programmable Input/Output Pins */
- writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
- writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
- writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
- writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
- writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
- writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
-
- /*
- * Turn off top board
- * Set StrataFlash chips to 16-bit width
- * Set StrataFlash chips to normal (non reset/power down) mode
- */
- pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
- pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
- pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
- pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
- writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
-
- /* Turn off auxiliary power output */
- writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
-
- /* Clear FPGA program mode */
- writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
-
- enet_setup_pars();
-
- /* Disable Watchdog */
- writew(0x3333, &sc520_mmcr->wdtmrctl);
- writew(0xcccc, &sc520_mmcr->wdtmrctl);
- writew(0x0000, &sc520_mmcr->wdtmrctl);
-
- /* Chip Select Configuration */
- writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
- writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
- writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
-
- writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
- writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
- writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
-
- writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
- writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
-
- /* enable posted-writes */
- writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
-
- return 0;
-}
-
-static void enet_setup_pars(void)
-{
- /*
- * PARs 11 and 12 are 2MB SRAM @ 0x19000000
- *
- * These are setup now because older version of U-Boot have them
- * mapped to a different PAR which gets clobbered which prevents
- * using SRAM for warm-booting a new image
- */
- writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
- writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
-
- /* PARs 0 and 1 are Compact Flash slots (4kB each) */
- writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
- writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
-
- /* PAR 2 is used for Cache-As-RAM */
-
- /*
- * PARs 5 through 8 are additional NS16550 UARTS
- * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
- */
- writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
- writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
- writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
- writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
-
- /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
- writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
- writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
-
- /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
- writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
-
- /*
- * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
- * Already configured in board_init16 (eNET_start16.S)
- *
- * PAR 15 is Boot ROM
- * Already configured in board_init16 (eNET_start16.S)
- */
-}
-
-
-int board_early_init_r(void)
-{
- /* CPU Speed to 100MHz */
- gd->cpu_clk = 100000000;
-
- /* Crystal is 33.000MHz */
- gd->bus_clk = 33000000;
-
- return 0;
-}
-
-void show_boot_progress(int val)
-{
- uchar led_mask;
-
- led_mask = 0x00;
-
- if (val < 0)
- led_mask |= LED_ERR_BITMASK;
-
- led_mask |= (uchar)(val & 0x001f);
- outb(led_mask, LED_LATCH_ADDRESS);
-}
-
-
-int last_stage_init(void)
-{
- outb(0x00, LED_LATCH_ADDRESS);
-
- register_timer_isr(enet_timer_isr);
-
- printf("Serck Controls eNET\n");
-
- return 0;
-}
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = FLASH_CFI_8BIT;
- info->chipwidth = FLASH_CFI_BY8;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else {
- return 0;
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
-void setup_pcat_compatibility()
-{
- /* disable global interrupt mode */
- writeb(0x40, &sc520_mmcr->picicr);
-
- /* set all irqs to edge */
- writeb(0x00, &sc520_mmcr->pic_mode[0]);
- writeb(0x00, &sc520_mmcr->pic_mode[1]);
- writeb(0x00, &sc520_mmcr->pic_mode[2]);
-
- /*
- * active low polarity on PIC interrupt pins,
- * active high polarity on all other irq pins
- */
- writew(0x0000, &sc520_mmcr->intpinpol);
-
- /*
- * PIT 0 -> IRQ0
- * RTC -> IRQ8
- * FP error -> IRQ13
- * UART1 -> IRQ4
- * UART2 -> IRQ3
- */
- writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
- writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
- writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
- writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
- writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
-
- /* Disable all other interrupt sources */
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
-}
-
-void enet_timer_isr(void)
-{
- static long enet_ticks;
-
- enet_ticks++;
-
- /* Toggle Watchdog every 100ms */
- if ((enet_ticks % 100) == 0)
- hw_watchdog_reset();
-
- /* Toggle Run LED every 500ms */
- if ((enet_ticks % 500) == 0)
- enet_toggle_run_led();
-}
-
-void hw_watchdog_reset(void)
-{
- /* Watchdog Reset must be atomic */
- long flag = disable_interrupts();
-
- if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
- sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
- else
- sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
-
- if (flag)
- enable_interrupts();
-}
-
-void enet_toggle_run_led(void)
-{
- unsigned char leds_state = inb(LED_LATCH_ADDRESS);
- if (leds_state & LED_RUN_BITMASK)
- outb(leds_state & ~LED_RUN_BITMASK, LED_LATCH_ADDRESS);
- else
- outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
-}
diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
--- a/board/eNET/eNET_pci.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2008,2009
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/pci.h>
-#include <asm/arch/pci.h>
-
-static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
- /* a configurable lists of IRQs to steal when we need one */
- static int irq_list[] = {
- CONFIG_SYS_FIRST_PCI_IRQ,
- CONFIG_SYS_SECOND_PCI_IRQ,
- CONFIG_SYS_THIRD_PCI_IRQ,
- CONFIG_SYS_FORTH_PCI_IRQ
- };
- static int next_irq_index;
-
- uchar tmp_pin;
- int pin;
-
- pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
- pin = tmp_pin;
-
- pin -= 1; /* PCI config space use 1-based numbering */
- if (pin == -1)
- return; /* device use no irq */
-
- /* map device number + pin to a pin on the sc520 */
- switch (PCI_DEV(dev)) {
- case 12: /* First Ethernet Chip */
- pin += SC520_PCI_INTA;
- break;
-
- case 13: /* Second Ethernet Chip */
- pin += SC520_PCI_INTB;
- break;
-
- default:
- return;
- }
-
- pin &= 3; /* wrap around */
-
- if (sc520_pci_ints[pin] == -1) {
- /* re-route one interrupt for us */
- if (next_irq_index > 3)
- return;
-
- if (pci_sc520_set_irq(pin, irq_list[next_irq_index]))
- return;
-
- next_irq_index++;
- }
-
- if (-1 != sc520_pci_ints[pin])
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
- sc520_pci_ints[pin]);
-
- printf("fixup_irq: device %d pin %c irq %d\n",
- PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
-}
-
-static struct pci_controller enet_hose = {
- fixup_irq: pci_enet_fixup_irq,
-};
-
-void pci_init_board(void)
-{
- pci_sc520_init(&enet_hose);
-}
-
-int pci_set_regions(struct pci_controller *hose)
-{
- /* System memory space */
- pci_set_region(hose->regions + 0,
- SC520_PCI_MEMORY_BUS,
- SC520_PCI_MEMORY_PHYS,
- SC520_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* ISA/PCI memory space */
- pci_set_region(hose->regions + 1,
- SC520_ISA_MEM_BUS,
- SC520_ISA_MEM_PHYS,
- SC520_ISA_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(hose->regions + 2,
- SC520_PCI_IO_BUS,
- SC520_PCI_IO_PHYS,
- SC520_PCI_IO_SIZE,
- PCI_REGION_IO);
-
- /* ISA/PCI I/O space */
- pci_set_region(hose->regions + 3,
- SC520_ISA_IO_BUS,
- SC520_ISA_IO_PHYS,
- SC520_ISA_IO_SIZE,
- PCI_REGION_IO);
-
- return 4;
-}
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * 16bit initialization code.
- * This code have to map the area of the boot flash
- * that is used by U-boot to its final destination.
- */
-
-#include "config.h"
-#include "hardware.h"
-#include <asm/arch/sc520.h>
-#include <generated/asm-offsets.h>
-
-.text
-.section .start16, "ax"
-.code16
-.globl board_init16
-board_init16:
- /* Alias MMCR to 0xdf000 */
- movw $0xfffc, %dx
- movl $0x800df0cb, %eax
- outl %eax, %dx
-
- /* Set ds to point to MMCR alias */
- movw $0xdf00, %ax
- movw %ax, %ds
-
- /* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
- movl $GENERATED_SC520_PAR14, %edi
- movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
- movl %eax, (%di)
-
- /* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
- movl $GENERATED_SC520_PAR15, %edi
- movl $CONFIG_SYS_SC520_LLIO_PAR, %eax
- movl %eax, (%di)
-
- /* Disabe MMCR alias */
- movw $0xfffc, %dx
- movl $0x000000cb, %eax
- outl %eax, %dx
-
- jmp board_init16_ret
-
-.section .bios, "ax"
-.code16
-.globl realmode_reset
-.hidden realmode_reset
-.type realmode_reset, @function
-realmode_reset:
- /* Alias MMCR to 0xdf000 */
- movw $0xfffc, %dx
- movl $0x800df0cb, %eax
- outl %eax, %dx
-
- /* Set ds to point to MMCR alias */
- movw $0xdf00, %ax
- movw %ax, %ds
-
- /* issue software reset thorugh MMCR */
- movl $0xd72, %edi
- movb $0x01, %al
- movb %al, (%di)
-
-1: hlt
- jmp 1
diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
index f3dc20b2949e307f490ccf739c91297e13c23f6e..9c211ac5245c7f68f0a054cb2ad9c26226cc3db1 100644 (file)
--- a/board/evb64260/mpsc.c
+++ b/board/evb64260/mpsc.c
/* GT64240A errata: cant read MPSC/BRG registers... so make mirrors in ram for read/modify write */
-#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->mirror_hack[0]))
+#define MIRROR_HACK ((struct _tag_mirror_hack *)&(gd->arch.mirror_hack[0]))
#define GT_REG_WRITE_MIRROR_G(a,d) {MIRROR_HACK->a ## _M = d; GT_REG_WRITE(a,d);}
#define GTREGREAD_MIRROR_G(a) (MIRROR_HACK->a ## _M)
similarity index 66%
rename from board/eNET/Makefile
rename to board/freescale/b4860qds/Makefile
index ad1c5b1e189b10fa64f9739a9bbd6a690e346a54..06018f49c971b583be1a62feac0c89ce236eb9a7 100644 (file)
rename from board/eNET/Makefile
rename to board/freescale/b4860qds/Makefile
index ad1c5b1e189b10fa64f9739a9bbd6a690e346a54..06018f49c971b583be1a62feac0c89ce236eb9a7 100644 (file)
--- a/board/eNET/Makefile
#
-# (C) Copyright 2008
-# Graeme Russ, graeme.russ@gmail.com.
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+# Copyright 2012 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
LIB = $(obj)lib$(BOARD).o
-COBJS-y += eNET.o
-COBJS-$(CONFIG_PCI) += eNET_pci.o
-SOBJS-y += eNET_start16.o
-SOBJS-y += eNET_start.o
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-$(CONFIG_B4860QDS)+= eth_b4860qds.o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-y += law.o
+COBJS-y += tlb.o
-SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
#########################################################################
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
--- /dev/null
@@ -0,0 +1,505 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "b4860qds.h"
+#include "b4860qds_qixis.h"
+#include "b4860qds_crossbar_con.h"
+
+#define CLK_MUX_SEL_MASK 0x4
+#define ETH_PHY_CLK_OUT 0x4
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+ struct cpu_type *cpu = gd->arch.cpu;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ unsigned int i;
+ static const char *const freq[] = {"100", "125", "156.25", "161.13",
+ "122.88", "122.88", "122.88"};
+ int clock;
+
+ printf("Board: %sQDS, ", cpu->name);
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+ QIXIS_READ(id), QIXIS_READ(arch));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw >= 0x8 && sw <= 0xE)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ /* Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+ puts("Reset Configuration Word (RCW):");
+ for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+ u32 rcw = in_be32(&gur->rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf("\n %08x:", i * 4);
+ printf(" %08x", rcw);
+ }
+ puts("\n");
+
+ /*
+ * Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES Reference Clocks: ");
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = (sw >> 5) & 7;
+ printf("Bank1=%sMHz ", freq[clock]);
+ sw = QIXIS_READ(brdcfg[4]);
+ clock = (sw >> 6) & 3;
+ printf("Bank2=%sMHz\n", freq[clock]);
+
+ return 0;
+}
+
+int select_i2c_ch_pca(u8 ch)
+{
+ int ret;
+
+ /* Selecting proper channel via PCA*/
+ ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
+ if (ret) {
+ printf("PCA: failed to select proper channel.\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int configure_vsc3316_3308(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ unsigned int num_vsc16_con, num_vsc08_con;
+ u32 serdes1_prtcl, serdes2_prtcl;
+ int ret;
+
+ serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ if (!serdes1_prtcl) {
+ printf("SERDES1 is not enabled\n");
+ return 0;
+ }
+ serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ if (!serdes2_prtcl) {
+ printf("SERDES2 is not enabled\n");
+ return 0;
+ }
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+ switch (serdes1_prtcl) {
+ case 0x2a:
+ case 0x2C:
+ case 0x2D:
+ case 0x2E:
+ /*
+ * Configuration:
+ * SERDES: 1
+ * Lanes: A,B: SGMII
+ * Lanes: C,D,E,F,G,H: CPRI
+ */
+ debug("Configuring crossbar to use onboard SGMII PHYs:"
+ "srds_prctl:%x\n", serdes1_prtcl);
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sgmii_lane_ab, num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sgmii_lane_ab, num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+
+#ifdef CONFIG_PPC_B4420
+ case 0x18:
+ /*
+ * Configuration:
+ * SERDES: 1
+ * Lanes: A,B,C,D: SGMII
+ * Lanes: E,F,G,H: CPRI
+ */
+ debug("Configuring crossbar to use onboard SGMII PHYs:"
+ "srds_prctl:%x\n", serdes1_prtcl);
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sgmii_lane_cd, num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sgmii_lane_cd, num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+#endif
+
+ case 0x3E:
+ case 0x0D:
+ case 0x0E:
+ case 0x12:
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sfp, num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sfp, num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+ default:
+ printf("WARNING:VSC crossbars programming not supported for:%x"
+ " SerDes1 Protocol.\n", serdes1_prtcl);
+ return -1;
+ }
+
+ switch (serdes2_prtcl) {
+ case 0x9E:
+ case 0x9A:
+ case 0x98:
+ case 0xb2:
+ case 0x49:
+ case 0x4E:
+ case 0x8D:
+ case 0x7A:
+ num_vsc08_con = NUM_CON_VSC3308;
+ /* Configure VSC3308 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3308);
+ if (!ret) {
+ ret = vsc3308_config(VSC3308_TX_ADDRESS,
+ vsc08_tx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+ ret = vsc3308_config(VSC3308_RX_ADDRESS,
+ vsc08_rx_amc, num_vsc08_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+ default:
+ printf("WARNING:VSC crossbars programming not supported for: %x"
+ " SerDes2 Protocol.\n", serdes2_prtcl);
+ return -1;
+ }
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ /* Configure VSC3316 and VSC3308 crossbar switches */
+ if (configure_vsc3316_3308())
+ printf("VSC:failed to configure VSC3316/3308.\n");
+ else
+ printf("VSC:VSC3316/3308 successfully configured.\n");
+
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((sysclk_conf & 0x0C) >> 2) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (ddrclk_conf & 0x03) {
+ case QIXIS_CLK_100:
+ return 100000000;
+ case QIXIS_CLK_125:
+ return 125000000;
+ case QIXIS_CLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+static int serdes_refclock(u8 sw, u8 sdclk)
+{
+ unsigned int clock;
+ int ret = -1;
+ u8 brdcfg4;
+
+ if (sdclk == 1) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
+ return SRDS_PLLCR0_RFCK_SEL_125;
+ else
+ clock = (sw >> 5) & 7;
+ } else
+ clock = (sw >> 6) & 3;
+
+ switch (clock) {
+ case 0:
+ ret = SRDS_PLLCR0_RFCK_SEL_100;
+ break;
+ case 1:
+ ret = SRDS_PLLCR0_RFCK_SEL_125;
+ break;
+ case 2:
+ ret = SRDS_PLLCR0_RFCK_SEL_156_25;
+ break;
+ case 3:
+ ret = SRDS_PLLCR0_RFCK_SEL_161_13;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ ret = SRDS_PLLCR0_RFCK_SEL_122_88;
+ break;
+ default:
+ ret = -1;
+ break;
+ }
+
+ return ret;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ case SRDS_PLLCR0_RFCK_SEL_161_13:
+ return "161.13";
+ default:
+ return "122.88";
+ }
+}
+
+#define NUM_SRDS_BANKS 2
+
+int misc_init_r(void)
+{
+ u8 sw;
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 actual[NUM_SRDS_BANKS];
+ unsigned int i;
+ int clock;
+
+ sw = QIXIS_READ(brdcfg[2]);
+ clock = serdes_refclock(sw, 1);
+ if (clock >= 0)
+ actual[0] = clock;
+ else
+ printf("Warning: SDREFCLK1 switch setting is unsupported\n");
+
+ sw = QIXIS_READ(brdcfg[4]);
+ clock = serdes_refclock(sw, 2);
+ if (clock >= 0)
+ actual[1] = clock;
+ else
+ printf("Warning: SDREFCLK2 switch setting unsupported\n");
+
+ for (i = 0; i < NUM_SRDS_BANKS; i++) {
+ u32 pllcr0 = srds_regs->bank[i].pllcr0;
+ u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (expected != actual[i]) {
+ printf("Warning: SERDES bank %u expects reference clock"
+ " %sMHz, but actual is %sMHz\n", i + 1,
+ serdes_clock_to_string(expected),
+ serdes_clock_to_string(actual[i]));
+ }
+ }
+
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+}
+
+/*
+ * Dump board switch settings.
+ * The bits that cannot be read/sampled via some FPGA or some
+ * registers, they will be displayed as
+ * underscore in binary format. mask[] has those bits.
+ * Some bits are calculated differently than the actual switches
+ * if booting with overriding by FPGA.
+ */
+void qixis_dump_switch(void)
+{
+ int i;
+ u8 sw[5];
+
+ /*
+ * Any bit with 1 means that bit cannot be reverse engineered.
+ * It will be displayed as _ in binary format.
+ */
+ static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
+ char buf[10];
+ u8 brdcfg[16], dutcfg[16];
+
+ for (i = 0; i < 16; i++) {
+ brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+ dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+ }
+
+ sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
+ (brdcfg[9] & 0x08);
+ sw[1] = ((dutcfg[1] & 0x01) << 7) | \
+ ((dutcfg[2] & 0x07) << 4) | \
+ ((dutcfg[6] & 0x10) >> 1) | \
+ ((dutcfg[6] & 0x80) >> 5) | \
+ ((dutcfg[1] & 0x40) >> 5) | \
+ (dutcfg[6] & 0x01);
+ sw[2] = dutcfg[0];
+ sw[3] = 0;
+ sw[4] = ((brdcfg[1] & 0x30) << 2) | \
+ ((brdcfg[1] & 0xc0) >> 2) | \
+ (brdcfg[1] & 0x0f);
+
+ puts("DIP switch settings:\n");
+ for (i = 0; i < 5; i++) {
+ printf("SW%d = 0b%s (0x%02x)\n",
+ i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+ }
+}
diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
--- /dev/null
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CROSSBAR_CONNECTIONS_H__
+#define __CROSSBAR_CONNECTIONS_H__
+
+#define NUM_CON_VSC3316 8
+#define NUM_CON_VSC3308 4
+
+static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
+ {5, 11}, {4, 5}, {2, 6}, {12, 9} };
+
+static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1},
+ {5, 15}, {4, 14}, {2, 12}, {12, 13} };
+
+static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+#ifdef CONFIG_PPC_B4420
+static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+#endif
+static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
+ {11, 11}, {5, 10}, {6, 3}, {9, 12} };
+
+static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+#ifdef CONFIG_PPC_B4420
+static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+#endif
+
+static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1},
+ {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
+
+static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} };
+
+static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
+
+static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} };
+
+#endif
diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h
--- /dev/null
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __B4860QDS_QIXIS_H__
+#define __B4860QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for B4860QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* CLK */
+#define QIXIS_CLK_66 0x0
+#define QIXIS_CLK_100 0x1
+#define QIXIS_CLK_125 0x2
+#define QIXIS_CLK_133 0x3
+
+#define QIXIS_SRDS1CLK_122 0x5a
+#define QIXIS_SRDS1CLK_125 0x5e
+#endif
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
--- /dev/null
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 2147483648u,
+ .capacity = 4294967296u,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 1,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 2, /* ECC */
+ .burst_lengths_bitmask = 0x0c,
+
+ .tCKmin_X_ps = 1071,
+ .caslat_X = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
+ .tAA_ps = 13910,
+ .tWR_ps = 15000,
+ .tRCD_ps = 13910,
+ .tRRD_ps = 6000,
+ .tRP_ps = 13910,
+ .tRAS_ps = 34000,
+ .tRC_ps = 48910,
+ .tRFC_ps = 260000,
+ .tWTR_ps = 7500,
+ .tRTP_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tFAW_ps = 35000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "RAW timing DDR";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2T;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
+ {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
+ {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
+ {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
+ {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
+ {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twoT_en = pbsp->force_2T;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->twoT_en = pbsp_highest->force_2T;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
--- /dev/null
@@ -0,0 +1,338 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Author: Sandeep Kumar Singh <sandeep@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
+
+/*
+ * This file handles the board muxing between the Fman Ethernet MACs and
+ * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
+ * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
+ * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
+ * one Fman device on B4860. The SERDES configuration is used to determine
+ * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
+ * to which PHYs. So for a given Fman MAC, there is one and only PHY it
+ * connects to. MACs cannot be routed to PHYs dynamically. This configuration
+ * is done at boot time by reading SERDES protocol from RCW.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fdt_support.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+#include "../common/qixis.h"
+#include "b4860qds_qixis.h"
+
+#define EMI_NONE 0xFFFFFFFF
+
+#ifdef CONFIG_FMAN_ENET
+
+/*
+ * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
+ * lane at index is mapped to slot number n. A value of '0' will mean
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 1, 1, 1, 1,
+ 0, 0, 0, 0
+};
+
+/*
+ * This function initializes the lane_to_slot[] array. It reads RCW to check
+ * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
+ * lane_to_slot[] accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+ unsigned int serdes2_prtcl;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Initializing lane to slot: Serdes2 protocol: %x\n",
+ serdes2_prtcl);
+
+ switch (serdes2_prtcl) {
+ case 0x18:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: SGMII
+ * Lanes: E,F: Aur
+ * Lanes: G,H: SRIO
+ */
+ case 0x91:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B: SGMII
+ * Lanes: C,D: SRIO2
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x93:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: SGMII
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x98:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: XAUI2
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x9a:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B: PCI
+ * Lanes: C,D: SGMII
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0x9e:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: PCI
+ * Lanes: E,F,G,H: XAUI2
+ */
+ case 0xb2:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B,C,D: PCI
+ * Lanes: E,F: SGMII 3&4
+ * Lanes: G,H: XFI
+ */
+ case 0xc2:
+ /*
+ * Configuration:
+ * SERDES: 2
+ * Lanes: A,B: SGMII
+ * Lanes: C,D: SRIO2
+ * Lanes: E,F,G,H: XAUI2
+ */
+ lane_to_slot[12] = 2;
+ lane_to_slot[13] = lane_to_slot[12];
+ lane_to_slot[14] = lane_to_slot[12];
+ lane_to_slot[15] = lane_to_slot[12];
+ break;
+
+ default:
+ printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ break;
+ }
+ return;
+}
+
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+ struct memac_mdio_info memac_mdio_info;
+ struct memac_mdio_info tg_memac_mdio_info;
+ unsigned int i;
+ unsigned int serdes1_prtcl, serdes2_prtcl;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ if (!serdes1_prtcl) {
+ printf("SERDES1 is not enabled\n");
+ return 0;
+ }
+ serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ if (!serdes2_prtcl) {
+ printf("SERDES2 is not enabled\n");
+ return 0;
+ }
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+ printf("Initializing Fman\n");
+
+ initialize_lane_to_slot();
+
+ memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+ memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fm_memac_mdio_init(bis, &memac_mdio_info);
+
+ tg_memac_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the real 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tg_memac_mdio_info);
+
+ /*
+ * Program the two on board DTSEC PHY addresses assuming that they are
+ * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
+ * 6 to on board SGMII phys
+ */
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+
+ switch (serdes1_prtcl) {
+ case 0x2a:
+ /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
+ debug("Setting phy addresses for FM1_DTSEC5: %x and"
+ "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ /* Fixing Serdes clock by programming FPGA register */
+ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+ fm_info_set_phy_address(FM1_DTSEC5,
+ CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6,
+ CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ break;
+#ifdef CONFIG_PPC_B4420
+ case 0x18:
+ /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
+ debug("Setting phy addresses for FM1_DTSEC3: %x and"
+ "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
+ CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ /* Fixing Serdes clock by programming FPGA register */
+ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ break;
+#endif
+ default:
+ printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
+ serdes1_prtcl);
+ break;
+ }
+ switch (serdes2_prtcl) {
+ case 0x18:
+ debug("Setting phy addresses on SGMII Riser card for"
+ "FM1_DTSEC ports: \n");
+ fm_info_set_phy_address(FM1_DTSEC1,
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
+ break;
+ case 0x49:
+ debug("Setting phy addresses on SGMII Riser card for"
+ "FM1_DTSEC ports: \n");
+ fm_info_set_phy_address(FM1_DTSEC1,
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
+ break;
+ case 0x8d:
+ case 0xb2:
+ debug("Setting phy addresses on SGMII Riser card for"
+ "FM1_DTSEC ports: \n");
+ fm_info_set_phy_address(FM1_DTSEC3,
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4,
+ CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+ break;
+ default:
+ printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
+ serdes2_prtcl);
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1;
+
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ fm_info_set_mdio(i,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+ break;
+ case PHY_INTERFACE_MODE_NONE:
+ fm_info_set_phy_address(i, 0);
+ break;
+ default:
+ printf("Fman1: DTSEC%u set to unknown interface %i\n",
+ idx + 1, fm_info_get_enet_if(i));
+ fm_info_set_phy_address(i, 0);
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif
+
+ return pci_eth_init(bis);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ int phy;
+ char alias[32];
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ phy = fm_info_get_phy_address(port);
+
+ sprintf(alias, "phy_sgmii_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ int i;
+ char alias[32];
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_NONE:
+ sprintf(alias, "ethernet%u", i);
+ fdt_status_disabled_by_alias(fdt, alias);
+ break;
+ default:
+ break;
+ }
+ }
+}
similarity index 51%
rename from board/micronas/vct/u-boot.lds
rename to board/freescale/b4860qds/law.c
index 2ce8d0e158f4cb29b5d05ebc4e762000b26f92f4..4142e014d6f2f9f39b7c354aa7d5fe8b7a367972 100644 (file)
rename from board/micronas/vct/u-boot.lds
rename to board/freescale/b4860qds/law.c
index 2ce8d0e158f4cb29b5d05ebc4e762000b26f92f4..4142e014d6f2f9f39b7c354aa7d5fe8b7a367972 100644 (file)
/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- . = ALIGN(4);
- .sdata : { *(.sdata*) }
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- . = ALIGN(4);
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss*) }
- . = ALIGN(4);
- .bss (NOLOAD) : { *(.bss*) }
- uboot_end = .;
-}
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
similarity index 71%
rename from arch/x86/include/asm/arch-sc520/ssi.h
rename to board/freescale/b4860qds/pci.c
index bd48eab1610c15fdad6ba85a3fcf9b1fbf0a1a46..b130d130374ac8161f1033ca3f4f631dddaf9125 100644 (file)
rename from arch/x86/include/asm/arch-sc520/ssi.h
rename to board/freescale/b4860qds/pci.c
index bd48eab1610c15fdad6ba85a3fcf9b1fbf0a1a46..b130d130374ac8161f1033ca3f4f631dddaf9125 100644 (file)
/*
- * (C) Copyright 2008
- * Graeme Russ <graeme.russ@gmail.com>.
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-#ifndef _ASM_IC_SSI_H_
-#define _ASM_IC_SSI_H_ 1
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
-int ssi_set_interface(int, int, int, int);
-void ssi_chip_select(int);
-u8 ssi_txrx_byte(u8);
-void ssi_tx_byte(u8);
-u8 ssi_rx_byte(void);
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
-
-#endif
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
--- /dev/null
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_64K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_64K, 1),
+#endif
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_4K, 1),
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
index 2e0e55f47b6cfc5018f6247d377a0042d69e375c..fe870b64d202f975d5d1fa0c78ecd2af4bab67d1 100644 (file)
{
struct cpu_type *cpu;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
printf("Board: %sRDB\n", cpu->name);
return 0;
similarity index 71%
rename from board/isee/igep0030/Makefile
rename to board/freescale/bsc9132qds/Makefile
index cbc03d43149301493474ed10e90c06d66f2f3293..267400becb14a2be4ccd82d49f7338bf6cbd45e5 100644 (file)
rename from board/isee/igep0030/Makefile
rename to board/freescale/bsc9132qds/Makefile
index cbc03d43149301493474ed10e90c06d66f2f3293..267400becb14a2be4ccd82d49f7338bf6cbd45e5 100644 (file)
#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright 2013 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
LIB = $(obj)lib$(BOARD).o
-COBJS := igep0030.o
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
-SRCS := $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS)
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS))
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
#########################################################################
# defines $(obj).depend target
diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README
--- /dev/null
@@ -0,0 +1,150 @@
+Overview
+--------
+ The BSC9132 is a highly integrated device that targets the evolving
+ Microcell, Picocell, and Enterprise-Femto base station market subsegments.
+
+ The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
+ core technologies with MAPLE-B2P baseband acceleration processing elements
+ to address the need for a high performance, low cost, integrated solution
+ that handles all required processing layers without the need for an
+ external device except for an RF transceiver or, in a Micro base station
+ configuration, a host device that handles the L3/L4 and handover between
+ sectors.
+
+ The BSC9132 SoC includes the following function and features:
+ - Power Architecture subsystem including two e500 processors with
+ 512-Kbyte shared L2 cache
+ - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
+ cache
+ - 32 Kbyte of shared M3 memory
+ - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
+ Processing (MAPLE-B2P)
+ - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
+ ECC), up to 1333 MHz data rate
+ - Dedicated security engine featuring trusted boot
+ - Two DMA controllers
+ - OCNDMA with four bidirectional channels
+ - SysDMA with sixteen bidirectional channels
+ - Interfaces
+ - Four-lane SerDes PHY
+ - PCI Express controller complies with the PEX Specification-Rev 2.0
+ - Two Common Public Radio Interface (CPRI) controller lanes
+ - High-speed USB 2.0 host and device controller with ULPI interface
+ - Enhanced secure digital (SD/MMC) host controller (eSDHC)
+ - Antenna interface controller (AIC), supporting four industry
+ standard JESD207/four custom ADI RF interfaces
+ - ADI lanes support both full duplex FDD support & half duplex TDD
+ - Universal Subscriber Identity Module (USIM) interface that
+ facilitates communication to SIM cards or Eurochip pre-paid phone
+ cards
+ - Two DUART, two eSPI, and two I2C controllers
+ - Integrated Flash memory controller (IFC)
+ - GPIO
+ - Sixteen 32-bit timers
+
+The SC3850 core subsystem consists of the following:
+ - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
+ - 32 KB, 8-way, level 1 data cache (L1 DCache)
+ - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory)
+ - Memory management unit (MMU)
+ - Global interrupt controller ( GIC)
+ - Debug and profiling unit (DPU)
+ - Two 32-bit quad timers
+
+BSC9132QDS board Overview
+-------------------------
+ 2Gbyte DDR3 (on board DDR), Dual Ranki
+ 32Mbyte 16bit NOR flash
+ 128Mbyte 2K page size NAND Flash
+ 256 Kbit M24256 I2C EEPROM
+ 128 Mbit SPI Flash memory
+ SD slot
+ USB-ULPI
+ eTSEC1: Connected to SGMII PHY
+ eTSEC2: Connected to SGMII PHY
+ PCIe
+ CPRI
+ SerDes
+ I2C RTC
+ DUART interface: supports one UARTs up to 115200 bps for console display
+
+Frequency Combinations Supported
+--------------------------------
+Core MHz/CCB MHz/DDR(MT/s)
+1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz
+ (SYSCLK = 100MHz, DDRCLK = 100MHz)
+2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz
+ (SYSCLK = 100MHz, DDRCLK = 133MHz)
+
+Boot Methods Supported
+-----------------------
+1. NOR Flash
+2. NAND Flash
+3. SD Card
+4. SPI flash
+
+Default Boot Method
+--------------------
+NOR boot
+
+Building U-boot
+--------------
+To build the u-boot for BSC9132QDS:
+1. NOR Flash
+ make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
+ make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
+2. NAND Flash : It is currently not supported
+3. SPI Flash
+ make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
+ make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
+4. SD Card
+ make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
+ make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
+
+Memory map
+-----------
+ 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable
+ 0x8000_0000 0x8FFF_FFFF NOR Flash 256M
+ 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M
+ 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M
+ 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M
+ 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M
+ 0xC000_0000 0xC000_7FFF M3 Memory 32K
+ 0xC001_0000 0xC001_FFFF PCI Express I/O 64K
+ 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
+ 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K
+ 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K
+ 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
+ 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
+ 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
+ 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
+ 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
+
+Flashing Images
+---------------
+To place a new u-boot image in the NAND flash and then boot
+with that new image temporarily, use this:
+ tftp 1000000 u-boot-nand.bin
+ nand erase 0 100000
+ nand write 1000000 0 100000
+ reset
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts
+
+Booting Linux
+-------------
+Place a linux uImage in the TFTP disk area.
+
+ tftp 1000000 uImage
+ tftp 2000000 rootfs.ext2.gz.uboot
+ tftp c00000 bsc9132qds.dtb
+ bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
--- /dev/null
@@ -0,0 +1,403 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_mdio.h>
+#include <tsec.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <asm/fsl_ifc.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <asm/fsl_ddr_sdram.h>
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#endif
+
+#include "../common/qixis.h"
+DECLARE_GLOBAL_DATA_PTR;
+
+
+int board_early_init_f(void)
+{
+ struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;
+
+ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
+
+ return 0;
+}
+
+void board_config_serdes_mux(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 pordevsr = in_be32(&gur->pordevsr);
+ u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+ MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+
+ switch (srds_cfg) {
+ /* PEX(1) PEX(2) CPRI 2 CPRI 1 */
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ case 5:
+ case 22:
+ case 23:
+ case 24:
+ case 25:
+ case 26:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x03);
+ break;
+
+ /* PEX(1) PEX(2) SGMII1 CPRI 1 */
+ case 6:
+ case 7:
+ case 8:
+ case 9:
+ case 10:
+ case 27:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x01);
+ break;
+
+ /* PEX(1) PEX(2) SGMII1 SGMII2 */
+ case 11:
+ case 32:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x00);
+ break;
+
+ /* PEX(1) SGMII2 CPRI 2 CPRI 1 */
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 16:
+ case 33:
+ case 34:
+ case 35:
+ case 36:
+ case 37:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x07);
+ break;
+
+ /* PEX(1) SGMII2 SGMII1 CPRI 1 */
+ case 17:
+ case 18:
+ case 19:
+ case 20:
+ case 21:
+ case 38:
+ case 39:
+ case 40:
+ case 41:
+ case 42:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x05);
+ break;
+
+ /* SGMII1 SGMII2 CPRI 2 CPRI 1 */
+ case 43:
+ case 44:
+ case 45:
+ case 46:
+ case 47:
+ QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
+ break;
+
+
+ default:
+ break;
+ }
+}
+
+int board_early_init_r(void)
+{
+#ifndef CONFIG_SYS_NO_FLASH
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_64M, 1);
+
+ set_tlb(1, flashbase + 0x4000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
+#endif
+ board_config_serdes_mux();
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+#endif /* ifdef CONFIG_PCI */
+
+int checkboard(void)
+{
+ struct cpu_type *cpu;
+ u8 sw;
+
+ cpu = gd->arch.cpu;
+ printf("Board: %sQDS\n", cpu->name);
+
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
+ QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ printf("IFC chip select:");
+ switch (sw) {
+ case 0:
+ printf("NOR\n");
+ break;
+ case 2:
+ printf("Promjet\n");
+ break;
+ case 4:
+ printf("NAND\n");
+ break;
+ default:
+ printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+ break;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[4];
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+
+#endif
+
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ num++;
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+
+ fsl_pq_mdio_init(bis, &mdio_info);
+ tsec_eth_init(bis, tsec_info, num);
+
+ #ifdef CONFIG_PCI
+ pci_eth_init(bis);
+ #endif
+
+ return 0;
+}
+#endif
+
+#define USBMUX_SEL_MASK 0xc0
+#define USBMUX_SEL_UART2 0xc0
+#define USBMUX_SEL_USB 0x40
+#define SPIMUX_SEL_UART3 0x80
+#define GPS_MUX_SEL_GPS 0x40
+
+#define TSEC_1588_CLKIN_MASK 0x03
+#define CON_XCVR_REF_CLK 0x00
+
+int misc_init_r(void)
+{
+ u8 val;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 porbmsr = in_be32(&gur->porbmsr);
+ u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+
+ /*Configure 1588 clock-in source from RF Card*/
+ val = QIXIS_READ_I2C(brdcfg[5]);
+ QIXIS_WRITE_I2C(brdcfg[5],
+ (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);
+
+ if (hwconfig("uart2") && hwconfig("usb1")) {
+ printf("UART2 and USB cannot work together on the board\n");
+ printf("Remove one from hwconfig and reset\n");
+ } else {
+ if (hwconfig("uart2")) {
+ val = QIXIS_READ_I2C(brdcfg[5]);
+ QIXIS_WRITE_I2C(brdcfg[5],
+ (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
+ clrbits_be32(&gur->pmuxcr3,
+ MPC85xx_PMUXCR3_USB_SEL_MASK);
+ setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
+ } else {
+ /* By default USB should be selected.
+ * Programming FPGA to select USB. */
+ val = QIXIS_READ_I2C(brdcfg[5]);
+ QIXIS_WRITE_I2C(brdcfg[5],
+ (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
+ }
+
+ }
+
+ if (hwconfig("sim")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SPI) {
+
+ val = QIXIS_READ_I2C(brdcfg[3]);
+ QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
+ clrbits_be32(&gur->pmuxcr,
+ MPC85xx_PMUXCR0_SIM_SEL_MASK);
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
+ }
+ }
+
+ if (hwconfig("uart3")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SDHC) {
+
+ /* UART3 and SPI1 (Flashes) are muxed together */
+ val = QIXIS_READ_I2C(brdcfg[3]);
+ QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
+ clrbits_be32(&gur->pmuxcr3,
+ MPC85xx_PMUXCR3_UART3_SEL_MASK);
+ setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);
+
+ /* MUX to select UART3 connection to J24 header
+ * or to GPS */
+ val = QIXIS_READ_I2C(brdcfg[6]);
+ if (hwconfig("gps"))
+ QIXIS_WRITE_I2C(brdcfg[6],
+ (val | GPS_MUX_SEL_GPS));
+ else
+ QIXIS_WRITE_I2C(brdcfg[6],
+ (val & ~(GPS_MUX_SEL_GPS)));
+ }
+ }
+ return 0;
+}
+
+void fdt_del_node_compat(void *blob, const char *compatible)
+{
+ int err;
+ int off = fdt_node_offset_by_compatible(blob, -1, compatible);
+ if (off < 0) {
+ printf("WARNING: could not find compatible node %s: %s.\n",
+ compatible, fdt_strerror(off));
+ return;
+ }
+ err = fdt_del_node(blob, off);
+ if (err < 0) {
+ printf("WARNING: could not remove %s: %s.\n",
+ compatible, fdt_strerror(err));
+ }
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ #if defined(CONFIG_PCI)
+ FT_FSL_PCI_SETUP;
+ #endif
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 porbmsr = in_be32(&gur->porbmsr);
+ u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf;
+
+ if (!(hwconfig("uart2") && hwconfig("usb1"))) {
+ /* If uart2 is there in hwconfig remove usb node from
+ * device tree */
+
+ if (hwconfig("uart2")) {
+ /* remove dts usb node */
+ fdt_del_node_compat(blob, "fsl-usb2-dr");
+ } else {
+ fdt_fixup_dr_usb(blob, bd);
+ fdt_del_node_and_alias(blob, "serial2");
+ }
+ }
+
+ if (hwconfig("uart3")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SDHC)
+ /* Delete SPI node from the device tree */
+ fdt_del_node_and_alias(blob, "spi1");
+ } else
+ fdt_del_node_and_alias(blob, "serial3");
+
+ if (hwconfig("sim")) {
+ if (romloc == PORBMSR_ROMLOC_NAND_2K ||
+ romloc == PORBMSR_ROMLOC_NOR ||
+ romloc == PORBMSR_ROMLOC_SPI) {
+
+ /* remove dts sdhc node */
+ fdt_del_node_compat(blob, "fsl,esdhc");
+ } else if (romloc == PORBMSR_ROMLOC_SDHC) {
+
+ /* remove dts sim node */
+ fdt_del_node_compat(blob, "fsl,sim-v1.0");
+ printf("SIM & SDHC can't work together on the board");
+ printf("\nRemove sim from hwconfig and reset\n");
+ }
+ }
+}
+#endif
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
--- /dev/null
@@ -0,0 +1,209 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/processor.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = {
+ .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
+ .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
+ .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
+ .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333,
+ .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333,
+ .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
+ .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333,
+ .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
+ .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
+ .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333,
+ .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333,
+ .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
+ .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333,
+ .ddr_data_init = CONFIG_MEM_INIT_VALUE,
+ .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333,
+ .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
+ .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
+ .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
+ .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
+ .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
+ .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333,
+ .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
+ .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
+ .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
+};
+
+
+fixed_ddr_parm_t fixed_ddr_parm_0[] = {
+ {750, 850, &ddr_cfg_regs_800},
+ {1060, 1333, &ddr_cfg_regs_1333},
+ {0, 0, NULL}
+};
+
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+phys_size_t fixed_sdram(void)
+{
+ int i;
+ char buf[32];
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
+ phys_size_t ddr_size;
+ ulong ddr_freq, ddr_freq_mhz;
+
+ ddr_freq = get_ddr_freq(0);
+ ddr_freq_mhz = ddr_freq / 1000000;
+
+ printf("Configuring DDR for %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
+ if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
+ (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
+ memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
+ sizeof(ddr_cfg_regs));
+ break;
+ }
+ }
+
+ if (fixed_ddr_parm_0[i].max_freq == 0)
+ panic("Unsupported DDR data rate %s MT/s data rate\n",
+ strmhz(buf, ddr_freq));
+
+ ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
+ LAW_TRGT_IF_DDR_1) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ }
+
+ return ddr_size;
+}
+
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
+/* Micron MT41J512M8_187E */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 1073741824u,
+ .capacity = 1073741824u,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 0,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+
+ .tCKmin_X_ps = 1870,
+ .caslat_X = 0x1e << 4, /* 5,6,7,8 */
+ .tAA_ps = 13125,
+ .tWR_ps = 15000,
+ .tRCD_ps = 13125,
+ .tRRD_ps = 7500,
+ .tRP_ps = 13125,
+ .tRAS_ps = 37500,
+ .tRC_ps = 50625,
+ .tRFC_ps = 160000,
+ .tWTR_ps = 7500,
+ .tRTP_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tFAW_ps = 37500,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR on board";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ int i;
+ popts->clk_adjust = 6;
+ popts->cpo_override = 0x1f;
+ popts->write_data_delay = 2;
+ popts->half_strength_driver_enable = 1;
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+ popts->wrlvl_start = 0x8;
+ popts->trwt_override = 1;
+ popts->trwt = 0;
+
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
+ popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
+ }
+}
+
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
similarity index 60%
rename from arch/x86/include/asm/realmode.h
rename to board/freescale/bsc9132qds/law.c
index 0f12a893b441adb148954774165feeb8dd53033f..dc2365851b49f974fb71806d5a30029dc8914de1 100644 (file)
rename from arch/x86/include/asm/realmode.h
rename to board/freescale/bsc9132qds/law.c
index 0f12a893b441adb148954774165feeb8dd53033f..dc2365851b49f974fb71806d5a30029dc8914de1 100644 (file)
/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ * Copyright 2013 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-#ifndef __ASM_REALMODE_H_
-#define __ASM_REALMODE_H_
-#include <asm/ptrace.h>
-
-extern ulong __realmode_start;
-extern ulong __realmode_size;
-extern char realmode_enter;
-
-int bios_setup(void);
-int enter_realmode(u16 seg, u16 off, struct pt_regs *in, struct pt_regs *out);
-int enter_realmode_int(u8 lvl, struct pt_regs *in, struct pt_regs *out);
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC),
#endif
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
--- /dev/null
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR (PA) */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_64M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_64M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT)
+ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 8, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_PCI
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_64K, 1),
+#endif
+
+ /* *I*G - Board FPGA */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_256K, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
index c92902a92edc2b327304d92f2e67ef0f33239ba4..2b74d0201e4bdf31c090698134f50675c8c1b86d 100644 (file)
#include <common.h>
#include <command.h>
#include <asm/io.h>
+#include <linux/time.h>
+#include <i2c.h>
#include "qixis.h"
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+u8 qixis_read_i2c(unsigned int reg)
+{
+ return i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);
+}
+
+void qixis_write_i2c(unsigned int reg, u8 value)
+{
+ u8 val = value;
+ i2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);
+}
+#endif
+
u8 qixis_read(unsigned int reg)
{
void *p = (void *)QIXIS_BASE;
out_8(p + reg, value);
}
+u16 qixis_read_minor(void)
+{
+ u16 minor;
+
+ /* this data is in little endian */
+ QIXIS_WRITE(tagdata, 5);
+ minor = QIXIS_READ(tagdata);
+ QIXIS_WRITE(tagdata, 6);
+ minor += QIXIS_READ(tagdata) << 8;
+
+ return minor;
+}
+
+char *qixis_read_time(char *result)
+{
+ time_t time = 0;
+ int i;
+
+ /* timestamp is in 32-bit big endian */
+ for (i = 8; i <= 11; i++) {
+ QIXIS_WRITE(tagdata, i);
+ time = (time << 8) + QIXIS_READ(tagdata);
+ }
+
+ return ctime_r(&time, result);
+}
+
+char *qixis_read_tag(char *buf)
+{
+ int i;
+ char tag, *ptr = buf;
+
+ for (i = 16; i <= 63; i++) {
+ QIXIS_WRITE(tagdata, i);
+ tag = QIXIS_READ(tagdata);
+ *(ptr++) = tag;
+ if (!tag)
+ break;
+ }
+ if (i > 63)
+ *ptr = '\0';
+
+ return buf;
+}
+
+/*
+ * return the string of binary of u8 in the format of
+ * 1010 10_0. The masked bit is filled as underscore.
+ */
+const char *byte_to_binary_mask(u8 val, u8 mask, char *buf)
+{
+ char *ptr;
+ int i;
+
+ ptr = buf;
+ for (i = 0x80; i > 0x08 ; i >>= 1, ptr++)
+ *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
+ *(ptr++) = ' ';
+ for (i = 0x08; i > 0 ; i >>= 1, ptr++)
+ *ptr = (val & i) ? '1' : ((mask & i) ? '_' : '0');
+
+ *ptr = '\0';
+
+ return buf;
+}
+
void qixis_reset(void)
{
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
QIXIS_WRITE(brdcfg[0], reg);
}
-#ifdef DEBUG
static void qixis_dump_regs(void)
{
int i;
printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
}
-#endif
+
+static void __qixis_dump_switch(void)
+{
+ puts("Reverse engineering switch is not implemented for this board\n");
+}
+
+void qixis_dump_switch(void)
+ __attribute__((weak, alias("__qixis_dump_switch")));
int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -122,16 +209,13 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
}
- }
-
-#ifdef DEBUG
- else if (strcmp(argv[1], "dump") == 0) {
+ } else if (strcmp(argv[1], "dump") == 0) {
qixis_dump_regs();
return 0;
- }
-#endif
-
- else {
+ } else if (strcmp(argv[1], "switch") == 0) {
+ qixis_dump_switch();
+ return 0;
+ } else {
printf("Invalid option: %s\n", argv[1]);
return 1;
}
"qixis_reset altbank - reset to alternate bank\n"
"qixis watchdog <watchdog_period> - set the watchdog period\n"
" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
-#ifdef DEBUG
"qixis_reset dump - display the QIXIS registers\n"
-#endif
+ "qixis_reset switch - display switch\n"
);
index b98b18065569ee3f1e58413f5c1c0d5e9f21205c..8d914d54859ce134eaa076b5e9173482346ff49b 100644 (file)
u8 qixis_read(unsigned int reg);
void qixis_write(unsigned int reg, u8 value);
+u16 qixis_read_minor(void);
+char *qixis_read_time(char *result);
+char *qixis_read_tag(char *buf);
+const char *byte_to_binary_mask(u8 val, u8 mask, char *buf);
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+u8 qixis_read_i2c(unsigned int reg);
+void qixis_write_i2c(unsigned int reg, u8 value);
+#endif
#define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
#define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
+#ifdef CONFIG_SYS_I2C_FPGA_ADDR
+#define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
+#define QIXIS_WRITE_I2C(reg, value) \
+ qixis_write_i2c(offsetof(struct qixis, reg), value)
+#endif
#endif
index 21428e3347633eeddaaedf6a7ee619144ea73449..48f7155faf4354f6633202a9bf29a744c09e3b0a 100644 (file)
int checkboard (void)
{
u8 sw;
- struct cpu_type *cpu = gd->cpu;
+ struct cpu_type *cpu = gd->arch.cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
static const char * const freq[] = {"100", "125", "156.25", "212.5" };
diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/corenet_ds/rcw_p2041rdb.cfg
--- /dev/null
@@ -0,0 +1,11 @@
+#
+# Default RCW for P2041RDB.
+#
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+12600000 00000000 241C0000 00000000
+649FA0C1 C3C02000 58000000 40000000
+00000000 00000000 00000000 D0030F07
+00000000 00000000 00000000 00000000
index 1071803c79ad001dd1abf72c7d39bb70edf9240a..648f0ec3e3feaa369a52a19aece54dbbf9e5e44f 100644 (file)
#include <vsc7385.h>
#include <ns16550.h>
#include <nand.h>
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
#include <asm/gpio.h>
#endif
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
gd->flags |= GD_FLG_SILENT;
#endif
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
mpc83xx_gpio_init_f();
#endif
int board_early_init_r(void)
{
-#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_MPC83XX_GPIO) && !defined(CONFIG_SPL_BUILD)
mpc83xx_gpio_init_r();
#endif
return 0;
}
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
static struct pci_region pci_regions[] = {
{
.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
#endif
}
#endif
-#else /* CONFIG_NAND_SPL */
+#else /* CONFIG_SPL_BUILD */
void board_init_f(ulong bootflag)
{
board_early_init_f();
index 6d00caffa373e4369505f749cb6b3ce057b0f561..49310bdb149fbb0a86ff6cb1d53aa6db5f99ae91 100644 (file)
struct cpu_type *cpu;
phys_size_t ddr_size;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
/* P1014 and it's derivatives support max 16it DDR width */
if (cpu->soc_ver == SVR_P1014)
ddr_size = (CONFIG_SYS_DRAM_SIZE / 2);
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, ddr_freq));
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
/* P1014 and it's derivatives support max 16bit DDR width */
if (cpu->soc_ver == SVR_P1014) {
ddr_cfg_regs.ddr_sdram_cfg &= ~SDRAM_CFG_DBW_MASK;
popts->trwt_override = 1;
popts->trwt = 0;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
/* P1014 and it's derivatives support max 16it DDR width */
if (cpu->soc_ver == SVR_P1014)
popts->data_bus_width = DDR_DATA_BUS_WIDTH_16;
index dfeb86f63e6847f407caf2f12f51bebd69e7b41f..11e2e8ae4801b3151940f5f8b4812b8cd9747939 100644 (file)
{
struct cpu_type *cpu;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
printf("Board: %sRDB\n", cpu->name);
return 0;
struct cpu_type *cpu;
int num = 0;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
phys_size_t size;
struct cpu_type *cpu;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
ft_cpu_setup(blob, bd);
index 916439c17f2afdb8300722fa4f17aeacee650b95..b16b8c8a902afd319e45fa9ca93b910ff7c4c4ef 100644 (file)
struct cpu_type *cpu;
ulong ddr_freq, ddr_freq_mhz;
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
/* P1020 and it's derivatives support max 32bit DDR width */
if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
index 437eaf0fdd6e0852aa791855abdebf8c138137df..9c6683d49288ee8a22e0fc2353944a6cbcb41d59 100644 (file)
else
panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
- cpu = gd->cpu;
+ cpu = gd->arch.cpu;
printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
setbits_be32(&pgpio->gpdir, GPIO_DIR);
index fec97773eab9323667e84d416323ed3e39aed573..4b0d577e2c14c81bf739079290701ef9287b6a9e 100644 (file)
}
#endif /* #ifdef CONFIG_FMAN_ENET */
-#define CPLD_LANE_A_SEL 0x1
-#define CPLD_LANE_G_SEL 0x2
-#define CPLD_LANE_C_SEL 0x4
-#define CPLD_LANE_D_SEL 0x8
-
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
- int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
- FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
- u8 mux = CPLD_READ(serdes_mux);
printf("Initializing Fman\n");
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
- mux &= ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL);
- switch (srds_prtcl) {
- case 0x2:
- case 0xf:
- mux &= ~CPLD_LANE_G_SEL;
- break;
- case 0x5:
- case 0x9:
- case 0xa:
- case 0x17:
- mux |= CPLD_LANE_G_SEL;
- break;
- case 0x14:
- mux = (mux & (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL;
- break;
- case 0x8:
- case 0x16:
- case 0x19:
- case 0x1a:
- mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
- break;
- case 0x1c:
- mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
- break;
- default:
- printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
- break;
- }
- CPLD_WRITE(serdes_mux, mux);
-
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
index d2732f5505966da68e25c905f3c1699465f5f497..a706a6d00ca6fd2ce6b5533442a6c8b3d38d5394 100644 (file)
int checkboard(void)
{
u8 sw;
- struct cpu_type *cpu = gd->cpu;
+ struct cpu_type *cpu = gd->arch.cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
return 0;
}
+#define CPLD_LANE_A_SEL 0x1
+#define CPLD_LANE_G_SEL 0x2
+#define CPLD_LANE_C_SEL 0x4
+#define CPLD_LANE_D_SEL 0x8
+
+void board_config_lanes_mux(void)
+{
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+ u8 mux = 0;
+ switch (srds_prtcl) {
+ case 0x2:
+ case 0x5:
+ case 0x9:
+ case 0xa:
+ case 0xf:
+ break;
+ case 0x8:
+ mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+ break;
+ case 0x14:
+ mux |= CPLD_LANE_A_SEL;
+ break;
+ case 0x17:
+ mux |= CPLD_LANE_G_SEL;
+ break;
+ case 0x16:
+ case 0x19:
+ case 0x1a:
+ mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+ break;
+ case 0x1c:
+ mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
+ break;
+ default:
+ printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
+ break;
+ }
+ CPLD_WRITE(serdes_mux, mux);
+}
+
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
set_liodns();
setup_portals();
+ board_config_lanes_mux();
return 0;
}
index 5debcf612a86f4e618c6b2875a7c3c7f972fcb81..6f2c5c86b4d2dc0d8d83734a33021ff1cdc0a91d 100644 (file)
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
index 88b8cedf48cce2ff30687dbcece5b7a527c6e87a..3c95f3fb7852dc2316fbacb53b9be170e81e679b 100644 (file)
DECLARE_GLOBAL_DATA_PTR;
+static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+ {8, 8}, {9, 9}, {14, 14}, {15, 15} };
+
+static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+ {10, 10}, {11, 11}, {12, 12}, {13, 13} };
+
+static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+ {10, 11}, {11, 10}, {12, 2}, {13, 3} };
+
+static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+ {8, 9}, {9, 8}, {14, 1}, {15, 0} };
+
int checkboard(void)
{
+ char buf[64];
u8 sw;
- struct cpu_type *cpu = gd->cpu;
+ struct cpu_type *cpu = gd->arch.cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
printf("Board: %sQDS, ", cpu->name);
- printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
- QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
+ QIXIS_READ(id), QIXIS_READ(arch));
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+ printf("FPGA: v%d (%s), build %d",
+ (int)QIXIS_READ(scver), qixis_read_tag(buf),
+ (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
/* Display the RCW, so that no one gets confused as to what RCW
* we're actually using for this boot.
*/
fdt_fixup_board_enet(blob);
#endif
}
+
+/*
+ * Reverse engineering switch settings.
+ * Some bits cannot be figured out. They will be displayed as
+ * underscore in binary format. mask[] has those bits.
+ * Some bits are calculated differently than the actual switches
+ * if booting with overriding by FPGA.
+ */
+void qixis_dump_switch(void)
+{
+ int i;
+ u8 sw[9];
+
+ /*
+ * Any bit with 1 means that bit cannot be reverse engineered.
+ * It will be displayed as _ in binary format.
+ */
+ static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f};
+ char buf[10];
+ u8 brdcfg[16], dutcfg[16];
+
+ for (i = 0; i < 16; i++) {
+ brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
+ dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
+ }
+
+ sw[0] = dutcfg[0];
+ sw[1] = (dutcfg[1] << 0x07) | \
+ ((dutcfg[12] & 0xC0) >> 1) | \
+ ((dutcfg[11] & 0xE0) >> 3) | \
+ ((dutcfg[6] & 0x80) >> 6) | \
+ ((dutcfg[1] & 0x80) >> 7);
+ sw[2] = ((brdcfg[1] & 0x0f) << 4) | \
+ ((brdcfg[1] & 0x30) >> 2) | \
+ ((brdcfg[1] & 0x40) >> 5) | \
+ ((brdcfg[1] & 0x80) >> 7);
+ sw[3] = brdcfg[2];
+ sw[4] = ((dutcfg[2] & 0x01) << 7) | \
+ ((dutcfg[2] & 0x06) << 4) | \
+ ((~QIXIS_READ(present)) & 0x10) | \
+ ((brdcfg[3] & 0x80) >> 4) | \
+ ((brdcfg[3] & 0x01) << 2) | \
+ ((brdcfg[6] == 0x62) ? 3 : \
+ ((brdcfg[6] == 0x5a) ? 2 : \
+ ((brdcfg[6] == 0x5e) ? 1 : 0)));
+ sw[5] = ((brdcfg[0] & 0x0f) << 4) | \
+ ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
+ ((brdcfg[0] & 0x40) >> 5);
+ sw[6] = (brdcfg[11] & 0x20);
+ sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
+ ((brdcfg[5] & 0x10) << 2);
+ sw[8] = ((brdcfg[12] & 0x08) << 4) | \
+ ((brdcfg[12] & 0x03) << 5);
+
+ puts("DIP switch (reverse-engineering)\n");
+ for (i = 0; i < 9; i++) {
+ printf("SW%d = 0b%s (0x%02x)\n",
+ i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
+ }
+}
index c6a3492cb6b4958adf818ff811722ede07a6735e..f290f3ca1696719b8383dd0ced64d9d4729d5a63 100644 (file)
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
- {8, 8}, {9, 9}, {14, 14}, {15, 15} };
-
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
- {10, 10}, {11, 11}, {12, 12}, {13, 13} };
-
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
- {10, 11}, {11, 10}, {12, 2}, {13, 3} };
-
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
- {8, 9}, {9, 8}, {14, 1}, {15, 0} };
#endif
index 078a6e415cdb993282468d347099ba95b43570bd..80eb511e1d301f409eb36c06a1a8f6da869b6a98 100644 (file)
*/
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 16, BOOKE_PAGESZ_1M, 1),
+ 0, 16, BOOKE_PAGESZ_64K, 1),
#endif
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
index bc9b7d0a971bd78bfd62f5000d95813d0ded3e63..622117109280b0e976607d74161787dbbac90df9 100644 (file)
int get_fpga_state(unsigned dev)
{
- return gd->fpga_state[dev];
+ return gd->arch.fpga_state[dev];
}
void print_fpga_state(unsigned dev)
{
- if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
puts(" Waiting for FPGA-DONE timed out.\n");
- if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
puts(" FPGA reflection test failed.\n");
}
unsigned k;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->fpga_state[k] = 0;
+ gd->arch.fpga_state[k] = 0;
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
unsigned ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->fpga_state[k] = 0;
+ gd->arch.fpga_state[k] = 0;
/*
* reset FPGA
while (!gd405ep_get_fpga_done(k)) {
udelay(100000);
if (ctr++ > 5) {
- gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_DONE_FAILED;
break;
}
}
udelay(100000);
if (ctr++ > 5) {
- gd->fpga_state[k] |=
+ gd->arch.fpga_state[k] |=
FPGA_STATE_REFLECTION_FAILED;
break;
}
index 5766c0f562fa953a9105ae6b703c04b7430d60c2..32e24c08cb9ce8340f589ab21d1772ef61bea087 100644 (file)
int get_fpga_state(unsigned dev)
{
- return gd->fpga_state[dev];
+ return gd->arch.fpga_state[dev];
}
void print_fpga_state(unsigned dev)
{
- if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
puts(" Waiting for FPGA-DONE timed out.\n");
- if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
puts(" FPGA reflection test failed.\n");
}
unsigned ctr;
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->fpga_state[k] = 0;
+ gd->arch.fpga_state[k] = 0;
/*
* reset FPGA
while (!gd405ex_get_fpga_done(k)) {
udelay(100000);
if (ctr++ > 5) {
- gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+ gd->arch.fpga_state[k] |=
+ FPGA_STATE_DONE_FAILED;
break;
}
}
udelay(100000);
if (ctr++ > 5) {
- gd->fpga_state[k] |=
+ gd->arch.fpga_state[k] |=
FPGA_STATE_REFLECTION_FAILED;
break;
}
index 41fdef7da81bb8919d36150923a0a1add6b3489f..7d2899dc94a30bc047c8ab76dac0e9ad3ec5ff99 100644 (file)
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
if (i2c_probe(0x22)) { /* i2c_probe returns 0 on success */
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
- gd->fpga_state[k] |= FPGA_STATE_PLATFORM;
+ gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
} else {
pca9698_direction_output(0x22, 39, 1);
}
index f41bf05a518c1da4b2134639b67f2cfb1e33c72f..09cd45d3744154722d39dd4f5c1cb8dbe3fe2570 100644 (file)
void reset_cpu(ulong addr)
{
writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
- asm(" wfi");
+
+ wfi();
}
diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds
--- a/board/incaip/u-boot.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- .sdata : { *(.sdata*) }
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss*) }
- .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
index cf82f61ef70e01ec12c1517f15423844c7dfca0d..1c01bb45b55bb185363d8a8b343fa1d90564392d 100644 (file)
--- a/board/inka4x0/inkadiag.c
+++ b/board/inka4x0/inkadiag.c
/* select clock sources */
out_be16(&psc->psc_clock_select, 0);
- baseclk = (gd->ipb_clk + 16) / 32;
+ baseclk = (gd->arch.ipb_clk + 16) / 32;
/* switch to UART mode */
out_be32(&psc->sicr, 0);
{
volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
- const u32 prescale = gd->ipb_clk / freq / 128;
+ const u32 prescale = gd->arch.ipb_clk / freq / 128;
const u32 count = 128;
const u32 width = 64;
freq = simple_strtol(argv[0], NULL, 0);
/* avoid zero prescale in buzzer_turn_on() */
- if (freq > gd->ipb_clk / 128) {
+ if (freq > gd->arch.ipb_clk / 128) {
printf("%dHz exceeds maximum (%ldHz)\n", freq,
- gd->ipb_clk / 128);
+ gd->arch.ipb_clk / 128);
} else if (!freq)
printf("Zero frequency is senseless\n");
else
diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <twl4030.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/mmc_host_def.h>
-#include <asm/arch/mux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
-#include "igep0030.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: omap_rev_string
- * Description: For SPL builds output board rev
- */
-void omap_rev_string(void)
-{
-}
-
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- timings->mr = MICRON_V_MR_165;
-#ifdef CONFIG_BOOT_NAND
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
-#else
- if (get_cpu_family() == CPU_OMAP34XX) {
- timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_165;
- timings->ctrlb = NUMONYX_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
-
- } else {
- timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_200;
- timings->ctrlb = NUMONYX_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- }
-#endif
-}
-#endif
-
-#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
-{
- omap_mmc_init(0, 0, 0);
- return 0;
-}
-#endif
-
-/*
- * Routine: misc_init_r
- * Description: Configure board specific parts
- */
-int misc_init_r(void)
-{
- twl4030_power_init();
-
- dieid_num_r();
-
- return 0;
-}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_DEFAULT();
-}
diff --git a/board/isee/igep0030/igep0030.h b/board/isee/igep0030/igep0030.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * (C) Copyright 2010
- * ISEE 2007 SL, <www.iseebcn.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef _IGEP0030_H_
-#define _IGEP0030_H_
-
-const omap3_sysinfo sysinfo = {
- DDR_STACKED,
- "OMAP3 IGEP module",
-#if defined(CONFIG_ENV_IS_IN_ONENAND)
- "ONENAND",
-#else
- "NAND",
-#endif
-};
-
-/*
- * IEN - Input Enable
- * IDIS - Input Disable
- * PTD - Pull type Down
- * PTU - Pull type Up
- * DIS - Pull type selection is inactive
- * EN - Pull type selection is active
- * M0 - Mode 0
- * The commented string gives the final mux configuration for that pin
- */
-
-#define MUX_DEFAULT()\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
- MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
- MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
- MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
- MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
- MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
- MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE*/\
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
- MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
- MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /* I2C1_SDA */\
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /* I2C4_SCL */\
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /* I2C4_SDA */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /* SYS_32K */\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
- MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
- MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
-#endif
similarity index 98%
rename from board/isee/igep0020/Makefile
rename to board/isee/igep00x0/Makefile
index 00463e168e2801fa5b1a7247f9851828cea11cc7..f59595473fc47484c53215aa0f68446126dba343 100644 (file)
rename from board/isee/igep0020/Makefile
rename to board/isee/igep00x0/Makefile
index 00463e168e2801fa5b1a7247f9851828cea11cc7..f59595473fc47484c53215aa0f68446126dba343 100644 (file)
LIB = $(obj)lib$(BOARD).o
-COBJS := igep0020.o
+COBJS := igep00x0.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
similarity index 86%
rename from board/isee/igep0020/igep0020.c
rename to board/isee/igep00x0/igep00x0.c
index a0f2aa3e4e2ad89e41de4cf52a0dca325662a708..49fcf348930e95a085d3b682eaa537bf94256fe5 100644 (file)
rename from board/isee/igep0020/igep0020.c
rename to board/isee/igep00x0/igep00x0.c
index a0f2aa3e4e2ad89e41de4cf52a0dca325662a708..49fcf348930e95a085d3b682eaa537bf94256fe5 100644 (file)
* MA 02111-1307 USA
*/
#include <common.h>
-#include <netdev.h>
#include <twl4030.h>
-#include <asm/io.h>
+#include <netdev.h>
#include <asm/gpio.h>
+#include <asm/arch/omap_gpmc.h>
+#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/omap_gpmc.h>
#include <asm/mach-types.h>
-#include "igep0020.h"
+#include "igep00x0.h"
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_CMD_NET)
/* GPMC definitions for LAN9221 chips */
static const u32 gpmc_lan_config[] = {
- NET_LAN9221_GPMC_CONFIG1,
- NET_LAN9221_GPMC_CONFIG2,
- NET_LAN9221_GPMC_CONFIG3,
- NET_LAN9221_GPMC_CONFIG4,
- NET_LAN9221_GPMC_CONFIG5,
- NET_LAN9221_GPMC_CONFIG6,
+ NET_LAN9221_GPMC_CONFIG1,
+ NET_LAN9221_GPMC_CONFIG2,
+ NET_LAN9221_GPMC_CONFIG3,
+ NET_LAN9221_GPMC_CONFIG4,
+ NET_LAN9221_GPMC_CONFIG5,
+ NET_LAN9221_GPMC_CONFIG6,
};
+#endif
/*
* Routine: board_init
return 0;
}
+#if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD)
+void show_boot_progress(int val)
+{
+ if (val < 0) {
+ /* something went wrong */
+ return;
+ }
+
+ if (!gpio_request(IGEP00X0_GPIO_LED, ""))
+ gpio_direction_output(IGEP00X0_GPIO_LED, 1);
+}
+#endif
+
#ifdef CONFIG_SPL_BUILD
/*
* Routine: omap_rev_string
}
#endif
+#if defined(CONFIG_CMD_NET)
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
* Ethernet hardware.
*/
-#if defined(CONFIG_CMD_NET)
static void setup_net_chip(void)
{
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
gpio_set_value(64, 1);
}
}
+#else
+static inline void setup_net_chip(void) {}
#endif
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
{
twl4030_power_init();
-#if defined(CONFIG_CMD_NET)
setup_net_chip();
-#endif
dieid_num_r();
void set_muxconf_regs(void)
{
MUX_DEFAULT();
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+ MUX_IGEP0020();
+#endif
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+ MUX_IGEP0030();
+#endif
}
+#if defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bis)
{
int rc = 0;
#endif
return rc;
}
+#endif
similarity index 93%
rename from board/isee/igep0020/igep0020.h
rename to board/isee/igep00x0/igep00x0.h
index 3335ecc787d8131441d7cb695a85383f87ecd16b..5ef22aeda42b5e877581e908f0797463102a9f10 100644 (file)
rename from board/isee/igep0020/igep0020.h
rename to board/isee/igep00x0/igep00x0.h
index 3335ecc787d8131441d7cb695a85383f87ecd16b..5ef22aeda42b5e877581e908f0797463102a9f10 100644 (file)
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-#ifndef _IGEP0020_H_
-#define _IGEP0020_H_
+#ifndef _IGEP00X0_H_
+#define _IGEP00X0_H_
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+#define IGEP00X0_GPIO_LED 27
+#endif
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+#define IGEP00X0_GPIO_LED 16
+#endif
const omap3_sysinfo sysinfo = {
DDR_STACKED,
- "IGEP v2 board",
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+ "IGEPv2",
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+ "IGEP COM MODULE/ELECTRON",
+#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
+ "IGEP COM PROTON",
+#endif
#if defined(CONFIG_ENV_IS_IN_ONENAND)
"ONENAND",
#else
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /* GPMC_nWP */\
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /* MMC1_CMD */\
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /* MMC1_DAT0 */\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
#endif
+
+#define MUX_IGEP0020() \
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
+
+#define MUX_IGEP0030() \
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */
index 54f25e097cbc4868f637f6c94d0883e6c4c42674..0d895c2b421bfbac20c847f17afe5801570d592b 100644 (file)
--- a/board/kmc/kzm9g/kzm9g.c
+++ b/board/kmc/kzm9g/kzm9g.c
writel(0x0017040a, &sbsc->sdwcr01);
writel(0x31020707, &sbsc->sdwcr10);
writel(0x0017040a, &sbsc->sdwcr11);
- writel(0x05555555, &sbsc->sddrvcr0);
+ writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */
writel(0x30000000, &sbsc->sdwcr2);
writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
writel(0x0, SDMRA1A);
writel(0x00000402, &sbsc->sdmracr0);
writel(0x0, SDMRA1A);
- writel(0x00000403, &sbsc->sdmracr0);
+ writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
writel(0x0, SDMRA1A);
writel(0x0, SDMRA2A);
} else {
writel(0x0, SDMRA1B);
writel(0x00000402, &sbsc->sdmracr0);
writel(0x0, SDMRA1B);
- writel(0x00000403, &sbsc->sdmracr0);
+ writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
writel(0x0, SDMRA1B);
writel(0x0, SDMRA2B);
}
/* FRQCR Init */
writel(0x0012453C, &cpg->frqcra);
- writel(0x80331350, &cpg->frqcrb);
+ writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */
cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
writel(0x00000B0B, &cpg->frqcrd);
cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
return 0;
}
+void adjust_core_voltage(void)
+{
+ u8 data;
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ data = 0x35;
+ i2c_set_bus_num(0);
+ i2c_write(0x40, 3, 1, &data, 1);
+}
+
int board_init(void)
{
+ adjust_core_voltage();
sh73a0_pinmux_init();
/* SCIFA 4 */
diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index b5e524bb2f4e8459cd91888a648fb2193eba0ebd..34c6675fd8a13243f98681f325c492190e0cd875 100644 (file)
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- gd->kbd_status = 0;
+ gd->arch.kbd_status = 0;
/* Forced by PIC. Delays <= 175us loose */
udelay(1000);
/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
if (errcd) {
- gd->kbd_status |= errcd << 8;
+ gd->arch.kbd_status |= errcd << 8;
}
/* Reset error code and verify */
val = KEYBD_CMD_RESET_ERRORS;
val &= KEYBD_STATUS_MASK; /* clear unused bits */
if (val) { /* permanent error, report it */
- gd->kbd_status |= val;
+ gd->arch.kbd_status |= val;
return;
}
{
uchar kbd_data[KEYBD_DATALEN];
char keybd_env[2 * KEYBD_DATALEN + 1];
- uchar kbd_init_status = gd->kbd_status >> 8;
- uchar kbd_status = gd->kbd_status;
+ uchar kbd_init_status = gd->arch.kbd_status >> 8;
+ uchar kbd_status = gd->arch.kbd_status;
uchar val;
char *str;
int i;
diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c
index 5231c7a5c6f94d60eb7a6f2c0c63ced7d86f47c0..b66f681eeb748d0393152a89df68fb0989e31762 100644 (file)
--- a/board/lwmon5/kbd.c
+++ b/board/lwmon5/kbd.c
i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- gd->kbd_status = 0;
+ gd->arch.kbd_status = 0;
/* Forced by PIC. Delays <= 175us loose */
udelay(1000);
/* clear "irrelevant" bits. Recommended by Martin Rajek, LWN */
errcd &= ~(KEYBD_STATUS_H_RESET|KEYBD_STATUS_BROWNOUT);
if (errcd) {
- gd->kbd_status |= errcd << 8;
+ gd->arch.kbd_status |= errcd << 8;
}
/* Reset error code and verify */
val = KEYBD_CMD_RESET_ERRORS;
val &= KEYBD_STATUS_MASK; /* clear unused bits */
if (val) { /* permanent error, report it */
- gd->kbd_status |= val;
+ gd->arch.kbd_status |= val;
return;
}
{
uchar kbd_data[KEYBD_DATALEN];
char keybd_env[2 * KEYBD_DATALEN + 1];
- uchar kbd_init_status = gd->kbd_status >> 8;
- uchar kbd_status = gd->kbd_status;
+ uchar kbd_init_status = gd->arch.kbd_status >> 8;
+ uchar kbd_status = gd->arch.kbd_status;
uchar val;
ushort data, inv_data;
char *str;
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index ecd9536145a63dfce56308a2a22e8b555ed4deea..29e24fb26fe98769ddf7aa114cf632248bf8feb6 100644 (file)
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
* Don't allow watch-dog triggering more frequently than
* the predefined value CONFIG_WD_MAX_RATE [ticks].
*/
- if (ct >= gd->wdt_last) {
- if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE)
+ if (ct >= gd->arch.wdt_last) {
+ if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
return;
} else {
/* Time base counter had been reset */
- if (((unsigned long long)(-1) - gd->wdt_last + ct) <
+ if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
CONFIG_WD_MAX_RATE)
return;
}
- gd->wdt_last = get_ticks();
+ gd->arch.wdt_last = get_ticks();
#endif
/*
index dacc13845dc473549560bdabfa48d5a4c2f98c64..3fcf9685e95732d7d7a5e09001ca157b1d188000 100644 (file)
#include <ACEX1K.h>
#include <command.h>
#include <asm/gpio.h>
+#include <linux/byteorder/generic.h>
#include "fpga.h"
#ifdef FPGA_DEBUG
{
unsigned char *data = (unsigned char *) buf;
int i;
+ int headerlen = len - cyclone2.size;
+
+ if (headerlen < 0)
+ return FPGA_FAIL;
+ else if (headerlen == sizeof(uint32_t)) {
+ const unsigned int fpgavers_len = 11; /* '0x' + 8 hex digits + \0 */
+ char fpgavers_str[fpgavers_len];
+ snprintf(fpgavers_str, fpgavers_len, "0x%08x",
+ be32_to_cpup((uint32_t*)data));
+ setenv("fpgavers", fpgavers_str);
+ }
fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
- for (i = 0; i < len; i++)
+ for (i = headerlen; i < len; i++)
_write_fpga(data[i]);
fpga_debug("-%s\n", __func__);
index 945a36dfe6658196b95d2f81f3cfc70d0ade41b4..15269c6d7a1ad847d737ab3738f3553ec1e370b2 100644 (file)
return 0;
}
+static inline int is_portrait(void)
+{
+ int i;
+ unsigned int orient_index = 0; /* idx of char which determines orientation */
+
+ for (i = sizeof(e.id)/sizeof(*e.id) - 1; i>=0; i--) {
+ if (e.id[i] == '-') {
+ orient_index = i+1;
+ break;
+ }
+ }
+
+ return (orient_index &&
+ (e.id[orient_index] >= '5') && (e.id[orient_index] <= '8'));
+}
+
int mac_read_from_eeprom(void)
{
u32 crc, crc_offset = offsetof(struct eeprom, crc);
u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+#define FILENAME_LANDSCAPE "mvBlueLynx_X.rbf"
+#define FILENAME_PORTRAIT "mvBlueLynx_X_sensor_cd.rbf"
if (read_eeprom()) {
printf("EEPROM Read failed.\n");
setenv("serial#", serial_num);
}
+ /* decide which fpga file to load depending on orientation */
+ if (is_portrait())
+ setenv("fpgafilename", FILENAME_PORTRAIT);
+ else
+ setenv("fpgafilename", FILENAME_LANDSCAPE);
+
/* TODO should I calculate CRC here? */
return 0;
}
diff --git a/board/nvidia/cardhu/Makefile b/board/nvidia/cardhu/Makefile
--- /dev/null
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2010-2012
+# NVIDIA Corporation <www.nvidia.com>
+#
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
similarity index 67%
rename from arch/x86/cpu/sc520/sc520_reset.c
rename to board/nvidia/cardhu/cardhu.c
index 137af978c1b127fc37f944355b479423df1a2fda..df4cb6b728bd2441e148e185db9a7e47628b2ce6 100644 (file)
rename from arch/x86/cpu/sc520/sc520_reset.c
rename to board/nvidia/cardhu/cardhu.c
index 137af978c1b127fc37f944355b479423df1a2fda..df4cb6b728bd2441e148e185db9a7e47628b2ce6 100644 (file)
/*
- * (C) Copyright 2011
- * Graeme Russ, <graeme.russ@gmail.com>
- *
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc520.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-cardhu.h"
-void reset_cpu(ulong addr)
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
{
- printf("Resetting using SC520 MMCR\n");
- /* Write a '1' to the SYS_RST of the RESCFG MMCR */
- writeb(0x01, &sc520_mmcr->rescfg);
+ pinmux_config_table(tegra3_pinmux_common,
+ ARRAY_SIZE(tegra3_pinmux_common));
- /* NOTREACHED */
+ pinmux_config_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
}
diff --git a/board/nvidia/cardhu/cardhu.c.mmc b/board/nvidia/cardhu/cardhu.c.mmc
--- /dev/null
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-cardhu.h"
+
+#include <asm/arch/clock.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/pmu.h>
+#include <asm/arch/sdmmc.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+#include <mmc.h>
+#include <i2c.h>
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_table(tegra3_pinmux_common,
+ ARRAY_SIZE(tegra3_pinmux_common));
+
+ pinmux_config_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+}
+
+#if defined(CONFIG_MMC)
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+}
+
+/* Do I2C/PMU writes to bring up SD card bus power */
+static void board_sdmmc_voltage_init(void)
+{
+ uchar reg, data_buffer[1];
+ int i;
+
+ i2c_set_bus_num(0); /* PMU is on bus 0 */
+
+ data_buffer[0] = 0x65;
+ reg = 0x32;
+
+ for (i = 0; i < MAX_I2C_RETRY; ++i) {
+ if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+ udelay(100);
+ }
+
+ data_buffer[0] = 0x09;
+ reg = 0x67;
+
+ for (i = 0; i < MAX_I2C_RETRY; ++i) {
+ if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+ udelay(100);
+ }
+}
+
+static void pad_init_mmc(struct tegra_mmc *reg)
+{
+ struct apb_misc_gp_ctlr *const gpc =
+ (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
+ struct sdmmc_ctlr *const sdmmc = (struct sdmmc_ctlr *)reg;
+ u32 val, offset = (unsigned int)reg;
+ u32 padcfg, padmask;
+
+ debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)sdmmc);
+
+ /* Set the pad drive strength for SDMMC1 or 3 only */
+ if (offset != TEGRA_SDMMC1_BASE && offset != TEGRA_SDMMC3_BASE) {
+ debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
+ __func__);
+ return;
+ }
+
+ /* Set pads as per T30 TRM, section 24.6.1.2 */
+ padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \
+ GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN);
+ padmask = 0x00000FFF;
+ if (offset == TEGRA_SDMMC1_BASE) {
+ val = readl(&gpc->sdio1cfg);
+ val &= padmask;
+ val |= padcfg;
+ writel(val, &gpc->sdio1cfg);
+ } else { /* SDMMC3 */
+ val = readl(&gpc->sdio3cfg);
+ val &= padmask;
+ val |= padcfg;
+ writel(val, &gpc->sdio3cfg);
+ }
+
+ val = readl(&sdmmc->sdmmc_sdmemcomp_pad_ctrl);
+ val &= 0xFFFFFFF0;
+ val |= MEMCOMP_PADCTRL_VREF;
+ writel(val, &sdmmc->sdmmc_sdmemcomp_pad_ctrl);
+
+ val = readl(&sdmmc->sdmmc_auto_cal_config);
+ val &= 0xFFFF0000;
+ val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+ writel(val, &sdmmc->sdmmc_auto_cal_config);
+}
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+ debug("board_mmc_init called\n");
+
+ /* Turn on SD-card bus power */
+ board_sdmmc_voltage_init();
+
+ /* Set up the SDMMC pads as per the TRM */
+ pad_init_mmc((struct tegra_mmc *)TEGRA_SDMMC1_BASE);
+
+ /* Enable muxes, etc. for SDMMC controllers */
+ pin_mux_mmc();
+
+ /* init dev 0 (SDMMC4), ("HSMMC") with 8-bit bus */
+ tegra_mmc_init(0, 8, -1, -1);
+
+ /* init dev 1 (SDMMC0), ("SDIO") with 8-bit bus */
+ tegra_mmc_init(1, 8, -1, -1);
+
+ return 0;
+}
+#endif /* MMC */
diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h b/board/nvidia/cardhu/pinmux-config-cardhu.h
--- /dev/null
@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_CARDHU_H_
+#define _PINMUX_CONFIG_CARDHU_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+static struct pingroup_config tegra3_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT7, RSVD1, NORMAL, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C3 pinmux */
+ I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C4 pinmux */
+ I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR2, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDIN, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_WR_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_SCK, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PWR0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_PCLK, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DE, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D0, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D2, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D3, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D4, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D5, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D6, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D7, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D8, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D9, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D10, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D11, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D12, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D13, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D14, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D15, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D16, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D17, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D18, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D19, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D20, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D21, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D22, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_D23, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_M1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(LCD_DC1, DISPA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT),
+ LV_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D3, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D5, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D7, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_MCLK, VI, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT), /* EN_VDD_BL1 */
+ DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_PWM */
+ DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), /* LCD1_BL_EN */
+ DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* KBC keys */
+ DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW11, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SPI2_CS1_N, SPI2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ /* GPIOs */
+ /* SDMMC1 CD gpio */
+ DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
+ /* SDMMC1 WP gpio */
+ LV_PINMUX(VI_D11, RSVD1, UP, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* Touch panel GPIO */
+ /* Touch IRQ */
+ DEFAULT_PINMUX(GMI_AD12, NAND, UP, NORMAL, INPUT),
+
+ /* Touch RESET */
+ DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
+
+ /* Power rails GPIO */
+ DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP, NORMAL, INPUT),
+
+ LV_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_PCLK, RSVD1, UP, TRISTATE, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+#endif /* _PINMUX_CONFIG_CARDHU_H_ */
index 76ec6876e21b51d4ea4da512109c2fc76215cfc1..d1d8a29cbaa1ae689c98348e435a6a65a265d9cb 100644 (file)
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#ifdef CONFIG_LCD
#include <asm/arch/display.h>
-#include <asm/arch/emc.h>
+#endif
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/pmu.h>
+#ifdef CONFIG_PWM_TEGRA
#include <asm/arch/pwm.h>
+#endif
#include <asm/arch/tegra.h>
-#include <asm/arch/usb.h>
#include <asm/arch-tegra/board.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/sys_proto.h>
#include <asm/arch-tegra/uart.h>
#include <asm/arch-tegra/warmboot.h>
-#include <spi.h>
+#ifdef CONFIG_TEGRA_CLOCK_SCALING
+#include <asm/arch/emc.h>
+#endif
+#ifdef CONFIG_USB_EHCI_TEGRA
+#include <asm/arch/usb.h>
+#endif
#include <i2c.h>
+#include <spi.h>
#include "emc.h"
DECLARE_GLOBAL_DATA_PTR;
void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
+void __pin_mux_display(void)
+{
+}
+
+void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display")));
+
/*
* Routine: power_det_init
* Description: turn off power detects
#ifdef CONFIG_SPI_UART_SWITCH
gpio_config_uart();
#endif
-#ifdef CONFIG_TEGRA_SPI
+#if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK)
pin_mux_spi();
spi_init();
#endif
+
#ifdef CONFIG_PWM_TEGRA
if (pwm_init(gd->fdt_blob))
debug("%s: Failed to init pwm\n", __func__);
#endif
#ifdef CONFIG_LCD
+ pin_mux_display();
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
/* boot param addr */
int board_early_init_f(void)
{
+#if !defined(CONFIG_TEGRA20)
+ pinmux_init();
+#endif
board_init_uart_f();
/* Initialize periph GPIOs */
diff --git a/board/nvidia/dalmore/Makefile b/board/nvidia/dalmore/Makefile
--- /dev/null
@@ -0,0 +1,36 @@
+#
+# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms and conditions of the GNU General Public License,
+# version 2, as published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+# more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-dalmore.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+ pinmux_config_table(tegra114_pinmux_common,
+ ARRAY_SIZE(tegra114_pinmux_common));
+
+ pinmux_config_table(unused_pins_lowpower,
+ ARRAY_SIZE(unused_pins_lowpower));
+}
diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h
--- /dev/null
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_CONFIG_DALMORE_H_
+#define _PINMUX_CONFIG_DALMORE_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_DEFAULT, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_##_od, \
+ .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
+ }
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+ { \
+ .pingroup = PINGRP_##_pingroup, \
+ .func = PMUX_FUNC_##_mux, \
+ .pull = PMUX_PULL_##_pull, \
+ .tristate = PMUX_TRI_##_tri, \
+ .io = PMUX_PIN_##_io, \
+ .lock = PMUX_PIN_LOCK_##_lock, \
+ .od = PMUX_PIN_OD_DEFAULT, \
+ .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
+ }
+
+static struct pingroup_config tegra114_pinmux_common[] = {
+ /* SDMMC1 pinmux */
+ DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC1_WP_N, SDMMC1, UP, NORMAL, INPUT),
+
+ /* SDMMC3 pinmux */
+ DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, NORMAL, NORMAL, OUTPUT),
+
+ DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
+
+ /* SDMMC4 pinmux */
+ LV_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE),
+ LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE),
+
+ /* I2C1 pinmux */
+ I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C2 pinmux */
+ I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C3 pinmux */
+ I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* I2C4 pinmux */
+ I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ /* Power I2C pinmux */
+ I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+ I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+ DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DATA1, UARTA, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CLK3_REQ, DEV3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WP_N, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_CS2_N, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+ /* KBC keys */
+ DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW9, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL4, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL5, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV0, RSVD1, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PV1, RSVD1, UP, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+ DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+
+ DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS1_N, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_CS2_N, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+
+ /* GPIOs */
+ /* SDMMC1 CD gpio */
+ DEFAULT_PINMUX(GMI_IORDY, RSVD1, UP, NORMAL, INPUT),
+
+ /* Touch RESET */
+ DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, OUTPUT),
+
+ /* Power rails GPIO */
+ DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT),
+ DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+ DEFAULT_PINMUX(GMI_CS0_N, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS3_N, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS4_N, NAND, UP, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_CS7_N, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, INPUT),
+ DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, TRISTATE, OUTPUT),
+ DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
+ DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+#endif /* _PINMUX_CONFIG_DALMORE_H_ */
diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts
--- /dev/null
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "NVIDIA Dalmore";
+ compatible = "nvidia,dalmore", "nvidia,tegra114";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+};
index 5645a8d4772dbd2c973ab981ac4df2d7f3a93593..aeda3a1ffbbd9cc92e13b38b979fa5031a17cd20 100644 (file)
reg = <0x00000000 0x40000000>;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = <32000>;
- };
- osc {
- clock-frequency = <12000000>;
- };
- };
-
- clock@60006000 {
- clocks = <&clk_32k &osc>;
- };
-
serial@70006300 {
clock-frequency = < 216000000 >;
};
+ nand-controller@70008000 {
+ nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
+ nvidia,width = <8>;
+ nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+ nand@0 {
+ reg = <0>;
+ compatible = "hynix,hy27uf4g2b", "nand-flash";
+ };
+ };
+
i2c@7000c000 {
status = "disabled";
};
usb@c5004000 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
};
-
- nand-controller@70008000 {
- nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */
- nvidia,width = <8>;
- nvidia,timing = <26 100 20 80 20 10 12 10 70>;
- nand@0 {
- reg = <0>;
- compatible = "hynix,hy27uf4g2b", "nand-flash";
- };
- };
};
index dd98ca48e9f26bcb54e0ba49cf43f4544534745b..527a29689da21f660027387d0f2e910c6ab69a9c 100644 (file)
reg = < 0x00000000 0x40000000 >;
};
+ host1x {
+ status = "okay";
+ dc@54200000 {
+ status = "okay";
+ rgb {
+ status = "okay";
+ nvidia,panel = <&lcd_panel>;
+ };
+ };
+ };
+
/* This is not used in U-Boot, but is expected to be in kernel .dts */
i2c@7000d000 {
clock-frequency = <100000>;
};
};
- clocks {
- osc {
- clock-frequency = <12000000>;
- };
- };
-
- clock@60006000 {
- clocks = <&clk_32k &osc>;
- };
-
serial@70006300 {
clock-frequency = < 216000000 >;
};
- sdhci@c8000400 {
- cd-gpios = <&gpio 69 0>; /* gpio PI5 */
- wp-gpios = <&gpio 57 0>; /* gpio PH1 */
- power-gpios = <&gpio 70 0>; /* gpio PI6 */
- };
-
- sdhci@c8000600 {
- support-8bit;
- };
-
- usb@c5000000 {
- nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
- dr_mode = "otg";
- };
-
- usb@c5004000 {
- status = "disabled";
+ nand-controller@70008000 {
+ nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
+ nvidia,width = <8>;
+ nvidia,timing = <26 100 20 80 20 10 12 10 70>;
+ nand@0 {
+ reg = <0>;
+ compatible = "hynix,hy27uf4g2b", "nand-flash";
+ };
};
i2c@7000c000 {
clock-frequency = <100000>;
};
+ kbc@7000e200 {
+ linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
+ 0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
+ 0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
+ 0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
+ 0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
+ 0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
+ 0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
+ 0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
+ 0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
+ 0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
+ 0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
+ 0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
+ 0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
+ 0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
+ 0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
+ 0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
+ 0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
+ 0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
+ 0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
+ 0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
+ 0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
+ 0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
+ 0x1f04008a>;
+ linux,fn-keymap = <0x05040002>;
+ };
+
emc@7000f400 {
emc-table@190000 {
reg = < 190000 >;
};
};
- kbc@7000e200 {
- linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
- 0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
- 0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
- 0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023
- 0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a
- 0x05010009 0x05020016 0x05030015 0x05040024 0x05050031
- 0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018
- 0x06030017 0x06040026 0x06050025 0x06060033 0x06070032
- 0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036
- 0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019
- 0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044
- 0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067
- 0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068
- 0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057
- 0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d
- 0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f
- 0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040
- 0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f
- 0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050
- 0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053
- 0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072
- 0x1d0700e1 0x1e000045 0x1e010046 0x1e020071
- 0x1f04008a>;
- linux,fn-keymap = <0x05040002>;
+ usb@c5000000 {
+ nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+ dr_mode = "otg";
};
- nand-controller@70008000 {
- nvidia,wp-gpios = <&gpio 59 0>; /* PH3 */
- nvidia,width = <8>;
- nvidia,timing = <26 100 20 80 20 10 12 10 70>;
- nand@0 {
- reg = <0>;
- compatible = "hynix,hy27uf4g2b", "nand-flash";
- };
+ usb@c5004000 {
+ status = "disabled";
};
- host1x {
- status = "okay";
- dc@54200000 {
- status = "okay";
- rgb {
- status = "okay";
- nvidia,panel = <&lcd_panel>;
- };
- };
+ sdhci@c8000400 {
+ cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+ wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+ power-gpios = <&gpio 70 0>; /* gpio PI6 */
+ };
+
+ sdhci@c8000600 {
+ support-8bit;
};
lcd_panel: panel {
nvidia,panel-vdd-gpios = <&gpio 22 0>; /* PC6 */
nvidia,panel-timings = <400 4 203 17 15>;
};
-
};
index 38b7b1355d3fc7a28f366c8d474a819d78f92e1a..3e5e39da632201d34c9e03c06b37e10966c3bb48 100644 (file)
reg = <0x00000000 0x40000000>;
};
- clocks {
- clk_32k: clk_32k {
- clock-frequency = <32000>;
- };
- osc {
- clock-frequency = <12000000>;
- };
- };
-
- clock@60006000 {
- clocks = <&clk_32k &osc>;
- };
-
serial@70006300 {
clock-frequency = < 216000000 >;
};
index f830cf3995d9dc5e4b172a05ad20f8fc63318120..4579557d6d140e95648a866418aefbd1f35d5116 100644 (file)
reg = < 0x00000000 0x20000000 >;
};
- clocks {
- osc {
- clock-frequency = <12000000>;
- };
- };
-
- clock@60006000 {
- clocks = <&clk_32k &osc>;
- };
-
serial@70006000 {
clock-frequency = < 216000000 >;
};
diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts
--- /dev/null
@@ -0,0 +1,47 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+ model = "NVIDIA Cardhu";
+ compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+ aliases {
+ i2c0 = "/i2c@7000d000";
+ i2c1 = "/i2c@7000c000";
+ i2c2 = "/i2c@7000c400";
+ i2c3 = "/i2c@7000c500";
+ i2c4 = "/i2c@7000c700";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ i2c@7000c000 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c400 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c500 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000c700 {
+ clock-frequency = <100000>;
+ };
+
+ i2c@7000d000 {
+ clock-frequency = <100000>;
+ };
+
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+ };
+};
diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds
--- a/board/pb1x00/u-boot.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips")
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- .sdata : { *(.sdata*) }
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
- . = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss*) }
- .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
diff --git a/board/phytec/pcm051/Makefile b/board/phytec/pcm051/Makefile
--- /dev/null
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS := mux.o
+endif
+
+COBJS += board.o
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
--- /dev/null
@@ -0,0 +1,266 @@
+/*
+ * board.c
+ *
+ * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+#ifdef CONFIG_SPL_BUILD
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
+
+/* MII mode defines */
+#define MII_MODE_ENABLE 0x0
+#define RGMII_MODE_ENABLE 0xA
+#define RMII_RGMII2_MODE_ENABLE 0x49
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* UART defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET (0x1 << 1)
+#define UART_CLK_RUNNING_MASK 0x1
+#define UART_SMART_IDLE_EN (0x1 << 0x3)
+
+/* DDR RAM defines */
+#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
+
+static void rtc32k_enable(void)
+{
+ struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+
+ /*
+ * Unlock the RTC's registers. For more details please see the
+ * RTC_SS section of the TRM. In order to unlock we need to
+ * write these specific values (keys) in this order.
+ */
+ writel(0x83e70b13, &rtc->kick0r);
+ writel(0x95a4f1e0, &rtc->kick1r);
+
+ /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+ writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+static const struct ddr_data ddr3_data = {
+ .datardsratio0 = MT41J256M8HX15E_RD_DQS,
+ .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
+ .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
+ .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+ .cmd0csratio = MT41J256M8HX15E_RATIO,
+ .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
+ .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41J256M8HX15E_RATIO,
+ .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
+ .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41J256M8HX15E_RATIO,
+ .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
+ .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+ .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
+ .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
+ .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
+ .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
+ .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
+ .zq_config = MT41J256M8HX15E_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY,
+};
+#endif
+
+/*
+ * early system init of muxing and clocks.
+ */
+void s_init(void)
+{
+ /*
+ * WDT1 is already running when the bootloader gets control
+ * Disable it to avoid "random" resets
+ */
+ writel(0xAAAA, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+ writel(0x5555, &wdtimer->wdtwspr);
+ while (readl(&wdtimer->wdtwwps) != 0x0)
+ ;
+
+#ifdef CONFIG_SPL_BUILD
+ /* Setup the PLLs and the clocks for the peripherals */
+ pll_init();
+
+ /* Enable RTC32K clock */
+ rtc32k_enable();
+
+ /* UART softreset */
+ u32 regval;
+
+ enable_uart0_pin_mux();
+
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_RESET;
+ writel(regval, &uart_base->uartsyscfg);
+ while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
+ != UART_CLK_RUNNING_MASK)
+ ;
+
+ /* Disable smart idle */
+ regval = readl(&uart_base->uartsyscfg);
+ regval |= UART_SMART_IDLE_EN;
+ writel(regval, &uart_base->uartsyscfg);
+
+ gd = &gdata;
+
+ preloader_console_init();
+
+ /* Initalize the board header */
+ enable_i2c0_pin_mux();
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ enable_board_pin_mux();
+
+ config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
+ &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+#endif
+}
+
+/*
+ * Basic board specific setup. Pinmux has been handled already.
+ */
+int board_init(void)
+{
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+ /* VTP can be added here */
+
+ return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+ {
+ .slave_reg_ofs = 0x208,
+ .sliver_reg_ofs = 0xd80,
+ .phy_id = 0,
+ .phy_if = PHY_INTERFACE_MODE_RGMII,
+ },
+ {
+ .slave_reg_ofs = 0x308,
+ .sliver_reg_ofs = 0xdc0,
+ .phy_id = 1,
+ .phy_if = PHY_INTERFACE_MODE_RGMII,
+ },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+ .mdio_base = AM335X_CPSW_MDIO_BASE,
+ .cpsw_base = AM335X_CPSW_BASE,
+ .mdio_div = 0xff,
+ .channels = 8,
+ .cpdma_reg_ofs = 0x800,
+ .slaves = 1,
+ .slave_data = cpsw_slaves,
+ .ale_reg_ofs = 0xd00,
+ .ale_entries = 1024,
+ .host_port_reg_ofs = 0x108,
+ .hw_stats_reg_ofs = 0x900,
+ .mac_control = (1 << 5),
+ .control = cpsw_control,
+ .host_port_num = 0,
+ .version = CPSW_CTRL_VERSION_2,
+};
+#endif
+
+#if defined(CONFIG_DRIVER_TI_CPSW) || \
+ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
+int board_eth_init(bd_t *bis)
+{
+ int rv, n = 0;
+#ifdef CONFIG_DRIVER_TI_CPSW
+ uint8_t mac_addr[6];
+ uint32_t mac_hi, mac_lo;
+
+ if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ printf("<ethaddr> not set. Reading from E-fuse\n");
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("ethaddr", mac_addr);
+ else
+ goto try_usbether;
+ }
+
+ writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
+
+ rv = cpsw_register(&cpsw_data);
+ if (rv < 0)
+ printf("Error %d registering CPSW switch\n", rv);
+ else
+ n += rv;
+try_usbether:
+#endif
+
+#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
+ rv = usb_eth_initialize(bis);
+ if (rv < 0)
+ printf("Error %d registering USB_ETHER\n", rv);
+ else
+ n += rv;
+#endif
+ return n;
+}
+#endif
diff --git a/board/phytec/pcm051/board.h b/board/phytec/pcm051/board.h
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * board.h
+ *
+ * Phytec phyCORE-AM335x (pcm051) boards information header
+ *
+ * Copyright (C) 2013, Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist. We must be able to enable
+ * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_cbmux_pin_mux(void);
+#endif
diff --git a/board/phytec/pcm051/mux.c b/board/phytec/pcm051/mux.c
--- /dev/null
@@ -0,0 +1,127 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+ {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
+ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
+ {-1},
+};
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+ {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
+ {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
+ {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
+ {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
+ {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
+ {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
+ {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
+ {-1},
+};
+#endif
+
+#ifdef CONFIG_I2C
+static struct module_pin_mux i2c0_pin_mux[] = {
+ {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+ PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+#endif
+
+#ifdef CONFIG_SPI
+static struct module_pin_mux spi0_pin_mux[] = {
+ {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
+ {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+ PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
+ {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
+ {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+ PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
+ {-1},
+};
+#endif
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+ {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
+ {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
+ {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
+ {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
+ {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
+ {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
+ {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
+ {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+ {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
+ {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+ {-1},
+};
+
+static struct module_pin_mux cbmux_pin_mux[] = {
+ {OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
+ {OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN}, /* JP4 */
+ {-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+ {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
+ {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
+ {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
+ {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
+ {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
+ {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
+ {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
+ {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
+ {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+ {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
+ {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
+ {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+ {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
+ {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
+ {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
+ {-1},
+};
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+ configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+ configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux()
+{
+ configure_module_pin_mux(rmii1_pin_mux);
+ configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(cbmux_pin_mux);
+#ifdef CONFIG_NAND
+ configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifdef CONFIG_SPI
+ configure_module_pin_mux(spi0_pin_mux);
+#endif
+}
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk Engineering, <wd@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
-OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
-*/
-#if defined(CONFIG_64BIT)
-OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
-#else
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
-#endif
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) +0x7ff0;
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- . = ALIGN(4);
- .sdata : { *(.sdata*) }
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- uboot_end_data = .;
-#if defined(CONFIG_64BIT)
- num_got_entries = (__got_end - __got_start) >> 3;
-#else
- num_got_entries = (__got_end - __got_start) >> 2;
-#endif
-
- . = ALIGN(4);
- .sbss : { *(.sbss*) }
- .bss : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
diff --git a/board/qi/qi_lb60/u-boot.lds b/board/qi/qi_lb60/u-boot.lds
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * (C) Copyright 2006
- * Ingenic Semiconductor, <jlwei@ingenic.cn>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
-
-OUTPUT_ARCH(mips)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = .;
- _gp = ALIGN(16) + 0x7ff0;
-
- __got_start = .;
- .got : { *(.got) }
- __got_end = .;
-
- .sdata : { *(.sdata*) }
-
-
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
- . = ALIGN(4);
- .sbss : { *(.sbss*) }
- .bss : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
-}
diff --git a/board/sc3/init.S b/board/sc3/init.S
index d374db4143bf999704634869a3603bc80cf6907a..635236835a5787b4d38e95aa43f44e2cf420114f 100644 (file)
--- a/board/sc3/init.S
+++ b/board/sc3/init.S
* This is need for the external flash access
*/
lis r25,0x0800
- ori r25,r25,0x0280 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280
+ /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
+ ori r25,r25,0x0280
/*
* Second, create a fast timing:
* 90ns first cycle - 3 clock access
* This is used for the internal access
*/
lis r26,0x8900
- ori r26,r26,0x0280 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx
+ /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
+ ori r26,r26,0x0280
/*
* We can't change settings on CS# if we currently use them.
* -> load a few instructions into cache and run this code from cache
index ed4229e258d24e58584b059abbf720625ebffbc8..441758fdf0077ce8ad5f3d79c2bc075e81d7e666 100644 (file)
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
return !strncmp(header.config, "SKU#02", 6);
}
+static int board_is_gp_evm(void)
+{
+ return !strncmp("A33515BB", header.name, 8);
+}
+
+int board_is_evm_15_or_later(void)
+{
+ return (!strncmp("A33515BB", header.name, 8) &&
+ strncmp("1.5", header.version, 3) <= 0);
+}
+
/*
* Read header information from EEPROM into global structure.
*/
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
+static const struct ddr_data ddr3_evm_data = {
+ .datardsratio0 = MT41J512M8RH125_RD_DQS,
+ .datawdsratio0 = MT41J512M8RH125_WR_DQS,
+ .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
+ .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
+ .datadldiff0 = PHY_DLL_LOCK_DIFF,
+};
+
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J128MJT125_RATIO,
.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};
+static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
+ .cmd0csratio = MT41J512M8RH125_RATIO,
+ .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+ .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+ .cmd1csratio = MT41J512M8RH125_RATIO,
+ .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+ .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+
+ .cmd2csratio = MT41J512M8RH125_RATIO,
+ .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
+ .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
+};
+
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41J128MJT125_EMIF_SDCFG,
.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
.zq_config = MT41J128MJT125_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
};
+
+static struct emif_regs ddr3_evm_emif_reg_data = {
+ .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
+ .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
+ .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
+ .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
+ .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+ .zq_config = MT41J512M8RH125_ZQ_CFG,
+ .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
+};
#endif
/*
if (board_is_evm_sk() || board_is_bone_lt())
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+ else if (board_is_evm_15_or_later())
+ config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
+ &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
else
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
}
#endif
-#ifdef CONFIG_DRIVER_TI_CPSW
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
-#ifdef CONFIG_DRIVER_TI_CPSW
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
- if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
- debug("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+ /* try reading mac address from efuse */
+ mac_lo = readl(&cdev->macid0l);
+ mac_hi = readl(&cdev->macid0h);
+ mac_addr[0] = mac_hi & 0xFF;
+ mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+ mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+ mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+ mac_addr[4] = mac_lo & 0xFF;
+ mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+ if (!getenv("ethaddr")) {
+ printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ether_addr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
- else
- goto try_usbether;
}
if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
+
+ /*
+ *
+ * CPSW RGMII Internal Delay Mode is not supported in all PVT
+ * operating points. So we must set the TX clock delay feature
+ * in the AR8051 PHY. Since we only support a single ethernet
+ * device in U-Boot, we only do this for the first instance.
+ */
+#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
+#define AR8051_PHY_DEBUG_DATA_REG 0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
+#define AR8051_RGMII_TX_CLK_DLY 0x100
+
+ if (board_is_evm_sk() || board_is_gp_evm()) {
+ const char *devname;
+ devname = miiphy_get_current_dev();
+
+ miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
+ AR8051_DEBUG_RGMII_CLK_DLY_REG);
+ miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
+ AR8051_RGMII_TX_CLK_DLY);
+ }
#endif
-try_usbether:
-#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_USB_ETHER) && \
+ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+ if (is_valid_ether_addr(mac_addr))
+ eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
+
rv = usb_eth_initialize(bis);
if (rv < 0)
printf("Error %d registering USB_ETHER\n", rv);
index b829a792b2c49b06e04508ce3b2bf9b4f3eb225a..58bd55620847d1a352d61f32028065b8b811f0ed 100644 (file)
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
#define BBTOYS_LCD 0x03000B00
#define BCT_BRETTL3 0x01000F00
#define BCT_BRETTL4 0x02000F00
+#define LSR_COM6L_ADPT 0x01001300
#define BEAGLE_NO_EEPROM 0xffffffff
DECLARE_GLOBAL_DATA_PTR;
i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
sizeof(expansion_config));
+ /* retry reading configuration data with 16bit addressing */
+ if ((expansion_config.device_vendor == 0xFFFFFF00) ||
+ (expansion_config.device_vendor == 0xFFFFFFFF)) {
+ printf("EEPROM is blank or 8bit addressing failed: retrying with 16bit:\n");
+ i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 2, (u8 *)&expansion_config,
+ sizeof(expansion_config));
+ }
+
i2c_set_bus_num(TWL4030_I2C_BUS);
return expansion_config.device_vendor;
case BCT_BRETTL4:
printf("Recognized bct electronic GmbH brettl4 board\n");
break;
+ case LSR_COM6L_ADPT:
+ printf("Recognized LSR COM6L Adapter Board\n");
+ MUX_BBTOYS_WIFI()
+ setenv("buddy", "lsr-com6l-adpt");
+ break;
case BEAGLE_NO_EEPROM:
printf("No EEPROM on expansion board\n");
setenv("buddy", "none");
diff --git a/board/xilinx/common/xbasic_types.c b/board/xilinx/common/xbasic_types.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
- *
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.c
-*
-* This file contains basic functions for Xilinx software IP.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/**
- * This variable allows testing to be done easier with asserts. An assert
- * sets this variable such that a driver can evaluate this variable
- * to determine if an assert occurred.
- */
-unsigned int XAssertStatus;
-
-/**
- * This variable allows the assert functionality to be changed for testing
- * such that it does not wait infinitely. Use the debugger to disable the
- * waiting during testing of asserts.
- */
-u32 XWaitInAssert = TRUE;
-
-/* The callback function to be invoked when an assert is taken */
-static XAssertCallback XAssertCallbackRoutine = (XAssertCallback) NULL;
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/**
-*
-* Implements assert. Currently, it calls a user-defined callback function
-* if one has been set. Then, it potentially enters an infinite loop depending
-* on the value of the XWaitInAssert variable.
-*
-* @param File is the name of the filename of the source
-* @param Line is the linenumber within File
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XAssert(char *File, int Line)
-{
- /* if the callback has been set then invoke it */
- if (XAssertCallbackRoutine != NULL) {
- (*XAssertCallbackRoutine) (File, Line);
- }
-
- /* if specified, wait indefinitely such that the assert will show up
- * in testing
- */
- while (XWaitInAssert) {
- }
-}
-
-/*****************************************************************************/
-/**
-*
-* Sets up a callback function to be invoked when an assert occurs. If there
-* was already a callback installed, then it is replaced.
-*
-* @param Routine is the callback to be invoked when an assert is taken
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* This function has no effect if NDEBUG is set
-*
-******************************************************************************/
-void
-XAssertSetCallback(XAssertCallback Routine)
-{
- XAssertCallbackRoutine = Routine;
-}
-
-/*****************************************************************************/
-/**
-*
-* Null handler function. This follows the XInterruptHandler signature for
-* interrupt handlers. It can be used to assign a null handler (a stub) to an
-* interrupt controller vector table.
-*
-* @param NullParameter is an arbitrary void pointer and not used.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XNullHandler(void *NullParameter)
-{
-}
diff --git a/board/xilinx/common/xbasic_types.h b/board/xilinx/common/xbasic_types.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xbasic_types.h
-*
-* This file contains basic types for Xilinx software IP. These types do not
-* follow the standard naming convention with respect to using the component
-* name in front of each name because they are considered to be primitives.
-*
-* @note
-*
-* This file contains items which are architecture dependent.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -------------------------------------------------------
-* 1.00a rmm 12/14/01 First release
-* rmm 05/09/03 Added "xassert always" macros to rid ourselves of diab
-* compiler warnings
-* 1.00a rpm 11/07/03 Added XNullHandler function as a stub interrupt handler
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
-#define XBASIC_TYPES_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-/************************** Constant Definitions *****************************/
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-/** Null */
-
-#define XCOMPONENT_IS_READY 0x11111111 /* component has been initialized */
-#define XCOMPONENT_IS_STARTED 0x22222222 /* component has been started */
-
-/* the following constants and declarations are for unit test purposes and are
- * designed to be used in test applications.
- */
-#define XTEST_PASSED 0
-#define XTEST_FAILED 1
-
-#define XASSERT_NONE 0
-#define XASSERT_OCCURRED 1
-
-extern unsigned int XAssertStatus;
-extern void XAssert(char *, int);
-
-/**************************** Type Definitions *******************************/
-
-/** @name Primitive types
- * These primitive types are created for transportability.
- * They are dependent upon the target architecture.
- * @{
- */
-#include <linux/types.h>
-
-typedef struct {
- u32 Upper;
- u32 Lower;
-} Xuint64;
-
-/*@}*/
-
-/**
- * This data type defines an interrupt handler for a device.
- * The argument points to the instance of the component
- */
-typedef void (*XInterruptHandler) (void *InstancePtr);
-
-/**
- * This data type defines a callback to be invoked when an
- * assert occurs. The callback is invoked only when asserts are enabled
- */
-typedef void (*XAssertCallback) (char *FilenamePtr, int LineNumber);
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/**
-* Return the most significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return
-*
-* The upper 32 bits of the 64 bit word.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XUINT64_MSW(x) ((x).Upper)
-
-/*****************************************************************************/
-/**
-* Return the least significant half of the 64 bit data type.
-*
-* @param x is the 64 bit word.
-*
-* @return
-*
-* The lower 32 bits of the 64 bit word.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XUINT64_LSW(x) ((x).Lower)
-
-#ifndef NDEBUG
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do not return anything
-* (void). This in conjunction with the XWaitInAssert boolean can be used to
-* accomodate tests so that asserts which fail allow execution to continue.
-*
-* @param expression is the expression to evaluate. If it evaluates to false,
-* the assert occurs.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_VOID(expression) \
-{ \
- if (expression) { \
- XAssertStatus = XASSERT_NONE; \
- } else { \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* This assert macro is to be used for functions that do return a value. This in
-* conjunction with the XWaitInAssert boolean can be used to accomodate tests so
-* that asserts which fail allow execution to continue.
-*
-* @param expression is the expression to evaluate. If it evaluates to false,
-* the assert occurs.
-*
-* @return
-*
-* Returns 0 unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_NONVOID(expression) \
-{ \
- if (expression) { \
- XAssertStatus = XASSERT_NONE; \
- } else { \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return 0; \
- } \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do not
-* return anything (void). Use for instances where an assert should always
-* occur.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_VOID_ALWAYS() \
-{ \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return; \
-}
-
-/*****************************************************************************/
-/**
-* Always assert. This assert macro is to be used for functions that do return
-* a value. Use for instances where an assert should always occur.
-*
-* @return
-*
-* Returns void unless the XWaitInAssert variable is true, in which case
-* no return is made and an infinite loop is entered.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-#define XASSERT_NONVOID_ALWAYS() \
-{ \
- XAssert(__FILE__, __LINE__); \
- XAssertStatus = XASSERT_OCCURRED; \
- return 0; \
-}
-
-#else
-
-#define XASSERT_VOID(expression)
-#define XASSERT_VOID_ALWAYS()
-#define XASSERT_NONVOID(expression)
-#define XASSERT_NONVOID_ALWAYS()
-#endif
-
-/************************** Function Prototypes ******************************/
-
-void XAssertSetCallback(XAssertCallback Routine);
-void XNullHandler(void *NullParameter);
-
-#endif /* end of protection macro */
diff --git a/board/xilinx/common/xbuf_descriptor.h b/board/xilinx/common/xbuf_descriptor.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xbuf_descriptor.h
-*
-* DESCRIPTION:
-*
-* This file contains the interface for the XBufDescriptor component.
-* The XBufDescriptor component is a passive component that only maps over
-* a buffer descriptor data structure shared by the scatter gather DMA hardware
-* and software. The component's primary purpose is to provide encapsulation of
-* the buffer descriptor processing. See the source file xbuf_descriptor.c for
-* details.
-*
-* NOTES:
-*
-* Most of the functions of this component are implemented as macros in order
-* to optimize the processing. The names are not all uppercase such that they
-* can be switched between macros and functions easily.
-*
-******************************************************************************/
-
-#ifndef XBUF_DESCRIPTOR_H /* prevent circular inclusions */
-#define XBUF_DESCRIPTOR_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xdma_channel_i.h"
-
-/************************** Constant Definitions *****************************/
-
-/* The following constants allow access to all fields of a buffer descriptor
- * and are necessary at this level of visibility to allow macros to access
- * and modify the fields of a buffer descriptor. It is not expected that the
- * user of a buffer descriptor would need to use these constants.
- */
-
-#define XBD_DEVICE_STATUS_OFFSET 0
-#define XBD_CONTROL_OFFSET 1
-#define XBD_SOURCE_OFFSET 2
-#define XBD_DESTINATION_OFFSET 3
-#define XBD_LENGTH_OFFSET 4
-#define XBD_STATUS_OFFSET 5
-#define XBD_NEXT_PTR_OFFSET 6
-#define XBD_ID_OFFSET 7
-#define XBD_FLAGS_OFFSET 8
-#define XBD_RQSTED_LENGTH_OFFSET 9
-
-#define XBD_SIZE_IN_WORDS 10
-
-/*
- * The following constants define the bits of the flags field of a buffer
- * descriptor
- */
-
-#define XBD_FLAGS_LOCKED_MASK 1UL
-
-/**************************** Type Definitions *******************************/
-
-typedef u32 XBufDescriptor[XBD_SIZE_IN_WORDS];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/* each of the following macros are named the same as functions rather than all
- * upper case in order to allow either the macros or the functions to be
- * used, see the source file xbuf_descriptor.c for documentation
- */
-
-#define XBufDescriptor_Initialize(InstancePtr) \
-{ \
- (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_ID_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = 0); \
- (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = 0); \
-}
-
-#define XBufDescriptor_GetControl(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET))
-
-#define XBufDescriptor_SetControl(InstancePtr, Control) \
- (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) = (u32)Control)
-
-#define XBufDescriptor_IsLastControl(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) & \
- XDC_CONTROL_LAST_BD_MASK)
-
-#define XBufDescriptor_SetLast(InstancePtr) \
- (*((u32 *)InstancePtr + XBD_CONTROL_OFFSET) |= XDC_CONTROL_LAST_BD_MASK)
-
-#define XBufDescriptor_GetSrcAddress(InstancePtr) \
- ((u32 *)(*((u32 *)InstancePtr + XBD_SOURCE_OFFSET)))
-
-#define XBufDescriptor_SetSrcAddress(InstancePtr, Source) \
- (*((u32 *)InstancePtr + XBD_SOURCE_OFFSET) = (u32)Source)
-
-#define XBufDescriptor_GetDestAddress(InstancePtr) \
- ((u32 *)(*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET)))
-
-#define XBufDescriptor_SetDestAddress(InstancePtr, Destination) \
- (*((u32 *)InstancePtr + XBD_DESTINATION_OFFSET) = (u32)Destination)
-
-#define XBufDescriptor_GetLength(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) - \
- *((u32 *)InstancePtr + XBD_LENGTH_OFFSET))
-
-#define XBufDescriptor_SetLength(InstancePtr, Length) \
-{ \
- (*((u32 *)InstancePtr + XBD_LENGTH_OFFSET) = (u32)(Length)); \
- (*((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET) = (u32)(Length));\
-}
-
-#define XBufDescriptor_GetStatus(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET))
-
-#define XBufDescriptor_SetStatus(InstancePtr, Status) \
- (*((u32 *)InstancePtr + XBD_STATUS_OFFSET) = (u32)Status)
-
-#define XBufDescriptor_IsLastStatus(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_STATUS_OFFSET) & \
- XDC_STATUS_LAST_BD_MASK)
-
-#define XBufDescriptor_GetDeviceStatus(InstancePtr) \
- ((u32)(*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET)))
-
-#define XBufDescriptor_SetDeviceStatus(InstancePtr, Status) \
- (*((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET) = (u32)Status)
-
-#define XBufDescriptor_GetNextPtr(InstancePtr) \
- (XBufDescriptor *)(*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET))
-
-#define XBufDescriptor_SetNextPtr(InstancePtr, NextPtr) \
- (*((u32 *)InstancePtr + XBD_NEXT_PTR_OFFSET) = (u32)NextPtr)
-
-#define XBufDescriptor_GetId(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_ID_OFFSET))
-
-#define XBufDescriptor_SetId(InstancePtr, Id) \
- (*((u32 *)InstancePtr + XBD_ID_OFFSET) = (u32)Id)
-
-#define XBufDescriptor_GetFlags(InstancePtr) \
- (u32)(*((u32 *)InstancePtr + XBD_FLAGS_OFFSET))
-
-#define XBufDescriptor_SetFlags(InstancePtr, Flags) \
- (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) = (u32)Flags)
-
-#define XBufDescriptor_Lock(InstancePtr) \
- (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) |= XBD_FLAGS_LOCKED_MASK)
-
-#define XBufDescriptor_Unlock(InstancePtr) \
- (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) &= ~XBD_FLAGS_LOCKED_MASK)
-
-#define XBufDescriptor_IsLocked(InstancePtr) \
- (*((u32 *)InstancePtr + XBD_FLAGS_OFFSET) & XBD_FLAGS_LOCKED_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/* The following prototypes are provided to allow each of the functions to
- * be implemented as a function rather than a macro, and to provide the
- * syntax to allow users to understand how to call the macros, they are
- * commented out to prevent linker errors
- *
-
-u32 XBufDescriptor_Initialize(XBufDescriptor* InstancePtr);
-
-u32 XBufDescriptor_GetControl(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetControl(XBufDescriptor* InstancePtr, u32 Control);
-
-u32 XBufDescriptor_IsLastControl(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetLast(XBufDescriptor* InstancePtr);
-
-u32 XBufDescriptor_GetLength(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetLength(XBufDescriptor* InstancePtr, u32 Length);
-
-u32 XBufDescriptor_GetStatus(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetStatus(XBufDescriptor* InstancePtr, u32 Status);
-u32 XBufDescriptor_IsLastStatus(XBufDescriptor* InstancePtr);
-
-u32 XBufDescriptor_GetDeviceStatus(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetDeviceStatus(XBufDescriptor* InstancePtr,
- u32 Status);
-
-u32 XBufDescriptor_GetSrcAddress(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetSrcAddress(XBufDescriptor* InstancePtr,
- u32 SourceAddress);
-
-u32 XBufDescriptor_GetDestAddress(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetDestAddress(XBufDescriptor* InstancePtr,
- u32 DestinationAddress);
-
-XBufDescriptor* XBufDescriptor_GetNextPtr(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetNextPtr(XBufDescriptor* InstancePtr,
- XBufDescriptor* NextPtr);
-
-u32 XBufDescriptor_GetId(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetId(XBufDescriptor* InstancePtr, u32 Id);
-
-u32 XBufDescriptor_GetFlags(XBufDescriptor* InstancePtr);
-void XBufDescriptor_SetFlags(XBufDescriptor* InstancePtr, u32 Flags);
-
-void XBufDescriptor_Lock(XBufDescriptor* InstancePtr);
-void XBufDescriptor_Unlock(XBufDescriptor* InstancePtr);
-u32 XBufDescriptor_IsLocked(XBufDescriptor* InstancePtr);
-
-void XBufDescriptor_Copy(XBufDescriptor* InstancePtr,
- XBufDescriptor* DestinationPtr);
-
-*/
-
-#endif /* end of protection macro */
diff --git a/board/xilinx/common/xdma_channel.c b/board/xilinx/common/xdma_channel.c
+++ /dev/null
@@ -1,738 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel.c
-*
-* DESCRIPTION:
-*
-* This file contains the DMA channel component. This component supports
-* a distributed DMA design in which each device can have it's own dedicated
-* DMA channel, as opposed to a centralized DMA design. This component
-* performs processing for DMA on all devices.
-*
-* See xdma_channel.h for more information about this component.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdma_channel.h"
-#include "xbasic_types.h"
-#include "xio.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_Initialize
-*
-* DESCRIPTION:
-*
-* This function initializes a DMA channel. This function must be called
-* prior to using a DMA channel. Initialization of a channel includes setting
-* up the registers base address, and resetting the channel such that it's in a
-* known state. Interrupts for the channel are disabled when the channel is
-* reset.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* BaseAddress contains the base address of the registers for the DMA channel.
-*
-* RETURN VALUE:
-*
-* XST_SUCCESS indicating initialization was successful.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress)
-{
- /* assert to verify input arguments, don't assert base address */
-
- XASSERT_NONVOID(InstancePtr != NULL);
-
- /* setup the base address of the registers for the DMA channel such
- * that register accesses can be done
- */
- InstancePtr->RegBaseAddress = BaseAddress;
-
- /* initialize the scatter gather list such that it indicates it has not
- * been created yet and the DMA channel is ready to use (initialized)
- */
- InstancePtr->GetPtr = NULL;
- InstancePtr->PutPtr = NULL;
- InstancePtr->CommitPtr = NULL;
- InstancePtr->LastPtr = NULL;
-
- InstancePtr->TotalDescriptorCount = 0;
- InstancePtr->ActiveDescriptorCount = 0;
- InstancePtr->IsReady = XCOMPONENT_IS_READY;
-
- /* initialize the version of the component
- */
- XVersion_FromString(&InstancePtr->Version, (s8 *)"1.00a");
-
- /* reset the DMA channel such that it's in a known state and ready
- * and indicate the initialization occured with no errors, note that
- * the is ready variable must be set before this call or reset will assert
- */
- XDmaChannel_Reset(InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_IsReady
-*
-* DESCRIPTION:
-*
-* This function determines if a DMA channel component has been successfully
-* initialized such that it's ready to use.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* TRUE if the DMA channel component is ready, FALSE otherwise.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_IsReady(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments used by the base component */
-
- XASSERT_NONVOID(InstancePtr != NULL);
-
- return InstancePtr->IsReady == XCOMPONENT_IS_READY;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetVersion
-*
-* DESCRIPTION:
-*
-* This function gets the software version for the specified DMA channel
-* component.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* A pointer to the software version of the specified DMA channel.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XVersion *
-XDmaChannel_GetVersion(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* return a pointer to the version of the DMA channel */
-
- return &InstancePtr->Version;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SelfTest
-*
-* DESCRIPTION:
-*
-* This function performs a self test on the specified DMA channel. This self
-* test is destructive as the DMA channel is reset and a register default is
-* verified.
-*
-* ARGUMENTS:
-*
-* InstancePtr is a pointer to the DMA channel to be operated on.
-*
-* RETURN VALUE:
-*
-* XST_SUCCESS is returned if the self test is successful, or one of the
-* following errors.
-*
-* XST_DMA_RESET_REGISTER_ERROR Indicates the control register value
-* after a reset was not correct
-*
-* NOTES:
-*
-* This test does not performs a DMA transfer to test the channel because the
-* DMA hardware will not currently allow a non-local memory transfer to non-local
-* memory (memory copy), but only allows a non-local memory to or from the device
-* memory (typically a FIFO).
-*
-******************************************************************************/
-
-#define XDC_CONTROL_REG_RESET_MASK 0x98000000UL /* control reg reset value */
-
-XStatus
-XDmaChannel_SelfTest(XDmaChannel * InstancePtr)
-{
- u32 ControlReg;
-
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* reset the DMA channel such that it's in a known state before the test
- * it resets to no interrupts enabled, the desired state for the test
- */
- XDmaChannel_Reset(InstancePtr);
-
- /* this should be the first test to help prevent a lock up with the polling
- * loop that occurs later in the test, check the reset value of the DMA
- * control register to make sure it's correct, return with an error if not
- */
- ControlReg = XDmaChannel_GetControl(InstancePtr);
- if (ControlReg != XDC_CONTROL_REG_RESET_MASK) {
- return XST_DMA_RESET_REGISTER_ERROR;
- }
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_Reset
-*
-* DESCRIPTION:
-*
-* This function resets the DMA channel. This is a destructive operation such
-* that it should not be done while a channel is being used. If the DMA channel
-* is transferring data into other blocks, such as a FIFO, it may be necessary
-* to reset other blocks. This function does not modify the contents of a
-* scatter gather list for a DMA channel such that the user is responsible for
-* getting buffer descriptors from the list if necessary.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_Reset(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* reset the DMA channel such that it's in a known state, the reset
- * register is self clearing such that it only has to be set
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_RST_REG_OFFSET,
- XDC_RESET_MASK);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetControl
-*
-* DESCRIPTION:
-*
-* This function gets the control register contents of the DMA channel.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The control register contents of the DMA channel. One or more of the
-* following values may be contained the register. Each of the values are
-* unique bit masks.
-*
-* XDC_DMACR_SOURCE_INCR_MASK Increment the source address
-* XDC_DMACR_DEST_INCR_MASK Increment the destination address
-* XDC_DMACR_SOURCE_LOCAL_MASK Local source address
-* XDC_DMACR_DEST_LOCAL_MASK Local destination address
-* XDC_DMACR_SG_ENABLE_MASK Scatter gather enable
-* XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt
-* XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetControl(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* return the contents of the DMA control register */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetControl
-*
-* DESCRIPTION:
-*
-* This function sets the control register of the specified DMA channel.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* Control contains the value to be written to the control register of the DMA
-* channel. One or more of the following values may be contained the register.
-* Each of the values are unique bit masks such that they may be ORed together
-* to enable multiple bits or inverted and ANDed to disable multiple bits.
-*
-* XDC_DMACR_SOURCE_INCR_MASK Increment the source address
-* XDC_DMACR_DEST_INCR_MASK Increment the destination address
-* XDC_DMACR_SOURCE_LOCAL_MASK Local source address
-* XDC_DMACR_DEST_LOCAL_MASK Local destination address
-* XDC_DMACR_SG_ENABLE_MASK Scatter gather enable
-* XDC_DMACR_GEN_BD_INTR_MASK Individual buffer descriptor interrupt
-* XDC_DMACR_LAST_BD_MASK Last buffer descriptor in a packet
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control)
-{
- /* assert to verify input arguments except the control which can't be
- * asserted since all values are valid
- */
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* set the DMA control register to the specified value */
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET, Control);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetStatus
-*
-* DESCRIPTION:
-*
-* This function gets the status register contents of the DMA channel.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The status register contents of the DMA channel. One or more of the
-* following values may be contained the register. Each of the values are
-* unique bit masks.
-*
-* XDC_DMASR_BUSY_MASK The DMA channel is busy
-* XDC_DMASR_BUS_ERROR_MASK A bus error occurred
-* XDC_DMASR_BUS_TIMEOUT_MASK A bus timeout occurred
-* XDC_DMASR_LAST_BD_MASK The last buffer descriptor of a packet
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetStatus(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* return the contents of the DMA status register */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetIntrStatus
-*
-* DESCRIPTION:
-*
-* This function sets the interrupt status register of the specified DMA channel.
-* Setting any bit of the interrupt status register will clear the bit to
-* indicate the interrupt processing has been completed. The definitions of each
-* bit in the register match the definition of the bits in the interrupt enable
-* register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* Status contains the value to be written to the status register of the DMA
-* channel. One or more of the following values may be contained the register.
-* Each of the values are unique bit masks such that they may be ORed together
-* to enable multiple bits or inverted and ANDed to disable multiple bits.
-*
-* XDC_IXR_DMA_DONE_MASK The dma operation is done
-* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
-* XDC_IXR_PKT_DONE_MASK A packet is complete
-* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
-* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-* XDC_IXR_BD_MASK A buffer descriptor is done
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status)
-{
- /* assert to verify input arguments except the status which can't be
- * asserted since all values are valid
- */
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* set the interrupt status register with the specified value such that
- * all bits which are set in the register are cleared effectively clearing
- * any active interrupts
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET, Status);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetIntrStatus
-*
-* DESCRIPTION:
-*
-* This function gets the interrupt status register of the specified DMA channel.
-* The interrupt status register indicates which interrupts are active
-* for the DMA channel. If an interrupt is active, the status register must be
-* set (written) with the bit set for each interrupt which has been processed
-* in order to clear the interrupts. The definitions of each bit in the register
-* match the definition of the bits in the interrupt enable register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The interrupt status register contents of the specified DMA channel.
-* One or more of the following values may be contained the register.
-* Each of the values are unique bit masks.
-*
-* XDC_IXR_DMA_DONE_MASK The dma operation is done
-* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
-* XDC_IXR_PKT_DONE_MASK A packet is complete
-* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
-* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-* XDC_IXR_SG_END_MASK Current descriptor was the end of the list
-* XDC_IXR_BD_MASK A buffer descriptor is done
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* return the contents of the interrupt status register */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetIntrEnable
-*
-* DESCRIPTION:
-*
-* This function sets the interrupt enable register of the specified DMA
-* channel. The interrupt enable register contains bits which enable
-* individual interrupts for the DMA channel. The definitions of each bit
-* in the register match the definition of the bits in the interrupt status
-* register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* Enable contains the interrupt enable register contents to be written
-* in the DMA channel. One or more of the following values may be contained
-* the register. Each of the values are unique bit masks such that they may be
-* ORed together to enable multiple bits or inverted and ANDed to disable
-* multiple bits.
-*
-* XDC_IXR_DMA_DONE_MASK The dma operation is done
-* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
-* XDC_IXR_PKT_DONE_MASK A packet is complete
-* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
-* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-* XDC_IXR_SG_END_MASK Current descriptor was the end of the list
-* XDC_IXR_BD_MASK A buffer descriptor is done
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable)
-{
- /* assert to verify input arguments except the enable which can't be
- * asserted since all values are valid
- */
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* set the interrupt enable register to the specified value */
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET, Enable);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetIntrEnable
-*
-* DESCRIPTION:
-*
-* This function gets the interrupt enable of the DMA channel. The
-* interrupt enable contains flags which enable individual interrupts for the
-* DMA channel. The definitions of each bit in the register match the definition
-* of the bits in the interrupt status register.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* RETURN VALUE:
-*
-* The interrupt enable of the DMA channel. One or more of the following values
-* may be contained the register. Each of the values are unique bit masks.
-*
-* XDC_IXR_DMA_DONE_MASK The dma operation is done
-* XDC_IXR_DMA_ERROR_MASK The dma operation had an error
-* XDC_IXR_PKT_DONE_MASK A packet is complete
-* XDC_IXR_PKT_THRESHOLD_MASK The packet count threshold reached
-* XDC_IXR_PKT_WAIT_BOUND_MASK The packet wait bound reached
-* XDC_IXR_SG_DISABLE_ACK_MASK The scatter gather disable completed
-* XDC_IXR_BD_MASK A buffer descriptor is done
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* return the contents of the interrupt enable register */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_IE_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_Transfer
-*
-* DESCRIPTION:
-*
-* This function starts the DMA channel transferring data from a memory source
-* to a memory destination. This function only starts the operation and returns
-* before the operation may be complete. If the interrupt is enabled, an
-* interrupt will be generated when the operation is complete, otherwise it is
-* necessary to poll the channel status to determine when it's complete. It is
-* the responsibility of the caller to determine when the operation is complete
-* by handling the generated interrupt or polling the status. It is also the
-* responsibility of the caller to ensure that the DMA channel is not busy with
-* another transfer before calling this function.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on.
-*
-* SourcePtr contains a pointer to the source memory where the data is to
-* be tranferred from and must be 32 bit aligned.
-*
-* DestinationPtr contains a pointer to the destination memory where the data
-* is to be transferred and must be 32 bit aligned.
-*
-* ByteCount contains the number of bytes to transfer during the DMA operation.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* The DMA h/w will not currently allow a non-local memory transfer to non-local
-* memory (memory copy), but only allows a non-local memory to or from the device
-* memory (typically a FIFO).
-*
-* It is the responsibility of the caller to ensure that the cache is
-* flushed and invalidated both before and after the DMA operation completes
-* if the memory pointed to is cached. The caller must also ensure that the
-* pointers contain a physical address rather than a virtual address
-* if address translation is being used.
-*
-******************************************************************************/
-void
-XDmaChannel_Transfer(XDmaChannel * InstancePtr,
- u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount)
-{
- /* assert to verify input arguments and the alignment of any arguments
- * which have expected alignments
- */
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(SourcePtr != NULL);
- XASSERT_VOID(((u32) SourcePtr & 3) == 0);
- XASSERT_VOID(DestinationPtr != NULL);
- XASSERT_VOID(((u32) DestinationPtr & 3) == 0);
- XASSERT_VOID(ByteCount != 0);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* setup the source and destination address registers for the transfer */
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_SA_REG_OFFSET,
- (u32) SourcePtr);
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_DA_REG_OFFSET,
- (u32) DestinationPtr);
-
- /* start the DMA transfer to copy from the source buffer to the
- * destination buffer by writing the length to the length register
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_LEN_REG_OFFSET, ByteCount);
-}
diff --git a/board/xilinx/common/xdma_channel.h b/board/xilinx/common/xdma_channel.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel.h
-*
-* DESCRIPTION:
-*
-* This file contains the DMA channel component implementation. This component
-* supports a distributed DMA design in which each device can have it's own
-* dedicated DMA channel, as opposed to a centralized DMA design.
-* A device which uses DMA typically contains two DMA channels, one for
-* sending data and the other for receiving data.
-*
-* This component is designed to be used as a basic building block for
-* designing a device driver. It provides registers accesses such that all
-* DMA processing can be maintained easier, but the device driver designer
-* must still understand all the details of the DMA channel.
-*
-* The DMA channel allows a CPU to minimize the CPU interaction required to move
-* data between a memory and a device. The CPU requests the DMA channel to
-* perform a DMA operation and typically continues performing other processing
-* until the DMA operation completes. DMA could be considered a primitive form
-* of multiprocessing such that caching and address translation can be an issue.
-*
-* Scatter Gather Operations
-*
-* The DMA channel may support scatter gather operations. A scatter gather
-* operation automates the DMA channel such that multiple buffers can be
-* sent or received with minimal software interaction with the hardware. Buffer
-* descriptors, contained in the XBufDescriptor component, are used by the
-* scatter gather operations of the DMA channel to describe the buffers to be
-* processed.
-*
-* Scatter Gather List Operations
-*
-* A scatter gather list may be supported by each DMA channel. The scatter
-* gather list allows buffer descriptors to be put into the list by a device
-* driver which requires scatter gather. The hardware processes the buffer
-* descriptors which are contained in the list and modifies the buffer
-* descriptors to reflect the status of the DMA operations. The device driver
-* is notified by interrupt that specific DMA events occur including scatter
-* gather events. The device driver removes the completed buffer descriptors
-* from the scatter gather list to evaluate the status of each DMA operation.
-*
-* The scatter gather list is created and buffer descriptors are inserted into
-* the list. Buffer descriptors are never removed from the list after it's
-* creation such that a put operation copies from a temporary buffer descriptor
-* to a buffer descriptor in the list. Get operations don't copy from the list
-* to a temporary, but return a pointer to the buffer descriptor in the list.
-* A buffer descriptor in the list may be locked to prevent it from being
-* overwritten by a put operation. This allows the device driver to get a
-* descriptor from a scatter gather list and prevent it from being overwritten
-* until the buffer associated with the buffer descriptor has been processed.
-*
-* Typical Scatter Gather Processing
-*
-* The following steps illustrate the typical processing to use the
-* scatter gather features of a DMA channel.
-*
-* 1. Create a scatter gather list for the DMA channel which puts empty buffer
-* descriptors into the list.
-* 2. Create buffer descriptors which describe the buffers to be filled with
-* receive data or the buffers which contain data to be sent.
-* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
-* gather operations are requested.
-* 4. Commit the buffer descriptors in the list such that they are ready to be
-* used by the DMA channel hardware.
-* 5. Start the scatter gather operations of the DMA channel.
-* 6. Process any interrupts which occur as a result of the scatter gather
-* operations or poll the DMA channel to determine the status.
-*
-* Interrupts
-*
-* Each DMA channel has the ability to generate an interrupt. This component
-* does not perform processing for the interrupt as this processing is typically
-* tightly coupled with the device which is using the DMA channel. It is the
-* responsibility of the caller of DMA functions to manage the interrupt
-* including connecting to the interrupt and enabling/disabling the interrupt.
-*
-* Critical Sections
-*
-* It is the responsibility of the device driver designer to use critical
-* sections as necessary when calling functions of the DMA channel. This
-* component does not use critical sections and it does access registers using
-* read-modify-write operations. Calls to DMA functions from a main thread
-* and from an interrupt context could produce unpredictable behavior such that
-* the caller must provide the appropriate critical sections.
-*
-* Address Translation
-*
-* All addresses of data structures which are passed to DMA functions must
-* be physical (real) addresses as opposed to logical (virtual) addresses.
-*
-* Caching
-*
-* The memory which is passed to the function which creates the scatter gather
-* list must not be cached such that buffer descriptors are non-cached. This
-* is necessary because the buffer descriptors are kept in a ring buffer and
-* not directly accessible to the caller of DMA functions.
-*
-* The caller of DMA functions is responsible for ensuring that any data
-* buffers which are passed to the DMA channel are cache-line aligned if
-* necessary.
-*
-* The caller of DMA functions is responsible for ensuring that any data
-* buffers which are passed to the DMA channel have been flushed from the cache.
-*
-* The caller of DMA functions is responsible for ensuring that the cache is
-* invalidated prior to using any data buffers which are the result of a DMA
-* operation.
-*
-* Memory Alignment
-*
-* The addresses of data buffers which are passed to DMA functions must be
-* 32 bit word aligned since the DMA hardware performs 32 bit word transfers.
-*
-* Mutual Exclusion
-*
-* The functions of the DMA channel are not thread safe such that the caller
-* of all DMA functions is responsible for ensuring mutual exclusion for a
-* DMA channel. Mutual exclusion across multiple DMA channels is not
-* necessary.
-*
-* NOTES:
-*
-* Many of the provided functions which are register accessors don't provide
-* a lot of error detection. The caller is expected to understand the impact
-* of a function call based upon the current state of the DMA channel. This
-* is done to minimize the overhead in this component.
-*
-******************************************************************************/
-
-#ifndef XDMA_CHANNEL_H /* prevent circular inclusions */
-#define XDMA_CHANNEL_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xdma_channel_i.h" /* constants shared with buffer descriptor */
-#include "xbasic_types.h"
-#include "xstatus.h"
-#include "xversion.h"
-#include "xbuf_descriptor.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constants provide access to the bit fields of the DMA control
- * register (DMACR)
- */
-#define XDC_DMACR_SOURCE_INCR_MASK 0x80000000UL /* increment source address */
-#define XDC_DMACR_DEST_INCR_MASK 0x40000000UL /* increment dest address */
-#define XDC_DMACR_SOURCE_LOCAL_MASK 0x20000000UL /* local source address */
-#define XDC_DMACR_DEST_LOCAL_MASK 0x10000000UL /* local dest address */
-#define XDC_DMACR_SG_DISABLE_MASK 0x08000000UL /* scatter gather disable */
-#define XDC_DMACR_GEN_BD_INTR_MASK 0x04000000UL /* descriptor interrupt */
-#define XDC_DMACR_LAST_BD_MASK XDC_CONTROL_LAST_BD_MASK /* last buffer */
- /* descriptor */
-
-/* the following constants provide access to the bit fields of the DMA status
- * register (DMASR)
- */
-#define XDC_DMASR_BUSY_MASK 0x80000000UL /* channel is busy */
-#define XDC_DMASR_BUS_ERROR_MASK 0x40000000UL /* bus error occurred */
-#define XDC_DMASR_BUS_TIMEOUT_MASK 0x20000000UL /* bus timeout occurred */
-#define XDC_DMASR_LAST_BD_MASK XDC_STATUS_LAST_BD_MASK /* last buffer */
- /* descriptor */
-#define XDC_DMASR_SG_BUSY_MASK 0x08000000UL /* scatter gather is busy */
-
-/* the following constants provide access to the bit fields of the interrupt
- * status register (ISR) and the interrupt enable register (IER), bit masks
- * match for both registers such that they are named IXR
- */
-#define XDC_IXR_DMA_DONE_MASK 0x1UL /* dma operation done */
-#define XDC_IXR_DMA_ERROR_MASK 0x2UL /* dma operation error */
-#define XDC_IXR_PKT_DONE_MASK 0x4UL /* packet done */
-#define XDC_IXR_PKT_THRESHOLD_MASK 0x8UL /* packet count threshold */
-#define XDC_IXR_PKT_WAIT_BOUND_MASK 0x10UL /* packet wait bound reached */
-#define XDC_IXR_SG_DISABLE_ACK_MASK 0x20UL /* scatter gather disable
- acknowledge occurred */
-#define XDC_IXR_SG_END_MASK 0x40UL /* last buffer descriptor
- disabled scatter gather */
-#define XDC_IXR_BD_MASK 0x80UL /* buffer descriptor done */
-
-/**************************** Type Definitions *******************************/
-
-/*
- * the following structure contains data which is on a per instance basis
- * for the XDmaChannel component
- */
-typedef struct XDmaChannelTag {
- XVersion Version; /* version of the driver */
- u32 RegBaseAddress; /* base address of registers */
- u32 IsReady; /* device is initialized and ready */
-
- XBufDescriptor *PutPtr; /* keep track of where to put into list */
- XBufDescriptor *GetPtr; /* keep track of where to get from list */
- XBufDescriptor *CommitPtr; /* keep track of where to commit in list */
- XBufDescriptor *LastPtr; /* keep track of the last put in the list */
- u32 TotalDescriptorCount; /* total # of descriptors in the list */
- u32 ActiveDescriptorCount; /* # of descriptors pointing to buffers
- * in the buffer descriptor list */
-} XDmaChannel;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-XStatus XDmaChannel_Initialize(XDmaChannel * InstancePtr, u32 BaseAddress);
-u32 XDmaChannel_IsReady(XDmaChannel * InstancePtr);
-XVersion *XDmaChannel_GetVersion(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_SelfTest(XDmaChannel * InstancePtr);
-void XDmaChannel_Reset(XDmaChannel * InstancePtr);
-
-/* Control functions */
-
-u32 XDmaChannel_GetControl(XDmaChannel * InstancePtr);
-void XDmaChannel_SetControl(XDmaChannel * InstancePtr, u32 Control);
-
-/* Status functions */
-
-u32 XDmaChannel_GetStatus(XDmaChannel * InstancePtr);
-void XDmaChannel_SetIntrStatus(XDmaChannel * InstancePtr, u32 Status);
-u32 XDmaChannel_GetIntrStatus(XDmaChannel * InstancePtr);
-void XDmaChannel_SetIntrEnable(XDmaChannel * InstancePtr, u32 Enable);
-u32 XDmaChannel_GetIntrEnable(XDmaChannel * InstancePtr);
-
-/* DMA without scatter gather functions */
-
-void XDmaChannel_Transfer(XDmaChannel * InstancePtr,
- u32 * SourcePtr, u32 * DestinationPtr, u32 ByteCount);
-
-/* Scatter gather functions */
-
-XStatus XDmaChannel_SgStart(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_SgStop(XDmaChannel * InstancePtr,
- XBufDescriptor ** BufDescriptorPtr);
-XStatus XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
- u32 * MemoryPtr, u32 ByteCount);
-u32 XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr);
-
-XStatus XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
- XBufDescriptor * BufDescriptorPtr);
-XStatus XDmaChannel_CommitPuts(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
- XBufDescriptor ** BufDescriptorPtr);
-
-/* Packet functions for interrupt collescing */
-
-u32 XDmaChannel_GetPktCount(XDmaChannel * InstancePtr);
-void XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr);
-XStatus XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold);
-u8 XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr);
-void XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound);
-u32 XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr);
-
-#endif /* end of protection macro */
diff --git a/board/xilinx/common/xdma_channel_i.h b/board/xilinx/common/xdma_channel_i.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel_i.h
-*
-* DESCRIPTION:
-*
-* This file contains data which is shared internal data for the DMA channel
-* component. It is also shared with the buffer descriptor component which is
-* very tightly coupled with the DMA channel component.
-*
-* NOTES:
-*
-* The last buffer descriptor constants must be located here to prevent a
-* circular dependency between the DMA channel component and the buffer
-* descriptor component.
-*
-******************************************************************************/
-
-#ifndef XDMA_CHANNEL_I_H /* prevent circular inclusions */
-#define XDMA_CHANNEL_I_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xstatus.h"
-#include "xversion.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XDC_DMA_CHANNEL_V1_00_A "1.00a"
-
-/* the following constant provides access to the bit fields of the DMA control
- * register (DMACR) which must be shared between the DMA channel component
- * and the buffer descriptor component
- */
-#define XDC_CONTROL_LAST_BD_MASK 0x02000000UL /* last buffer descriptor */
-
-/* the following constant provides access to the bit fields of the DMA status
- * register (DMASR) which must be shared between the DMA channel component
- * and the buffer descriptor component
- */
-#define XDC_STATUS_LAST_BD_MASK 0x10000000UL /* last buffer descriptor */
-
-/* the following constants provide access to each of the registers of a DMA
- * channel
- */
-#define XDC_RST_REG_OFFSET 0 /* reset register */
-#define XDC_MI_REG_OFFSET 0 /* module information register */
-#define XDC_DMAC_REG_OFFSET 4 /* DMA control register */
-#define XDC_SA_REG_OFFSET 8 /* source address register */
-#define XDC_DA_REG_OFFSET 12 /* destination address register */
-#define XDC_LEN_REG_OFFSET 16 /* length register */
-#define XDC_DMAS_REG_OFFSET 20 /* DMA status register */
-#define XDC_BDA_REG_OFFSET 24 /* buffer descriptor address register */
-#define XDC_SWCR_REG_OFFSET 28 /* software control register */
-#define XDC_UPC_REG_OFFSET 32 /* unserviced packet count register */
-#define XDC_PCT_REG_OFFSET 36 /* packet count threshold register */
-#define XDC_PWB_REG_OFFSET 40 /* packet wait bound register */
-#define XDC_IS_REG_OFFSET 44 /* interrupt status register */
-#define XDC_IE_REG_OFFSET 48 /* interrupt enable register */
-
-/* the following constant is written to the reset register to reset the
- * DMA channel
- */
-#define XDC_RESET_MASK 0x0000000AUL
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-#endif /* end of protection macro */
diff --git a/board/xilinx/common/xdma_channel_sg.c b/board/xilinx/common/xdma_channel_sg.c
+++ /dev/null
@@ -1,1317 +0,0 @@
-/* $Id: xdma_channel_sg.c,v 1.6 2003/02/03 19:50:33 moleres Exp $ */
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* FILENAME:
-*
-* xdma_channel_sg.c
-*
-* DESCRIPTION:
-*
-* This file contains the implementation of the XDmaChannel component which is
-* related to scatter gather operations.
-*
-* Scatter Gather Operations
-*
-* The DMA channel may support scatter gather operations. A scatter gather
-* operation automates the DMA channel such that multiple buffers can be
-* sent or received with minimal software interaction with the hardware. Buffer
-* descriptors, contained in the XBufDescriptor component, are used by the
-* scatter gather operations of the DMA channel to describe the buffers to be
-* processed.
-*
-* Scatter Gather List Operations
-*
-* A scatter gather list may be supported by each DMA channel. The scatter
-* gather list allows buffer descriptors to be put into the list by a device
-* driver which requires scatter gather. The hardware processes the buffer
-* descriptors which are contained in the list and modifies the buffer
-* descriptors to reflect the status of the DMA operations. The device driver
-* is notified by interrupt that specific DMA events occur including scatter
-* gather events. The device driver removes the completed buffer descriptors
-* from the scatter gather list to evaluate the status of each DMA operation.
-*
-* The scatter gather list is created and buffer descriptors are inserted into
-* the list. Buffer descriptors are never removed from the list after it's
-* creation such that a put operation copies from a temporary buffer descriptor
-* to a buffer descriptor in the list. Get operations don't copy from the list
-* to a temporary, but return a pointer to the buffer descriptor in the list.
-* A buffer descriptor in the list may be locked to prevent it from being
-* overwritten by a put operation. This allows the device driver to get a
-* descriptor from a scatter gather list and prevent it from being overwritten
-* until the buffer associated with the buffer descriptor has been processed.
-*
-* The get and put functions only operate on the list and are asynchronous from
-* the hardware which may be using the list of descriptors. This is important
-* because there are no checks in the get and put functions to ensure that the
-* hardware has processed the descriptors. This must be handled by the driver
-* using the DMA scatter gather channel through the use of the other functions.
-* When a scatter gather operation is started, the start function does ensure
-* that the descriptor to start has not already been processed by the hardware
-* and is not the first of a series of descriptors that have not been committed
-* yet.
-*
-* Descriptors are put into the list but not marked as ready to use by the
-* hardware until a commit operation is done. This allows multiple descriptors
-* which may contain a single packet of information for a protocol to be
-* guaranteed not to cause any underflow conditions during transmission. The
-* hardware design only allows descriptors to cause it to stop after a descriptor
-* has been processed rather than before it is processed. A series of
-* descriptors are put into the list followed by a commit operation, or each
-* descriptor may be commited. A commit operation is performed by changing a
-* single descriptor, the first of the series of puts, to indicate that the
-* hardware may now use all descriptors after it. The last descriptor in the
-* list is always set to cause the hardware to stop after it is processed.
-*
-* Typical Scatter Gather Processing
-*
-* The following steps illustrate the typical processing to use the
-* scatter gather features of a DMA channel.
-*
-* 1. Create a scatter gather list for the DMA channel which puts empty buffer
-* descriptors into the list.
-* 2. Create buffer descriptors which describe the buffers to be filled with
-* receive data or the buffers which contain data to be sent.
-* 3. Put buffer descriptors into the DMA channel scatter list such that scatter
-* gather operations are requested.
-* 4. Commit the buffer descriptors in the list such that they are ready to be
-* used by the DMA channel hardware.
-* 5. Start the scatter gather operations of the DMA channel.
-* 6. Process any interrupts which occur as a result of the scatter gather
-* operations or poll the DMA channel to determine the status. This may
-* be accomplished by getting the packet count for the channel and then
-* getting the appropriate number of descriptors from the list for that
-* number of packets.
-*
-* Minimizing Interrupts
-*
-* The Scatter Gather operating mode is designed to reduce the amount of CPU
-* throughput necessary to manage the hardware for devices. A key to the CPU
-* throughput is the number and rate of interrupts that the CPU must service.
-* Devices with higher data rates can cause larger numbers of interrupts and
-* higher frequency interrupts. Ideally the number of interrupts can be reduced
-* by only generating an interrupt when a specific amount of data has been
-* received from the interface. This design suffers from a lack of interrupts
-* when the amount of data received is less than the specified amount of data
-* to generate an interrupt. In order to help minimize the number of interrupts
-* which the CPU must service, an algorithm referred to as "interrupt coalescing"
-* is utilized.
-*
-* Interrupt Coalescing
-*
-* The principle of interrupt coalescing is to wait before generating an
-* interrupt until a certain number of packets have been received or sent. An
-* interrupt is also generated if a smaller number of packets have been received
-* followed by a certain period of time with no packet reception. This is a
-* trade-off of latency for bandwidth and is accomplished using several
-* mechanisms of the hardware including a counter for packets received or
-* transmitted and a packet timer. These two hardware mechanisms work in
-* combination to allow a reduction in the number of interrupts processed by the
-* CPU for packet reception.
-*
-* Unserviced Packet Count
-*
-* The purpose of the packet counter is to count the number of packets received
-* or transmitted and provide an interrupt when a specific number of packets
-* have been processed by the hardware. An interrupt is generated whenever the
-* counter is greater than or equal to the Packet Count Threshold. This counter
-* contains an accurate count of the number of packets that the hardware has
-* processed, either received or transmitted, and the software has not serviced.
-*
-* The packet counter allows the number of interrupts to be reduced by waiting
-* to generate an interrupt until enough packets are received. For packet
-* reception, packet counts of less than the number to generate an interrupt
-* would not be serviced without the addition of a packet timer. This counter is
-* continuously updated by the hardware, not latched to the value at the time
-* the interrupt occurred.
-*
-* The packet counter can be used within the interrupt service routine for the
-* device to reduce the number of interrupts. The interrupt service routine
-* loops while performing processing for each packet which has been received or
-* transmitted and decrements the counter by a specified value. At the same time,
-* the hardware is possibly continuing to receive or transmit more packets such
-* that the software may choose, based upon the value in the packet counter, to
-* remain in the interrupt service routine rather than exiting and immediately
-* returning. This feature should be used with caution as reducing the number of
-* interrupts is beneficial, but unbounded interrupt processing is not desirable.
-*
-* Since the hardware may be incrementing the packet counter simultaneously
-* with the software decrementing the counter, there is a need for atomic
-* operations. The hardware ensures that the operation is atomic such that
-* simultaneous accesses are properly handled.
-*
-* Packet Wait Bound
-*
-* The purpose of the packet wait bound is to augment the unserviced packet
-* count. Whenever there is no pending interrupt for the channel and the
-* unserviced packet count is non-zero, a timer starts counting timeout at the
-* value contained the the packet wait bound register. If the timeout is
-* reached, an interrupt is generated such that the software may service the
-* data which was buffered.
-*
-* NOTES:
-*
-* Special Test Conditions:
-*
-* The scatter gather list processing must be thoroughly tested if changes are
-* made. Testing should include putting and committing single descriptors and
-* putting multiple descriptors followed by a single commit. There are some
-* conditions in the code which handle the exception conditions.
-*
-* The Put Pointer points to the next location in the descriptor list to copy
-* in a new descriptor. The Get Pointer points to the next location in the
-* list to get a descriptor from. The Get Pointer only allows software to
-* have a traverse the list after the hardware has finished processing some
-* number of descriptors. The Commit Pointer points to the descriptor in the
-* list which is to be committed. It is also used to determine that no
-* descriptor is waiting to be commited (NULL). The Last Pointer points to
-* the last descriptor that was put into the list. It typically points
-* to the previous descriptor to the one pointed to by the Put Pointer.
-* Comparisons are done between these pointers to determine when the following
-* special conditions exist.
-
-* Single Put And Commit
-*
-* The buffer descriptor is ready to be used by the hardware so it is important
-* for the descriptor to not appear to be waiting to be committed. The commit
-* pointer is reset when a commit is done indicating there are no descriptors
-* waiting to be committed. In all cases but this one, the descriptor is
-* changed to cause the hardware to go to the next descriptor after processing
-* this one. But in this case, this is the last descriptor in the list such
-* that it must not be changed.
-*
-* 3 Or More Puts And Commit
-*
-* A series of 3 or more puts followed by a single commit is different in that
-* only the 1st descriptor put into the list is changed when the commit is done.
-* This requires each put starting on the 3rd to change the previous descriptor
-* so that it allows the hardware to continue to the next descriptor in the list.
-*
-* The 1st Put Following A Commit
-*
-* The commit caused the commit pointer to be NULL indicating that there are no
-* descriptors waiting to be committed. It is necessary for the next put to set
-* the commit pointer so that a commit must follow the put for the hardware to
-* use the descriptor.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- ------------------------------------------------------
-* 1.00a rpm 02/03/03 Removed the XST_DMA_SG_COUNT_EXCEEDED return code
-* from SetPktThreshold.
-* </pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xdma_channel.h"
-#include "xbasic_types.h"
-#include "xio.h"
-#include "xbuf_descriptor.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-#define XDC_SWCR_SG_ENABLE_MASK 0x80000000UL /* scatter gather enable */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/* the following macro copies selected fields of a buffer descriptor to another
- * buffer descriptor, this was provided by the buffer descriptor component but
- * was moved here since it is only used internally to this component and since
- * it does not copy all fields
- */
-#define CopyBufferDescriptor(InstancePtr, DestinationPtr) \
-{ \
- *((u32 *)DestinationPtr + XBD_CONTROL_OFFSET) = \
- *((u32 *)InstancePtr + XBD_CONTROL_OFFSET); \
- *((u32 *)DestinationPtr + XBD_SOURCE_OFFSET) = \
- *((u32 *)InstancePtr + XBD_SOURCE_OFFSET); \
- *((u32 *)DestinationPtr + XBD_DESTINATION_OFFSET) = \
- *((u32 *)InstancePtr + XBD_DESTINATION_OFFSET); \
- *((u32 *)DestinationPtr + XBD_LENGTH_OFFSET) = \
- *((u32 *)InstancePtr + XBD_LENGTH_OFFSET); \
- *((u32 *)DestinationPtr + XBD_STATUS_OFFSET) = \
- *((u32 *)InstancePtr + XBD_STATUS_OFFSET); \
- *((u32 *)DestinationPtr + XBD_DEVICE_STATUS_OFFSET) = \
- *((u32 *)InstancePtr + XBD_DEVICE_STATUS_OFFSET); \
- *((u32 *)DestinationPtr + XBD_ID_OFFSET) = \
- *((u32 *)InstancePtr + XBD_ID_OFFSET); \
- *((u32 *)DestinationPtr + XBD_FLAGS_OFFSET) = \
- *((u32 *)InstancePtr + XBD_FLAGS_OFFSET); \
- *((u32 *)DestinationPtr + XBD_RQSTED_LENGTH_OFFSET) = \
- *((u32 *)InstancePtr + XBD_RQSTED_LENGTH_OFFSET); \
-}
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SgStart
-*
-* DESCRIPTION:
-*
-* This function starts a scatter gather operation for a scatter gather
-* DMA channel. The first buffer descriptor in the buffer descriptor list
-* will be started with the scatter gather operation. A scatter gather list
-* should have previously been created for the DMA channel and buffer
-* descriptors put into the scatter gather list such that there are scatter
-* operations ready to be performed.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* A status containing XST_SUCCESS if scatter gather was started successfully
-* for the DMA channel.
-*
-* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
-* been created.
-*
-* A value of XST_DMA_SG_LIST_EMPTY indicates scatter gather was not started
-* because the scatter gather list of the DMA channel does not contain any
-* buffer descriptors that are ready to be processed by the hardware.
-*
-* A value of XST_DMA_SG_IS_STARTED indicates scatter gather was not started
-* because the scatter gather was not stopped, but was already started.
-*
-* A value of XST_DMA_SG_BD_NOT_COMMITTED indicates the buffer descriptor of
-* scatter gather list which was to be started is not committed to the list.
-* This status is more likely if this function is being called from an ISR
-* and non-ISR processing is putting descriptors into the list.
-*
-* A value of XST_DMA_SG_NO_DATA indicates that the buffer descriptor of the
-* scatter gather list which was to be started had already been used by the
-* hardware for a DMA transfer that has been completed.
-*
-* NOTES:
-*
-* It is the responsibility of the caller to get all the buffer descriptors
-* after performing a stop operation and before performing a start operation.
-* If buffer descriptors are not retrieved between stop and start operations,
-* buffer descriptors may be processed by the hardware more than once.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_SgStart(XDmaChannel * InstancePtr)
-{
- u32 Register;
- XBufDescriptor *LastDescriptorPtr;
-
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if a scatter gather list has not been created yet, return a status */
-
- if (InstancePtr->TotalDescriptorCount == 0) {
- return XST_DMA_SG_NO_LIST;
- }
-
- /* if the scatter gather list exists but is empty then return a status */
-
- if (XDmaChannel_IsSgListEmpty(InstancePtr)) {
- return XST_DMA_SG_LIST_EMPTY;
- }
-
- /* if scatter gather is busy for the DMA channel, return a status because
- * restarting it could lose data
- */
-
- Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAS_REG_OFFSET);
- if (Register & XDC_DMASR_SG_BUSY_MASK) {
- return XST_DMA_SG_IS_STARTED;
- }
-
- /* get the address of the last buffer descriptor which the DMA hardware
- * finished processing
- */
- LastDescriptorPtr =
- (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress +
- XDC_BDA_REG_OFFSET);
-
- /* setup the first buffer descriptor that will be sent when the scatter
- * gather channel is enabled, this is only necessary one time since
- * the BDA register of the channel maintains the last buffer descriptor
- * processed
- */
- if (LastDescriptorPtr == NULL) {
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_BDA_REG_OFFSET,
- (u32) InstancePtr->GetPtr);
- } else {
- XBufDescriptor *NextDescriptorPtr;
-
- /* get the next descriptor to be started, if the status indicates it
- * hasn't already been used by the h/w, then it's OK to start it,
- * s/w sets the status of each descriptor to busy and then h/w clears
- * the busy when it is complete
- */
- NextDescriptorPtr =
- XBufDescriptor_GetNextPtr(LastDescriptorPtr);
-
- if ((XBufDescriptor_GetStatus(NextDescriptorPtr) &
- XDC_DMASR_BUSY_MASK) == 0) {
- return XST_DMA_SG_NO_DATA;
- }
- /* don't start the DMA SG channel if the descriptor to be processed
- * by h/w is to be committed by the s/w, this function can be called
- * such that it interrupts a thread that was putting into the list
- */
- if (NextDescriptorPtr == InstancePtr->CommitPtr) {
- return XST_DMA_SG_BD_NOT_COMMITTED;
- }
- }
-
- /* start the scatter gather operation by clearing the stop bit in the
- * control register and setting the enable bit in the s/w control register,
- * both of these are necessary to cause it to start, right now the order of
- * these statements is important, the software control register should be
- * set 1st. The other order can cause the CPU to have a loss of sync
- * because it cannot read/write the register while the DMA operation is
- * running
- */
-
- Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET);
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET,
- Register | XDC_SWCR_SG_ENABLE_MASK);
-
- Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET);
-
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_DMAC_REG_OFFSET,
- Register & ~XDC_DMACR_SG_DISABLE_MASK);
-
- /* indicate the DMA channel scatter gather operation was started
- * successfully
- */
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SgStop
-*
-* DESCRIPTION:
-*
-* This function stops a scatter gather operation for a scatter gather
-* DMA channel. This function starts the process of stopping a scatter
-* gather operation that is in progress and waits for the stop to be completed.
-* Since it waits for the operation to stopped before returning, this function
-* could take an amount of time relative to the size of the DMA scatter gather
-* operation which is in progress. The scatter gather list of the DMA channel
-* is not modified by this function such that starting the scatter gather
-* channel after stopping it will cause it to resume. This operation is
-* considered to be a graceful stop in that the scatter gather operation
-* completes the current buffer descriptor before stopping.
-*
-* If the interrupt is enabled, an interrupt will be generated when the
-* operation is stopped and the caller is responsible for handling the
-* interrupt.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* BufDescriptorPtr is also a return value which contains a pointer to the
-* buffer descriptor which the scatter gather operation completed when it
-* was stopped.
-*
-* RETURN VALUE:
-*
-* A status containing XST_SUCCESS if scatter gather was stopped successfully
-* for the DMA channel.
-*
-* A value of XST_DMA_SG_IS_STOPPED indicates scatter gather was not stoppped
-* because the scatter gather is not started, but was already stopped.
-*
-* BufDescriptorPtr contains a pointer to the buffer descriptor which was
-* completed when the operation was stopped.
-*
-* NOTES:
-*
-* This function implements a loop which polls the hardware for an infinite
-* amount of time. If the hardware is not operating correctly, this function
-* may never return.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_SgStop(XDmaChannel * InstancePtr,
- XBufDescriptor ** BufDescriptorPtr)
-{
- u32 Register;
-
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufDescriptorPtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the contents of the software control register, if scatter gather is not
- * enabled (started), then return a status because the disable acknowledge
- * would not be generated
- */
- Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET);
-
- if ((Register & XDC_SWCR_SG_ENABLE_MASK) == 0) {
- return XST_DMA_SG_IS_STOPPED;
- }
-
- /* Ensure the interrupt status for the scatter gather is cleared such
- * that this function will wait til the disable has occurred, writing
- * a 1 to only that bit in the register will clear only it
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET,
- XDC_IXR_SG_DISABLE_ACK_MASK);
-
- /* disable scatter gather by writing to the software control register
- * without modifying any other bits of the register
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_SWCR_REG_OFFSET,
- Register & ~XDC_SWCR_SG_ENABLE_MASK);
-
- /* scatter gather does not disable immediately, but after the current
- * buffer descriptor is complete, so wait for the DMA channel to indicate
- * the disable is complete
- */
- do {
- Register =
- XIo_In32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET);
- } while ((Register & XDC_IXR_SG_DISABLE_ACK_MASK) == 0);
-
- /* Ensure the interrupt status for the scatter gather disable is cleared,
- * writing a 1 to only that bit in the register will clear only it
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_IS_REG_OFFSET,
- XDC_IXR_SG_DISABLE_ACK_MASK);
-
- /* set the specified buffer descriptor pointer to point to the buffer
- * descriptor that the scatter gather DMA channel was processing
- */
- *BufDescriptorPtr =
- (XBufDescriptor *) XIo_In32(InstancePtr->RegBaseAddress +
- XDC_BDA_REG_OFFSET);
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_CreateSgList
-*
-* DESCRIPTION:
-*
-* This function creates a scatter gather list in the DMA channel. A scatter
-* gather list consists of a list of buffer descriptors that are available to
-* be used for scatter gather operations. Buffer descriptors are put into the
-* list to request a scatter gather operation to be performed.
-*
-* A number of buffer descriptors are created from the specified memory and put
-* into a buffer descriptor list as empty buffer descriptors. This function must
-* be called before non-empty buffer descriptors may be put into the DMA channel
-* to request scatter gather operations.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* MemoryPtr contains a pointer to the memory which is to be used for buffer
-* descriptors and must not be cached.
-*
-* ByteCount contains the number of bytes for the specified memory to be used
-* for buffer descriptors.
-*
-* RETURN VALUE:
-*
-* A status contains XST_SUCCESS if the scatter gather list was successfully
-* created.
-*
-* A value of XST_DMA_SG_LIST_EXISTS indicates that the scatter gather list
-* was not created because the list has already been created.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_CreateSgList(XDmaChannel * InstancePtr,
- u32 * MemoryPtr, u32 ByteCount)
-{
- XBufDescriptor *BufferDescriptorPtr = (XBufDescriptor *) MemoryPtr;
- XBufDescriptor *PreviousDescriptorPtr = NULL;
- XBufDescriptor *StartOfListPtr = BufferDescriptorPtr;
- u32 UsedByteCount;
-
- /* assert to verify valid input arguments, alignment for those
- * arguments that have alignment restrictions, and at least enough
- * memory for one buffer descriptor
- */
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(MemoryPtr != NULL);
- XASSERT_NONVOID(((u32) MemoryPtr & 3) == 0);
- XASSERT_NONVOID(ByteCount != 0);
- XASSERT_NONVOID(ByteCount >= sizeof (XBufDescriptor));
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if the scatter gather list has already been created, then return
- * with a status
- */
- if (InstancePtr->TotalDescriptorCount != 0) {
- return XST_DMA_SG_LIST_EXISTS;
- }
-
- /* loop thru the specified memory block and create as many buffer
- * descriptors as possible putting each into the list which is
- * implemented as a ring buffer, make sure not to use any memory which
- * is not large enough for a complete buffer descriptor
- */
- UsedByteCount = 0;
- while ((UsedByteCount + sizeof (XBufDescriptor)) <= ByteCount) {
- /* setup a pointer to the next buffer descriptor in the memory and
- * update # of used bytes to know when all of memory is used
- */
- BufferDescriptorPtr = (XBufDescriptor *) ((u32) MemoryPtr +
- UsedByteCount);
-
- /* initialize the new buffer descriptor such that it doesn't contain
- * garbage which could be used by the DMA hardware
- */
- XBufDescriptor_Initialize(BufferDescriptorPtr);
-
- /* if this is not the first buffer descriptor to be created,
- * then link it to the last created buffer descriptor
- */
- if (PreviousDescriptorPtr != NULL) {
- XBufDescriptor_SetNextPtr(PreviousDescriptorPtr,
- BufferDescriptorPtr);
- }
-
- /* always keep a pointer to the last created buffer descriptor such
- * that they can be linked together in the ring buffer
- */
- PreviousDescriptorPtr = BufferDescriptorPtr;
-
- /* keep a count of the number of descriptors in the list to allow
- * error processing to be performed
- */
- InstancePtr->TotalDescriptorCount++;
-
- UsedByteCount += sizeof (XBufDescriptor);
- }
-
- /* connect the last buffer descriptor created and inserted in the list
- * to the first such that a ring buffer is created
- */
- XBufDescriptor_SetNextPtr(BufferDescriptorPtr, StartOfListPtr);
-
- /* initialize the ring buffer to indicate that there are no
- * buffer descriptors in the list which point to valid data buffers
- */
- InstancePtr->PutPtr = BufferDescriptorPtr;
- InstancePtr->GetPtr = BufferDescriptorPtr;
- InstancePtr->CommitPtr = NULL;
- InstancePtr->LastPtr = BufferDescriptorPtr;
- InstancePtr->ActiveDescriptorCount = 0;
-
- /* indicate the scatter gather list was successfully created */
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_IsSgListEmpty
-*
-* DESCRIPTION:
-*
-* This function determines if the scatter gather list of a DMA channel is
-* empty with regard to buffer descriptors which are pointing to buffers to be
-* used for scatter gather operations.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* A value of TRUE if the scatter gather list is empty, otherwise a value of
-* FALSE.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_IsSgListEmpty(XDmaChannel * InstancePtr)
-{
- /* assert to verify valid input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if the number of descriptors which are being used in the list is zero
- * then the list is empty
- */
- return (InstancePtr->ActiveDescriptorCount == 0);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_PutDescriptor
-*
-* DESCRIPTION:
-*
-* This function puts a buffer descriptor into the DMA channel scatter
-* gather list. A DMA channel maintains a list of buffer descriptors which are
-* to be processed. This function puts the specified buffer descriptor
-* at the next location in the list. Note that since the list is already intact,
-* the information in the parameter is copied into the list (rather than modify
-* list pointers on the fly).
-*
-* After buffer descriptors are put into the list, they must also be committed
-* by calling another function. This allows multiple buffer descriptors which
-* span a single packet to be put into the list while preventing the hardware
-* from starting the first buffer descriptor of the packet.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* BufferDescriptorPtr is a pointer to the buffer descriptor to be put into
-* the next available location of the scatter gather list.
-*
-* RETURN VALUE:
-*
-* A status which indicates XST_SUCCESS if the buffer descriptor was
-* successfully put into the scatter gather list.
-*
-* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
-* been created.
-*
-* A value of XST_DMA_SG_LIST_FULL indicates the buffer descriptor was not
-* put into the list because the list was full.
-*
-* A value of XST_DMA_SG_BD_LOCKED indicates the buffer descriptor was not
-* put into the list because the buffer descriptor in the list which is to
-* be overwritten was locked. A locked buffer descriptor indicates the higher
-* layered software is still using the buffer descriptor.
-*
-* NOTES:
-*
-* It is necessary to create a scatter gather list for a DMA channel before
-* putting buffer descriptors into it.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_PutDescriptor(XDmaChannel * InstancePtr,
- XBufDescriptor * BufferDescriptorPtr)
-{
- u32 Control;
-
- /* assert to verify valid input arguments and alignment for those
- * arguments that have alignment restrictions
- */
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufferDescriptorPtr != NULL);
- XASSERT_NONVOID(((u32) BufferDescriptorPtr & 3) == 0);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if a scatter gather list has not been created yet, return a status */
-
- if (InstancePtr->TotalDescriptorCount == 0) {
- return XST_DMA_SG_NO_LIST;
- }
-
- /* if the list is full because all descriptors are pointing to valid
- * buffers, then indicate an error, this code assumes no list or an
- * empty list is detected above
- */
- if (InstancePtr->ActiveDescriptorCount ==
- InstancePtr->TotalDescriptorCount) {
- return XST_DMA_SG_LIST_FULL;
- }
-
- /* if the buffer descriptor in the list which is to be overwritten is
- * locked, then don't overwrite it and return a status
- */
- if (XBufDescriptor_IsLocked(InstancePtr->PutPtr)) {
- return XST_DMA_SG_BD_LOCKED;
- }
-
- /* set the scatter gather stop bit in the control word of the descriptor
- * to cause the h/w to stop after it processes this descriptor since it
- * will be the last in the list
- */
- Control = XBufDescriptor_GetControl(BufferDescriptorPtr);
- XBufDescriptor_SetControl(BufferDescriptorPtr,
- Control | XDC_DMACR_SG_DISABLE_MASK);
-
- /* set both statuses in the descriptor so we tell if they are updated with
- * the status of the transfer, the hardware should change the busy in the
- * DMA status to be false when it completes
- */
- XBufDescriptor_SetStatus(BufferDescriptorPtr, XDC_DMASR_BUSY_MASK);
- XBufDescriptor_SetDeviceStatus(BufferDescriptorPtr, 0);
-
- /* copy the descriptor into the next position in the list so it's ready to
- * be used by the h/w, this assumes the descriptor in the list prior to this
- * one still has the stop bit in the control word set such that the h/w
- * use this one yet
- */
- CopyBufferDescriptor(BufferDescriptorPtr, InstancePtr->PutPtr);
-
- /* only the last in the list and the one to be committed have scatter gather
- * disabled in the control word, a commit requires only one descriptor
- * to be changed, when # of descriptors to commit > 2 all others except the
- * 1st and last have scatter gather enabled
- */
- if ((InstancePtr->CommitPtr != InstancePtr->LastPtr) &&
- (InstancePtr->CommitPtr != NULL)) {
- Control = XBufDescriptor_GetControl(InstancePtr->LastPtr);
- XBufDescriptor_SetControl(InstancePtr->LastPtr,
- Control & ~XDC_DMACR_SG_DISABLE_MASK);
- }
-
- /* update the list data based upon putting a descriptor into the list,
- * these operations must be last
- */
- InstancePtr->ActiveDescriptorCount++;
-
- /* only update the commit pointer if it is not already active, this allows
- * it to be deactivated after every commit such that a single descriptor
- * which is committed does not appear to be waiting to be committed
- */
- if (InstancePtr->CommitPtr == NULL) {
- InstancePtr->CommitPtr = InstancePtr->LastPtr;
- }
-
- /* these updates MUST BE LAST after the commit pointer update in order for
- * the commit pointer to track the correct descriptor to be committed
- */
- InstancePtr->LastPtr = InstancePtr->PutPtr;
- InstancePtr->PutPtr = XBufDescriptor_GetNextPtr(InstancePtr->PutPtr);
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_CommitPuts
-*
-* DESCRIPTION:
-*
-* This function commits the buffer descriptors which have been put into the
-* scatter list for the DMA channel since the last commit operation was
-* performed. This enables the calling functions to put several buffer
-* descriptors into the list (e.g.,a packet's worth) before allowing the scatter
-* gather operations to start. This prevents the DMA channel hardware from
-* starting to use the buffer descriptors in the list before they are ready
-* to be used (multiple buffer descriptors for a single packet).
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* A status indicating XST_SUCCESS if the buffer descriptors of the list were
-* successfully committed.
-*
-* A value of XST_DMA_SG_NOTHING_TO_COMMIT indicates that the buffer descriptors
-* were not committed because there was nothing to commit in the list. All the
-* buffer descriptors which are in the list are commited.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_CommitPuts(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if the buffer descriptor to be committed is already committed or
- * the list is empty (none have been put in), then indicate an error
- */
- if ((InstancePtr->CommitPtr == NULL) ||
- XDmaChannel_IsSgListEmpty(InstancePtr)) {
- return XST_DMA_SG_NOTHING_TO_COMMIT;
- }
-
- /* last descriptor in the list must have scatter gather disabled so the end
- * of the list is hit by h/w, if descriptor to commit is not last in list,
- * commit descriptors by enabling scatter gather in the descriptor
- */
- if (InstancePtr->CommitPtr != InstancePtr->LastPtr) {
- u32 Control;
-
- Control = XBufDescriptor_GetControl(InstancePtr->CommitPtr);
- XBufDescriptor_SetControl(InstancePtr->CommitPtr, Control &
- ~XDC_DMACR_SG_DISABLE_MASK);
- }
- /* Update the commit pointer to indicate that there is nothing to be
- * committed, this state is used by start processing to know that the
- * buffer descriptor to start is not waiting to be committed
- */
- InstancePtr->CommitPtr = NULL;
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetDescriptor
-*
-* DESCRIPTION:
-*
-* This function gets a buffer descriptor from the scatter gather list of the
-* DMA channel. The buffer descriptor is retrieved from the scatter gather list
-* and the scatter gather list is updated to not include the retrieved buffer
-* descriptor. This is typically done after a scatter gather operation
-* completes indicating that a data buffer has been successfully sent or data
-* has been received into the data buffer. The purpose of this function is to
-* allow the device using the scatter gather operation to get the results of the
-* operation.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* BufDescriptorPtr is a pointer to a pointer to the buffer descriptor which
-* was retrieved from the list. The buffer descriptor is not really removed
-* from the list, but it is changed to a state such that the hardware will not
-* use it again until it is put into the scatter gather list of the DMA channel.
-*
-* RETURN VALUE:
-*
-* A status indicating XST_SUCCESS if a buffer descriptor was retrieved from
-* the scatter gather list of the DMA channel.
-*
-* A value of XST_DMA_SG_NO_LIST indicates the scatter gather list has not
-* been created.
-*
-* A value of XST_DMA_SG_LIST_EMPTY indicates no buffer descriptor was
-* retrieved from the list because there are no buffer descriptors to be
-* processed in the list.
-*
-* BufDescriptorPtr is updated to point to the buffer descriptor which was
-* retrieved from the list if the status indicates success.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_GetDescriptor(XDmaChannel * InstancePtr,
- XBufDescriptor ** BufDescriptorPtr)
-{
- u32 Control;
-
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufDescriptorPtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if a scatter gather list has not been created yet, return a status */
-
- if (InstancePtr->TotalDescriptorCount == 0) {
- return XST_DMA_SG_NO_LIST;
- }
-
- /* if the buffer descriptor list is empty, then indicate an error */
-
- if (XDmaChannel_IsSgListEmpty(InstancePtr)) {
- return XST_DMA_SG_LIST_EMPTY;
- }
-
- /* retrieve the next buffer descriptor which is ready to be processed from
- * the buffer descriptor list for the DMA channel, set the control word
- * such that hardware will stop after the descriptor has been processed
- */
- Control = XBufDescriptor_GetControl(InstancePtr->GetPtr);
- XBufDescriptor_SetControl(InstancePtr->GetPtr,
- Control | XDC_DMACR_SG_DISABLE_MASK);
-
- /* set the input argument, which is also an output, to point to the
- * buffer descriptor which is to be retrieved from the list
- */
- *BufDescriptorPtr = InstancePtr->GetPtr;
-
- /* update the pointer of the DMA channel to reflect the buffer descriptor
- * was retrieved from the list by setting it to the next buffer descriptor
- * in the list and indicate one less descriptor in the list now
- */
- InstancePtr->GetPtr = XBufDescriptor_GetNextPtr(InstancePtr->GetPtr);
- InstancePtr->ActiveDescriptorCount--;
-
- return XST_SUCCESS;
-}
-
-/*********************** Interrupt Collescing Functions **********************/
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetPktCount
-*
-* DESCRIPTION:
-*
-* This function returns the value of the unserviced packet count register of
-* the DMA channel. This count represents the number of packets that have been
-* sent or received by the hardware, but not processed by software.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* The unserviced packet counter register contents for the DMA channel.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetPktCount(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the unserviced packet count from the register and return it */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_DecrementPktCount
-*
-* DESCRIPTION:
-*
-* This function decrements the value of the unserviced packet count register.
-* This informs the hardware that the software has processed a packet. The
-* unserviced packet count register may only be decremented by one in the
-* hardware.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_DecrementPktCount(XDmaChannel * InstancePtr)
-{
- u32 Register;
-
- /* assert to verify input arguments */
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* if the unserviced packet count register can be decremented (rather
- * than rolling over) decrement it by writing a 1 to the register,
- * this is the only valid write to the register as it serves as an
- * acknowledge that a packet was handled by the software
- */
- Register = XIo_In32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET);
- if (Register > 0) {
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_UPC_REG_OFFSET,
- 1UL);
- }
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetPktThreshold
-*
-* DESCRIPTION:
-*
-* This function sets the value of the packet count threshold register of the
-* DMA channel. It reflects the number of packets that must be sent or
-* received before generating an interrupt. This value helps implement
-* a concept called "interrupt coalescing", which is used to reduce the number
-* of interrupts from devices with high data rates.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* Threshold is the value that is written to the threshold register of the
-* DMA channel.
-*
-* RETURN VALUE:
-*
-* A status containing XST_SUCCESS if the packet count threshold was
-* successfully set.
-*
-* NOTES:
-*
-* The packet threshold could be set to larger than the number of descriptors
-* allocated to the DMA channel. In this case, the wait bound will take over
-* and always indicate data arrival. There was a check in this function that
-* returned an error if the treshold was larger than the number of descriptors,
-* but that was removed because users would then have to set the threshold
-* only after they set descriptor space, which is an order dependency that
-* caused confustion.
-*
-******************************************************************************/
-XStatus
-XDmaChannel_SetPktThreshold(XDmaChannel * InstancePtr, u8 Threshold)
-{
- /* assert to verify input arguments, don't assert the threshold since
- * it's range is unknown
- */
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* set the packet count threshold in the register such that an interrupt
- * may be generated, if enabled, when the packet count threshold is
- * reached or exceeded
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET,
- (u32) Threshold);
-
- /* indicate the packet count threshold was successfully set */
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetPktThreshold
-*
-* DESCRIPTION:
-*
-* This function gets the value of the packet count threshold register of the
-* DMA channel. This value reflects the number of packets that must be sent or
-* received before generating an interrupt. This value helps implement a concept
-* called "interrupt coalescing", which is used to reduce the number of
-* interrupts from devices with high data rates.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* The packet threshold register contents for the DMA channel and is a value in
-* the range 0 - 1023. A value of 0 indicates the packet wait bound timer is
-* disabled.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u8
-XDmaChannel_GetPktThreshold(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the packet count threshold from the register and return it,
- * since only 8 bits are used, cast it to return only those bits */
-
- return (u8) XIo_In32(InstancePtr->RegBaseAddress + XDC_PCT_REG_OFFSET);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_SetPktWaitBound
-*
-* DESCRIPTION:
-*
-* This function sets the value of the packet wait bound register of the
-* DMA channel. This value reflects the timer value used to trigger an
-* interrupt when not enough packets have been received to reach the packet
-* count threshold.
-*
-* The timer is in millisecond units with +/- 33% accuracy.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* WaitBound is the value, in milliseconds, to be stored in the wait bound
-* register of the DMA channel and is a value in the range 0 - 1023. A value
-* of 0 disables the packet wait bound timer.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-void
-XDmaChannel_SetPktWaitBound(XDmaChannel * InstancePtr, u32 WaitBound)
-{
- /* assert to verify input arguments */
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(WaitBound < 1024);
- XASSERT_VOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* set the packet wait bound in the register such that interrupt may be
- * generated, if enabled, when packets have not been handled for a specific
- * amount of time
- */
- XIo_Out32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET, WaitBound);
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XDmaChannel_GetPktWaitBound
-*
-* DESCRIPTION:
-*
-* This function gets the value of the packet wait bound register of the
-* DMA channel. This value contains the timer value used to trigger an
-* interrupt when not enough packets have been received to reach the packet
-* count threshold.
-*
-* The timer is in millisecond units with +/- 33% accuracy.
-*
-* ARGUMENTS:
-*
-* InstancePtr contains a pointer to the DMA channel to operate on. The DMA
-* channel should be configured to use scatter gather in order for this function
-* to be called.
-*
-* RETURN VALUE:
-*
-* The packet wait bound register contents for the DMA channel.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-u32
-XDmaChannel_GetPktWaitBound(XDmaChannel * InstancePtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the packet wait bound from the register and return it */
-
- return XIo_In32(InstancePtr->RegBaseAddress + XDC_PWB_REG_OFFSET);
-}
diff --git a/board/xilinx/common/xio.h b/board/xilinx/common/xio.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * xio.h
- *
- * Defines XIo functions for Xilinx OCP in terms of Linux primitives
- *
- * Author: MontaVista Software, Inc.
- * source@mvista.com
- *
- * Copyright 2002 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
- * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef XIO_H
-#define XIO_H
-
-#include "xbasic_types.h"
-#include <asm/io.h>
-
-typedef u32 XIo_Address;
-
-extern inline u8
-XIo_In8(XIo_Address InAddress)
-{
- return (u8) in_8((volatile unsigned char *) InAddress);
-}
-extern inline u16
-XIo_In16(XIo_Address InAddress)
-{
- return (u16) in_be16((volatile unsigned short *) InAddress);
-}
-extern inline u32
-XIo_In32(XIo_Address InAddress)
-{
- return (u32) in_be32((volatile unsigned *) InAddress);
-}
-extern inline void
-XIo_Out8(XIo_Address OutAddress, u8 Value)
-{
- out_8((volatile unsigned char *) OutAddress, Value);
-}
-extern inline void
-XIo_Out16(XIo_Address OutAddress, u16 Value)
-{
- out_be16((volatile unsigned short *) OutAddress, Value);
-}
-extern inline void
-XIo_Out32(XIo_Address OutAddress, u32 Value)
-{
- out_be32((volatile unsigned *) OutAddress, Value);
-}
-
-#define XIo_ToLittleEndian16(s,d) (*(u16*)(d) = cpu_to_le16((u16)(s)))
-#define XIo_ToLittleEndian32(s,d) (*(u32*)(d) = cpu_to_le32((u32)(s)))
-#define XIo_ToBigEndian16(s,d) (*(u16*)(d) = cpu_to_be16((u16)(s)))
-#define XIo_ToBigEndian32(s,d) (*(u32*)(d) = cpu_to_be32((u32)(s)))
-
-#define XIo_FromLittleEndian16(s,d) (*(u16*)(d) = le16_to_cpu((u16)(s)))
-#define XIo_FromLittleEndian32(s,d) (*(u32*)(d) = le32_to_cpu((u32)(s)))
-#define XIo_FromBigEndian16(s,d) (*(u16*)(d) = be16_to_cpu((u16)(s)))
-#define XIo_FromBigEndian32(s,d) (*(u32*)(d) = be32_to_cpu((u32)(s)))
-
-#endif /* XIO_H */
diff --git a/board/xilinx/common/xipif_v1_23_b.c b/board/xilinx/common/xipif_v1_23_b.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/* $Id: xipif_v1_23_b.c,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
-/******************************************************************************
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE.
-*
-* (c) Copyright 2002 Xilinx Inc.
-* All rights reserved.
-*
-******************************************************************************/
-/******************************************************************************
-*
-* FILENAME:
-*
-* xipif.c
-*
-* DESCRIPTION:
-*
-* This file contains the implementation of the XIpIf component. The
-* XIpIf component encapsulates the IPIF, which is the standard interface
-* that IP must adhere to when connecting to a bus. The purpose of this
-* component is to encapsulate the IPIF processing such that maintainability
-* is increased. This component does not provide a lot of abstraction from
-* from the details of the IPIF as it is considered a building block for
-* device drivers. A device driver designer must be familiar with the
-* details of the IPIF hardware to use this component.
-*
-* The IPIF hardware provides a building block for all hardware devices such
-* that each device does not need to reimplement these building blocks. The
-* IPIF contains other building blocks, such as FIFOs and DMA channels, which
-* are also common to many devices. These blocks are implemented as separate
-* hardware blocks and instantiated within the IPIF. The primary hardware of
-* the IPIF which is implemented by this software component is the interrupt
-* architecture. Since there are many blocks of a device which may generate
-* interrupts, all the interrupt processing is contained in the common part
-* of the device, the IPIF. This interrupt processing is for the device level
-* only and does not include any processing for the interrupt controller.
-*
-* A device is a mechanism such as an Ethernet MAC. The device is made
-* up of several parts which include an IPIF and the IP. The IPIF contains most
-* of the device infrastructure which is common to all devices, such as
-* interrupt processing, DMA channels, and FIFOs. The infrastructure may also
-* be referred to as IPIF internal blocks since they are part of the IPIF and
-* are separate blocks that can be selected based upon the needs of the device.
-* The IP of the device is the logic that is unique to the device and interfaces
-* to the IPIF of the device.
-*
-* In general, there are two levels of registers within the IPIF. The first
-* level, referred to as the device level, contains registers which are for the
-* entire device. The second level, referred to as the IP level, contains
-* registers which are specific to the IP of the device. The two levels of
-* registers are designed to be hierarchical such that the device level is
-* is a more general register set above the more specific registers of the IP.
-* The IP level of registers provides functionality which is typically common
-* across all devices and allows IP designers to focus on the unique aspects
-* of the IP.
-*
-* The interrupt registers of the IPIF are parameterizable such that the only
-* the number of bits necessary for the device are implemented. The functions
-* of this component do not attempt to validate that the passed in arguments are
-* valid based upon the number of implemented bits. This is necessary to
-* maintain the level of performance required for the common components. Bits
-* of the registers are assigned starting at the least significant bit of the
-* registers.
-*
-* Critical Sections
-*
-* It is the responsibility of the device driver designer to use critical
-* sections as necessary when calling functions of the IPIF. This component
-* does not use critical sections and it does access registers using
-* read-modify-write operations. Calls to IPIF functions from a main thread
-* and from an interrupt context could produce unpredictable behavior such that
-* the caller must provide the appropriate critical sections.
-*
-* Mutual Exclusion
-*
-* The functions of the IPIF are not thread safe such that the caller of all
-* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual
-* exclusion across multiple IPIF components is not necessary.
-*
-* NOTES:
-*
-* None.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.23b jhl 02/27/01 Repartioned to reduce size
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xipif_v1_23_b.h"
-#include "xio.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constant is used to generate bit masks for register testing
- * in the self test functions, it defines the starting bit mask that is to be
- * shifted from the LSB to MSB in creating a register test mask
- */
-#define XIIF_V123B_FIRST_BIT_MASK 1UL
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Variable Definitions *****************************/
-
-/************************** Function Prototypes ******************************/
-
-static XStatus IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth);
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* XIpIf_SelfTest
-*
-* DESCRIPTION:
-*
-* This function performs a self test on the specified IPIF component. Many
-* of the registers in the IPIF are tested to ensure proper operation. This
-* function is destructive because the IPIF is reset at the start of the test
-* and at the end of the test to ensure predictable results. The IPIF reset
-* also resets the entire device that uses the IPIF. This function exits with
-* all interrupts for the device disabled.
-*
-* ARGUMENTS:
-*
-* InstancePtr points to the XIpIf to operate on.
-*
-* DeviceRegistersWidth contains the number of bits in the device interrupt
-* registers. The hardware is parameterizable such that only the number of bits
-* necessary to support a device are implemented. This value must be between 0
-* and 32 with 0 indicating there are no device interrupt registers used.
-*
-* IpRegistersWidth contains the number of bits in the IP interrupt registers
-* of the device. The hardware is parameterizable such that only the number of
-* bits necessary to support a device are implemented. This value must be
-* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
-*
-* RETURN VALUE:
-*
-* A value of XST_SUCCESS indicates the test was successful with no errors.
-* Any one of the following error values may also be returned.
-*
-* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
-* not valid
-* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
-* register did not read back correctly
-* XST_IPIF_IP_ACK_ERROR One or more bits in the IP interrupt
-* status register did not reset when acked
-* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
-* did not read back correctly based upon
-* what was written to it
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-
-/* the following constant defines the maximum number of bits which may be
- * used in the registers at the device and IP levels, this is based upon the
- * number of bits available in the registers
- */
-#define XIIF_V123B_MAX_REG_BIT_COUNT 32
-
-XStatus
-XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth)
-{
- XStatus Status;
-
- /* assert to verify arguments are valid */
-
- XASSERT_NONVOID(IpRegistersWidth <= XIIF_V123B_MAX_REG_BIT_COUNT);
-
- /* reset the IPIF such that it's in a known state before the test
- * and interrupts are globally disabled
- */
- XIIF_V123B_RESET(RegBaseAddress);
-
- /* perform the self test on the IP interrupt registers, if
- * it is not successful exit with the status
- */
- Status = IpIntrSelfTest(RegBaseAddress, IpRegistersWidth);
- if (Status != XST_SUCCESS) {
- return Status;
- }
-
- /* reset the IPIF such that it's in a known state before exiting test */
-
- XIIF_V123B_RESET(RegBaseAddress);
-
- /* reaching this point means there were no errors, return success */
-
- return XST_SUCCESS;
-}
-
-/******************************************************************************
-*
-* FUNCTION:
-*
-* IpIntrSelfTest
-*
-* DESCRIPTION:
-*
-* Perform a self test on the IP interrupt registers of the IPIF. This
-* function modifies registers of the IPIF such that they are not guaranteed
-* to be in the same state when it returns. Any bits in the IP interrupt
-* status register which are set are assumed to be set by default after a reset
-* and are not tested in the test.
-*
-* ARGUMENTS:
-*
-* InstancePtr points to the XIpIf to operate on.
-*
-* IpRegistersWidth contains the number of bits in the IP interrupt registers
-* of the device. The hardware is parameterizable such that only the number of
-* bits necessary to support a device are implemented. This value must be
-* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
-*
-* RETURN VALUE:
-*
-* A status indicating XST_SUCCESS if the test was successful. Otherwise, one
-* of the following values is returned.
-*
-* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
-* not valid
-* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
-* register did not read back correctly
-* XST_IPIF_IP_ACK_ERROR One or more bits in the IP status
-* register did not reset when acked
-* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
-* did not read back correctly based upon
-* what was written to it
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-static XStatus
-IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth)
-{
- /* ensure that the IP interrupt interrupt enable register is zero
- * as it should be at reset, the interrupt status is dependent upon the
- * IP such that it's reset value is not known
- */
- if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
- return XST_IPIF_RESET_REGISTER_ERROR;
- }
-
- /* if there are any used IP interrupts, then test all of the interrupt
- * bits in all testable registers
- */
- if (IpRegistersWidth > 0) {
- u32 BitCount;
- u32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK;
- u32 Mask = XIIF_V123B_FIRST_BIT_MASK; /* bits assigned MSB to LSB */
- u32 InterruptStatus;
-
- /* generate the register masks to be used for IP register tests, the
- * number of bits supported by the hardware is parameterizable such
- * that only that number of bits are implemented in the registers, the
- * bits are allocated starting at the MSB of the registers
- */
- for (BitCount = 1; BitCount < IpRegistersWidth; BitCount++) {
- Mask = Mask << 1;
- IpInterruptMask |= Mask;
- }
-
- /* get the current IP interrupt status register contents, any bits
- * already set must default to 1 at reset in the device and these
- * bits can't be tested in the following test, remove these bits from
- * the mask that was generated for the test
- */
- InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
- IpInterruptMask &= ~InterruptStatus;
-
- /* set the bits in the device status register and verify them by reading
- * the register again, all bits of the register are latched
- */
- XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
- InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
- if ((InterruptStatus & IpInterruptMask) != IpInterruptMask)
- {
- return XST_IPIF_IP_STATUS_ERROR;
- }
-
- /* test to ensure that the bits set in the IP interrupt status register
- * can be cleared by acknowledging them in the IP interrupt status
- * register then read it again and verify it was cleared
- */
- XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
- InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
- if ((InterruptStatus & IpInterruptMask) != 0) {
- return XST_IPIF_IP_ACK_ERROR;
- }
-
- /* set the IP interrupt enable set register and then read the IP
- * interrupt enable register and verify the interrupts were enabled
- */
- XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask);
- if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask) {
- return XST_IPIF_IP_ENABLE_ERROR;
- }
-
- /* clear the IP interrupt enable register and then read the
- * IP interrupt enable register and verify the interrupts were disabled
- */
- XIIF_V123B_WRITE_IIER(RegBaseAddress, 0);
- if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
- return XST_IPIF_IP_ENABLE_ERROR;
- }
- }
- return XST_SUCCESS;
-}
diff --git a/board/xilinx/common/xipif_v1_23_b.h b/board/xilinx/common/xipif_v1_23_b.h
+++ /dev/null
@@ -1,746 +0,0 @@
-/* $Id: xipif_v1_23_b.h,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
-/******************************************************************************
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE.
-*
-* (c) Copyright 2002 Xilinx Inc.
-* All rights reserved.
-*
-******************************************************************************/
-/******************************************************************************
-*
-* FILENAME:
-*
-* xipif.h
-*
-* DESCRIPTION:
-*
-* The XIpIf component encapsulates the IPIF, which is the standard interface
-* that IP must adhere to when connecting to a bus. The purpose of this
-* component is to encapsulate the IPIF processing such that maintainability
-* is increased. This component does not provide a lot of abstraction from
-* from the details of the IPIF as it is considered a building block for
-* device drivers. A device driver designer must be familiar with the
-* details of the IPIF hardware to use this component.
-*
-* The IPIF hardware provides a building block for all hardware devices such
-* that each device does not need to reimplement these building blocks. The
-* IPIF contains other building blocks, such as FIFOs and DMA channels, which
-* are also common to many devices. These blocks are implemented as separate
-* hardware blocks and instantiated within the IPIF. The primary hardware of
-* the IPIF which is implemented by this software component is the interrupt
-* architecture. Since there are many blocks of a device which may generate
-* interrupts, all the interrupt processing is contained in the common part
-* of the device, the IPIF. This interrupt processing is for the device level
-* only and does not include any processing for the interrupt controller.
-*
-* A device is a mechanism such as an Ethernet MAC. The device is made
-* up of several parts which include an IPIF and the IP. The IPIF contains most
-* of the device infrastructure which is common to all devices, such as
-* interrupt processing, DMA channels, and FIFOs. The infrastructure may also
-* be referred to as IPIF internal blocks since they are part of the IPIF and
-* are separate blocks that can be selected based upon the needs of the device.
-* The IP of the device is the logic that is unique to the device and interfaces
-* to the IPIF of the device.
-*
-* In general, there are two levels of registers within the IPIF. The first
-* level, referred to as the device level, contains registers which are for the
-* entire device. The second level, referred to as the IP level, contains
-* registers which are specific to the IP of the device. The two levels of
-* registers are designed to be hierarchical such that the device level is
-* is a more general register set above the more specific registers of the IP.
-* The IP level of registers provides functionality which is typically common
-* across all devices and allows IP designers to focus on the unique aspects
-* of the IP.
-*
-* Critical Sections
-*
-* It is the responsibility of the device driver designer to use critical
-* sections as necessary when calling functions of the IPIF. This component
-* does not use critical sections and it does access registers using
-* read-modify-write operations. Calls to IPIF functions from a main thread
-* and from an interrupt context could produce unpredictable behavior such that
-* the caller must provide the appropriate critical sections.
-*
-* Mutual Exclusion
-*
-* The functions of the IPIF are not thread safe such that the caller of all
-* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual
-* exclusion across multiple IPIF components is not necessary.
-*
-* NOTES:
-*
-* None.
-*
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.23b jhl 02/27/01 Repartioned to minimize size
-*
-******************************************************************************/
-
-#ifndef XIPIF_H /* prevent circular inclusions */
-#define XIPIF_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-#include "xbasic_types.h"
-#include "xstatus.h"
-#include "xversion.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constants define the register offsets for the registers of the
- * IPIF, there are some holes in the memory map for reserved addresses to allow
- * other registers to be added and still match the memory map of the interrupt
- * controller registers
- */
-#define XIIF_V123B_DISR_OFFSET 0UL /* device interrupt status register */
-#define XIIF_V123B_DIPR_OFFSET 4UL /* device interrupt pending register */
-#define XIIF_V123B_DIER_OFFSET 8UL /* device interrupt enable register */
-#define XIIF_V123B_DIIR_OFFSET 24UL /* device interrupt ID register */
-#define XIIF_V123B_DGIER_OFFSET 28UL /* device global interrupt enable reg */
-#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
-#define XIIF_V123B_IIER_OFFSET 40UL /* IP interrupt enable register */
-#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
-
-#define XIIF_V123B_RESET_MASK 0xAUL
-
-/* the following constant is used for the device global interrupt enable
- * register, to enable all interrupts for the device, this is the only bit
- * in the register
- */
-#define XIIF_V123B_GINTR_ENABLE_MASK 0x80000000UL
-
-/* the following constants contain the masks to identify each internal IPIF
- * condition in the device registers of the IPIF, interrupts are assigned
- * in the register from LSB to the MSB
- */
-#define XIIF_V123B_ERROR_MASK 1UL /* LSB of the register */
-
-/* The following constants contain interrupt IDs which identify each internal
- * IPIF condition, this value must correlate with the mask constant for the
- * error
- */
-#define XIIF_V123B_ERROR_INTERRUPT_ID 0 /* interrupt bit #, (LSB = 0) */
-#define XIIF_V123B_NO_INTERRUPT_ID 128 /* no interrupts are pending */
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_RESET
-*
-* DESCRIPTION:
-*
-* Reset the IPIF component and hardware. This is a destructive operation that
-* could cause the loss of data since resetting the IPIF of a device also
-* resets the device using the IPIF and any blocks, such as FIFOs or DMA
-* channels, within the IPIF. All registers of the IPIF will contain their
-* reset value when this function returns.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-
-/* the following constant is used in the reset register to cause the IPIF to
- * reset
- */
-#define XIIF_V123B_RESET(RegBaseAddress) \
- XIo_Out32(RegBaseAddress + XIIF_V123B_RESETR_OFFSET, XIIF_V123B_RESET_MASK)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_DISR
-*
-* DESCRIPTION:
-*
-* This function sets the device interrupt status register to the value.
-* This register indicates the status of interrupt sources for a device
-* which contains the IPIF. The status is independent of whether interrupts
-* are enabled and could be used for polling a device at a higher level rather
-* than a more detailed level.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF. With the exception of some internal IPIF
-* conditions, the contents of this register are not latched but indicate
-* the live status of the interrupt sources within the device. Writing any of
-* the non-latched bits of the register will have no effect on the register.
-*
-* For the latched bits of this register only, setting a bit which is zero
-* within this register causes an interrupt to generated. The device global
-* interrupt enable register and the device interrupt enable register must be set
-* appropriately to allow an interrupt to be passed out of the device. The
-* interrupt is cleared by writing to this register with the bits to be
-* cleared set to a one and all others to zero. This register implements a
-* toggle on write functionality meaning any bits which are set in the value
-* written cause the bits in the register to change to the opposite state.
-*
-* This function writes the specified value to the register such that
-* some bits may be set and others cleared. It is the caller's responsibility
-* to get the value of the register prior to setting the value to prevent a
-* destructive behavior.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Status contains the value to be written to the interrupt status register of
-* the device. The only bits which can be written are the latched bits which
-* contain the internal IPIF conditions. The following values may be used to
-* set the status register or clear an interrupt condition.
-*
-* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_DISR(RegBaseAddress, Status) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET, (Status))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DISR
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt status register contents.
-* This register indicates the status of interrupt sources for a device
-* which contains the IPIF. The status is independent of whether interrupts
-* are enabled and could be used for polling a device at a higher level.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF. With the exception of some internal IPIF
-* conditions, the contents of this register are not latched but indicate
-* the live status of the interrupt sources within the device.
-*
-* For only the latched bits of this register, the interrupt may be cleared by
-* writing to these bits in the status register.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* A status which contains the value read from the interrupt status register of
-* the device. The bit definitions are specific to the device with
-* the exception of the latched internal IPIF condition bits. The following
-* values may be used to detect internal IPIF conditions in the status.
-*
-* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DISR(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_DISR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_DIER
-*
-* DESCRIPTION:
-*
-* This function sets the device interrupt enable register contents.
-* This register controls which interrupt sources of the device are allowed to
-* generate an interrupt. The device global interrupt enable register must also
-* be set appropriately for an interrupt to be passed out of the device.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF. Setting a bit in this register enables that
-* interrupt source to generate an interrupt. Clearing a bit in this register
-* disables interrupt generation for that interrupt source.
-*
-* This function writes only the specified value to the register such that
-* some interrupts source may be enabled and others disabled. It is the
-* caller's responsibility to get the value of the interrupt enable register
-* prior to setting the value to prevent an destructive behavior.
-*
-* An interrupt source may not be enabled to generate an interrupt, but can
-* still be polled in the interrupt status register.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Enable contains the value to be written to the interrupt enable register
-* of the device. The bit definitions are specific to the device with
-* the exception of the internal IPIF conditions. The following
-* values may be used to enable the internal IPIF conditions interrupts.
-*
-* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* Signature: u32 XIIF_V123B_WRITE_DIER(u32 RegBaseAddress,
-* u32 Enable)
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_DIER(RegBaseAddress, Enable) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET, (Enable))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DIER
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt enable register contents.
-* This register controls which interrupt sources of the device
-* are allowed to generate an interrupt. The device global interrupt enable
-* register and the device interrupt enable register must also be set
-* appropriately for an interrupt to be passed out of the device.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device which contains the IPIF. Setting a bit in this register enables that
-* interrupt source to generate an interrupt if the global enable is set
-* appropriately. Clearing a bit in this register disables interrupt generation
-* for that interrupt source regardless of the global interrupt enable.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* The value read from the interrupt enable register of the device. The bit
-* definitions are specific to the device with the exception of the internal
-* IPIF conditions. The following values may be used to determine from the
-* value if the internal IPIF conditions interrupts are enabled.
-*
-* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DIER(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_DIER_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DIPR
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt pending register contents.
-* This register indicates the pending interrupt sources, those that are waiting
-* to be serviced by the software, for a device which contains the IPIF.
-* An interrupt must be enabled in the interrupt enable register of the IPIF to
-* be pending.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* the device which contains the IPIF. With the exception of some internal IPIF
-* conditions, the contents of this register are not latched since the condition
-* is latched in the IP interrupt status register, by an internal block of the
-* IPIF such as a FIFO or DMA channel, or by the IP of the device. This register
-* is read only and is not latched, but it is necessary to acknowledge (clear)
-* the interrupt condition by performing the appropriate processing for the IP
-* or block within the IPIF.
-*
-* This register can be thought of as the contents of the interrupt status
-* register ANDed with the contents of the interrupt enable register.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* The value read from the interrupt pending register of the device. The bit
-* definitions are specific to the device with the exception of the latched
-* internal IPIF condition bits. The following values may be used to detect
-* internal IPIF conditions in the value.
-*
-* XIIF_V123B_ERROR_MASK Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DIPR(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_DIPR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_DIIR
-*
-* DESCRIPTION:
-*
-* This function gets the device interrupt ID for the highest priority interrupt
-* which is pending from the interrupt ID register. This function provides
-* priority resolution such that faster interrupt processing is possible.
-* Without priority resolution, it is necessary for the software to read the
-* interrupt pending register and then check each interrupt source to determine
-* if an interrupt is pending. Priority resolution becomes more important as the
-* number of interrupt sources becomes larger.
-*
-* Interrupt priorities are based upon the bit position of the interrupt in the
-* interrupt pending register with bit 0 being the highest priority. The
-* interrupt ID is the priority of the interrupt, 0 - 31, with 0 being the
-* highest priority. The interrupt ID register is live rather than latched such
-* that multiple calls to this function may not yield the same results. A
-* special value, outside of the interrupt priority range of 0 - 31, is
-* contained in the register which indicates that no interrupt is pending. This
-* may be useful for allowing software to continue processing interrupts in a
-* loop until there are no longer any interrupts pending.
-*
-* The interrupt ID is designed to allow a function pointer table to be used
-* in the software such that the interrupt ID is used as an index into that
-* table. The function pointer table could contain an instance pointer, such
-* as to DMA channel, and a function pointer to the function which handles
-* that interrupt. This design requires the interrupt processing of the device
-* driver to be partitioned into smaller more granular pieces based upon
-* hardware used by the device, such as DMA channels and FIFOs.
-*
-* It is not mandatory that this function be used by the device driver software.
-* It may choose to read the pending register and resolve the pending interrupt
-* priorities on it's own.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* An interrupt ID, 0 - 31, which identifies the highest priority interrupt
-* which is pending. A value of XIIF_NO_INTERRUPT_ID indicates that there is
-* no interrupt pending. The following values may be used to identify the
-* interrupt ID for the internal IPIF interrupts.
-*
-* XIIF_V123B_ERROR_INTERRUPT_ID Indicates a device error in the IPIF
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_DIIR(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_DIIR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_GLOBAL_INTR_DISABLE
-*
-* DESCRIPTION:
-*
-* This function disables all interrupts for the device by writing to the global
-* interrupt enable register. This register provides the ability to disable
-* interrupts without any modifications to the interrupt enable register such
-* that it is minimal effort to restore the interrupts to the previous enabled
-* state. The corresponding function, XIpIf_GlobalIntrEnable, is provided to
-* restore the interrupts to the previous enabled state. This function is
-* designed to be used in critical sections of device drivers such that it is
-* not necessary to disable other device interrupts.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_GINTR_DISABLE(RegBaseAddress) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, 0)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_GINTR_ENABLE
-*
-* DESCRIPTION:
-*
-* This function writes to the global interrupt enable register to enable
-* interrupts from the device. This register provides the ability to enable
-* interrupts without any modifications to the interrupt enable register such
-* that it is minimal effort to restore the interrupts to the previous enabled
-* state. This function does not enable individual interrupts as the interrupt
-* enable register must be set appropriately. This function is designed to be
-* used in critical sections of device drivers such that it is not necessary to
-* disable other device interrupts.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_GINTR_ENABLE(RegBaseAddress) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET, \
- XIIF_V123B_GINTR_ENABLE_MASK)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_IS_GINTR_ENABLED
-*
-* DESCRIPTION:
-*
-* This function determines if interrupts are enabled at the global level by
-* reading the gloabl interrupt register. This register provides the ability to
-* disable interrupts without any modifications to the interrupt enable register
-* such that it is minimal effort to restore the interrupts to the previous
-* enabled state.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_IS_GINTR_ENABLED(RegBaseAddress) \
- (XIo_In32((RegBaseAddress) + XIIF_V123B_DGIER_OFFSET) == \
- XIIF_V123B_GINTR_ENABLE_MASK)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_IISR
-*
-* DESCRIPTION:
-*
-* This function sets the IP interrupt status register to the specified value.
-* This register indicates the status of interrupt sources for the IP of the
-* device. The IP is defined as the part of the device that connects to the
-* IPIF. The status is independent of whether interrupts are enabled such that
-* the status register may also be polled when interrupts are not enabled.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* IP. All bits of this register are latched. Setting a bit which is zero
-* within this register causes an interrupt to be generated. The device global
-* interrupt enable register and the device interrupt enable register must be set
-* appropriately to allow an interrupt to be passed out of the device. The
-* interrupt is cleared by writing to this register with the bits to be
-* cleared set to a one and all others to zero. This register implements a
-* toggle on write functionality meaning any bits which are set in the value
-* written cause the bits in the register to change to the opposite state.
-*
-* This function writes only the specified value to the register such that
-* some status bits may be set and others cleared. It is the caller's
-* responsibility to get the value of the register prior to setting the value
-* to prevent an destructive behavior.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Status contains the value to be written to the IP interrupt status
-* register. The bit definitions are specific to the device IP.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_IISR(RegBaseAddress, Status) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET, (Status))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_IISR
-*
-* DESCRIPTION:
-*
-* This function gets the contents of the IP interrupt status register.
-* This register indicates the status of interrupt sources for the IP of the
-* device. The IP is defined as the part of the device that connects to the
-* IPIF. The status is independent of whether interrupts are enabled such
-* that the status register may also be polled when interrupts are not enabled.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* device. All bits of this register are latched. Writing a 1 to a bit within
-* this register causes an interrupt to be generated if enabled in the interrupt
-* enable register and the global interrupt enable is set. Since the status is
-* latched, each status bit must be acknowledged in order for the bit in the
-* status register to be updated. Each bit can be acknowledged by writing a
-* 0 to the bit in the status register.
-
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* A status which contains the value read from the IP interrupt status register.
-* The bit definitions are specific to the device IP.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_READ_IISR(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_IISR_OFFSET)
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_WRITE_IIER
-*
-* DESCRIPTION:
-*
-* This function sets the IP interrupt enable register contents. This register
-* controls which interrupt sources of the IP are allowed to generate an
-* interrupt. The global interrupt enable register and the device interrupt
-* enable register must also be set appropriately for an interrupt to be
-* passed out of the device containing the IPIF and the IP.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* IP. Setting a bit in this register enables the interrupt source to generate
-* an interrupt. Clearing a bit in this register disables interrupt generation
-* for that interrupt source.
-*
-* This function writes only the specified value to the register such that
-* some interrupt sources may be enabled and others disabled. It is the
-* caller's responsibility to get the value of the interrupt enable register
-* prior to setting the value to prevent an destructive behavior.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* Enable contains the value to be written to the IP interrupt enable register.
-* The bit definitions are specific to the device IP.
-*
-* RETURN VALUE:
-*
-* None.
-*
-* NOTES:
-*
-* None.
-*
-******************************************************************************/
-#define XIIF_V123B_WRITE_IIER(RegBaseAddress, Enable) \
- XIo_Out32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET, (Enable))
-
-/******************************************************************************
-*
-* MACRO:
-*
-* XIIF_V123B_READ_IIER
-*
-* DESCRIPTION:
-*
-*
-* This function gets the IP interrupt enable register contents. This register
-* controls which interrupt sources of the IP are allowed to generate an
-* interrupt. The global interrupt enable register and the device interrupt
-* enable register must also be set appropriately for an interrupt to be
-* passed out of the device containing the IPIF and the IP.
-*
-* Each bit of the register correlates to a specific interrupt source within the
-* IP. Setting a bit in this register enables the interrupt source to generate
-* an interrupt. Clearing a bit in this register disables interrupt generation
-* for that interrupt source.
-*
-* ARGUMENTS:
-*
-* RegBaseAddress contains the base address of the IPIF registers.
-*
-* RETURN VALUE:
-*
-* The contents read from the IP interrupt enable register. The bit definitions
-* are specific to the device IP.
-*
-* NOTES:
-*
-* Signature: u32 XIIF_V123B_READ_IIER(u32 RegBaseAddress)
-*
-******************************************************************************/
-#define XIIF_V123B_READ_IIER(RegBaseAddress) \
- XIo_In32((RegBaseAddress) + XIIF_V123B_IIER_OFFSET)
-
-/************************** Function Prototypes ******************************/
-
-/*
- * Initialization Functions
- */
-XStatus XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth);
-
-#endif /* end of protection macro */
diff --git a/board/xilinx/common/xpacket_fifo_v1_00_b.c b/board/xilinx/common/xpacket_fifo_v1_00_b.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/*
-*
-* @file xpacket_fifo_v1_00_b.c
-*
-* Contains functions for the XPacketFifoV100b component. See xpacket_fifo_v1_00_b.h
-* for more information about the component.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 03/26/02 First release
-* </pre>
-*
-*****************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xio.h"
-#include "xstatus.h"
-#include "xpacket_fifo_v1_00_b.h"
-
-/************************** Constant Definitions *****************************/
-
-/* width of a FIFO word */
-
-#define XPF_FIFO_WIDTH_BYTE_COUNT 4UL
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************* Variable Definitions ******************************/
-
-/************************** Function Prototypes ******************************/
-
-/*****************************************************************************/
-/*
-*
-* This function initializes a packet FIFO. Initialization resets the
-* FIFO such that it's empty and ready to use.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-* @param RegBaseAddress contains the base address of the registers for
-* the packet FIFO.
-* @param DataBaseAddress contains the base address of the data for
-* the packet FIFO.
-*
-* @return
-*
-* Always returns XST_SUCCESS.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
- u32 RegBaseAddress, u32 DataBaseAddress)
-{
- /* assert to verify input argument are valid */
-
- XASSERT_NONVOID(InstancePtr != NULL);
-
- /* initialize the component variables to the specified state */
-
- InstancePtr->RegBaseAddress = RegBaseAddress;
- InstancePtr->DataBaseAddress = DataBaseAddress;
- InstancePtr->IsReady = XCOMPONENT_IS_READY;
-
- /* reset the FIFO such that it's empty and ready to use and indicate the
- * initialization was successful, note that the is ready variable must be
- * set prior to calling the reset function to prevent an assert
- */
- XPF_V100B_RESET(InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-*
-* This function performs a self-test on the specified packet FIFO. The self
-* test resets the FIFO and reads a register to determine if it is the correct
-* reset value. This test is destructive in that any data in the FIFO will
-* be lost.
-*
-* @param InstancePtr is a pointer to the packet FIFO to be operated on.
-*
-* @param FifoType specifies the type of FIFO, read or write, for the self test.
-* The FIFO type is specified by the values XPF_READ_FIFO_TYPE or
-* XPF_WRITE_FIFO_TYPE.
-*
-* @return
-*
-* XST_SUCCESS is returned if the selftest is successful, or
-* XST_PFIFO_BAD_REG_VALUE indicating that the value readback from the
-* occupancy/vacancy count register after a reset does not match the
-* specified reset value.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType)
-{
- u32 Register;
-
- /* assert to verify valid input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID((FifoType == XPF_READ_FIFO_TYPE) ||
- (FifoType == XPF_WRITE_FIFO_TYPE));
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* reset the fifo and then check to make sure the occupancy/vacancy
- * register contents are correct for a reset condition
- */
- XPF_V100B_RESET(InstancePtr);
-
- Register = XIo_In32(InstancePtr->RegBaseAddress +
- XPF_COUNT_STATUS_REG_OFFSET);
-
- /* check the value of the register to ensure that it's correct for the
- * specified FIFO type since both FIFO types reset to empty, but a bit
- * in the register changes definition based upon FIFO type
- */
-
- if (FifoType == XPF_READ_FIFO_TYPE) {
- /* check the regiser value for a read FIFO which should be empty */
-
- if (Register != XPF_EMPTY_FULL_MASK) {
- return XST_PFIFO_BAD_REG_VALUE;
- }
- } else {
- /* check the register value for a write FIFO which should not be full
- * on reset
- */
- if ((Register & XPF_EMPTY_FULL_MASK) != 0) {
- return XST_PFIFO_BAD_REG_VALUE;
- }
- }
-
- /* the test was successful */
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-*
-* Read data from a FIFO and puts it into a specified buffer. The packet FIFO is
-* currently 32 bits wide such that an input buffer which is a series of bytes
-* is filled from the FIFO a word at a time. If the requested byte count is not
-* a multiple of 32 bit words, it is necessary for this function to format the
-* remaining 32 bit word from the FIFO into a series of bytes in the buffer.
-* There may be up to 3 extra bytes which must be extracted from the last word
-* of the FIFO and put into the buffer.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-* @param BufferPtr points to the memory buffer to write the data into. This
-* buffer must be 32 bit aligned or an alignment exception could be
-* generated. Since this buffer is a byte buffer, the data is assumed to
-* be endian independent.
-* @param ByteCount contains the number of bytes to read from the FIFO. This
-* number of bytes must be present in the FIFO or an error will be
-* returned.
-*
-* @return
-*
-* XST_SUCCESS indicates the operation was successful. If the number of
-* bytes specified by the byte count is not present in the FIFO
-* XST_PFIFO_LACK_OF_DATA is returned.
-*
-* If the function was successful, the specified buffer is modified to contain
-* the bytes which were removed from the FIFO.
-*
-* @note
-*
-* Note that the exact number of bytes which are present in the FIFO is
-* not known by this function. It can only check for a number of 32 bit
-* words such that if the byte count specified is incorrect, but is still
-* possible based on the number of words in the FIFO, up to 3 garbage bytes
-* may be present at the end of the buffer.
-* <br><br>
-* This function assumes that if the device consuming data from the FIFO is
-* a byte device, the order of the bytes to be consumed is from the most
-* significant byte to the least significant byte of a 32 bit word removed
-* from the FIFO.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
- u8 * BufferPtr, u32 ByteCount)
-{
- u32 FifoCount;
- u32 WordCount;
- u32 ExtraByteCount;
- u32 *WordBuffer = (u32 *) BufferPtr;
-
- /* assert to verify valid input arguments including 32 bit alignment of
- * the buffer pointer
- */
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufferPtr != NULL);
- XASSERT_NONVOID(((u32) BufferPtr &
- (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0);
- XASSERT_NONVOID(ByteCount != 0);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the count of how many 32 bit words are in the FIFO, if there aren't
- * enought words to satisfy the request, return an error
- */
-
- FifoCount = XIo_In32(InstancePtr->RegBaseAddress +
- XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
-
- if ((FifoCount * XPF_FIFO_WIDTH_BYTE_COUNT) < ByteCount) {
- return XST_PFIFO_LACK_OF_DATA;
- }
-
- /* calculate the number of words to read from the FIFO before the word
- * containing the extra bytes, and calculate the number of extra bytes
- * the extra bytes are defined as those at the end of the buffer when
- * the buffer does not end on a 32 bit boundary
- */
- WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT;
- ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT;
-
- /* Read the 32 bit words from the FIFO for all the buffer except the
- * last word which contains the extra bytes, the following code assumes
- * that the buffer is 32 bit aligned, otherwise an alignment exception could
- * be generated
- */
- for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
- WordBuffer[FifoCount] = XIo_In32(InstancePtr->DataBaseAddress);
- }
-
- /* if there are extra bytes to handle, read the last word from the FIFO
- * and insert the extra bytes into the buffer
- */
- if (ExtraByteCount > 0) {
- u32 LastWord;
- u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
-
- /* get the last word from the FIFO for the extra bytes */
-
- LastWord = XIo_In32(InstancePtr->DataBaseAddress);
-
- /* one extra byte in the last word, put the byte into the next location
- * of the buffer, bytes in a word of the FIFO are ordered from most
- * significant byte to least
- */
- if (ExtraByteCount == 1) {
- ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
- }
-
- /* two extra bytes in the last word, put each byte into the next two
- * locations of the buffer
- */
- else if (ExtraByteCount == 2) {
- ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
- ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
- }
- /* three extra bytes in the last word, put each byte into the next three
- * locations of the buffer
- */
- else if (ExtraByteCount == 3) {
- ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
- ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
- ExtraBytesBuffer[2] = (u8) (LastWord >> 8);
- }
- }
- return XST_SUCCESS;
-}
-
-/*****************************************************************************/
-/*
-*
-* Write data into a packet FIFO. The packet FIFO is currently 32 bits wide
-* such that an input buffer which is a series of bytes must be written into the
-* FIFO a word at a time. If the buffer is not a multiple of 32 bit words, it is
-* necessary for this function to format the remaining bytes into a single 32
-* bit word to be inserted into the FIFO. This is necessary to avoid any
-* accesses past the end of the buffer.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-* @param BufferPtr points to the memory buffer that data is to be read from
-* and written into the FIFO. Since this buffer is a byte buffer, the data
-* is assumed to be endian independent. This buffer must be 32 bit aligned
-* or an alignment exception could be generated.
-* @param ByteCount contains the number of bytes to read from the buffer and to
-* write to the FIFO.
-*
-* @return
-*
-* XST_SUCCESS is returned if the operation succeeded. If there is not enough
-* room in the FIFO to hold the specified bytes, XST_PFIFO_NO_ROOM is
-* returned.
-*
-* @note
-*
-* This function assumes that if the device inserting data into the FIFO is
-* a byte device, the order of the bytes in each 32 bit word is from the most
-* significant byte to the least significant byte.
-*
-******************************************************************************/
-XStatus
-XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
- u8 * BufferPtr, u32 ByteCount)
-{
- u32 FifoCount;
- u32 WordCount;
- u32 ExtraByteCount;
- u32 *WordBuffer = (u32 *) BufferPtr;
-
- /* assert to verify valid input arguments including 32 bit alignment of
- * the buffer pointer
- */
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(BufferPtr != NULL);
- XASSERT_NONVOID(((u32) BufferPtr &
- (XPF_FIFO_WIDTH_BYTE_COUNT - 1)) == 0);
- XASSERT_NONVOID(ByteCount != 0);
- XASSERT_NONVOID(InstancePtr->IsReady == XCOMPONENT_IS_READY);
-
- /* get the count of how many words may be inserted into the FIFO */
-
- FifoCount = XIo_In32(InstancePtr->RegBaseAddress +
- XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
-
- /* Calculate the number of 32 bit words required to insert the specified
- * number of bytes in the FIFO and determine the number of extra bytes
- * if the buffer length is not a multiple of 32 bit words
- */
-
- WordCount = ByteCount / XPF_FIFO_WIDTH_BYTE_COUNT;
- ExtraByteCount = ByteCount % XPF_FIFO_WIDTH_BYTE_COUNT;
-
- /* take into account the extra bytes in the total word count */
-
- if (ExtraByteCount > 0) {
- WordCount++;
- }
-
- /* if there's not enough room in the FIFO to hold the specified
- * number of bytes, then indicate an error,
- */
- if (FifoCount < WordCount) {
- return XST_PFIFO_NO_ROOM;
- }
-
- /* readjust the word count to not take into account the extra bytes */
-
- if (ExtraByteCount > 0) {
- WordCount--;
- }
-
- /* Write all the bytes of the buffer which can be written as 32 bit
- * words into the FIFO, waiting to handle the extra bytes seperately
- */
- for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
- XIo_Out32(InstancePtr->DataBaseAddress, WordBuffer[FifoCount]);
- }
-
- /* if there are extra bytes to handle, extract them from the buffer
- * and create a 32 bit word and write it to the FIFO
- */
- if (ExtraByteCount > 0) {
- u32 LastWord = 0;
- u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
-
- /* one extra byte in the buffer, put the byte into the last word
- * to be inserted into the FIFO, perform this processing inline rather
- * than in a loop to help performance
- */
- if (ExtraByteCount == 1) {
- LastWord = ExtraBytesBuffer[0] << 24;
- }
-
- /* two extra bytes in the buffer, put each byte into the last word
- * to be inserted into the FIFO
- */
- else if (ExtraByteCount == 2) {
- LastWord = ExtraBytesBuffer[0] << 24 |
- ExtraBytesBuffer[1] << 16;
- }
-
- /* three extra bytes in the buffer, put each byte into the last word
- * to be inserted into the FIFO
- */
- else if (ExtraByteCount == 3) {
- LastWord = ExtraBytesBuffer[0] << 24 |
- ExtraBytesBuffer[1] << 16 |
- ExtraBytesBuffer[2] << 8;
- }
-
- /* write the last 32 bit word to the FIFO and return with no errors */
-
- XIo_Out32(InstancePtr->DataBaseAddress, LastWord);
- }
-
- return XST_SUCCESS;
-}
diff --git a/board/xilinx/common/xpacket_fifo_v1_00_b.h b/board/xilinx/common/xpacket_fifo_v1_00_b.h
+++ /dev/null
@@ -1,306 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/*
-*
-* @file xpacket_fifo_v1_00_b.h
-*
-* This component is a common component because it's primary purpose is to
-* prevent code duplication in drivers. A driver which must handle a packet
-* FIFO uses this component rather than directly manipulating a packet FIFO.
-*
-* A FIFO is a device which has dual port memory such that one user may be
-* inserting data into the FIFO while another is consuming data from the FIFO.
-* A packet FIFO is designed for use with packet protocols such as Ethernet and
-* ATM. It is typically only used with devices when DMA and/or Scatter Gather
-* is used. It differs from a nonpacket FIFO in that it does not provide any
-* interrupts for thresholds of the FIFO such that it is less useful without
-* DMA.
-*
-* @note
-*
-* This component has the capability to generate an interrupt when an error
-* condition occurs. It is the user's responsibility to provide the interrupt
-* processing to handle the interrupt. This component provides the ability to
-* determine if that interrupt is active, a deadlock condition, and the ability
-* to reset the FIFO to clear the condition. In this condition, the device which
-* is using the FIFO should also be reset to prevent other problems. This error
-* condition could occur as a normal part of operation if the size of the FIFO
-* is not setup correctly. See the hardware IP specification for more details.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b rpm 03/26/02 First release
-* </pre>
-*
-*****************************************************************************/
-#ifndef XPACKET_FIFO_H /* prevent circular inclusions */
-#define XPACKET_FIFO_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/*
- * These constants specify the FIFO type and are mutually exclusive
- */
-#define XPF_READ_FIFO_TYPE 0 /* a read FIFO */
-#define XPF_WRITE_FIFO_TYPE 1 /* a write FIFO */
-
-/*
- * These constants define the offsets to each of the registers from the
- * register base address, each of the constants are a number of bytes
- */
-#define XPF_RESET_REG_OFFSET 0UL
-#define XPF_MODULE_INFO_REG_OFFSET 0UL
-#define XPF_COUNT_STATUS_REG_OFFSET 4UL
-
-/*
- * This constant is used with the Reset Register
- */
-#define XPF_RESET_FIFO_MASK 0x0000000A
-
-/*
- * These constants are used with the Occupancy/Vacancy Count Register. This
- * register also contains FIFO status
- */
-#define XPF_COUNT_MASK 0x0000FFFF
-#define XPF_DEADLOCK_MASK 0x20000000
-#define XPF_ALMOST_EMPTY_FULL_MASK 0x40000000
-#define XPF_EMPTY_FULL_MASK 0x80000000
-
-/**************************** Type Definitions *******************************/
-
-/*
- * The XPacketFifo driver instance data. The driver is required to allocate a
- * variable of this type for every packet FIFO in the device.
- */
-typedef struct {
- u32 RegBaseAddress; /* Base address of registers */
- u32 IsReady; /* Device is initialized and ready */
- u32 DataBaseAddress; /* Base address of data for FIFOs */
-} XPacketFifoV100b;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/*****************************************************************************/
-/*
-*
-* Reset the specified packet FIFO. Resetting a FIFO will cause any data
-* contained in the FIFO to be lost.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* Signature: void XPF_V100B_RESET(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_RESET(InstancePtr) \
- XIo_Out32((InstancePtr)->RegBaseAddress + XPF_RESET_REG_OFFSET, XPF_RESET_FIFO_MASK);
-
-/*****************************************************************************/
-/*
-*
-* Get the occupancy count for a read packet FIFO and the vacancy count for a
-* write packet FIFO. These counts indicate the number of 32-bit words
-* contained (occupancy) in the FIFO or the number of 32-bit words available
-* to write (vacancy) in the FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* The occupancy or vacancy count for the specified packet FIFO.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_GET_COUNT(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_GET_COUNT(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_COUNT_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is almost empty. Almost empty is
-* defined for a read FIFO when there is only one data word in the FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is almost empty, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_ALMOST_EMPTY(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_ALMOST_EMPTY(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_ALMOST_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is almost full. Almost full is
-* defined for a write FIFO when there is only one available data word in the
-* FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is almost full, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_ALMOST_FULL(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_ALMOST_FULL(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_ALMOST_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is empty. This applies only to a
-* read FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is empty, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_EMPTY(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_EMPTY(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is full. This applies only to a
-* write FIFO.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is full, FALSE otherwise.
-*
-* @note
-*
-* Signature: u32 XPF_V100B_IS_FULL(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_FULL(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_EMPTY_FULL_MASK)
-
-/*****************************************************************************/
-/*
-*
-* Determine if the specified packet FIFO is deadlocked. This condition occurs
-* when the FIFO is full and empty at the same time and is caused by a packet
-* being written to the FIFO which exceeds the total data capacity of the FIFO.
-* It occurs because of the mark/restore features of the packet FIFO which allow
-* retransmission of a packet. The software should reset the FIFO and any devices
-* using the FIFO when this condition occurs.
-*
-* @param InstancePtr contains a pointer to the FIFO to operate on.
-*
-* @return
-*
-* TRUE if the packet FIFO is deadlocked, FALSE otherwise.
-*
-* @note
-*
-* This component has the capability to generate an interrupt when an error
-* condition occurs. It is the user's responsibility to provide the interrupt
-* processing to handle the interrupt. This function provides the ability to
-* determine if a deadlock condition, and the ability to reset the FIFO to
-* clear the condition.
-*
-* In this condition, the device which is using the FIFO should also be reset
-* to prevent other problems. This error condition could occur as a normal part
-* of operation if the size of the FIFO is not setup correctly.
-*
-* Signature: u32 XPF_V100B_IS_DEADLOCKED(XPacketFifoV100b *InstancePtr)
-*
-******************************************************************************/
-#define XPF_V100B_IS_DEADLOCKED(InstancePtr) \
- (XIo_In32((InstancePtr)->RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET) & \
- XPF_DEADLOCK_MASK)
-
-/************************** Function Prototypes ******************************/
-
-/* Standard functions */
-
-XStatus XPacketFifoV100b_Initialize(XPacketFifoV100b * InstancePtr,
- u32 RegBaseAddress, u32 DataBaseAddress);
-XStatus XPacketFifoV100b_SelfTest(XPacketFifoV100b * InstancePtr, u32 FifoType);
-
-/* Data functions */
-
-XStatus XPacketFifoV100b_Read(XPacketFifoV100b * InstancePtr,
- u8 * ReadBufferPtr, u32 ByteCount);
-XStatus XPacketFifoV100b_Write(XPacketFifoV100b * InstancePtr,
- u8 * WriteBufferPtr, u32 ByteCount);
-
-#endif /* end of protection macro */
diff --git a/board/xilinx/common/xstatus.h b/board/xilinx/common/xstatus.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xstatus.h
-*
-* This file contains Xilinx software status codes. Status codes have their
-* own data type called XStatus. These codes are used throughout the Xilinx
-* device drivers.
-*
-******************************************************************************/
-
-#ifndef XSTATUS_H /* prevent circular inclusions */
-#define XSTATUS_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-
-/************************** Constant Definitions *****************************/
-
-/*********************** Common statuses 0 - 500 *****************************/
-
-#define XST_SUCCESS 0L
-#define XST_FAILURE 1L
-#define XST_DEVICE_NOT_FOUND 2L
-#define XST_DEVICE_BLOCK_NOT_FOUND 3L
-#define XST_INVALID_VERSION 4L
-#define XST_DEVICE_IS_STARTED 5L
-#define XST_DEVICE_IS_STOPPED 6L
-#define XST_FIFO_ERROR 7L /* an error occurred during an
- operation with a FIFO such as
- an underrun or overrun, this
- error requires the device to
- be reset */
-#define XST_RESET_ERROR 8L /* an error occurred which requires
- the device to be reset */
-#define XST_DMA_ERROR 9L /* a DMA error occurred, this error
- typically requires the device
- using the DMA to be reset */
-#define XST_NOT_POLLED 10L /* the device is not configured for
- polled mode operation */
-#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put
- the specified data into */
-#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough
- to hold the expected data */
-#define XST_NO_DATA 13L /* there was no data available */
-#define XST_REGISTER_ERROR 14L /* a register did not contain the
- expected value */
-#define XST_INVALID_PARAM 15L /* an invalid parameter was passed
- into the function */
-#define XST_NOT_SGDMA 16L /* the device is not configured for
- scatter-gather DMA operation */
-#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */
-#define XST_NO_CALLBACK 18L /* a callback has not yet been
- * registered */
-#define XST_NO_FEATURE 19L /* device is not configured with
- * the requested feature */
-#define XST_NOT_INTERRUPT 20L /* device is not configured for
- * interrupt mode operation */
-#define XST_DEVICE_BUSY 21L /* device is busy */
-#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device
- * have maxed out */
-#define XST_IS_STARTED 23L /* used when part of device is
- * already started i.e.
- * sub channel */
-#define XST_IS_STOPPED 24L /* used when part of device is
- * already stopped i.e.
- * sub channel */
-
-/***************** Utility Component statuses 401 - 500 *********************/
-
-#define XST_MEMTEST_FAILED 401L /* memory test failed */
-
-/***************** Common Components statuses 501 - 1000 *********************/
-
-/********************* Packet Fifo statuses 501 - 510 ************************/
-
-#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */
-#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */
-#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value
- was invalid after reset */
-
-/************************** DMA statuses 511 - 530 ***************************/
-
-#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer
- failed */
-#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value
- was invalid after reset */
-#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains
- no buffer descriptors ready
- to be processed */
-#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */
-#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */
-#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of
- the scatter gather list are
- being used */
-#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer
- descriptor which is to be
- copied over in the scatter
- list is locked */
-#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been
- put into the scatter gather
- list to be commited */
-#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold
- specified was larger than the
- total # of buffer descriptors
- in the scatter gather list */
-#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has
- already been created */
-#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has
- been created */
-#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was
- being started was not committed
- to the list */
-#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start
- has already been used by the
- hardware so it can't be reused
- */
-
-/************************** IPIF statuses 531 - 550 ***************************/
-
-#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width
- was passed into the function */
-#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at
- reset was not valid */
-#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status
- register did not reset when
- acked */
-#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable
- register was not updated when
- other registers changed */
-#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt
- status register did not read
- back correctly */
-#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register
- did not reset when acked */
-#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was
- not updated correctly when other
- registers changed */
-#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending
- register did not indicate the
- expected value */
-#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register
- did not indicate the expected
- value */
-
-/****************** Device specific statuses 1001 - 4095 *********************/
-
-/********************* Ethernet statuses 1001 - 1050 *************************/
-
-#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough
- * to hold the minimum number of
- * buffers or descriptors */
-#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */
-#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */
-#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */
-#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Adapter is out of buffers */
-#define XST_EMAC_PARSE_ERROR 1006L /* Invalid adapter init string */
-#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late
- * collision on polled send */
-
-/*********************** UART statuses 1051 - 1075 ***************************/
-#define XST_UART
-
-#define XST_UART_INIT_ERROR 1051L
-#define XST_UART_START_ERROR 1052L
-#define XST_UART_CONFIG_ERROR 1053L
-#define XST_UART_TEST_FAIL 1054L
-#define XST_UART_BAUD_ERROR 1055L
-#define XST_UART_BAUD_RANGE 1056L
-
-/************************ IIC statuses 1076 - 1100 ***************************/
-
-#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */
-#define XST_IIC_BUS_BUSY 1077 /* bus found busy */
-#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */
- /* general call address */
-#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */
- /* value after reset not valid */
-#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */
- /* value after reset not valid */
-#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */
- /* value after reset not valid */
-#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */
- /* didn't return value written */
-#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */
- /* didn't return value written */
-#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */
- /* didn't return value written */
-#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */
- /* didn't return written value */
-#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */
-
-/*********************** ATMC statuses 1101 - 1125 ***************************/
-
-#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM
- controller hit the max value
- which requires the statistics
- to be cleared */
-
-/*********************** Flash statuses 1126 - 1150 **************************/
-
-#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming */
-#define XST_FLASH_READY 1127L /* Flash is ready for commands */
-#define XST_FLASH_ERROR 1128L /* Flash had detected an internal
- error. Use XFlash_DeviceControl
- to retrieve device specific codes */
-#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state */
-#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state */
-#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by
- driver */
-#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */
-#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */
-#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation
- aborted due to a timeout */
-#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its
- addressible range */
-#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */
-#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from
- write/erase function with
- XFL_NON_BLOCKING_WRITE/ERASE
- option cleared */
-#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */
-
-/*********************** SPI statuses 1151 - 1175 ****************************/
-
-#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */
-#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */
-#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */
-#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */
-#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */
-#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being
- * selected */
-#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */
-#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only */
-#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */
-
-/********************** OPB Arbiter statuses 1176 - 1200 *********************/
-
-#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either
- * one master assigned to two or more
- * priorities, or one master not
- * assigned to any priority
- */
-#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the
- * priority levels without first
- * suspending the use of priority
- * levels
- */
-#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but
- * bus parking was not enabled
- */
-#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed
- * priority mode to allow the
- * priorities to be changed
- */
-
-/************************ Intc statuses 1201 - 1225 **************************/
-
-#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */
-#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */
-
-/********************** TmrCtr statuses 1226 - 1250 **************************/
-
-#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */
-
-/********************** WdtTb statuses 1251 - 1275 ***************************/
-
-#define XST_WDTTB_TIMER_FAILED 1251L
-
-/********************** PlbArb statuses 1276 - 1300 **************************/
-
-#define XST_PLBARB_FAIL_SELFTEST 1276L
-
-/********************** Plb2Opb statuses 1301 - 1325 *************************/
-
-#define XST_PLB2OPB_FAIL_SELFTEST 1301L
-
-/********************** Opb2Plb statuses 1326 - 1350 *************************/
-
-#define XST_OPB2PLB_FAIL_SELFTEST 1326L
-
-/********************** SysAce statuses 1351 - 1360 **************************/
-
-#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */
-
-/********************** PCI Bridge statuses 1361 - 1375 **********************/
-
-#define XST_PCI_INVALID_ADDRESS 1361L
-
-/**************************** Type Definitions *******************************/
-
-/**
- * The status typedef.
- */
-typedef u32 XStatus;
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-#endif /* end of protection macro */
diff --git a/board/xilinx/common/xversion.c b/board/xilinx/common/xversion.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************
-*
-* This file contains the implementation of the XVersion component. This
-* component represents a version ID. It is encapsulated within a component
-* so that it's type and implementation can change without affecting users of
-* it.
-*
-* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
-* X is the major revision, YY is the minor revision, and Z is the
-* compatability revision.
-*
-* Packed versions are also utilized for the configuration ROM such that
-* memory is minimized. A packed version consumes only 16 bits and is
-* formatted as follows.
-*
-* <pre>
-* Revision Range Bit Positions
-*
-* Major Revision 0 - 9 Bits 15 - 12
-* Minor Revision 0 - 99 Bits 11 - 5
-* Compatability Revision a - z Bits 4 - 0
-</pre>
-*
-******************************************************************************/
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xversion.h"
-
-/************************** Constant Definitions *****************************/
-
-/* the following constants define the masks and shift values to allow the
- * revisions to be packed and unpacked, a packed version is packed into a 16
- * bit value in the following format, XXXXYYYYYYYZZZZZ, where XXXX is the
- * major revision, YYYYYYY is the minor revision, and ZZZZZ is the compatability
- * revision
- */
-#define XVE_MAJOR_SHIFT_VALUE 12
-#define XVE_MINOR_ONLY_MASK 0x0FE0
-#define XVE_MINOR_SHIFT_VALUE 5
-#define XVE_COMP_ONLY_MASK 0x001F
-
-/* the following constants define the specific characters of a version string
- * for each character of the revision, a version string is in the following
- * format, "X.YYZ" where X is the major revision (0 - 9), YY is the minor
- * revision (00 - 99), and Z is the compatability revision (a - z)
- */
-#define XVE_MAJOR_CHAR 0 /* major revision 0 - 9 */
-#define XVE_MINOR_TENS_CHAR 2 /* minor revision tens 0 - 9 */
-#define XVE_MINOR_ONES_CHAR 3 /* minor revision ones 0 - 9 */
-#define XVE_COMP_CHAR 4 /* compatability revision a - z */
-#define XVE_END_STRING_CHAR 5
-
-/**************************** Type Definitions *******************************/
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-static u32 IsVersionStringValid(s8 * StringPtr);
-
-/*****************************************************************************
-*
-* Unpacks a packed version into the specified version. Versions are packed
-* into the configuration ROM to reduce the amount storage. A packed version
-* is a binary format as oppossed to a non-packed version which is implemented
-* as a string.
-*
-* @param InstancePtr points to the version to unpack the packed version into.
-* @param PackedVersion contains the packed version to unpack.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion)
-{
- /* not implemented yet since CROM related */
-}
-
-/*****************************************************************************
-*
-* Packs a version into the specified packed version. Versions are packed into
-* the configuration ROM to reduce the amount storage.
-*
-* @param InstancePtr points to the version to pack.
-* @param PackedVersionPtr points to the packed version which will receive
-* the new packed version.
-*
-* @return
-*
-* A status, XST_SUCCESS, indicating the packing was accomplished
-* successfully, or an error, XST_INVALID_VERSION, indicating the specified
-* input version was not valid such that the pack did not occur
-* <br><br>
-* The packed version pointed to by PackedVersionPtr is modified with the new
-* packed version if the status indicates success.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersionPtr)
-{
- /* not implemented yet since CROM related */
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************
-*
-* Determines if two versions are equal.
-*
-* @param InstancePtr points to the first version to be compared.
-* @param VersionPtr points to a second version to be compared.
-*
-* @return
-*
-* TRUE if the versions are equal, FALSE otherwise.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-u32
-XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr)
-{
- u8 *Version1 = (u8 *) InstancePtr;
- u8 *Version2 = (u8 *) VersionPtr;
- int Index;
-
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(VersionPtr != NULL);
-
- /* check each byte of the versions to see if they are the same,
- * return at any point a byte differs between them
- */
- for (Index = 0; Index < sizeof (XVersion); Index++) {
- if (Version1[Index] != Version2[Index]) {
- return FALSE;
- }
- }
-
- /* No byte was found to be different between the versions, so indicate
- * the versions are equal
- */
- return TRUE;
-}
-
-/*****************************************************************************
-*
-* Converts a version to a null terminated string.
-*
-* @param InstancePtr points to the version to convert.
-* @param StringPtr points to the string which will be the result of the
-* conversion. This does not need to point to a null terminated
-* string as an input, but must point to storage which is an adequate
-* amount to hold the result string.
-*
-* @return
-*
-* The null terminated string is inserted at the location pointed to by
-* StringPtr if the status indicates success.
-*
-* @note
-*
-* It is necessary for the caller to have already allocated the storage to
-* contain the string. The amount of memory necessary for the string is
-* specified in the version header file.
-*
-******************************************************************************/
-void
-XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(StringPtr != NULL);
-
- /* since version is implemented as a string, just copy the specified
- * input into the specified output
- */
- XVersion_Copy(InstancePtr, (XVersion *) StringPtr);
-}
-
-/*****************************************************************************
-*
-* Initializes a version from a null terminated string. Since the string may not
-* be a format which is compatible with the version, an error could occur.
-*
-* @param InstancePtr points to the version which is to be initialized.
-* @param StringPtr points to a null terminated string which will be
-* converted to a version. The format of the string must match the
-* version string format which is X.YYX where X = 0 - 9, YY = 00 - 99,
-* Z = a - z.
-*
-* @return
-*
-* A status, XST_SUCCESS, indicating the conversion was accomplished
-* successfully, or XST_INVALID_VERSION indicating the version string format
-* was not valid.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-XStatus
-XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr)
-{
- /* assert to verify input arguments */
-
- XASSERT_NONVOID(InstancePtr != NULL);
- XASSERT_NONVOID(StringPtr != NULL);
-
- /* if the version string specified is not valid, return an error */
-
- if (!IsVersionStringValid(StringPtr)) {
- return XST_INVALID_VERSION;
- }
-
- /* copy the specified string into the specified version and indicate the
- * conversion was successful
- */
- XVersion_Copy((XVersion *) StringPtr, InstancePtr);
-
- return XST_SUCCESS;
-}
-
-/*****************************************************************************
-*
-* Copies the contents of a version to another version.
-*
-* @param InstancePtr points to the version which is the source of data for
-* the copy operation.
-* @param VersionPtr points to another version which is the destination of
-* the copy operation.
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-void
-XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr)
-{
- u8 *Source = (u8 *) InstancePtr;
- u8 *Destination = (u8 *) VersionPtr;
- int Index;
-
- /* assert to verify input arguments */
-
- XASSERT_VOID(InstancePtr != NULL);
- XASSERT_VOID(VersionPtr != NULL);
-
- /* copy each byte of the source version to the destination version */
-
- for (Index = 0; Index < sizeof (XVersion); Index++) {
- Destination[Index] = Source[Index];
- }
-}
-
-/*****************************************************************************
-*
-* Determines if the specified version is valid.
-*
-* @param StringPtr points to the string to be validated.
-*
-* @return
-*
-* TRUE if the version string is a valid format, FALSE otherwise.
-*
-* @note
-*
-* None.
-*
-******************************************************************************/
-static u32
-IsVersionStringValid(s8 * StringPtr)
-{
- /* if the input string is not a valid format, "X.YYZ" where X = 0 - 9,
- * YY = 00 - 99, and Z = a - z, then indicate it's not valid
- */
- if ((StringPtr[XVE_MAJOR_CHAR] < '0') ||
- (StringPtr[XVE_MAJOR_CHAR] > '9') ||
- (StringPtr[XVE_MINOR_TENS_CHAR] < '0') ||
- (StringPtr[XVE_MINOR_TENS_CHAR] > '9') ||
- (StringPtr[XVE_MINOR_ONES_CHAR] < '0') ||
- (StringPtr[XVE_MINOR_ONES_CHAR] > '9') ||
- (StringPtr[XVE_COMP_CHAR] < 'a') ||
- (StringPtr[XVE_COMP_CHAR] > 'z')) {
- return FALSE;
- }
-
- return TRUE;
-}
diff --git a/board/xilinx/common/xversion.h b/board/xilinx/common/xversion.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/******************************************************************************
-*
-* Author: Xilinx, Inc.
-*
-*
-* This program is free software; you can redistribute it and/or modify it
-* under the terms of the GNU General Public License as published by the
-* Free Software Foundation; either version 2 of the License, or (at your
-* option) any later version.
-*
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-* FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-* Xilinx hardware products are not intended for use in life support
-* appliances, devices, or systems. Use in such applications is
-* expressly prohibited.
-*
-*
-* (c) Copyright 2002-2004 Xilinx Inc.
-* All rights reserved.
-*
-*
-* You should have received a copy of the GNU General Public License along
-* with this program; if not, write to the Free Software Foundation, Inc.,
-* 675 Mass Ave, Cambridge, MA 02139, USA.
-*
-******************************************************************************/
-/*****************************************************************************
-*
-* This file contains the interface for the XVersion component. This
-* component represents a version ID. It is encapsulated within a component
-* so that it's type and implementation can change without affecting users of
-* it.
-*
-* The version is formatted as X.YYZ where X = 0 - 9, Y = 00 - 99, Z = a - z
-* X is the major revision, YY is the minor revision, and Z is the
-* compatability revision.
-*
-* Packed versions are also utilized for the configuration ROM such that
-* memory is minimized. A packed version consumes only 16 bits and is
-* formatted as follows.
-*
-* <pre>
-* Revision Range Bit Positions
-*
-* Major Revision 0 - 9 Bits 15 - 12
-* Minor Revision 0 - 99 Bits 11 - 5
-* Compatability Revision a - z Bits 4 - 0
-* </pre>
-*
-******************************************************************************/
-
-#ifndef XVERSION_H /* prevent circular inclusions */
-#define XVERSION_H /* by using protection macros */
-
-/***************************** Include Files *********************************/
-
-#include "xbasic_types.h"
-#include "xstatus.h"
-
-/************************** Constant Definitions *****************************/
-
-/**************************** Type Definitions *******************************/
-
-/* the following data type is used to hold a null terminated version string
- * consisting of the following format, "X.YYX"
- */
-typedef s8 XVersion[6];
-
-/***************** Macros (Inline Functions) Definitions *********************/
-
-/************************** Function Prototypes ******************************/
-
-void XVersion_UnPack(XVersion * InstancePtr, u16 PackedVersion);
-
-XStatus XVersion_Pack(XVersion * InstancePtr, u16 * PackedVersion);
-
-u32 XVersion_IsEqual(XVersion * InstancePtr, XVersion * VersionPtr);
-
-void XVersion_ToString(XVersion * InstancePtr, s8 * StringPtr);
-
-XStatus XVersion_FromString(XVersion * InstancePtr, s8 * StringPtr);
-
-void XVersion_Copy(XVersion * InstancePtr, XVersion * VersionPtr);
-
-#endif /* end of protection macro */
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c
index b75e62c715d8e930fdd885629cd33da3313cd010..70f94c1a5973a12be8ae2ccf93f78a4390ef9f4a 100644 (file)
return 0;
}
-#ifdef CONFIG_SYS_FSL_2
-void fsl_isr2 (void *arg) {
- volatile int num;
- *((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)) =
- ++(*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)));
- GET (num, 2);
- NGET (num, 2);
- puts("*");
-}
-
-int fsl_init2 (void) {
- puts("fsl_init2\n");
- install_interrupt_handler (FSL_INTR_2, fsl_isr2, NULL);
- return 0;
-}
-#endif
-
void board_init(void)
{
gpio_init();
-#ifdef CONFIG_SYS_FSL_2
- fsl_init2();
-#endif
}
int board_eth_init(bd_t *bis)
diff --git a/board/xilinx/xilinx_iic/xiic_l.c b/board/xilinx/xilinx_iic/xiic_l.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/* $Id: xiic_l.c,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
-/******************************************************************************
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE.
-*
-* (c) Copyright 2002 Xilinx Inc.
-* All rights reserved.
-*
-******************************************************************************/
-/*****************************************************************************/
-/**
-*
-* @file xiic_l.c
-*
-* This file contains low-level driver functions that can be used to access the
-* device. The user should refer to the hardware device specification for more
-* details of the device operation.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- --- ------- -----------------------------------------------
-* 1.01b jhl 5/13/02 First release
-* 1.01b jhl 10/14/02 Corrected bug in the receive function, the setup of the
-* interrupt status mask was not being done in the loop such
-* that a read would sometimes fail on the last byte because
-* the transmit error which should have been ignored was
-* being used. This would leave an extra byte in the FIFO
-* and the bus throttled such that the next operation would
-* also fail. Also updated the receive function to not
-* disable the device after the last byte until after the
-* bus transitions to not busy which is more consistent
-* with the expected behavior.
-* 1.01c ecm 12/05/02 new rev
-* </pre>
-*
-****************************************************************************/
-
-/***************************** Include Files *******************************/
-
-#include "xbasic_types.h"
-#include "xio.h"
-#include "xipif_v1_23_b.h"
-#include "xiic_l.h"
-
-/************************** Constant Definitions ***************************/
-
-/**************************** Type Definitions *****************************/
-
-
-/***************** Macros (Inline Functions) Definitions *******************/
-
-
-/******************************************************************************
-*
-* This macro clears the specified interrupt in the IPIF interrupt status
-* register. It is non-destructive in that the register is read and only the
-* interrupt specified is cleared. Clearing an interrupt acknowledges it.
-*
-* @param BaseAddress contains the IPIF registers base address.
-*
-* @param InterruptMask contains the interrupts to be disabled
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* Signature: void XIic_mClearIisr(u32 BaseAddress,
-* u32 InterruptMask);
-*
-******************************************************************************/
-#define XIic_mClearIisr(BaseAddress, InterruptMask) \
- XIIF_V123B_WRITE_IISR((BaseAddress), \
- XIIF_V123B_READ_IISR(BaseAddress) & (InterruptMask))
-
-/******************************************************************************
-*
-* This macro sends the address for a 7 bit address during both read and write
-* operations. It takes care of the details to format the address correctly.
-* This macro is designed to be called internally to the drivers.
-*
-* @param SlaveAddress contains the address of the slave to send to.
-*
-* @param Operation indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION
-*
-* @return
-*
-* None.
-*
-* @note
-*
-* Signature: void XIic_mSend7BitAddr(u16 SlaveAddress, u8 Operation);
-*
-******************************************************************************/
-#define XIic_mSend7BitAddress(BaseAddress, SlaveAddress, Operation) \
-{ \
- u8 LocalAddr = (u8)(SlaveAddress << 1); \
- LocalAddr = (LocalAddr & 0xFE) | (Operation); \
- XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET, LocalAddr); \
-}
-
-/************************** Function Prototypes ****************************/
-
-static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr,
- unsigned ByteCount);
-static unsigned SendData (u32 BaseAddress, u8 * BufferPtr,
- unsigned ByteCount);
-
-/************************** Variable Definitions **************************/
-
-
-/****************************************************************************/
-/**
-* Receive data as a master on the IIC bus. This function receives the data
-* using polled I/O and blocks until the data has been received. It only
-* supports 7 bit addressing and non-repeated start modes of operation. The
-* user is responsible for ensuring the bus is not busy if multiple masters
-* are present on the bus.
-*
-* @param BaseAddress contains the base address of the IIC device.
-* @param Address contains the 7 bit IIC address of the device to send the
-* specified data to.
-* @param BufferPtr points to the data to be sent.
-* @param ByteCount is the number of bytes to be sent.
-*
-* @return
-*
-* The number of bytes received.
-*
-* @note
-*
-* None
-*
-******************************************************************************/
-unsigned XIic_Recv (u32 BaseAddress, u8 Address,
- u8 * BufferPtr, unsigned ByteCount)
-{
- u8 CntlReg;
- unsigned RemainingByteCount;
-
- /* Tx error is enabled incase the address (7 or 10) has no device to answer
- * with Ack. When only one byte of data, must set NO ACK before address goes
- * out therefore Tx error must not be enabled as it will go off immediately
- * and the Rx full interrupt will be checked. If full, then the one byte
- * was received and the Tx error will be disabled without sending an error
- * callback msg.
- */
- XIic_mClearIisr (BaseAddress,
- XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK |
- XIIC_INTR_ARB_LOST_MASK);
-
- /* Set receive FIFO occupancy depth for 1 byte (zero based)
- */
- XIo_Out8 (BaseAddress + XIIC_RFD_REG_OFFSET, 0);
-
- /* 7 bit slave address, send the address for a read operation
- * and set the state to indicate the address has been sent
- */
- XIic_mSend7BitAddress (BaseAddress, Address, XIIC_READ_OPERATION);
-
- /* MSMS gets set after putting data in FIFO. Start the master receive
- * operation by setting CR Bits MSMS to Master, if the buffer is only one
- * byte, then it should not be acknowledged to indicate the end of data
- */
- CntlReg = XIIC_CR_MSMS_MASK | XIIC_CR_ENABLE_DEVICE_MASK;
- if (ByteCount == 1) {
- CntlReg |= XIIC_CR_NO_ACK_MASK;
- }
-
- /* Write out the control register to start receiving data and call the
- * function to receive each byte into the buffer
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, CntlReg);
-
- /* Clear the latched interrupt status for the bus not busy bit which must
- * be done while the bus is busy
- */
- XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
-
- /* Try to receive the data from the IIC bus */
-
- RemainingByteCount = RecvData (BaseAddress, BufferPtr, ByteCount);
- /*
- * The receive is complete, disable the IIC device and return the number of
- * bytes that was received
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
-
- /* Return the number of bytes that was received */
-
- return ByteCount - RemainingByteCount;
-}
-
-/******************************************************************************
-*
-* Receive the specified data from the device that has been previously addressed
-* on the IIC bus. This function assumes that the 7 bit address has been sent
-* and it should wait for the transmit of the address to complete.
-*
-* @param BaseAddress contains the base address of the IIC device.
-* @param BufferPtr points to the buffer to hold the data that is received.
-* @param ByteCount is the number of bytes to be received.
-*
-* @return
-*
-* The number of bytes remaining to be received.
-*
-* @note
-*
-* This function does not take advantage of the receive FIFO because it is
-* designed for minimal code space and complexity. It contains loops that
-* that could cause the function not to return if the hardware is not working.
-*
-* This function assumes that the calling function will disable the IIC device
-* after this function returns.
-*
-******************************************************************************/
-static unsigned RecvData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
-{
- u8 CntlReg;
- u32 IntrStatusMask;
- u32 IntrStatus;
-
- /* Attempt to receive the specified number of bytes on the IIC bus */
-
- while (ByteCount > 0) {
- /* Setup the mask to use for checking errors because when receiving one
- * byte OR the last byte of a multibyte message an error naturally
- * occurs when the no ack is done to tell the slave the last byte
- */
- if (ByteCount == 1) {
- IntrStatusMask =
- XIIC_INTR_ARB_LOST_MASK | XIIC_INTR_BNB_MASK;
- } else {
- IntrStatusMask =
- XIIC_INTR_ARB_LOST_MASK |
- XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_BNB_MASK;
- }
-
- /* Wait for the previous transmit and the 1st receive to complete
- * by checking the interrupt status register of the IPIF
- */
- while (1) {
- IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
- if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
- break;
- }
- /* Check the transmit error after the receive full because when
- * sending only one byte transmit error will occur because of the
- * no ack to indicate the end of the data
- */
- if (IntrStatus & IntrStatusMask) {
- return ByteCount;
- }
- }
-
- CntlReg = XIo_In8 (BaseAddress + XIIC_CR_REG_OFFSET);
-
- /* Special conditions exist for the last two bytes so check for them
- * Note that the control register must be setup for these conditions
- * before the data byte which was already received is read from the
- * receive FIFO (while the bus is throttled
- */
- if (ByteCount == 1) {
- /* For the last data byte, it has already been read and no ack
- * has been done, so clear MSMS while leaving the device enabled
- * so it can get off the IIC bus appropriately with a stop.
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
- XIIC_CR_ENABLE_DEVICE_MASK);
- }
-
- /* Before the last byte is received, set NOACK to tell the slave IIC
- * device that it is the end, this must be done before reading the byte
- * from the FIFO
- */
- if (ByteCount == 2) {
- /* Write control reg with NO ACK allowing last byte to
- * have the No ack set to indicate to slave last byte read.
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
- CntlReg | XIIC_CR_NO_ACK_MASK);
- }
-
- /* Read in data from the FIFO and unthrottle the bus such that the
- * next byte is read from the IIC bus
- */
- *BufferPtr++ = XIo_In8 (BaseAddress + XIIC_DRR_REG_OFFSET);
-
- /* Clear the latched interrupt status so that it will be updated with
- * the new state when it changes, this must be done after the receive
- * register is read
- */
- XIic_mClearIisr (BaseAddress, XIIC_INTR_RX_FULL_MASK |
- XIIC_INTR_TX_ERROR_MASK |
- XIIC_INTR_ARB_LOST_MASK);
- ByteCount--;
- }
-
- /* Wait for the bus to transition to not busy before returning, the IIC
- * device cannot be disabled until this occurs. It should transition as
- * the MSMS bit of the control register was cleared before the last byte
- * was read from the FIFO.
- */
- while (1) {
- if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
- break;
- }
- }
-
- return ByteCount;
-}
-
-/****************************************************************************/
-/**
-* Send data as a master on the IIC bus. This function sends the data
-* using polled I/O and blocks until the data has been sent. It only supports
-* 7 bit addressing and non-repeated start modes of operation. The user is
-* responsible for ensuring the bus is not busy if multiple masters are present
-* on the bus.
-*
-* @param BaseAddress contains the base address of the IIC device.
-* @param Address contains the 7 bit IIC address of the device to send the
-* specified data to.
-* @param BufferPtr points to the data to be sent.
-* @param ByteCount is the number of bytes to be sent.
-*
-* @return
-*
-* The number of bytes sent.
-*
-* @note
-*
-* None
-*
-******************************************************************************/
-unsigned XIic_Send (u32 BaseAddress, u8 Address,
- u8 * BufferPtr, unsigned ByteCount)
-{
- unsigned RemainingByteCount;
-
- /* Put the address into the FIFO to be sent and indicate that the operation
- * to be performed on the bus is a write operation
- */
- XIic_mSend7BitAddress (BaseAddress, Address, XIIC_WRITE_OPERATION);
-
- /* Clear the latched interrupt status so that it will be updated with the
- * new state when it changes, this must be done after the address is put
- * in the FIFO
- */
- XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
- XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_ARB_LOST_MASK);
-
- /* MSMS must be set after putting data into transmit FIFO, indicate the
- * direction is transmit, this device is master and enable the IIC device
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
- XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK |
- XIIC_CR_ENABLE_DEVICE_MASK);
-
- /* Clear the latched interrupt
- * status for the bus not busy bit which must be done while the bus is busy
- */
- XIic_mClearIisr (BaseAddress, XIIC_INTR_BNB_MASK);
-
- /* Send the specified data to the device on the IIC bus specified by the
- * the address
- */
- RemainingByteCount = SendData (BaseAddress, BufferPtr, ByteCount);
-
- /*
- * The send is complete, disable the IIC device and return the number of
- * bytes that was sent
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET, 0);
-
- return ByteCount - RemainingByteCount;
-}
-
-/******************************************************************************
-*
-* Send the specified buffer to the device that has been previously addressed
-* on the IIC bus. This function assumes that the 7 bit address has been sent
-* and it should wait for the transmit of the address to complete.
-*
-* @param BaseAddress contains the base address of the IIC device.
-* @param BufferPtr points to the data to be sent.
-* @param ByteCount is the number of bytes to be sent.
-*
-* @return
-*
-* The number of bytes remaining to be sent.
-*
-* @note
-*
-* This function does not take advantage of the transmit FIFO because it is
-* designed for minimal code space and complexity. It contains loops that
-* that could cause the function not to return if the hardware is not working.
-*
-******************************************************************************/
-static unsigned SendData (u32 BaseAddress, u8 * BufferPtr, unsigned ByteCount)
-{
- u32 IntrStatus;
-
- /* Send the specified number of bytes in the specified buffer by polling
- * the device registers and blocking until complete
- */
- while (ByteCount > 0) {
- /* Wait for the transmit to be empty before sending any more data
- * by polling the interrupt status register
- */
- while (1) {
- IntrStatus = XIIF_V123B_READ_IISR (BaseAddress);
-
- if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
- XIIC_INTR_ARB_LOST_MASK |
- XIIC_INTR_BNB_MASK)) {
- return ByteCount;
- }
-
- if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
- break;
- }
- }
- /* If there is more than one byte to send then put the next byte to send
- * into the transmit FIFO
- */
- if (ByteCount > 1) {
- XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
- *BufferPtr++);
- } else {
- /* Set the stop condition before sending the last byte of data so that
- * the stop condition will be generated immediately following the data
- * This is done by clearing the MSMS bit in the control register.
- */
- XIo_Out8 (BaseAddress + XIIC_CR_REG_OFFSET,
- XIIC_CR_ENABLE_DEVICE_MASK |
- XIIC_CR_DIR_IS_TX_MASK);
-
- /* Put the last byte to send in the transmit FIFO */
-
- XIo_Out8 (BaseAddress + XIIC_DTR_REG_OFFSET,
- *BufferPtr++);
- }
-
- /* Clear the latched interrupt status register and this must be done after
- * the transmit FIFO has been written to or it won't clear
- */
- XIic_mClearIisr (BaseAddress, XIIC_INTR_TX_EMPTY_MASK);
-
- /* Update the byte count to reflect the byte sent and clear the latched
- * interrupt status so it will be updated for the new state
- */
- ByteCount--;
- }
-
- /* Wait for the bus to transition to not busy before returning, the IIC
- * device cannot be disabled until this occurs.
- * Note that this is different from a receive operation because the stop
- * condition causes the bus to go not busy.
- */
- while (1) {
- if (XIIF_V123B_READ_IISR (BaseAddress) & XIIC_INTR_BNB_MASK) {
- break;
- }
- }
-
- return ByteCount;
-}
diff --git a/board/xilinx/xilinx_iic/xiic_l.h b/board/xilinx/xilinx_iic/xiic_l.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/* $Id: xiic_l.h,v 1.2 2002/12/05 19:32:40 meinelte Exp $ */
-/*****************************************************************************
-*
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE.
-*
-* (c) Copyright 2002 Xilinx Inc.
-* All rights reserved.
-*
-*****************************************************************************/
-/****************************************************************************/
-/**
-*
-* @file xiic_l.h
-*
-* This header file contains identifiers and low-level driver functions (or
-* macros) that can be used to access the device. High-level driver functions
-* are defined in xiic.h.
-*
-* <pre>
-* MODIFICATION HISTORY:
-*
-* Ver Who Date Changes
-* ----- ---- -------- -----------------------------------------------
-* 1.00b jhl 05/07/02 First release
-* 1.01c ecm 12/05/02 new rev
-* </pre>
-*
-*****************************************************************************/
-
-#ifndef XIIC_L_H /* prevent circular inclusions */
-#define XIIC_L_H /* by using protection macros */
-
-/***************************** Include Files ********************************/
-
-#include "xbasic_types.h"
-
-/************************** Constant Definitions ****************************/
-
-#define XIIC_MSB_OFFSET 3
-
-#define XIIC_REG_OFFSET 0x100 + XIIC_MSB_OFFSET
-
-/*
- * Register offsets in bytes from RegisterBase. Three is added to the
- * base offset to access LSB (IBM style) of the word
- */
-#define XIIC_CR_REG_OFFSET 0x00+XIIC_REG_OFFSET /* Control Register */
-#define XIIC_SR_REG_OFFSET 0x04+XIIC_REG_OFFSET /* Status Register */
-#define XIIC_DTR_REG_OFFSET 0x08+XIIC_REG_OFFSET /* Data Tx Register */
-#define XIIC_DRR_REG_OFFSET 0x0C+XIIC_REG_OFFSET /* Data Rx Register */
-#define XIIC_ADR_REG_OFFSET 0x10+XIIC_REG_OFFSET /* Address Register */
-#define XIIC_TFO_REG_OFFSET 0x14+XIIC_REG_OFFSET /* Tx FIFO Occupancy */
-#define XIIC_RFO_REG_OFFSET 0x18+XIIC_REG_OFFSET /* Rx FIFO Occupancy */
-#define XIIC_TBA_REG_OFFSET 0x1C+XIIC_REG_OFFSET /* 10 Bit Address reg */
-#define XIIC_RFD_REG_OFFSET 0x20+XIIC_REG_OFFSET /* Rx FIFO Depth reg */
-
-/* Control Register masks */
-
-#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
-#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
-#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
-#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
-#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
-#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
-#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
-
-/* Status Register masks */
-
-#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
-#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
-#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
-#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
-#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
-#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
-#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
-
-/* IPIF Interrupt Status Register masks Interrupt occurs when... */
-
-#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
-#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete*/
-#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
-#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level*/
-#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
-#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
-#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
-#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
-
-/* IPIF Device Interrupt Register masks */
-
-#define XIIC_IPIF_IIC_MASK 0x00000004UL /* 1=inter enabled */
-#define XIIC_IPIF_ERROR_MASK 0x00000001UL /* 1=inter enabled */
-#define XIIC_IPIF_INTER_ENABLE_MASK (XIIC_IPIF_IIC_MASK | \
- XIIC_IPIF_ERROR_MASK)
-
-#define XIIC_TX_ADDR_SENT 0x00
-#define XIIC_TX_ADDR_MSTR_RECV_MASK 0x02
-
-/* The following constants specify the depth of the FIFOs */
-
-#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
-#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
-
-/* The following constants specify groups of interrupts that are typically
- * enabled or disables at the same time
- */
-#define XIIC_TX_INTERRUPTS \
- (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | \
- XIIC_INTR_TX_HALF_MASK)
-
-#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
-
-/* The following constants are used with the following macros to specify the
- * operation, a read or write operation.
- */
-#define XIIC_READ_OPERATION 1
-#define XIIC_WRITE_OPERATION 0
-
-/* The following constants are used with the transmit FIFO fill function to
- * specify the role which the IIC device is acting as, a master or a slave.
- */
-#define XIIC_MASTER_ROLE 1
-#define XIIC_SLAVE_ROLE 0
-
-/**************************** Type Definitions ******************************/
-
-
-/***************** Macros (Inline Functions) Definitions ********************/
-
-
-/************************** Function Prototypes *****************************/
-
-unsigned XIic_Recv(u32 BaseAddress, u8 Address,
- u8 *BufferPtr, unsigned ByteCount);
-
-unsigned XIic_Send(u32 BaseAddress, u8 Address,
- u8 *BufferPtr, unsigned ByteCount);
-
-#endif /* end of protection macro */
index ef4faa125ed9f4fc6c78bd5d67f1193e7e3d04ff..43c552dc3f2a49d833566f25e5caac651e781771 100644 (file)
#
include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
LIB = $(obj)lib$(BOARD).o
diff --git a/boards.cfg b/boards.cfg
index 7d03620e4f9cb7de17e23988c92edf4d579e9a95..7a0b79dd072f4b8a8c39fe75d638c4d163bdc385 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
integratorcp_cm946es arm arm946es integrator armltd - integratorcp:CM946ES
ca9x4_ct_vxp arm armv7 vexpress armltd
am335x_evm arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1
+am335x_evm_spiboot arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT
am335x_evm_uart1 arm armv7 am335x ti am33xx am335x_evm:SERIAL2,CONS_INDEX=2
am335x_evm_uart2 arm armv7 am335x ti am33xx am335x_evm:SERIAL3,CONS_INDEX=3
am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4
am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5
am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6
+pcm051 arm armv7 pcm051 phytec am33xx pcm051
highbank arm armv7 highbank - highbank
mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
omap3_overo arm armv7 overo - omap3
omap3_pandora arm armv7 pandora - omap3
dig297 arm armv7 dig297 comelit omap3
-igep0020 arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND
-igep0020_nand arm armv7 igep0020 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND
-igep0030 arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
-igep0030_nand arm armv7 igep0030 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
+igep0020 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND
+igep0020_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND
+igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
+igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
+igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND
am3517_evm arm armv7 am3517evm logicpd omap3
mt_ventoux arm armv7 mt_ventoux teejet omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
seaboard arm armv7:arm720t seaboard nvidia tegra20
ventana arm armv7:arm720t ventana nvidia tegra20
whistler arm armv7:arm720t whistler nvidia tegra20
+cardhu arm armv7:arm720t cardhu nvidia tegra30
+dalmore arm armv7:arm720t dalmore nvidia tegra114
colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20
u8500_href arm armv7 u8500 st-ericsson u8500
snowball arm armv7 snowball st-ericsson u8500
kzm9g arm armv7 kzm9g kmc rmobile
armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile
zynq arm armv7 zynq xilinx zynq
+zynq_dcc arm armv7 zynq xilinx zynq zynq:ZYNQ_DCC
socfpga_cyclone5 arm armv7 socfpga_cyclone5 altera socfpga
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
actux1_4_32 arm ixp actux1 - - actux1:FLASH2X2,RAM_32MB
MPC8308RDB powerpc mpc83xx mpc8308rdb freescale
MPC8313ERDB_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ
MPC8313ERDB_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ
-MPC8313ERDB_NAND_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ,NAND_U_BOOT
-MPC8313ERDB_NAND_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ,NAND_U_BOOT
+MPC8313ERDB_NAND_33 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_33MHZ,NAND
+MPC8313ERDB_NAND_66 powerpc mpc83xx mpc8313erdb freescale - MPC8313ERDB:SYS_66MHZ,NAND
MPC8315ERDB powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB
MPC8315ERDB_NAND powerpc mpc83xx mpc8315erdb freescale - MPC8315ERDB:NAND_U_BOOT
MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale
P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P5040DS powerpc mpc85xx corenet_ds freescale
BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH
+BSC9132QDS_NOR_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100
+BSC9132QDS_NOR_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133
+BSC9132QDS_SDCARD_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100
+BSC9132QDS_SDCARD_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133
+BSC9132QDS_SPIFLASH_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100
+BSC9132QDS_SPIFLASH_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx - stxssa
stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
T4240QDS powerpc mpc85xx t4qds freescale
T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+B4860QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860
+B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
+B4860QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+B4420QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420
+B4420QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
+B4420QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
xpedite520x powerpc mpc85xx - xes
xpedite537x powerpc mpc85xx - xes
xpedite550x powerpc mpc85xx - xes
grsim sparc leon3 - gaisler
gr_xc3s_1500 sparc leon3 - gaisler
coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0x01110000
-eNET x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000
-eNET_SRAM x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000
# Target ARCH CPU Board name Vendor SoC Options
########################################################################################################################
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 48cdd16dd21081c7890ff54513cec4701be24411..85279d5e7b828cd8994502535c57ac905146abb1 100644 (file)
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
printf("%-12s= %s\n", name, val);
}
+__maybe_unused
+static void print_eths(void)
+{
+ struct eth_device *dev;
+ int i = 0;
+
+ do {
+ dev = eth_get_dev_by_index(i);
+ if (dev) {
+ printf("eth%dname = %s\n", i, dev->name);
+ print_eth(i);
+ i++;
+ }
+ } while (dev);
+
+ printf("current eth = %s\n", eth_get_name());
+ printf("ip_addr = %s\n", getenv("ipaddr"));
+}
+
__maybe_unused
static void print_lnum(const char *name, unsigned long long value)
{
print_num("sram size ", (ulong)bd->bi_sramsize);
#endif
#if defined(CONFIG_CMD_NET)
- print_eth(0);
- printf("ip_addr = %s\n", getenv("ipaddr"));
+ print_eths();
#endif
- printf("baudrate = %u bps\n", (ulong)bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
}
#if defined(CONFIG_CMD_NET)
- print_eth(0);
- printf("ip_addr = %s\n", getenv("ipaddr"));
+ print_eths();
#endif
printf("baudrate = %u bps\n", bd->bi_baudrate);
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- print_num("TLB addr", gd->tlb_addr);
+ print_num("TLB addr", gd->arch.tlb_addr);
#endif
print_num("relocaddr", gd->relocaddr);
print_num("reloc off", gd->reloc_off);
print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
print_num("sp start ", gd->start_addr_sp);
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
print_num("FB base ", gd->fb_base);
+#endif
/*
* TODO: Currently only support for davinci SOC's is added.
* Remove this check once all the board implement this.
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
print_num("FB base ", gd->fb_base);
+#endif
return 0;
}
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 1b8a8c15610f68954643f967081d61ca8eee0e74..f0338babeba8f580a1f0fff7c77d3e590f137a6a 100644 (file)
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
#endif
#if defined(CONFIG_OF_LIBFDT)
-#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#endif
return CMD_RET_USAGE;
}
- if (images.state >= state) {
+ if (images.state < BOOTM_STATE_START ||
+ images.state >= state) {
printf("Trying to execute a command out of order\n");
return CMD_RET_USAGE;
}
diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c
index 9e2de34737f358fab0b9619b20b1e34ec0094e5c..6eec947fcb3ecbf572120b0b9fce7c0de2d94587 100644 (file)
--- a/common/cmd_fdt.c
+++ b/common/cmd_fdt.c
#include <linux/ctype.h>
#include <linux/types.h>
#include <asm/global_data.h>
-#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
diff --git a/common/cmd_immap.c b/common/cmd_immap.c
index 1f59c1e1d16745744c2bc41f5129f5a6f3bcdbd7..fdf9489b2e99270921240cf265c558b6afc81895 100644 (file)
--- a/common/cmd_immap.c
+++ b/common/cmd_immap.c
#if defined(CONFIG_8xx)
ulong clock = gd->cpu_clk;
#elif defined(CONFIG_8260)
- ulong clock = gd->brg_clk;
+ ulong clock = gd->arch.brg_clk;
#endif
printf ("BRG%d:", n);
diff --git a/common/cmd_time.c b/common/cmd_time.c
index 6dbdbbfbe7a3eeeef03d1880d53817d76b901a62..9808cd6699532bb6b29e785fc56338a9f79a7be6 100644 (file)
--- a/common/cmd_time.c
+++ b/common/cmd_time.c
#include <common.h>
#include <command.h>
-/*
- * TODO(clchiou): This function actually minics the bottom-half of the
- * run_command() function. Since this function has ARM-dependent timer
- * codes, we cannot merge it with the run_command() for now.
- */
-static int run_command_and_time_it(int flag, int argc, char * const argv[],
- ulong *cycles)
-{
- cmd_tbl_t *cmdtp = find_cmd(argv[0]);
- int retval = 0;
-
- if (!cmdtp) {
- printf("%s: command not found\n", argv[0]);
- return 1;
- }
- if (argc > cmdtp->maxargs)
- return CMD_RET_USAGE;
-
- /*
- * TODO(clchiou): get_timer_masked() is only defined in certain ARM
- * boards. We could use the new timer API that Graeme is proposing
- * so that this piece of code would be arch-independent.
- */
- *cycles = get_timer_masked();
- retval = cmdtp->cmd(cmdtp, flag, argc, argv);
- *cycles = get_timer_masked() - *cycles;
-
- return retval;
-}
-
static void report_time(ulong cycles)
{
ulong minutes, seconds, milliseconds;
{
ulong cycles = 0;
int retval = 0;
+ int repeatable;
if (argc == 1)
return CMD_RET_USAGE;
- retval = run_command_and_time_it(0, argc - 1, argv + 1, &cycles);
+ retval = cmd_process(0, argc - 1, argv + 1, &repeatable, &cycles);
report_time(cycles);
return retval;
diff --git a/common/command.c b/common/command.c
index 50c84292c166ef1fa5487997ce04298ae4fe834e..305a236faccb72604f760530da888d7467fdb146 100644 (file)
--- a/common/command.c
+++ b/common/command.c
}
enum command_ret_t cmd_process(int flag, int argc, char * const argv[],
- int *repeatable)
+ int *repeatable, ulong *ticks)
{
enum command_ret_t rc = CMD_RET_SUCCESS;
cmd_tbl_t *cmdtp;
/* If OK so far, then do the command */
if (!rc) {
+ if (ticks)
+ *ticks = get_timer(0);
rc = cmd_call(cmdtp, flag, argc, argv);
+ if (ticks)
+ *ticks = get_timer(*ticks);
*repeatable &= cmdtp->repeatable;
}
if (rc == CMD_RET_USAGE)
diff --git a/common/env_mmc.c b/common/env_mmc.c
index ce2167121004303ac4972f64cd31db37d16c6ccd..02bd5aed10cfeee50842cee00f9895050264c814 100644 (file)
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
#define CONFIG_ENV_OFFSET 0
#endif
-static int __mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
+__weak int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
{
*env_addr = CONFIG_ENV_OFFSET;
return 0;
}
-int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
- __attribute__((weak, alias("__mmc_get_env_addr")));
int env_init(void)
{
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 6b9fa0550f18e5694cd9f1e83911c52c089920d8..812acb401c176f81976fceb05e637fec024dc91c 100644 (file)
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
#include <linux/ctype.h>
#include <linux/types.h>
#include <asm/global_data.h>
-#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <exports.h>
u32 fdt_getprop_u32_default(const void *fdt, const char *path,
const char *prop, const u32 dflt)
{
- const u32 *val;
+ const fdt32_t *val;
int off;
off = fdt_path_offset(fdt, path);
if (nodeoff < 0)
return nodeoff;
- if ((!create) && (fdt_get_property(fdt, nodeoff, prop, 0) == NULL))
+ if ((!create) && (fdt_get_property(fdt, nodeoff, prop, NULL) == NULL))
return 0; /* create flag not set; so exit quietly */
return fdt_setprop(fdt, nodeoff, prop, val, len);
{
int nodeoffset;
int err, j, total;
- u32 tmp;
+ fdt32_t tmp;
const char *path;
uint64_t addr, size;
path = fdt_getprop(fdt, nodeoffset, "linux,initrd-start", NULL);
if ((path == NULL) || force) {
- tmp = __cpu_to_be32(initrd_start);
+ tmp = cpu_to_fdt32(initrd_start);
err = fdt_setprop(fdt, nodeoffset,
"linux,initrd-start", &tmp, sizeof(tmp));
if (err < 0) {
fdt_strerror(err));
return err;
}
- tmp = __cpu_to_be32(initrd_end);
+ tmp = cpu_to_fdt32(initrd_end);
err = fdt_setprop(fdt, nodeoffset,
"linux,initrd-end", &tmp, sizeof(tmp));
if (err < 0) {
void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
u32 val, int create)
{
- val = cpu_to_fdt32(val);
- do_fixup_by_path(fdt, path, prop, &val, sizeof(val), create);
+ fdt32_t tmp = cpu_to_fdt32(val);
+ do_fixup_by_path(fdt, path, prop, &tmp, sizeof(tmp), create);
}
void do_fixup_by_prop(void *fdt,
#endif
off = fdt_node_offset_by_prop_value(fdt, -1, pname, pval, plen);
while (off != -FDT_ERR_NOTFOUND) {
- if (create || (fdt_get_property(fdt, off, prop, 0) != NULL))
+ if (create || (fdt_get_property(fdt, off, prop, NULL) != NULL))
fdt_setprop(fdt, off, prop, val, len);
off = fdt_node_offset_by_prop_value(fdt, off, pname, pval, plen);
}
const char *pname, const void *pval, int plen,
const char *prop, u32 val, int create)
{
- val = cpu_to_fdt32(val);
- do_fixup_by_prop(fdt, pname, pval, plen, prop, &val, 4, create);
+ fdt32_t tmp = cpu_to_fdt32(val);
+ do_fixup_by_prop(fdt, pname, pval, plen, prop, &tmp, 4, create);
}
void do_fixup_by_compat(void *fdt, const char *compat,
#endif
off = fdt_node_offset_by_compatible(fdt, -1, compat);
while (off != -FDT_ERR_NOTFOUND) {
- if (create || (fdt_get_property(fdt, off, prop, 0) != NULL))
+ if (create || (fdt_get_property(fdt, off, prop, NULL) != NULL))
fdt_setprop(fdt, off, prop, val, len);
off = fdt_node_offset_by_compatible(fdt, off, compat);
}
void do_fixup_by_compat_u32(void *fdt, const char *compat,
const char *prop, u32 val, int create)
{
- val = cpu_to_fdt32(val);
- do_fixup_by_compat(fdt, compat, prop, &val, 4, create);
+ fdt32_t tmp = cpu_to_fdt32(val);
+ do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create);
}
/*
*/
static int get_cells_len(void *blob, char *nr_cells_name)
{
- const u32 *cell;
+ const fdt32_t *cell;
cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
if (cell && fdt32_to_cpu(*cell) == 2)
}
}
+#define MEMORY_BANKS_MAX 4
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
{
int err, nodeoffset;
int addr_cell_len, size_cell_len, len;
- u8 tmp[banks * 16]; /* Up to 64-bit address + 64-bit size */
+ u8 tmp[MEMORY_BANKS_MAX * 16]; /* Up to 64-bit address + 64-bit size */
int bank;
+ if (banks > MEMORY_BANKS_MAX) {
+ printf("%s: num banks %d exceeds hardcoded limit %d."
+ " Recompile with higher MEMORY_BANKS_MAX?\n",
+ __FUNCTION__, banks, MEMORY_BANKS_MAX);
+ return -1;
+ }
+
err = fdt_check_header(blob);
if (err < 0) {
printf("%s: %s\n", __FUNCTION__, fdt_strerror(err));
}
/* Helper to read a big number; size is in cells (not bytes) */
-static inline u64 of_read_number(const __be32 *cell, int size)
+static inline u64 of_read_number(const fdt32_t *cell, int size)
{
u64 r = 0;
while (size--)
- r = (r << 32) | be32_to_cpu(*(cell++));
+ r = (r << 32) | fdt32_to_cpu(*(cell++));
return r;
}
/* Debug utility */
#ifdef DEBUG
-static void of_dump_addr(const char *s, const u32 *addr, int na)
+static void of_dump_addr(const char *s, const fdt32_t *addr, int na)
{
printf("%s", s);
while(na--)
printf("\n");
}
#else
-static void of_dump_addr(const char *s, const u32 *addr, int na) { }
+static void of_dump_addr(const char *s, const fdt32_t *addr, int na) { }
#endif
/* Callbacks for bus specific translators */
const char *addresses;
void (*count_cells)(void *blob, int parentoffset,
int *addrc, int *sizec);
- u64 (*map)(u32 *addr, const u32 *range,
+ u64 (*map)(fdt32_t *addr, const fdt32_t *range,
int na, int ns, int pna);
- int (*translate)(u32 *addr, u64 offset, int na);
+ int (*translate)(fdt32_t *addr, u64 offset, int na);
};
/* Default translator (generic bus) */
static void of_bus_default_count_cells(void *blob, int parentoffset,
int *addrc, int *sizec)
{
- const u32 *prop;
+ const fdt32_t *prop;
if (addrc) {
prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL);
if (prop)
- *addrc = be32_to_cpup((u32 *)prop);
+ *addrc = be32_to_cpup(prop);
else
*addrc = 2;
}
if (sizec) {
prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL);
if (prop)
- *sizec = be32_to_cpup((u32 *)prop);
+ *sizec = be32_to_cpup(prop);
else
*sizec = 1;
}
}
-static u64 of_bus_default_map(u32 *addr, const u32 *range,
+static u64 of_bus_default_map(fdt32_t *addr, const fdt32_t *range,
int na, int ns, int pna)
{
u64 cp, s, da;
return da - cp;
}
-static int of_bus_default_translate(u32 *addr, u64 offset, int na)
+static int of_bus_default_translate(fdt32_t *addr, u64 offset, int na)
{
u64 a = of_read_number(addr, na);
memset(addr, 0, na * 4);
a += offset;
if (na > 1)
- addr[na - 2] = a >> 32;
- addr[na - 1] = a & 0xffffffffu;
+ addr[na - 2] = cpu_to_fdt32(a >> 32);
+ addr[na - 1] = cpu_to_fdt32(a & 0xffffffffu);
return 0;
}
};
static int of_translate_one(void * blob, int parent, struct of_bus *bus,
- struct of_bus *pbus, u32 *addr,
+ struct of_bus *pbus, fdt32_t *addr,
int na, int ns, int pna, const char *rprop)
{
- const u32 *ranges;
+ const fdt32_t *ranges;
int rlen;
int rone;
u64 offset = OF_BAD_ADDR;
* to translate addresses that aren't supposed to be translated in
* the first place. --BenH.
*/
- ranges = (u32 *)fdt_getprop(blob, parent, rprop, &rlen);
+ ranges = fdt_getprop(blob, parent, rprop, &rlen);
if (ranges == NULL || rlen == 0) {
offset = of_read_number(addr, na);
memset(addr, 0, pna * 4);
* that can be mapped to a cpu physical address). This is not really specified
* that way, but this is traditionally the way IBM at least do things
*/
-u64 __of_translate_address(void *blob, int node_offset, const u32 *in_addr,
- const char *rprop)
+static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in_addr,
+ const char *rprop)
{
int parent;
struct of_bus *bus, *pbus;
- u32 addr[OF_MAX_ADDR_CELLS];
+ fdt32_t addr[OF_MAX_ADDR_CELLS];
int na, ns, pna, pns;
u64 result = OF_BAD_ADDR;
return result;
}
-u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr)
+u64 fdt_translate_address(void *blob, int node_offset, const fdt32_t *in_addr)
{
return __of_translate_address(blob, node_offset, in_addr, "ranges");
}
{
int len, off = fdt_node_offset_by_compatible(blob, -1, compat);
while (off != -FDT_ERR_NOTFOUND) {
- u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
+ const fdt32_t *reg = fdt_getprop(blob, off, "reg", &len);
if (reg) {
if (compat_off == fdt_translate_address(blob, off, reg))
return off;
int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr)
{
const char *path;
- const u32 *reg;
+ const fdt32_t *reg;
int node, len;
u64 dt_addr;
{
int size;
u32 naddr;
- const u32 *prop;
+ const fdt32_t *prop;
prop = fdt_getprop(fdt, node, "#address-cells", &size);
if (prop && size == 4)
- naddr = *prop;
+ naddr = be32_to_cpup(prop);
else
naddr = 2;
diff --git a/common/hush.c b/common/hush.c
index eb6c879c534acc91404766a0599e116fd4e7cc3d..cc81c9c3e05fb57666944d6a89e9e4245bb62a5e 100644 (file)
--- a/common/hush.c
+++ b/common/hush.c
}
/* Process the command */
return cmd_process(flag, child->argc, child->argv,
- &flag_repeat);
+ &flag_repeat, NULL);
#endif
}
#ifndef __U_BOOT__
diff --git a/common/image.c b/common/image.c
index 95498e6186e2290cc79a6cb1c9ac84b446b3a6fb..ae1a9d3bd15bcdb14a4e58ca4a900c2dfcb1536d 100644 (file)
--- a/common/image.c
+++ b/common/image.c
#include <image.h>
#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
-#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#endif
diff --git a/common/main.c b/common/main.c
index 5d8454ea0e5a6407882e4b0e06a27426270036f2..e2d2e09bf9f750bc278fa8d5f452c63ccc6ad1e2 100644 (file)
--- a/common/main.c
+++ b/common/main.c
int abortboot(int bootdelay)
{
int abort = 0;
+ unsigned long ts;
#ifdef CONFIG_MENUPROMPT
printf(CONFIG_MENUPROMPT);
#endif
while ((bootdelay > 0) && (!abort)) {
- int i;
-
--bootdelay;
- /* delay 100 * 10ms */
- for (i=0; !abort && i<100; ++i) {
+ /* delay 1000 ms */
+ ts = get_timer(0);
+ do {
if (tstc()) { /* we got a key press */
abort = 1; /* don't auto boot */
bootdelay = 0; /* no more delay */
break;
}
udelay(10000);
- }
+ } while (!abort && get_timer(ts) < 1000);
printf("\b\b\b%2d ", bootdelay);
}
continue;
}
- if (cmd_process(flag, argc, argv, &repeatable))
+ if (cmd_process(flag, argc, argv, &repeatable, NULL))
rc = -1;
/* Did the user stop this? */
diff --git a/common/spl/spl.c b/common/spl/spl.c
index ff9ba7b0a59ef5cff6fddbb7771da8b6d63e26ee..6a5a1365a145af5e05f3e5063bb876873f2d8c25 100644 (file)
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
spl_net_load_image(NULL);
#endif
break;
+#endif
+#ifdef CONFIG_SPL_USBETH_SUPPORT
+ case BOOT_DEVICE_USBETH:
+ spl_net_load_image("usb_ether");
+ break;
#endif
default:
debug("SPL: Un-supported Boot Device\n");
diff --git a/common/stdio.c b/common/stdio.c
index 97ff9cf4a6a49f533f90240e9469bd4063986a11..5d5117c0ed838195a2caad7c28c128247771cd92 100644 (file)
--- a/common/stdio.c
+++ b/common/stdio.c
/* Initialize the list */
INIT_LIST_HEAD(&(devs.list));
-#ifdef CONFIG_ARM_DCC_MULTI
+#ifdef CONFIG_ARM_DCC
drv_arm_dcc_init ();
#endif
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
diff --git a/doc/README.b4860qds b/doc/README.b4860qds
--- /dev/null
+++ b/doc/README.b4860qds
@@ -0,0 +1,330 @@
+Overview
+--------
+The B4860QDS is a Freescale reference board that hosts the B4860 SoC (and variants).
+
+B4860 Overview
+-------------
+The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
+StarCore and Power Architecture® cores. It targets the broadband wireless
+infrastructure and builds upon the proven success of the existing multicore
+DSPs and Power CPUs. It is designed to bolster the rapidly changing and
+expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
+
+The B4860 is a highly-integrated StarCore and Power Architecture processor that
+contains:
+. Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
+clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for
+wireless base station applications
+. Four dual-thread e6500 Power Architecture processors organized in one cluster-each
+core runs up to 1.8 GHz
+. Two DDR3/3L controllers for high-speed, industry-standard memory interface each
+runs at up to 1866.67 MHz
+. MAPLE-B3 hardware acceleration-for forward error correction schemes including
+Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
+equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
+FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
+acceleration
+. CoreNet fabric that fully supports coherency using MESI protocol between the
+ e6500 cores, SC3900 FVP cores, memories and external interfaces.
+ CoreNet fabric interconnect runs at 667 MHz and supports coherent and
+ non-coherent out of order transactions with prioritization and bandwidth
+ allocation amongst CoreNet endpoints.
+. Data Path Acceleration Architecture, which includes the following:
+. Frame Manager (FMan), which supports in-line packet parsing and general
+ classification to enable policing and QoS-based packet distribution
+. Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
+ of queue management, task management, load distribution, flow ordering, buffer
+ management, and allocation tasks from the cores
+. Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec,
+ SSL, and 802.16
+. RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
+ outbound). Supports types 5, 6 (outbound only)
+. Large internal cache memory with snooping and stashing capabilities for
+ bandwidth saving and high utilization of processor elements. The 9856-Kbyte
+ internal memory space includes the following:
+. 32 Kbyte L1 ICache per e6500/SC3900 core
+. 32 Kbyte L1 DCache per e6500/SC3900 core
+. 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
+. 2048 Kbyte unified L2 cache for the e6500 cluster
+. Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
+. Sixteen 10-GHz SerDes lanes serving:
+. Two Serial RapidIO interfaces.
+ - Each supports up to 4 lanes and a total of up to 8 lanes
+. Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less
+ antenna connection
+. Two 10-Gbit Ethernet controllers (10GEC)
+. Six 1G/2.5-Gbit Ethernet controllers for network communications
+. PCI Express controller
+. Debug (Aurora)
+. Two OCeaN DMAs
+. Various system peripherals
+. 182 32-bit timers
+
+B4860QDS Overview
+------------------
+- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB
+ of memory in two ranks of 2 GB.
+- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB
+ of memory. Single rank.
+- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch
+ VSC3316
+- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308
+- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
+ B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable.
+- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors
+ for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for
+ AMC mode.
+- The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The
+ RCW source is set by appropriate DIP-switches:
+- 16-bit NOR Flash / PROMJet
+- QIXIS 8-bit NOR Flash Emulator
+- 8-bit NAND Flash
+- 24-bit SPI Flash
+- Long address I2C EEPROM
+- Available debug interfaces are:
+ - On-board eCWTAP controller with ETH and USB I/F
+ - JTAG/COP 16-pin header for any external TAP controller
+ - External JTAG source over AMC to support B2B configuration
+ - 70-pin Aurora debug connector
+- QIXIS (FPGA) logic:
+ - 2 KB internal memory space including
+- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1,2 and
+ RTCCLK.
+- Two 8T49N222A SerDes ref clock devices support two SerDes port clock frequency - total four
+ refclk, including CPRI clock scheme.
+
+B4420 Personality
+--------------------
+
+B4420 Personality
+--------------------
+B4420 is a reduced personality of B4860 with less core/clusters(both SC3900 and e6500), less DDR
+controllers, less serdes lanes, less SGMII interfaces and reduced target frequencies.
+
+Key differences between B4860 and B4420
+----------------------------------------
+
+B4420 has:
+1. Less e6500 cores: 1 cluster with 2 e6500 cores
+2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster.
+3. Single DDRC
+4. 2X 4 lane serdes
+5. 3 SGMII interfaces
+6. no sRIO
+7. no 10G
+
+B4860QDS Default Settings
+-------------------------
+
+Switch Settings
+----------------
+
+SW1 OFF [0] OFF [1] OFF [1] OFF [0] OFF [1] OFF [0] OFF [1] OFF [1]
+SW2 ON ON ON ON ON ON OFF OFF
+SW3 OFF OFF OFF ON OFF OFF ON OFF
+SW5 OFF OFF OFF OFF OFF OFF ON ON
+
+Note: PCIe slots modes: All the PCIe devices work as Root Complex.
+Note: Boot location: NOR flash.
+
+SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
+66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
+
+a) NAND boot
+ SW1 [1.1] = 0
+ SW2 [1.1] = 1
+ SW3 [1:4] = 0001
+b) NOR boot
+ SW1 [1.1] = 1
+ SW2 [1.1] = 0
+ SW3 [1:4] = 1000.
+
+B4420QDS Default Settings
+-------------------------
+
+Switch Settings
+----------------
+SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
+SW2 ON OFF ON OFF ON ON OFF OFF
+SW3 OFF OFF OFF ON OFF OFF ON OFF
+SW5 OFF OFF OFF OFF OFF OFF ON ON
+
+Note: PCIe slots modes: All the PCIe devices work as Root Complex.
+Note: Boot location: NOR flash.
+
+SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
+66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
+
+a) NAND boot
+ SW1 [1.1] = 0
+ SW2 [1.1] = 1
+ SW3 [1:4] = 0001
+b) NOR boot
+ SW1 [1.1] = 1
+ SW2 [1.1] = 0
+ SW3 [1:4] = 1000.
+
+Memory map on B4860QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+Start Address End Address Description Size
+0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
+0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
+0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
+0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
+0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
+0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
+0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
+0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
+0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
+0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
+0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
+0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
+0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4 MB
+0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
+0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
+0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
+0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
+0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
+0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB
+0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB
+
+Memory map on B4420QDS
+----------------------
+The addresses in brackets are physical addresses.
+
+Start Address End Address Description Size
+0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB
+0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB
+0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB
+0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB
+0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB
+0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB
+0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB
+0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB
+0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB
+0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB
+0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB
+0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB
+0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4 MB
+0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB
+0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB
+0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB
+0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB
+0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB
+0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB
+
+
+NOR Flash memory Map on B4860 and B4420QDS
+------------------------------------------
+ Start End Definition Size
+0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB
+0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB
+0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB
+0xEF300000 0xEFF3FFFF rootfs (alternate bank) 12MB + 256KB
+0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
+0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
+0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
+0xEDF80000 0xEDFFFFFF u-boot (alternate bank) 512KB
+0xEDF60000 0xEDF7FFFF u-boot env (alternate bank) 128KB
+0xEDF40000 0xEDF5FFFF FMAN ucode (alternate bank) 128KB
+0xED300000 0xEDF3FFFF rootfs (current bank) 12MB+256MB
+0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
+0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
+0xEC000000 0xEC01FFFF RCW (current bank) 128KB
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to both B4860QDS and B4420QDS.
+
+1. U-boot environment variable hwconfig
+ The default hwconfig is:
+ hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
+ dr_mode=host,phy_type=ulpi
+ Note: For USB gadget set "dr_mode=peripheral"
+
+2. FMAN Ucode versions
+ fsl_fman_ucode_B4860_106_3_6.bin
+
+3. Switching to alternate bank
+ Commands for switching to alternate bank.
+
+ 1. To change from vbank0 to vbank2
+ => qixis_reset altbank (it will boot using vbank2)
+
+ 2.To change from vbank2 to vbank0
+ => qixis reset (it will boot using vbank0)
+
+4. To change personality of board
+ For changing personality from B4860 to B4420
+ 1)Boot from vbank0
+ 2)Flash vbank2 with b4420 rcw and u-boot
+ 3)Give following commands to uboot prompt
+ => mw.b ffdf0040 0x30;
+ => mw.b ffdf0010 0x00;
+ => mw.b ffdf0062 0x02;
+ => mw.b ffdf0050 0x02;
+ => mw.b ffdf0010 0x30;
+ => reset
+
+ Note: Power off cycle will lead to default switch settings.
+ Note: 0xffdf0000 is the address of the QIXIS FPGA.
+
+5. Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
+
+ To change from NOR to NAND boot give following command on uboot prompt
+ => mw.b ffdf0040 0x30
+ => mw.b ffdf0010 0x00
+ => mw.b 0xffdf0050 0x08
+ => mw.b 0xffdf0060 0x82
+ => mw.b ffdf0061 0x00
+ => mw.b ffdf0010 0x30
+ => reset
+
+ To change from NAND to NOR boot give following command on uboot prompt:
+ => mw.b ffdf0040 0x30
+ => mw.b ffdf0010 0x00
+ => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
+ => mw.b 0xffdf0060 0x12
+ => mw.b ffdf0061 0x01
+ => mw.b ffdf0010 0x30
+ => reset
+
+ Note: Power off cycle will lead to default switch settings.
+ Note: 0xffdf0000 is the address of the QIXIS FPGA.
+
+6. Ethernet interfaces for B4860QDS
+ Serdes protocosl tested:
+ 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
+ 0x2a, 0xb2 (serdes1, serdes2)
+
+ When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
+ SGMII on SGMII riser card.
+ Under U-boot these network interfaces are recognized as:
+ FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
+
+ On Linux the interfaces are renamed as:
+ . eth2 -> fm1-gb2
+ . eth3 -> fm1-gb3
+ . eth4 -> fm1-gb4
+ . eth5 -> fm1-gb5
+
+7. RCW and Ethernet interfaces for B4420QDS
+ Serdes protocosl tested:
+ 0x18, 0x9e (serdes1, serdes2)
+
+ Under U-boot these network interfaces are recognized as:
+ FM1@DTSEC3, FM1@DTSEC4 and e1000#0.
+
+ On Linux the interfaces are renamed as:
+ . eth2 -> fm1-gb2
+ . eth3 -> fm1-gb3
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 3992640ba30546e3e3028b48b1fac8944b6c75e4..1243a1222760a8293b963fb5aca6a60ddcecb0b0 100644 (file)
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -263,23 +263,38 @@ Reference http://www.samsung.com/global/business/semiconductor/products/dram/dow
Interactive DDR debugging
===========================
-For DDR parameter tuning up and debugging, the interactive DDR debugging can
-be activated by saving an environment variable "ddr_interactive". The value
-doesn't matter. Once activated, U-boot prompts "FSL DDR>" before enabling DDR
-controller. The available commands can be seen by typing "help".
+For DDR parameter tuning up and debugging, the interactive DDR debugger can
+be activated by setting the environment variable "ddr_interactive" to any
+value. (The value of ddr_interactive may have a meaning in the future, but,
+for now, the presence of the variable will cause the debugger to run.) Once
+activated, U-boot will show the prompt "FSL DDR>" before enabling the DDR
+controller. The available commands are printed by typing "help".
+
+Another way to enter the interactive DDR debugger without setting the
+environment variable is to send the 'd' character early during the boot
+process. To save booting time, no additional delay is added, so the window
+to send the key press is very short -- basically, it is the time before the
+memory controller code starts to run. For example, when rebooting from
+within u-boot, the user must press 'd' IMMEDIATELY after hitting enter to
+initiate a 'reset' command. In case of power on/reset, the user can hold
+down the 'd' key while applying power or hitting the board's reset button.
The example flow of using interactive debugging is
type command "compute" to calculate the parameters from the default
type command "print" with arguments to show SPD, options, registers
type command "edit" with arguments to change any if desired
+type command "copy" with arguments to copy controller/dimm settings
type command "go" to continue calculation and enable DDR controller
+
+Additional commands to restart the debugging are:
type command "reset" to reset the board
type command "recompute" to reload SPD and start over
Note, check "next_step" to show the flow. For example, after edit opts, the
next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
-STEP_PROGRAM_REGS. Upon issuing command "go", DDR controller will be enabled
-with current setting without further calculation.
+STEP_PROGRAM_REGS. Upon issuing command "go", the debugger will program the
+DDR controller with the current setting without further calculation and then
+exit to resume the booting of the machine.
The detail syntax for each commands are
@@ -306,6 +321,10 @@ edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
byte number if the object is SPD
<value> - decimal or heximal (prefixed with 0x) numbers
+copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>
+ same as for "edit" command
+ DIMM numbers ignored for commonparms, opts, and regs
+
reset
no arguement - reset the board
FSL DDR>compute
Detected UDIMM UG51U6400N8SU-ACF
- SL DDR>print
+ FSL DDR>print
print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
FSL DDR>print dimmparms
DIMM parameters: Controller=0 DIMM=0
diff --git a/doc/README.mips b/doc/README.mips
index 85dea400c8fc1e4c8b85f6bcd2886cba21f4f720..f4f770b99fb281333a6cc3a5e4f848f7a6566969 100644 (file)
--- a/doc/README.mips
+++ b/doc/README.mips
Known Issues
------------
- * Little endian build problem
-
- If use non-ELDK toolchains, -EB will be set to CPPFLAGS. Therefore all
- objects will be generated in big-endian format.
-
* Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
Cache will be disabled before entering the loaded ELF image without
* Due to cache initialization issues, the DRAM on board must be
initialized in board specific assembler language before the cache init
code is run -- that is, initialize the DRAM in lowlevel_init().
+
+ * get rid of CONFIG_MANUAL_RELOC
+
+ * centralize/share more CPU code of MIPS32, MIPS64 and XBurst
+
+ * support Qemu Malta
diff --git a/board/qemu-mips/README b/doc/README.qemu-mips
similarity index 88%
rename from board/qemu-mips/README
rename to doc/README.qemu-mips
index 9fd97e1249a915dc9befd6414bba0a1a0089a156..1fdfbab67747a502fdda615767f8c87b8597bbcf 100644 (file)
rename from board/qemu-mips/README
rename to doc/README.qemu-mips
index 9fd97e1249a915dc9befd6414bba0a1a0089a156..1fdfbab67747a502fdda615767f8c87b8597bbcf 100644 (file)
--- a/board/qemu-mips/README
+++ b/doc/README.qemu-mips
Limitations & comments
----------------------
-Supports the "-m mips" configuration of qemu: serial,NE2000,IDE.
-Support is big endian only for now (or at least this is what I tested).
+Supports the "-M mips" configuration of qemu: serial,NE2000,IDE.
+Supports little and big endian as well as 32 bit and 64 bit.
Derived from au1x00 with a lot of things cut out.
Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
I) Example usage:
-# ln -s u-boot.bin mips_bios.bin
-start it:
-qemu-system-mips -L . /dev/null -nographic
+Using u-boot.bin as ROM (replaces Qemu monitor):
-or
+32 bit, big endian:
+# make qemu_mips
+# qemu-system-mips -M mips -bios u-boot.bin -nographic
+
+32 bit, little endian:
+# make qemu_mipsel
+# qemu-system-mipsel -M mips -bios u-boot.bin -nographic
+
+64 bit, big endian:
+# make qemu_mips64
+# qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
+
+64 bit, little endian:
+# make qemu_mips64el
+# qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
+
+or using u-boot.bin from emulated flash:
if you use a qemu version after commit 4224
create image:
# dd of=flash bs=1k count=4k if=/dev/zero
# dd of=flash bs=1k conv=notrunc if=u-boot.bin
-start it:
-# qemu-system-mips -M mips -pflash flash -monitor null -nographic
+start it (see above):
+# qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic
2) Download kernel + initrd
diff --git a/doc/SPL/README.am335x-network b/doc/SPL/README.am335x-network
--- /dev/null
@@ -0,0 +1,92 @@
+USING AM335x NETBOOT FEATURE
+
+ Some boards (like TI AM335x based ones) have quite big on-chip RAM and
+have support for booting via network in ROM. The following describes
+how to setup network booting and then optionally use this support to flash
+NAND and bricked (empty) board with only a network cable.
+
+ I. Building the required images
+ 1. You have to enable generic SPL configuration options (see
+docs/README.SPL) as well as CONFIG_SPL_NET_SUPPORT,
+CONFIG_ETH_SUPPORT, CONFIG_SPL_LIBGENERIC_SUPPORT and
+CONFIG_SPL_LIBCOMMON_SUPPORT in your board configuration file to build
+SPL with support for booting over the network. Also you have to enable
+the driver for the NIC used and CONFIG_SPL_BOARD_INIT option if your
+board needs some board-specific initialization (TI AM335x EVM does).
+If you want SPL to use some Vendor Class Identifier (VCI) you can set
+one with CONFIG_SPL_NET_VCI_STRING option. am335x_evm configuration
+comes with support for network booting preconfigured.
+ 2. Define CONFIG_BOOTCOMMAND for your board to load and run debrick
+script after boot:
+#define CONFIG_BOOTCOMMAND \
+ "setenv autoload no; " \
+ "bootp; " \
+ "if tftp 80000000 debrick.scr; then " \
+ "source 80000000; " \
+ "fi"
+(Or create additional board configuration with such option).
+ 3. Build U-Boot as usual
+ $ make <your_board_name>
+ You will need u-boot.img and spl/u-boot.bin images to perform
+network boot. Copy them to u-boot-restore.img and
+u-boot-spl-restore.bin respectively to distinguish this version
+(with automatic restore running) from the main one.
+
+ II. Host configuration.
+ 1. Setup DHCP server (recommended server is ISC DHCPd).
+ - Install DHCP server and setup it to listen on the interface you
+chose to connect to the board (usually configured in
+/etc/default/dhcpd or /etc/default/isc-dhcp-server). Make sure there
+are no other active DHCP servers in the same network segment.
+ - Edit your dhcpd.conf and subnet declaration matching the address
+on the interface. Specify the range of assigned addresses and bootfile
+to use. IMPORTANT! Both RBL and SPL use the image filename provided
+in the BOOTP reply but obviously they need different images (RBL needs
+raw SPL image -- u-boot-spl-restore.bin while SPL needs main U-Boot
+image -- u-boot-restore.img). So you have to configure DHCP server to
+provide different image filenames to RBL and SPL (and possibly another
+one to main U-Boot). This can be done by checking Vendor Class
+Identifier (VCI) set by BOOTP client (RBL sets VCI to "DM814x ROM v1.0"
+and you can set VCI used by SPL with CONFIG_SPL_NET_VCI_STRING option,
+see above).
+ - If you plan to use TFTP server on another machine you have to set
+server-name option to point to it.
+ - Here is sample configuration for ISC DHCPd, assuming the interface
+used to connect to the board is eth0, and it has address 192.168.8.1:
+
+subnet 192.168.8.0 netmask 255.255.255.0 {
+ range dynamic-bootp 192.168.8.100 192.168.8.199;
+
+ if substring (option vendor-class-identifier, 0, 10) = "DM814x ROM" {
+ filename "u-boot-spl-restore.bin";
+ } elsif substring (option vendor-class-identifier, 0, 17) = "AM335x U-Boot SPL" {
+ filename "u-boot-restore.img";
+ } else {
+ filename "uImage";
+ }
+}
+
+ 2. Setup TFTP server.
+ Install TFTP server and put image files to it's root directory
+(likely /tftpboot or /var/lib/tftpboot or /srv/tftp). You will need
+u-boot.img and spl/u-boot-spl-bin files from U-Boot build directory.
+
+ III. Reflashing (debricking) the board.
+ 1. Write debrick script. You will need to write a script that will
+be executed after network boot to perform actual rescue actions. You
+can use usual U-Boot commands from this script: tftp to load additional
+files, nand erase/nand write to erase/write the NAND flash.
+
+ 2. Create script image from your script. From U-Boot build directory:
+
+$ ./tools/mkimage -A arm -O U-Boot -C none -T script -d <your script> debrick.scr
+
+This will create debrick.scr file with your script inside.
+
+ 3. Copy debrick.scr to TFTP root directory. You also need to copy
+there all the files your script tries to load via TFTP. Example script
+loads u-boot.img and MLO. You have to create these files doing regular
+(not restore_flash) build and copy them to tftpboot directory.
+
+ 4. Boot the board from the network, U-Boot will load debrick script
+and run it after boot.
index 247cf060e43ef4695cb4f5e81dd200ba0105c511..bf29cbbb7a838b4db49b323a9db06942a07fc1ea 100644 (file)
writeb(val, base + off);
writeb(val >> 8, base + off + 1);
#endif
- }
- out16(base + off, val);
+ } else
+ out16(base + off, val);
}
static u16 ace_readw(unsigned off)
}
static unsigned long systemace_read(int dev, unsigned long start,
- unsigned long blkcnt, void *buffer);
+ lbaint_t blkcnt, void *buffer);
static block_dev_desc_t systemace_dev = { 0 };
* number of blocks read. A zero return indicates an error.
*/
static unsigned long systemace_read(int dev, unsigned long start,
- unsigned long blkcnt, void *buffer)
+ lbaint_t blkcnt, void *buffer)
{
int retry;
unsigned blk_countdown;
index 84d2b77d926d4be998402173ea831b1df78d6b25..271b8d93f4352b1471e938169e00940ef84884c1 100644 (file)
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
+#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
+static const struct pinmux_config gpio_pinmux[] = {
+ { pinmux(13), 8, 6 }, /* GP0[0] */
+ { pinmux(13), 8, 7 },
+ { pinmux(14), 8, 0 },
+ { pinmux(14), 8, 1 },
+ { pinmux(14), 8, 2 },
+ { pinmux(14), 8, 3 },
+ { pinmux(14), 8, 4 },
+ { pinmux(14), 8, 5 },
+ { pinmux(14), 8, 6 },
+ { pinmux(14), 8, 7 },
+ { pinmux(15), 8, 0 },
+ { pinmux(15), 8, 1 },
+ { pinmux(15), 8, 2 },
+ { pinmux(15), 8, 3 },
+ { pinmux(15), 8, 4 },
+ { pinmux(15), 8, 5 },
+ { pinmux(15), 8, 6 }, /* GP1[0] */
+ { pinmux(15), 8, 7 },
+ { pinmux(16), 8, 0 },
+ { pinmux(16), 8, 1 },
+ { pinmux(16), 8, 2 },
+ { pinmux(16), 8, 3 },
+ { pinmux(16), 8, 4 },
+ { pinmux(16), 8, 5 },
+ { pinmux(16), 8, 6 },
+ { pinmux(16), 8, 7 },
+ { pinmux(17), 8, 0 },
+ { pinmux(17), 8, 1 },
+ { pinmux(17), 8, 2 },
+ { pinmux(17), 8, 3 },
+ { pinmux(17), 8, 4 },
+ { pinmux(17), 8, 5 },
+ { pinmux(17), 8, 6 }, /* GP2[0] */
+ { pinmux(17), 8, 7 },
+ { pinmux(18), 8, 0 },
+ { pinmux(18), 8, 1 },
+ { pinmux(18), 8, 2 },
+ { pinmux(18), 8, 3 },
+ { pinmux(18), 8, 4 },
+ { pinmux(18), 8, 5 },
+ { pinmux(18), 8, 6 },
+ { pinmux(18), 8, 7 },
+ { pinmux(19), 8, 0 },
+ { pinmux(9), 8, 2 },
+ { pinmux(9), 8, 3 },
+ { pinmux(9), 8, 4 },
+ { pinmux(9), 8, 5 },
+ { pinmux(9), 8, 6 },
+ { pinmux(10), 8, 1 }, /* GP3[0] */
+ { pinmux(10), 8, 2 },
+ { pinmux(10), 8, 3 },
+ { pinmux(10), 8, 4 },
+ { pinmux(10), 8, 5 },
+ { pinmux(10), 8, 6 },
+ { pinmux(10), 8, 7 },
+ { pinmux(11), 8, 0 },
+ { pinmux(11), 8, 1 },
+ { pinmux(11), 8, 2 },
+ { pinmux(11), 8, 3 },
+ { pinmux(11), 8, 4 },
+ { pinmux(9), 8, 7 },
+ { pinmux(2), 8, 6 },
+ { pinmux(11), 8, 5 },
+ { pinmux(11), 8, 6 },
+ { pinmux(12), 8, 4 }, /* GP4[0] */
+ { pinmux(12), 8, 5 },
+ { pinmux(12), 8, 6 },
+ { pinmux(12), 8, 7 },
+ { pinmux(13), 8, 0 },
+ { pinmux(13), 8, 1 },
+ { pinmux(13), 8, 2 },
+ { pinmux(13), 8, 3 },
+ { pinmux(13), 8, 4 },
+ { pinmux(13), 8, 5 },
+ { pinmux(11), 8, 7 },
+ { pinmux(12), 8, 0 },
+ { pinmux(12), 8, 1 },
+ { pinmux(12), 8, 2 },
+ { pinmux(12), 8, 3 },
+ { pinmux(9), 8, 1 },
+ { pinmux(7), 8, 3 }, /* GP5[0] */
+ { pinmux(7), 8, 4 },
+ { pinmux(7), 8, 5 },
+ { pinmux(7), 8, 6 },
+ { pinmux(7), 8, 7 },
+ { pinmux(8), 8, 0 },
+ { pinmux(8), 8, 1 },
+ { pinmux(8), 8, 2 },
+ { pinmux(8), 8, 3 },
+ { pinmux(8), 8, 4 },
+ { pinmux(8), 8, 5 },
+ { pinmux(8), 8, 6 },
+ { pinmux(8), 8, 7 },
+ { pinmux(9), 8, 0 },
+ { pinmux(7), 8, 1 },
+ { pinmux(7), 8, 2 },
+ { pinmux(5), 8, 1 }, /* GP6[0] */
+ { pinmux(5), 8, 2 },
+ { pinmux(5), 8, 3 },
+ { pinmux(5), 8, 4 },
+ { pinmux(5), 8, 5 },
+ { pinmux(5), 8, 6 },
+ { pinmux(5), 8, 7 },
+ { pinmux(6), 8, 0 },
+ { pinmux(6), 8, 1 },
+ { pinmux(6), 8, 2 },
+ { pinmux(6), 8, 3 },
+ { pinmux(6), 8, 4 },
+ { pinmux(6), 8, 5 },
+ { pinmux(6), 8, 6 },
+ { pinmux(6), 8, 7 },
+ { pinmux(7), 8, 0 },
+ { pinmux(1), 8, 0 }, /* GP7[0] */
+ { pinmux(1), 8, 1 },
+ { pinmux(1), 8, 2 },
+ { pinmux(1), 8, 3 },
+ { pinmux(1), 8, 4 },
+ { pinmux(1), 8, 5 },
+ { pinmux(1), 8, 6 },
+ { pinmux(1), 8, 7 },
+ { pinmux(2), 8, 0 },
+ { pinmux(2), 8, 1 },
+ { pinmux(2), 8, 2 },
+ { pinmux(2), 8, 3 },
+ { pinmux(2), 8, 4 },
+ { pinmux(2), 8, 5 },
+ { pinmux(0), 1, 0 },
+ { pinmux(0), 1, 1 },
+};
+#else
static const struct pinmux_config gpio_pinmux[] = {
{ pinmux(1), 8, 7 }, /* GP0[0] */
{ pinmux(1), 8, 6 },
{ pinmux(18), 8, 3 },
{ pinmux(18), 8, 2 },
};
+#endif
int gpio_request(unsigned gpio, const char *label)
{
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 3cb232fdd110c44ab391e38252b707a89c565fa2..1c7265d897eea8f97fbd6254e3da4208ec7a3560 100644 (file)
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
static unsigned int get_i2c_clock(int bus)
{
if (bus)
- return gd->i2c2_clk; /* I2C2 clock */
+ return gd->arch.i2c2_clk; /* I2C2 clock */
else
- return gd->i2c1_clk; /* I2C1 clock */
+ return gd->arch.i2c1_clk; /* I2C1 clock */
}
void
int i2c_set_bus_speed(unsigned int speed)
{
- unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk;
+ unsigned int i2c_clk = (i2c_bus_num == 1)
+ ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */
i2c_bus_speed[i2c_bus_num] =
diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c
index b907f7b379bb6c6bb02aabffdff363f4560bc23c..2a5f110e1df06638f15f89f5de9bf56c722517df 100644 (file)
--- a/drivers/i2c/mxs_i2c.c
+++ b/drivers/i2c/mxs_i2c.c
#define MXS_I2C_MAX_TIMEOUT 1000000
-void mxs_i2c_reset(void)
+static void mxs_i2c_reset(void)
{
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
int ret;
i2c_set_bus_speed(speed);
}
-void mxs_i2c_setup_read(uint8_t chip, int len)
+static void mxs_i2c_setup_read(uint8_t chip, int len)
{
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
}
-void mxs_i2c_write(uchar chip, uint addr, int alen,
+static void mxs_i2c_write(uchar chip, uint addr, int alen,
uchar *buf, int blen, int stop)
{
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
}
-int mxs_i2c_wait_for_ack(void)
+static int mxs_i2c_wait_for_ack(void)
{
struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
uint32_t tmp;
diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c
index a655a16d7555b4955faae01c53bcaf066c11366f..bcbe52af154c5cd18674caa1a671bc5bf41471a1 100644 (file)
--- a/drivers/input/ps2ser.c
+++ b/drivers/input/ps2ser.c
/* select clock sources */
psc->psc_clock_select = 0;
- baseclk = (gd->ipb_clk + 16) / 32;
+ baseclk = (gd->arch.ipb_clk + 16) / 32;
/* switch to UART mode */
psc->sicr = 0;
index 3d5c9c0f77ef9f3910590c7a36212675d2b17b56..b90f3e77698636a1fff74d01e930fa4d355e7468 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
- mmc->f_max = MIN(gd->sdhc_clk, 52000000);
+ mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
mmc->b_max = 0;
mmc_register(mmc);
cfg = malloc(sizeof(struct fsl_esdhc_cfg));
memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
- cfg->sdhc_clk = gd->sdhc_clk;
+ cfg->sdhc_clk = gd->arch.sdhc_clk;
return fsl_esdhc_initialize(bis, cfg);
}
#endif
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
- gd->sdhc_clk, 1);
+ gd->arch.sdhc_clk, 1);
do_fixup_by_compat(blob, compat, "status", "okay",
4 + 1, 1);
index 32b76e0e9072196802b75963293f7ca2fddca106..9288672c84cfbfb1ba8b076a03b2c58e54d63ffe 100644 (file)
.name = "S25FL129P_64K",
},
{
- .idcode1 = 0x2019,
+ .idcode1 = 0x0219,
.idcode2 = 0x4d01,
.pages_per_sector = 256,
.nr_sectors = 512,
index 30b626a39f8923a398f575cbbdb70abff2fb35f9..8a193449d0cda34b983feed97b4fa4b481321569 100644 (file)
.nr_sectors = 64,
.name = "M25P128",
},
+ {
+ .id = 0xba16,
+ .pages_per_sector = 256,
+ .nr_sectors = 64,
+ .name = "N25Q32",
+ },
+ {
+ .id = 0xbb16,
+ .pages_per_sector = 256,
+ .nr_sectors = 64,
+ .name = "N25Q32A",
+ },
+ {
+ .id = 0xba17,
+ .pages_per_sector = 256,
+ .nr_sectors = 128,
+ .name = "N25Q064",
+ },
+ {
+ .id = 0xbb17,
+ .pages_per_sector = 256,
+ .nr_sectors = 128,
+ .name = "N25Q64A",
+ },
{
.id = 0xba18,
.pages_per_sector = 256,
.nr_sectors = 512,
.name = "N25Q256",
},
+ {
+ .id = 0xbb19,
+ .pages_per_sector = 256,
+ .nr_sectors = 512,
+ .name = "N25Q256A",
+ },
};
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode)
index f6aab3d32f459d82d0a9e606f4382fe67981160f..441830216944ef035d233ee72afd8e13b4662e50 100644 (file)
.nr_blocks = 128,
.name = "W25Q80",
},
+ {
+ .id = 0x6017,
+ .nr_blocks = 128,
+ .name = "W25Q64DW",
+ },
};
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
index 7fbb50a562347ab5bca287979c681414d667bcf6..f191c79a25c26a84dc1c835795b9c4ffbff92ea0 100644 (file)
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
COBJS-$(CONFIG_PPC_P5020) += p5020.o
COBJS-$(CONFIG_PPC_P5040) += p5040.o
COBJS-$(CONFIG_PPC_T4240) += t4240.o
+COBJS-$(CONFIG_PPC_B4420) += b4860.o
COBJS-$(CONFIG_PPC_B4860) += b4860.o
endif
diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c
--- /dev/null
+++ b/drivers/net/fm/b4860.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+u32 port_to_devdisr[] = {
+ [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
+ [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
+ [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
+ [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
+ [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
+ [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
+ [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
+ [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr2 = in_be32(&gur->devdisr2);
+
+ return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+ if (is_device_disabled(port))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if ((port == FM1_10GEC1 || port == FM1_10GEC2)
+ && (is_serdes_configured(XAUI_FM1)))
+ return PHY_INTERFACE_MODE_XGMII;
+
+ /* Fix me need to handle RGMII here first */
+
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC3:
+ case FM1_DTSEC4:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII;
+ break;
+ default:
+ return PHY_INTERFACE_MODE_NONE;
+ }
+
+ return PHY_INTERFACE_MODE_NONE;
+}
index ad57d566be288acf3b8c5ecf2106c10658f54fda..427e0b8b46f2306d07eff51774bfa9990d45a6eb 100644 (file)
* and do not drop the Preamble.
*/
out_be32(&fec->eth->mii_speed,
- (((gd->ips_clk / 1000000) / 5) + 1) << 1);
+ (((gd->arch.ips_clk / 1000000) / 5) + 1) << 1);
/*
* Reset PHY, then delay 300ns
index 3d180db7498b7d0f9bf186035c6f11d4ef6d0437..1093ba59dac1e4d4ffd7228573315e88814224a7 100644 (file)
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
+ * No MII for 7-wire mode
*/
- fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
+ fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
}
if (fec->xcv_type != SEVENWIRE) {
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
+ * No MII for 7-wire mode
*/
- fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
+ fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
}
#if (DEBUG & 0x3)
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
+ * No MII for 7-wire mode
*/
- fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
+ fec->eth->mii_speed = (((gd->arch.ipb_clk >> 20) / 5) << 1);
}
dev->priv = (void *)fec;
diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c
index 73e9060d572d64be28a474ddb5214bd61aa117ce..5a0f277d0a3b37c1b426c1af04de13d43e6e9e09 100644 (file)
--- a/drivers/qe/fdt.c
+++ b/drivers/qe/fdt.c
void ft_qe_setup(void *blob)
{
do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
- "bus-frequency", gd->qe_clk, 1);
+ "bus-frequency", gd->arch.qe_clk, 1);
do_fixup_by_prop_u32(blob, "device_type", "qe", 4,
- "brg-frequency", gd->brg_clk, 1);
+ "brg-frequency", gd->arch.brg_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe",
- "clock-frequency", gd->qe_clk, 1);
+ "clock-frequency", gd->arch.qe_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe",
- "bus-frequency", gd->qe_clk, 1);
+ "bus-frequency", gd->arch.qe_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe",
- "brg-frequency", gd->brg_clk, 1);
+ "brg-frequency", gd->arch.brg_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe-gtm",
- "clock-frequency", gd->qe_clk / 2, 1);
+ "clock-frequency", gd->arch.qe_clk / 2, 1);
fdt_fixup_qe_firmware(blob);
}
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 345587be63ed8414d76379953a5278a04ff5a1e0..5fd213546d6cba795e11a5a6ee364dcef2387e89 100644 (file)
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
uint savebase;
align_mask = align - 1;
- savebase = gd->mp_alloc_base;
+ savebase = gd->arch.mp_alloc_base;
- if ((off = (gd->mp_alloc_base & align_mask)) != 0)
- gd->mp_alloc_base += (align - off);
+ off = gd->arch.mp_alloc_base & align_mask;
+ if (off != 0)
+ gd->arch.mp_alloc_base += (align - off);
if ((off = size & align_mask) != 0)
size += (align - off);
- if ((gd->mp_alloc_base + size) >= gd->mp_alloc_top) {
- gd->mp_alloc_base = savebase;
+ if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
+ gd->arch.mp_alloc_base = savebase;
printf("%s: ran out of ram.\n", __FUNCTION__);
}
- retloc = gd->mp_alloc_base;
- gd->mp_alloc_base += size;
+ retloc = gd->arch.mp_alloc_base;
+ gd->arch.mp_alloc_base += size;
memset((void *)&qe_immr->muram[retloc], 0, size);
out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
#endif
- gd->mp_alloc_base = QE_DATAONLY_BASE;
- gd->mp_alloc_top = gd->mp_alloc_base + QE_DATAONLY_SIZE;
+ gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
+ gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
qe_sdma_init();
qe_snums_init();
from CLKn pin, we have te change the function.
*/
-#define BRG_CLK (gd->brg_clk)
+#define BRG_CLK (gd->arch.brg_clk)
int qe_set_brg(uint brg, uint rate)
{
index 7b5ecb5132d0de3bd5c508448579caea717104e0..c217c88e59aec10c47bb547520d5eb7a1e61906c 100644 (file)
--- a/drivers/serial/arm_dcc.c
+++ b/drivers/serial/arm_dcc.c
#define TIMEOUT_COUNT 0x4000000
-#ifndef CONFIG_ARM_DCC_MULTI
-#define arm_dcc_init serial_init
-void serial_setbrg(void) {}
-#define arm_dcc_getc serial_getc
-#define arm_dcc_putc serial_putc
-#define arm_dcc_puts serial_puts
-#define arm_dcc_tstc serial_tstc
-#endif
-
int arm_dcc_init(void)
{
return 0;
return reg;
}
-#ifdef CONFIG_ARM_DCC_MULTI
static struct stdio_dev arm_dcc_dev;
int drv_arm_dcc_init(void)
{
- int rc;
-
- /* Device initialization */
- memset(&arm_dcc_dev, 0, sizeof(arm_dcc_dev));
-
strcpy(arm_dcc_dev.name, "dcc");
arm_dcc_dev.ext = 0; /* No extensions */
arm_dcc_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT;
return stdio_register(&arm_dcc_dev);
}
-#endif
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return NULL;
+}
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 824d357d94818ea9c05fa5b0d437aff181b50195..83abcbda282dabfc276699ce8eea8447320f89bc 100644 (file)
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o
+COBJS-$(CONFIG_TEGRA_SLINK) += tegra_slink.o
COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o
COBJS := $(COBJS-y)
diff --git a/drivers/spi/tegra_slink.c b/drivers/spi/tegra_slink.c
--- /dev/null
@@ -0,0 +1,343 @@
+/*
+ * NVIDIA Tegra SPI-SLINK controller
+ *
+ * Copyright (c) 2010-2013 NVIDIA Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/tegra_slink.h>
+#include <spi.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra_spi_ctrl {
+ struct slink_tegra *regs;
+ unsigned int freq;
+ unsigned int mode;
+ int periph_id;
+ int valid;
+};
+
+struct tegra_spi_slave {
+ struct spi_slave slave;
+ struct tegra_spi_ctrl *ctrl;
+};
+
+static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
+
+static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct tegra_spi_slave, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
+ return 0;
+ else
+ return 1;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct tegra_spi_slave *spi;
+
+ debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
+ bus, cs, max_hz, mode);
+
+ if (!spi_cs_is_valid(bus, cs)) {
+ printf("SPI error: unsupported bus %d / chip select %d\n",
+ bus, cs);
+ return NULL;
+ }
+
+ if (max_hz > TEGRA_SPI_MAX_FREQ) {
+ printf("SPI error: unsupported frequency %d Hz. Max frequency"
+ " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
+ return NULL;
+ }
+
+ spi = malloc(sizeof(struct tegra_spi_slave));
+ if (!spi) {
+ printf("SPI error: malloc of SPI structure failed\n");
+ return NULL;
+ }
+ spi->slave.bus = bus;
+ spi->slave.cs = cs;
+ spi->ctrl = &spi_ctrls[bus];
+ if (!spi->ctrl) {
+ printf("SPI error: could not find controller for bus %d\n",
+ bus);
+ return NULL;
+ }
+
+ if (max_hz < spi->ctrl->freq) {
+ debug("%s: limiting frequency from %u to %u\n", __func__,
+ spi->ctrl->freq, max_hz);
+ spi->ctrl->freq = max_hz;
+ }
+ spi->ctrl->mode = mode;
+
+ return &spi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+ free(spi);
+}
+
+void spi_init(void)
+{
+ struct tegra_spi_ctrl *ctrl;
+ int i;
+#ifdef CONFIG_OF_CONTROL
+ int node = 0;
+ int count;
+ int node_list[CONFIG_TEGRA_SLINK_CTRLS];
+
+ count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi",
+ COMPAT_NVIDIA_TEGRA20_SLINK,
+ node_list,
+ CONFIG_TEGRA_SLINK_CTRLS);
+ for (i = 0; i < count; i++) {
+ ctrl = &spi_ctrls[i];
+ node = node_list[i];
+
+ ctrl->regs = (struct slink_tegra *)fdtdec_get_addr(gd->fdt_blob,
+ node, "reg");
+ if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
+ debug("%s: no slink register found\n", __func__);
+ continue;
+ }
+ ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
+ "spi-max-frequency", 0);
+ if (!ctrl->freq) {
+ debug("%s: no slink max frequency found\n", __func__);
+ continue;
+ }
+
+ ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
+ if (ctrl->periph_id == PERIPH_ID_NONE) {
+ debug("%s: could not decode periph id\n", __func__);
+ continue;
+ }
+ ctrl->valid = 1;
+
+ debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
+ __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
+ }
+#else
+ for (i = 0; i < CONFIG_TEGRA_SLINK_CTRLS; i++) {
+ ctrl = &spi_ctrls[i];
+ u32 base_regs[] = {
+ NV_PA_SLINK1_BASE,
+ NV_PA_SLINK2_BASE,
+ NV_PA_SLINK3_BASE,
+ NV_PA_SLINK4_BASE,
+ NV_PA_SLINK5_BASE,
+ NV_PA_SLINK6_BASE,
+ };
+ int periph_ids[] = {
+ PERIPH_ID_SBC1,
+ PERIPH_ID_SBC2,
+ PERIPH_ID_SBC3,
+ PERIPH_ID_SBC4,
+ PERIPH_ID_SBC5,
+ PERIPH_ID_SBC6,
+ };
+ ctrl->regs = (struct slink_tegra *)base_regs[i];
+ ctrl->freq = TEGRA_SPI_MAX_FREQ;
+ ctrl->periph_id = periph_ids[i];
+ ctrl->valid = 1;
+
+ debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
+ __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
+ }
+#endif
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct tegra_spi_slave *spi = to_tegra_spi(slave);
+ struct slink_tegra *regs = spi->ctrl->regs;
+ u32 reg;
+
+ /* Change SPI clock to correct frequency, PLLP_OUT0 source */
+ clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
+ spi->ctrl->freq);
+
+ /* Clear stale status here */
+ reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
+ SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
+ writel(reg, ®s->status);
+ debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
+
+ /* Set master mode and sw controlled CS */
+ reg = readl(®s->command);
+ reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
+ writel(reg, ®s->command);
+ debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct tegra_spi_slave *spi = to_tegra_spi(slave);
+ struct slink_tegra *regs = spi->ctrl->regs;
+
+ /* CS is negated on Tegra, so drive a 1 to get a 0 */
+ setbits_le32(®s->command, SLINK_CMD_CS_VAL);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct tegra_spi_slave *spi = to_tegra_spi(slave);
+ struct slink_tegra *regs = spi->ctrl->regs;
+
+ /* CS is negated on Tegra, so drive a 0 to get a 1 */
+ clrbits_le32(®s->command, SLINK_CMD_CS_VAL);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+ const void *data_out, void *data_in, unsigned long flags)
+{
+ struct tegra_spi_slave *spi = to_tegra_spi(slave);
+ struct slink_tegra *regs = spi->ctrl->regs;
+ u32 reg, tmpdout, tmpdin = 0;
+ const u8 *dout = data_out;
+ u8 *din = data_in;
+ int num_bytes;
+ int ret;
+
+ debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
+ __func__, slave->bus, slave->cs, dout, din, bitlen);
+ if (bitlen % 8)
+ return -1;
+ num_bytes = bitlen / 8;
+
+ ret = 0;
+
+ reg = readl(®s->status);
+ writel(reg, ®s->status); /* Clear all SPI events via R/W */
+ debug("%s entry: STATUS = %08x\n", __func__, reg);
+
+ reg = readl(®s->status2);
+ writel(reg, ®s->status2); /* Clear all STATUS2 events via R/W */
+ debug("%s entry: STATUS2 = %08x\n", __func__, reg);
+
+ debug("%s entry: COMMAND = %08x\n", __func__, readl(®s->command));
+
+ clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK,
+ SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
+ (slave->cs << SLINK_CMD2_SS_EN_SHIFT));
+ debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2));
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ /* handle data in 32-bit chunks */
+ while (num_bytes > 0) {
+ int bytes;
+ int is_read = 0;
+ int tm, i;
+
+ tmpdout = 0;
+ bytes = (num_bytes > 4) ? 4 : num_bytes;
+
+ if (dout != NULL) {
+ for (i = 0; i < bytes; ++i)
+ tmpdout = (tmpdout << 8) | dout[i];
+ dout += bytes;
+ }
+
+ num_bytes -= bytes;
+
+ clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK,
+ bytes * 8 - 1);
+ writel(tmpdout, ®s->tx_fifo);
+ setbits_le32(®s->command, SLINK_CMD_GO);
+
+ /*
+ * Wait for SPI transmit FIFO to empty, or to time out.
+ * The RX FIFO status will be read and cleared last
+ */
+ for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
+ u32 status;
+
+ status = readl(®s->status);
+
+ /* We can exit when we've had both RX and TX activity */
+ if (is_read && (status & SLINK_STAT_TXF_EMPTY))
+ break;
+
+ if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
+ SLINK_STAT_RDY)
+ tm++;
+
+ else if (!(status & SLINK_STAT_RXF_EMPTY)) {
+ tmpdin = readl(®s->rx_fifo);
+ is_read = 1;
+
+ /* swap bytes read in */
+ if (din != NULL) {
+ for (i = bytes - 1; i >= 0; --i) {
+ din[i] = tmpdin & 0xff;
+ tmpdin >>= 8;
+ }
+ din += bytes;
+ }
+ }
+ }
+
+ if (tm >= SPI_TIMEOUT)
+ ret = tm;
+
+ /* clear ACK RDY, etc. bits */
+ writel(readl(®s->status), ®s->status);
+ }
+
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ debug("%s: transfer ended. Value=%08x, status = %08x\n",
+ __func__, tmpdin, readl(®s->status));
+
+ if (ret) {
+ printf("%s: timeout during SPI transfer, tm %d\n",
+ __func__, ret);
+ return -1;
+ }
+
+ return 0;
+}
index 9bb34e29381f7a452717854b0d6dcc4edc5a879b..ce19095af03d931f5db46094289a48d79f464ebf 100644 (file)
--- a/drivers/spi/tegra_spi.c
+++ b/drivers/spi/tegra_spi.c
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/tegra_spi.h>
#include <spi.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SPI_CORRUPTS_UART)
#define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
struct spi_tegra *regs;
unsigned int freq;
unsigned int mode;
+ int periph_id;
};
static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
}
spi->slave.bus = bus;
spi->slave.cs = cs;
- spi->freq = max_hz;
+#ifdef CONFIG_OF_CONTROL
+ int node = fdtdec_next_compatible(gd->fdt_blob, 0,
+ COMPAT_NVIDIA_TEGRA20_SFLASH);
+ if (node < 0) {
+ debug("%s: cannot locate sflash node\n", __func__);
+ return NULL;
+ }
+ if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
+ debug("%s: sflash is disabled\n", __func__);
+ return NULL;
+ }
+ spi->regs = (struct spi_tegra *)fdtdec_get_addr(gd->fdt_blob,
+ node, "reg");
+ if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) {
+ debug("%s: no sflash register found\n", __func__);
+ return NULL;
+ }
+ spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0);
+ if (!spi->freq) {
+ debug("%s: no sflash max frequency found\n", __func__);
+ return NULL;
+ }
+ spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
+ if (spi->periph_id == PERIPH_ID_NONE) {
+ debug("%s: could not decode periph id\n", __func__);
+ return NULL;
+ }
+#else
spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE;
+ spi->freq = TEGRA_SPI_MAX_FREQ;
+ spi->periph_id = PERIPH_ID_SPI1;
+#endif
+ if (max_hz < spi->freq) {
+ debug("%s: limiting frequency from %u to %u\n", __func__,
+ spi->freq, max_hz);
+ spi->freq = max_hz;
+ }
+ debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n",
+ __func__, spi->regs, spi->freq, spi->periph_id);
spi->mode = mode;
return &spi->slave;
u32 reg;
/* Change SPI clock to correct frequency, PLLP_OUT0 source */
- clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq);
+ clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq);
/* Clear stale status here */
reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
index 52a4134f18b956963d8aa65c6a814f57bb9b585e..db01cc25f71ae37a9ba54c10c87b019becfa885e 100644 (file)
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__,
bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
+ writel(SPISSR_RESET_VALUE, &xilspi->regs->srr);
+
return &xilspi->slave;
}
index 32610d2a121ab3791e8d922c6121fe7e0f853f67..69d0b940582f760aa94ae4d064a5bd22e7d82142 100644 (file)
--- a/drivers/spi/xilinx_spi.h
+++ b/drivers/spi/xilinx_spi.h
#define SPIRFOR_OCYVAL_POS 0
#define SPIRFOR_OCYVAL_MASK (0xf << SPIRFOR_OCYVAL_POS)
+/* SPI Software Reset Register (ssr) */
+#define SPISSR_RESET_VALUE 0x0a
+
struct xilinx_spi_slave {
struct spi_slave slave;
struct xilinx_spi_reg *regs;
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index 750a2834383f035109ed2f6bd012f63bbfc64243..afcb00881e53202944b03539f22fa5d42324550c 100644 (file)
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
void lcd_ctrl_init(void *lcdbase)
{
- int line_length, size;
int type = DCACHE_OFF;
+ int size;
assert(disp_config);
&& disp_config->height <= LCD_MAX_HEIGHT
&& disp_config->log2_bpp <= LCD_MAX_LOG2_BPP)
update_panel_size(disp_config);
- size = lcd_get_size(&line_length);
+ size = lcd_get_size(&lcd_line_length);
/* Set up the LCD caching as requested */
if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
diff --git a/dts/Makefile b/dts/Makefile
index 785104e6d6409aa1b956db10107e17ddc6257a6d..922c78c1ca497c18916456359950403ac34774b3 100644 (file)
--- a/dts/Makefile
+++ b/dts/Makefile
Please define CONFIG_ARCH_DEVICE_TREE))
# We preprocess the device tree file provide a useful define
-DTS_CPPFLAGS := -ansi \
+DTS_CPPFLAGS := -x assembler-with-cpp \
-DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" \
-DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\"
diff --git a/examples/standalone/mem_to_mem_idma2intr.c b/examples/standalone/mem_to_mem_idma2intr.c
index d0a75eadfd1d607baf93d30cdc4a95738997a37b..e466c904a7866235dae68f5e5c780085501b4e15 100644 (file)
/* Pointer to initial global data area */
if (dpinit_done == 0) {
- dpbase = gd->dp_alloc_base;
+ dpbase = gd->arch.dp_alloc_base;
dpinit_done = 1;
}
if ((off = size & align_mask) != 0)
size += align - off;
- if ((dpbase + size) >= gd->dp_alloc_top) {
+ if ((dpbase + size) >= gd->arch.dp_alloc_top) {
dpbase = savebase;
printf ("dpalloc: ran out of dual port ram!");
return 0;
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index 393c3781eb65ba8201339042dc44531f9a36df39..66d54738a024fa0892c1b302b0763ce0543b608c 100644 (file)
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
#include <part.h>
#include <malloc.h>
#include <linux/compiler.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_SUPPORT_VFAT
+static const int vfat_enabled = 1;
+#else
+static const int vfat_enabled = 0;
+#endif
/*
* Convert a string to lowercase.
static void downcase(char *str)
{
while (*str != '\0') {
- TOLOWER(*str);
+ *str = tolower(*str);
str++;
}
}
} while (1);
}
-#ifdef CONFIG_SUPPORT_VFAT
/*
* Extract the file name information from 'slotptr' into 'l_name',
* starting at l_name[*idx].
__u8 ret = 0;
- for (i = 0; i < sizeof(name); i++)
+ for (i = 0; i < 8; i++)
ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + name[i];
- for (i = 0; i < sizeof(ext); i++)
+ for (i = 0; i < 3; i++)
ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + ext[i];
return ret;
}
-#endif /* CONFIG_SUPPORT_VFAT */
/*
* Get the directory entry associated with 'filename' from the directory
continue;
}
if ((dentptr->attr & ATTR_VOLUME)) {
-#ifdef CONFIG_SUPPORT_VFAT
- if ((dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
+ if (vfat_enabled &&
+ (dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
prevcksum = ((dir_slot *)dentptr)->alias_checksum;
get_vfatname(mydata, curclust,
continue;
}
debug("vfatname: |%s|\n", l_name);
- } else
-#endif
- {
+ } else {
/* Volume label or VFAT entry */
dentptr++;
continue;
debug("Dentname == NULL - %d\n", i);
return NULL;
}
-#ifdef CONFIG_SUPPORT_VFAT
- __u8 csum = mkcksum(dentptr->name, dentptr->ext);
- if (dols && csum == prevcksum) {
- prevcksum = 0xffff;
- dentptr++;
- continue;
+ if (vfat_enabled) {
+ __u8 csum = mkcksum(dentptr->name, dentptr->ext);
+ if (dols && csum == prevcksum) {
+ prevcksum = 0xffff;
+ dentptr++;
+ continue;
+ }
}
-#endif
+
get_name(dentptr, s_name);
if (dols) {
int isdir = (dentptr->attr & ATTR_DIR);
return -1;
}
-#ifdef CONFIG_SUPPORT_VFAT
- debug("VFAT Support enabled\n");
-#endif
+ if (vfat_enabled)
+ debug("VFAT Support enabled\n");
+
debug("FAT%d, fat_sect: %d, fatlength: %d\n",
mydata->fatsize, mydata->fat_sect, mydata->fatlength);
debug("Rootdir begins at cluster: %d, sector: %d, offset: %x\n"
continue;
}
- csum = mkcksum(dentptr->name, dentptr->ext);
+ if (vfat_enabled)
+ csum = mkcksum(dentptr->name, dentptr->ext);
+
if (dentptr->attr & ATTR_VOLUME) {
-#ifdef CONFIG_SUPPORT_VFAT
- if ((dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
+ if (vfat_enabled &&
+ (dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
prevcksum =
((dir_slot *)dentptr)->alias_checksum;
}
debug("Rootvfatname: |%s|\n",
l_name);
- } else
-#endif
- {
+ } else {
/* Volume label or VFAT entry */
dentptr++;
continue;
}
goto exit;
}
-#ifdef CONFIG_SUPPORT_VFAT
- else if (dols == LS_ROOT && csum == prevcksum) {
+ else if (vfat_enabled &&
+ dols == LS_ROOT && csum == prevcksum) {
prevcksum = 0xffff;
dentptr++;
continue;
}
-#endif
+
get_name(dentptr, s_name);
if (dols == LS_ROOT) {
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index 4a1bda0a37effd984885800ec4679be6f0f71666..b4022aa29054abae1ae22d19e0015d18883c9545 100644 (file)
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
#include <fat.h>
#include <asm/byteorder.h>
#include <part.h>
+#include <linux/ctype.h>
#include "fat.c"
static void uppercase(char *str, int len)
int i;
for (i = 0; i < len; i++) {
- TOUPPER(*str);
+ *str = toupper(*str);
str++;
}
}
return ret;
}
-#ifdef CONFIG_SUPPORT_VFAT
/*
* Set the file name information from 'name' into 'slotptr',
*/
return 0;
}
-#endif
-
/*
* Set the entry at index 'entry' in a FAT (16/32) table.
*/
continue;
}
if ((dentptr->attr & ATTR_VOLUME)) {
-#ifdef CONFIG_SUPPORT_VFAT
- if ((dentptr->attr & ATTR_VFAT) &&
+ if (vfat_enabled &&
+ (dentptr->attr & ATTR_VFAT) &&
(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
get_long_file_name(mydata, curclust,
get_dentfromdir_block,
&dentptr, l_name);
debug("vfatname: |%s|\n", l_name);
- } else
-#endif
- {
+ } else {
/* Volume label or VFAT entry */
dentptr++;
if (is_next_clust(mydata, dentptr))
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
--- /dev/null
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * (C) Copyright 2002-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_GENERIC_GBL_DATA_H
+#define __ASM_GENERIC_GBL_DATA_H
+/*
+ * The following data structure is placed in some memory which is
+ * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
+ * some locked parts of the data cache) to allow for a minimum set of
+ * global variables during system initialization (until we have set
+ * up the memory controller so that we can use RAM).
+ *
+ * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
+ *
+ * Each architecture has its own private fields. For now all are private
+ */
+
+#ifndef __ASSEMBLY__
+typedef struct global_data {
+ bd_t *bd;
+ unsigned long flags;
+ unsigned long baudrate;
+ unsigned long cpu_clk; /* CPU clock in Hz! */
+ unsigned long bus_clk;
+ /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
+ unsigned long pci_clk;
+ unsigned long mem_clk;
+#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
+ unsigned long fb_base; /* Base address of framebuffer mem */
+#endif
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+ unsigned long post_log_word; /* Record POST activities */
+ unsigned long post_log_res; /* success of POST test */
+ unsigned long post_init_f_time; /* When post_init_f started */
+#endif
+#ifdef CONFIG_BOARD_TYPES
+ unsigned long board_type;
+#endif
+ unsigned long have_console; /* serial_init() was called */
+#ifdef CONFIG_PRE_CONSOLE_BUFFER
+ unsigned long precon_buf_idx; /* Pre-Console buffer index */
+#endif
+#ifdef CONFIG_MODEM_SUPPORT
+ unsigned long do_mdm_init;
+ unsigned long be_quiet;
+#endif
+ unsigned long env_addr; /* Address of Environment struct */
+ unsigned long env_valid; /* Checksum of Environment valid? */
+
+ /* TODO: is this the same as relocaddr, or something else? */
+ unsigned long dest_addr; /* Post-relocation address of U-Boot */
+ unsigned long dest_addr_sp;
+ unsigned long ram_top; /* Top address of RAM used by U-Boot */
+
+ unsigned long relocaddr; /* Start address of U-Boot in RAM */
+ phys_size_t ram_size; /* RAM size */
+ unsigned long mon_len; /* monitor len */
+ unsigned long irq_sp; /* irq stack pointer */
+ unsigned long start_addr_sp; /* start_addr_stackpointer */
+ unsigned long reloc_off;
+ struct global_data *new_gd; /* relocated global data */
+ const void *fdt_blob; /* Our device tree, NULL if none */
+ void **jt; /* jump table */
+ char env_buf[32]; /* buffer for getenv() before reloc. */
+ struct arch_global_data arch; /* architecture-specific data */
+} gd_t;
+#endif
+
+/*
+ * Global Data Flags
+ */
+#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
+#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
+#define GD_FLG_SILENT 0x00004 /* Silent mode */
+#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
+#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
+#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
+#define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */
+
+#endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/command.h b/include/command.h
index 476e7cffc2856523df090a54d73b03926e1b73ba..3785eb987f4863352d7de87fa3853725ad819b4d 100644 (file)
--- a/include/command.h
+++ b/include/command.h
* @param repeatable This function sets this to 0 if the command is not
* repeatable. If the command is repeatable, the value
* is left unchanged.
+ * @param ticks If ticks is not null, this function set it to the
+ * number of ticks the command took to complete.
* @return 0 if the command succeeded, 1 if it failed
*/
int cmd_process(int flag, int argc, char * const argv[],
- int *repeatable);
+ int *repeatable, unsigned long *ticks);
#endif /* __ASSEMBLY__ */
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
--- /dev/null
@@ -0,0 +1,820 @@
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * B4860 QDS board configuration file
+ */
+#define CONFIG_B4860QDS
+#define CONFIG_PHYS_64BIT
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E6500
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_MP /* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#ifndef CONFIG_PPC_B4420
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+#define CONFIG_SRIO2 /* SRIO port 2 */
+#endif
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR 0x77
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define I2C_CH_DEFAULT 0x8
+#define I2C_CH_VSC3316 0xc
+#define I2C_CH_VSC3308 0xd
+
+#define VSC3316_TX_ADDRESS 0x70
+#define VSC3316_RX_ADDRESS 0x71
+#define VSC3308_TX_ADDRESS 0x02
+#define VSC3308_RX_ADDRESS 0x03
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_SYS_NO_FLASH */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#if 0
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
+#endif
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_FSL_DDR3
+#define CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x53
+
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
+ FTIM0_NOR_TEADC(0x01) | \
+ FTIM0_NOR_TEAHC(0x20))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
+ FTIM2_NOR_TCH(0x0E) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS /* use common QIXIS code */
+#define CONFIG_FSL_QIXIS_V2
+#define QIXIS_BASE 0xffdf0000
+#ifdef CONFIG_PHYS_64BIT
+#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
+#else
+#define QIXIS_BASE_PHYS QIXIS_BASE
+#endif
+#define QIXIS_LBMAP_SWITCH 0x01
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x02
+#define QIXIS_RST_CTL_RESET 0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+
+#define CONFIG_SYS_CSPR3_EXT (0xf)
+#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
+#define CONFIG_SYS_CSOR3 0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3 0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed in Hz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x118000
+#define CONFIG_SYS_I2C2_OFFSET 0x119000
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * RapidIO
+ */
+#ifdef CONFIG_SYS_SRIO
+#ifdef CONFIG_SRIO1
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
+#endif
+
+#ifdef CONFIG_SRIO2
+#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
+#endif
+#endif
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 25
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 25
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x10
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x11
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
+#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE 115200
+
+#define __USB_PHY_TYPE ulpi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=null," \
+ "bank_intlv=cs0_cs1;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=b4860qds/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=b4860qds/b4860qds.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+/* For emulation this causes u-boot to jump to the start of the proof point
+ app code automatically */
+#define CONFIG_PROOF_POINTS \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x29000000 - - -;" \
+ "cpu 2 release 0x29000000 - - -;" \
+ "cpu 3 release 0x29000000 - - -;" \
+ "cpu 4 release 0x29000000 - - -;" \
+ "cpu 5 release 0x29000000 - - -;" \
+ "cpu 6 release 0x29000000 - - -;" \
+ "cpu 7 release 0x29000000 - - -;" \
+ "go 0x29000000"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x01000000 - - -;" \
+ "cpu 2 release 0x01000000 - - -;" \
+ "cpu 3 release 0x01000000 - - -;" \
+ "cpu 4 release 0x01000000 - - -;" \
+ "cpu 5 release 0x01000000 - - -;" \
+ "cpu 6 release 0x01000000 - - -;" \
+ "cpu 7 release 0x01000000 - - -;" \
+ "go 0x01000000"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
--- /dev/null
@@ -0,0 +1,667 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * BSC9132 QDS board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_BSC9132QDS
+#define CONFIG_BSC9132
+#endif
+
+#define CONFIG_MISC_INIT_R
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_RAMBOOT_SDCARD
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
+#ifdef CONFIG_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH
+#define CONFIG_SYS_RAMBOOT
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_SYS_TEXT_BASE 0x11000000
+#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
+#endif
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0x8ff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE /* BOOKE */
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_MPC85xx
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
+
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+
+#define CONFIG_E1000 /* E1000 pci Ethernet card*/
+
+/*
+ * PCI Windows
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+/* controller 1, Slot 1, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TSEC_ENET /* ethernet */
+
+#if defined(CONFIG_SYS_CLK_100_DDR_100)
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 100000000
+#elif defined(CONFIG_SYS_CLK_100_DDR_133)
+#define CONFIG_SYS_CLK_FREQ 100000000
+#define CONFIG_DDR_CLK_FREQ 133000000
+#endif
+
+#define CONFIG_MP
+
+#define CONFIG_HWCONFIG
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* enable branch predition */
+
+#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x01ffffff
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
+#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
+#define CONFIG_FSL_DDR_INTERACTIVE
+
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+#define CONFIG_SYS_SDRAM_SIZE (1024)
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+
+/* DDR3 Controller Settings */
+#define CONFIG_CHIP_SELECTS_PER_CTRL 1
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
+#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
+#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
+#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
+#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
+#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
+#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
+#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
+
+#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
+#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
+#define CONFIG_SYS_DDR_RCW_1 0x00000000
+#define CONFIG_SYS_DDR_RCW_2 0x00000000
+#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
+#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
+#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
+#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
+
+#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
+#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
+#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
+#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
+
+#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
+#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
+#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
+#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
+#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
+#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
+#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
+
+#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
+#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
+#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
+#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
+#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
+#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
+#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
+#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
+#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
+
+/*FIXME: the following params are constant w.r.t diff freq
+combinations. this should be removed later
+*/
+#if CONFIG_DDR_CLK_FREQ == 100000000
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
+#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
+#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
+#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
+#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
+#elif CONFIG_DDR_CLK_FREQ == 133000000
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
+#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
+#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
+#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
+#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
+#else
+#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
+#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
+#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
+#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
+#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
+#endif
+
+
+/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
+
+#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
+
+/*
+ * IFC Definitions
+ */
+/* NOR Flash on IFC */
+#define CONFIG_SYS_FLASH_BASE 0x88000000
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
+
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_SYS_NOR_CSPR 0x88000101
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
+/* NOR Flash Timing Params */
+
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
+ | FTIM0_NOR_TEADC(0x03) \
+ | FTIM0_NOR_TAVDS(0x00) \
+ | FTIM0_NOR_TEAHC(0x0f))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
+ | FTIM1_NOR_TRAD_NOR(0x09) \
+ | FTIM1_NOR_TSEQRAD_NOR(0x09))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
+ | FTIM2_NOR_TCH(0x4) \
+ | FTIM2_NOR_TWPH(0x7) \
+ | FTIM2_NOR_TWP(0x1e))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+/* CFI for NOR Flash */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/* NAND Flash on IFC */
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+/* NAND Flash Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
+ | FTIM0_NAND_TWP(0x05) \
+ | FTIM0_NAND_TWCHT(0x02) \
+ | FTIM0_NAND_TWH(0x04))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
+ | FTIM1_NAND_TWBE(0x1e) \
+ | FTIM1_NAND_TRR(0x07) \
+ | FTIM1_NAND_TRP(0x05))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
+ | FTIM2_NAND_TREH(0x04) \
+ | FTIM2_NAND_TWHRE(0x11))
+#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+
+/* NAND */
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#define CONFIG_FSL_QIXIS
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_SYS_FPGA_BASE 0xffb00000
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+#define QIXIS_BASE CONFIG_SYS_FPGA_BASE
+#define QIXIS_LBMAP_SWITCH 9
+#define QIXIS_LBMAP_MASK 0x07
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_RST_CTL_RESET 0x83
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+
+#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
+
+#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR2 0x0
+/* CPLD Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
+ FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS2_FTIM3 0x0
+#endif
+
+/* Set up IFC registers for boot location NOR/NAND */
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
+#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
+ - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
+
+#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER /* hush parser */
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 400800 /* I2C speed and slave address*/
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+
+/* I2C EEPROM */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+
+/* enable read and write access to EEPROM */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/* I2C FPGA */
+#define CONFIG_I2C_FPGA
+#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
+
+#define CONFIG_RTC_DS3231
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * SPI interface will not be available in case of NAND boot SPI CS0 will be
+ * used for SLIC
+ */
+/* eSPI - Enhanced SPI */
+#define CONFIG_FSL_ESPI /* SPI */
+#ifdef CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1 1
+#define CONFIG_TSEC1_NAME "eTSEC1"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "eTSEC2"
+
+#define TSEC1_PHY_ADDR 0
+#define TSEC2_PHY_ADDR 1
+
+#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+#define CONFIG_ETHPRIME "eTSEC1"
+
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+
+/* TBI PHY configuration for SGMII mode */
+#define CONFIG_TSEC_TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_ANEG_ENABLE \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
+#endif /* CONFIG_TSEC_ENET */
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FSL_ESDHC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#endif
+
+#define CONFIG_USB_EHCI /* USB */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_STORAGE
+#define CONFIG_HAS_FSL_DR_USB
+#endif
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_SIZE 0x2000
+#else
+#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
+#endif
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR 0xfff80000
+#else
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+ /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq:1ms ticks */
+
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_HOSTNAME BSC9132qds
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin"
+
+#define CONFIG_BAUDRATE 115200
+
+#ifdef CONFIG_SDCARD
+#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+#else
+#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" CONFIG_UBOOTPATH "\0" \
+ "loadaddr=1000000\0" \
+ "bootfile=uImage\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=rootfs.ext2.gz.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=bsc9132qds.dtb\0" \
+ "bdev=sda1\0" \
+ CONFIG_DEF_HWCONFIG\
+ "othbootargs=mem=880M ramdisk_size=600000 " \
+ "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
+ "isolcpus=0\0" \
+ "usbext2boot=setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "usb start;" \
+ "ext2load usb 0:4 $loadaddr $bootfile;" \
+ "ext2load usb 0:4 $fdtaddr $fdtfile;" \
+ "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
+ "debug_halt_off=mw ff7e0e30 0xf0000000;"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "usb start;" \
+ "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
+ "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs; " \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
+
+#endif /* __CONFIG_H */
index fd80be59042d7c993b0a36a7d0b2c84b1d3bd0a7..275d4f2af633558848145fc2455922ee6bef74b9 100644 (file)
#define CONFIG_MPC8313 1
#define CONFIG_MPC8313ERDB 1
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SPL_MAX_SIZE (4 * 1024)
+#define CONFIG_SPL_PAD_TO 0xfff04000
+
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-#ifdef CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#endif /* CONFIG_NAND_SPL */
-#endif /* CONFIG_NAND_U_BOOT */
+#endif
+
+#endif /* CONFIG_NAND */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define CONFIG_SYS_IMMR 0xE0000000
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if defined(CONFIG_NAND) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
#endif
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \
- !defined(CONFIG_NAND_SPL)
+ !defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */
/* drivers/mtd/nand/nand.c */
-#ifdef CONFIG_NAND_SPL
+#if defined(CONFIG_NAND) && defined(CONFIG_SPL_BUILD)
#define CONFIG_SYS_NAND_BASE 0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE 0xE2800000
| OR_FCM_EHTR)
/* 0xFFFF8396 */
-#ifdef CONFIG_NAND_U_BOOT
+#ifdef CONFIG_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
/*
* Environment
*/
-#if defined(CONFIG_NAND_U_BOOT)
+#if defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET (512 * 1024)
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND)
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN)
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_NAND
#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_ROM_LOC_NAND_SP_8BIT |\
index 83b8668bac88b094480342d13093f7a9c0d106c2..d5f3c5f56f293404b4027dd63b661f142afa5ba3 100644 (file)
#define CONFIG_CMD_EXT2
#endif
+/*
+ * USB
+ */
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_STORAGE
+#define CONFIG_PCI_EHCI_DEVICE 0
+#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
index a62b7d53a950aba11f9e0d7b0dee1c8678d01eed..d233365b7d0e5dc9cff1162b11474e84c52b759b 100644 (file)
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
-"hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \
+"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
index 0cc57816927d8b8720586a8bf70959bfd73bc604..a975ee10edb30cd6ac4788953532a8d8aa7a3f22 100644 (file)
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
/* video */
-#define CONFIG_VIDEO
+#undef CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_BIOSEMU
index 8b9b0dbc22153404b76a52a90688ed90511964cb..bbc53ceafd22ff5093dd5b52089eba5f3f237e4c 100644 (file)
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg
+#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg
#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
index 72459d859d18e5e1c8a7ecc7a9d71113e54607f0..0dc2a5040825bfb69a54a4f04b654cb29c530d23 100644 (file)
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x80F80000\0" \
+ "fdt_high=0xffffffff\0" \
"rdaddr=0x81000000\0" \
"bootfile=/boot/uImage\0" \
"fdtfile=\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 ro\0" \
"mmcrootfstype=ext4 rootwait\0" \
+ "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
+ "nandrootfstype=ubifs rootwait=1\0" \
+ "nandsrcaddr=0x280000\0" \
+ "nandimgsize=0x500000\0" \
+ "rootpath=/export/rootfs\0" \
+ "nfsopts=nolock\0" \
+ "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+ "::off\0" \
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
"ramrootfstype=ext2\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "spiroot=/dev/mtdblock4 rw\0" \
+ "spirootfstype=jffs2\0" \
+ "spisrcaddr=0xe0000\0" \
+ "spiimgsize=0x362000\0" \
+ "spibusno=0\0" \
+ "spiargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${spiroot} " \
+ "rootfstype=${spirootfstype}\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=/dev/nfs " \
+ "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+ "ip=dhcp\0" \
"bootenv=uEnv.txt\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \
+ "bootm ${loadaddr}\0" \
+ "spiboot=echo Booting from spi ...; " \
+ "run spiargs; " \
+ "sf probe ${spibusno}:0; " \
+ "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
+ "bootm ${loadaddr}\0" \
+ "netboot=echo Booting from network ...; " \
+ "setenv autoload no; " \
+ "dhcp; " \
+ "tftp ${loadaddr} ${bootfile}; " \
+ "run netargs; " \
+ "bootm ${loadaddr}\0" \
"ramboot=echo Booting from ramdisk ...; " \
"run ramargs; " \
"bootm ${loadaddr}\0" \
"if run loaduimage; then " \
"run mmcboot;" \
"fi;" \
+ "else " \
+ "run nandboot;" \
"fi;" \
/* Clock Defines */
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000
+#define CONFIG_SPL_MUSB_NEW_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
#ifdef CONFIG_MUSB_GADGET
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
#endif /* CONFIG_MUSB_GADGET */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
+/* disable host part of MUSB in SPL */
+#undef CONFIG_MUSB_HOST
+/*
+ * Disable UART, CPSW ethernet support and extra environment settings so we
+ * will fit within 101KiB.
+ */
+#undef CONFIG_SPL_ETH_SUPPORT
+#undef CONFIG_SPL_YMODEM_SUPPORT
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#endif
+
+/*
+ * Default to using SPI for environment, etc. We have multiple copies
+ * of SPL as the ROM will check these locations.
+ * 0x0 - 0x20000 : First copy of SPL
+ * 0x20000 - 0x40000 : Second copy of SPL
+ * 0x40000 - 0x60000 : Third copy of SPL
+ * 0x60000 - 0x80000 : Fourth copy of SPL
+ * 0x80000 - 0xDF000 : U-Boot
+ * 0xDF000 - 0xE0000 : U-Boot Environment
+ * 0xE0000 - 0x442000 : Linux Kernel
+ * 0x442000 - 0x800000 : Userland
+ */
+#if defined(CONFIG_SPI_BOOT)
+# undef CONFIG_ENV_IS_NOWHERE
+# define CONFIG_ENV_IS_IN_SPI_FLASH
+# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */
+# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
+#endif /* SPI support */
+
/* Unsupported features */
#undef CONFIG_USE_IRQ
/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
devices */
+#if !defined(CONFIG_SPI_BOOT)
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#endif
+#endif
#endif /* ! __CONFIG_AM335X_EVM_H */
index e1ad1e58ff63bbb4cbe95b3f8a742a480f4a878e..bf9d63e8952704c23adf0c42e5a60019a3dd82fa 100644 (file)
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#undef CONFIG_CMD_NET
index ba1532540e6b6e76bac3d2b97f69090b43ebb8d5..17fe88df4e24692071060f611b62e1fc2d127106 100644 (file)
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#undef CONFIG_CMD_NET
index 6764b4749c9b90e6bc26c4cf43a73033252861a4..73c66af06d5b54ecd53c0c0b2a8705a7d5f7819b 100644 (file)
#define CONFIG_FEC_MXC_PHYADDR 0
#define IMX_FEC_BASE MXS_ENET0_BASE
#define CONFIG_MII
-#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_XCV_TYPE RMII
#endif
diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h
--- /dev/null
+++ b/include/configs/cardhu.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+
+#include "tegra30-common.h"
+
+/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT "Tegra30 (Cardhu) # "
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_CMD_I2C
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* SPI */
+#define CONFIG_TEGRA_SLINK
+#define CONFIG_TEGRA_SLINK_CTRLS 6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE (4 << 20)
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
index 7d072153ee8295a4e1407152015c15c5d4d5031b..943b65841c611db084d2d7438ae22967042989a1 100644 (file)
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
index d8aabd4cc8890166b931c569ca91fe8c71730b7c..c7f36ff148fe93fa25f3adbde6d5f82fa768cc5f 100644 (file)
#define CONFIG_SYS_COREBOOT
#define CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_LAST_STAGE_INIT
-#define CONFIG_X86_NO_RESET_VECTOR
#define CONFIG_SYS_VSNPRINTF
#define CONFIG_INTEL_CORE_ARCH /* Sandy bridge and ivy bridge chipsets. */
#define CONFIG_ZBOOT_32
diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+
+#include "tegra114-common.h"
+
+/* Must be off for Dalmore to boot !?!? FIXME */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT "Tegra114 (Dalmore) # "
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
+
+#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ENV_IS_NOWHERE
+
+#define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
index 83a8b5d59feec8f5f01117e270f914e0d339d120..d926f740263e57491345a354c4c25931546c4138 100644 (file)
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/* TWL4030 */
index 721b91c4df91875470fa5e07b8e2465bf2e0cdb9..e68654f3baf7204cb0fcbb5864c6db1ad1280d42 100644 (file)
--- a/include/configs/dig297.h
+++ b/include/configs/dig297.h
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
--- a/include/configs/eNET.h
+++ /dev/null
@@ -1,619 +0,0 @@
-/*
- * (C) Copyright 2008
- * Graeme Russ, graeme.russ@gmail.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/ibmpc.h>
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_SYS_SC520
-#define CONFIG_SYS_SC520_SSI
-#define CONFIG_SHOW_BOOT_PROGRESS
-#define CONFIG_LAST_STAGE_INIT
-
-/*-----------------------------------------------------------------------
- * Watchdog Configuration
- * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
- * bottom (processor) board MUST be removed!
- */
-#undef CONFIG_WATCHDOG
-#define CONFIG_HW_WATCHDOG
-
-/*-----------------------------------------------------------------------
- * Real Time Clock Configuration
- */
-#define CONFIG_RTC_MC146818
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 1843200
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
- 9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 UART1_BASE
-#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
-#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
-#define CONFIG_SYS_NS16550_PORT_MAPPED
-
-/*-----------------------------------------------------------------------
- * Video Configuration
- */
-#undef CONFIG_VIDEO
-#undef CONFIG_CFB_CONSOLE
-
-/*-----------------------------------------------------------------------
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IMLS
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ITEST
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_XIMG
-#define CONFIG_CMD_ZBOOT
-
-#define CONFIG_BOOTDELAY 15
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200
-#define CONFIG_KGDB_SER_INDEX 2
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "boot > "
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + \
- 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000
-#define CONFIG_SYS_MEMTEST_END 0x01000000
-#define CONFIG_SYS_LOAD_ADDR 0x100000
-#define CONFIG_SYS_HZ 1000
-
-/*-----------------------------------------------------------------------
- * SDRAM Configuration
- */
-#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
-#define CONFIG_SYS_SDRAM_REFRESH_RATE 156
-#define CONFIG_NR_DRAM_BANKS 4
-
-/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
-#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
-#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
-
-/*-----------------------------------------------------------------------
- * CPU Features
- */
-#define CONFIG_SYS_SC520_HIGH_SPEED 0
-#define CONFIG_SYS_SC520_RESET
-#define CONFIG_SYS_SC520_TIMER
-#undef CONFIG_SYS_GENERIC_TIMER
-#define CONFIG_SYS_PCAT_INTERRUPTS
-#define CONFIG_SYS_NUM_IRQS 16
-#define CONFIG_SYS_PC_BIOS
-#define CONFIG_SYS_PCI_BIOS
-#define CONFIG_SYS_X86_REALMODE
-#define CONFIG_SYS_X86_ISR_TIMER
-
-/*-----------------------------------------------------------------------
- * Memory organization:
- * 32kB Stack
- * 16kB Cache-As-RAM @ 0x19200000
- * 256kB Monitor
- * (128kB + Environment Sector Size) malloc pool
- */
-#define CONFIG_SYS_STACK_SIZE (32 * 1024)
-#define CONFIG_SYS_CAR_ADDR 0x19200000
-#define CONFIG_SYS_CAR_SIZE (16 * 1024)
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + \
- 128*1024)
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * FLASH configuration
- * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
- * 16MB StrataFlash #1 @ 0x10000000
- * 16MB StrataFlash #2 @ 0x11000000
- */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_SYS_MAX_FLASH_BANKS 3
-#define CONFIG_SYS_FLASH_BASE 0x38000000
-#define CONFIG_SYS_FLASH_BASE_1 0x10000000
-#define CONFIG_SYS_FLASH_BASE_2 0x11000000
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_FLASH_BASE_1, \
- CONFIG_SYS_FLASH_BASE_2}
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
-#define CONFIG_SYS_FLASH_LEGACY_512Kx8
-#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
-
-/*-----------------------------------------------------------------------
- * Environment configuration
- * - Boot flash is 512kB with 64kB sectors
- * - StrataFlash is 32MB with 128kB sectors
- * - Redundant embedded environment is 25% of the Boot flash
- * - Redundant StrataFlash environment is <1% of the StrataFlash
- * - Environment is therefore located in StrataFlash
- * - Primary copy is located in first sector of first flash
- * - Redundant copy is located in second sector of first flash
- * - Stack is only 32kB, so environment size is limited to 4kB
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_SIZE 0x01000
-#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * PCI configuration
- */
-#define CONFIG_PCI
-#define CONFIG_PCI_PNP
-#define CONFIG_SYS_FIRST_PCI_IRQ 10
-#define CONFIG_SYS_SECOND_PCI_IRQ 9
-#define CONFIG_SYS_THIRD_PCI_IRQ 11
-#define CONFIG_SYS_FORTH_PCI_IRQ 15
-
-/*-----------------------------------------------------------------------
- * Network device (TRL8100B) support
- */
-#define CONFIG_RTL8139
-
-/*-----------------------------------------------------------------------
- * BOOTCS Control (for AM29LV040B-120JC)
- *
- * 000 0 00 0 000 11 0 011 }- 0x0033
- * \ / | \| | \ / \| | \ /
- * | | | | | | | |
- * | | | | | | | +---- 3 Wait States (First Access)
- * | | | | | | +------- Reserved
- * | | | | | +--------- 3 Wait States (Subsequent Access)
- * | | | | +------------- Reserved
- * | | | +---------------- Non-Paged Mode
- * | | +------------------ 8 Bit Wide
- * | +--------------------- GP Bus
- * +------------------------ Reserved
- */
-#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
-
-/*-----------------------------------------------------------------------
- * ROMCS Control (for E28F128J3A-150 StrataFlash)
- *
- * 000 0 01 1 000 01 0 101 }- 0x0615
- * \ / | \| | \ / \| | \ /
- * | | | | | | | |
- * | | | | | | | +---- 5 Wait States (First Access)
- * | | | | | | +------- Reserved
- * | | | | | +--------- 1 Wait State (Subsequent Access)
- * | | | | +------------- Reserved
- * | | | +---------------- Paged Mode
- * | | +------------------ 16 Bit Wide
- * | +--------------------- GP Bus
- * +------------------------ Reserved
- */
-#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
-#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
-
-/*-----------------------------------------------------------------------
- * SC520 General Purpose Bus configuration
- *
- * Chip Select Offset 1 Clock Cycle
- * Chip Select Pulse Width 8 Clock Cycles
- * Chip Select Read Offset 2 Clock Cycles
- * Chip Select Read Width 6 Clock Cycles
- * Chip Select Write Offset 2 Clock Cycles
- * Chip Select Write Width 6 Clock Cycles
- * Chip Select Recovery Time 2 Clock Cycles
- *
- * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
- *
- * |<-------------General Purpose Bus Cycle---------------->|
- * | |
- * ----------------------\__________________/------------------
- * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
- *
- * ------------------------\_______________/-------------------
- * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
- *
- * --------------------------\_______________/-----------------
- * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
- *
- * ________/-----------\_______________________________________
- * |<--->|<--------->|
- * ^ ^
- * (GPALEOFF + 1) |
- * |
- * (GPALEW + 1)
- */
-#define CONFIG_SYS_SC520_GPCSOFF 0x00
-#define CONFIG_SYS_SC520_GPCSPW 0x07
-#define CONFIG_SYS_SC520_GPRDOFF 0x01
-#define CONFIG_SYS_SC520_GPRDW 0x05
-#define CONFIG_SYS_SC520_GPWROFF 0x01
-#define CONFIG_SYS_SC520_GPWRW 0x05
-#define CONFIG_SYS_SC520_GPCSRT 0x01
-
-/*-----------------------------------------------------------------------
- * SC520 Programmable I/O configuration
- *
- * Pin Mode Dir. Description
- * ----------------------------------------------------------------------
- * PIO0 PIO Output Unused
- * PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
- * PIO2 PIO Output Auxiliary power output enable
- * PIO3 GPAEN Output GP Bus Address Enable
- * PIO4 PIO Output Top Board Enable (active low)
- * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
- * PIO6 PIO Input Data output of Power Supply ADC
- * PIO7 PIO Output Clock input to Power Supply ADC
- * PIO8 PIO Output Chip Select input of Power Supply ADC
- * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
- * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
- * PIO11 PIO Input StrataFlash 1 Status
- * PIO12 PIO Input StrataFlash 2 Status
- * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
- * PIO14 PIO Input Low Input Voltage Warning (active low)
- * PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
- * PIO16 PIO Input Power Fail
- * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
- * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
- * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
- * PIO20 GPIRQ3 Input UART D IRQ
- * PIO21 GPIRQ2 Input UART C IRQ
- * PIO22 GPIRQ1 Input UART B IRQ
- * PIO23 GPIRQ0 Input UART A IRQ
- * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
- * PIO25 PIO Input Battery OK Indication
- * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
- * PIO27 GPCS0# Output SRAM 1 Chip Select
- * PIO28 PIO Input Top Board UART CTS
- * PIO29 PIO Output FPGA Program Mode (active low)
- * PIO30 PIO Input FPGA Initialised (active low)
- * PIO31 PIO Input FPGA Done (active low)
- */
-#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
-#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
-#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
-#define CONFIG_SYS_SC520_PIODIR31_16 0x2900
-
-/*-----------------------------------------------------------------------
- * PIO Pin defines
- */
-#define CONFIG_SYS_ENET_AUX_PWR 0x0004
-#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
-#define CONFIG_SYS_ENET_SF_WIDTH 0x0020
-#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
-#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
-#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
-#define CONFIG_SYS_ENET_SF1_MODE 0x0200
-#define CONFIG_SYS_ENET_SF2_MODE 0x0400
-#define CONFIG_SYS_ENET_SF1_STATUS 0x0800
-#define CONFIG_SYS_ENET_SF2_STATUS 0x1000
-#define CONFIG_SYS_ENET_PWR_STATUS 0x4000
-#define CONFIG_SYS_ENET_WATCHDOG 0x8000
-
-#define CONFIG_SYS_ENET_PWR_FAIL 0x0001
-#define CONFIG_SYS_ENET_BAT_OK 0x0200
-#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
-#define CONFIG_SYS_ENET_FPGA_PROG 0x2000
-#define CONFIG_SYS_ENET_FPGA_INIT 0x4000
-#define CONFIG_SYS_ENET_FPGA_DONE 0x8000
-
-/*-----------------------------------------------------------------------
- * Chip Select Pin Function Select
- *
- * 1 1 1 1 1 0 0 0 }- 0xf8
- * | | | | | | | |
- * | | | | | | | +--- Reserved
- * | | | | | | +----- GPCS1_SEL = ROMCS1#
- * | | | | | +------- GPCS2_SEL = ROMCS2#
- * | | | | +--------- GPCS3_SEL = GPCS3
- * | | | +----------- GPCS4_SEL = GPCS4
- * | | +------------- GPCS5_SEL = GPCS5
- * | +--------------- GPCS6_SEL = GPCS6
- * +----------------- GPCS7_SEL = GPCS7
- */
-#define CONFIG_SYS_SC520_CSPFS 0xf8
-
-/*-----------------------------------------------------------------------
- * Clock Select (CLKTIMER[CLKTEST] pin)
- *
- * 0 111 00 1 0 }- 0x72
- * | \ / \| | |
- * | | | | +--- Pin Disabled
- * | | | +----- Pin is an output
- * | | +------- Reserved
- * | +----------- Disabled (pin stays Low)
- * +-------------- Reserved
- */
-#define CONFIG_SYS_SC520_CLKSEL 0x72
-
-/*-----------------------------------------------------------------------
- * Address Decode Control
- *
- * 0 00 0 0 0 0 0 }- 0x00
- * | \| | | | | |
- * | | | | | | +--- Integrated UART 1 is enabled
- * | | | | | +----- Integrated UART 2 is enabled
- * | | | | +------- Integrated RTC is enabled
- * | | | +--------- Reserved
- * | | +----------- I/O Hole accesses are forwarded to the external GP bus
- * | +------------- Reserved
- * +---------------- Write-protect violations do not generate an IRQ
- */
-#define CONFIG_SYS_SC520_ADDDECCTL 0x00
-
-/*-----------------------------------------------------------------------
- * UART Control
- *
- * 00000 1 1 1 }- 0x07
- * \___/ | | |
- * | | | +--- Transmit TC interrupt enable
- * | | +----- Receive TC interrupt enable
- * | +------- 1.8432 MHz
- * +----------- Reserved
- */
-#define CONFIG_SYS_SC520_UART1CTL 0x07
-#define CONFIG_SYS_SC520_UART2CTL 0x07
-
-/*-----------------------------------------------------------------------
- * System Arbiter Control
- *
- * 00000 1 1 0 }- 0x06
- * \___/ | | |
- * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
- * | | +----- The system arbiter operates in concurrent mode
- * | +------- Park the PCI bus on the last master that acquired the bus
- * +----------- Reserved
- */
-#define CONFIG_SYS_SC520_SYSARBCTL 0x06
-
-/*-----------------------------------------------------------------------
- * System Arbiter Master Enable
- *
- * 00000000000 0 0 0 1 1 }- 0x06
- * \_________/ | | | | |
- * | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
- * | | | | +----- PCI master REQ1 enabled (Ethernet 2)
- * | | | +------- PCI master REQ2 disabled
- * | | +--------- PCI master REQ3 disabled
- * | +----------- PCI master REQ4 disabled
- * +------------------ Reserved
- */
-#define CONFIG_SYS_SC520_SYSARBMENB 0x0003
-
-/*-----------------------------------------------------------------------
- * System Arbiter Master Enable
- *
- * 0 0000 0 00 0000 1 000 }- 0x06
- * | \__/ | \| \__/ | \_/
- * | | | | | | +---- Reserved
- * | | | | | +------- Enable CPU-to-PCI bus write posting
- * | | | | +---------- Reserved
- * | | | +-------------- PCI bus reads to SDRAM are not automatically
- * | | | retried
- * | | +----------------- Target read FIFOs are not snooped during write
- * | | transactions
- * | +-------------------- Reserved
- * +------------------------ Deassert the PCI bus reset signal
- */
-#define CONFIG_SYS_SC520_HBCTL 0x08
-
-/*-----------------------------------------------------------------------
- * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
- * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
- * \ / | | | | \----+----/ \-----+------/
- * | | | | | | +---------- Start at 0x38000000
- * | | | | | +----------------------- 512kB Region Size
- * | | | | | ((7 + 1) * 64kB)
- * | | | | +------------------------------ 64kB Page Size
- * | | | +-------------------------------- Writes Enabled (So it can be
- * | | | reprogrammed!)
- * | | +---------------------------------- Caching Disabled
- * | +------------------------------------ Execution Enabled
- * +--------------------------------------- BOOTCS
- */
-#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
-
-/*-----------------------------------------------------------------------
- * Cache-As-RAM (Targets Boot Flash)
- *
- * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
- * \ / | | | | \--+--/ \-------+--------/
- * | | | | | | +------------ Start at 0x19200000
- * | | | | | +------------------------- 64k Region Size
- * | | | | | ((15 + 1) * 4kB)
- * | | | | +------------------------------ 4kB Page Size
- * | | | +-------------------------------- Writes Enabled
- * | | +---------------------------------- Caching Enabled
- * | +------------------------------------ Execution Prevented
- * +--------------------------------------- BOOTCS
- */
-#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200
-
-/*-----------------------------------------------------------------------
- * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
- *
- * 001 110 0 000100000 0001000000000000 }- 0x38201000
- * \ / \ / | \---+---/ \------+-------/
- * | | | | +----------- Start at 0x00001000
- * | | | +------------------------ 33 Bytes (0x20 + 1)
- * | | +------------------------------ Ignored
- * | +--------------------------------- GPCS6
- * +------------------------------------- GP Bus I/O
- */
-#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
-
-/*-----------------------------------------------------------------------
- * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
- * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
- *
- * 010 101 0 0000000 100000000000000000 }- 0x54020000
- * 010 111 0 0000000 100000000000000001 }- 0x5c020001
- * \ / \ / | \--+--/ \-------+--------/
- * | | | | +------------ Start at 0x200000000
- * | | | | 0x200010000
- * | | | +------------------------- 4kB Region Size
- * | | | ((0 + 1) * 4kB)
- * | | +------------------------------ 4k Page Size
- * | +--------------------------------- GPCS5
- * | GPCS7
- * +------------------------------------- GP Bus Memory
- */
-#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
-#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
-
-/*-----------------------------------------------------------------------
- * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
- * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
- * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
- * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
- *
- * 001 000 0 000000111 0001001111111000 }- 0x200713f8
- * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
- * 001 011 0 000000111 0001001011111000 }- 0x300711f8
- * 001 011 0 000000111 0001001011111000 }- 0x340710f8
- * \ / \ / | \---+---/ \------+-------/
- * | | | | +----------- Start at 0x013f8
- * | | | | 0x012f8
- * | | | | 0x011f8
- * | | | | 0x010f8
- * | | | +------------------------ 33 Bytes (32 + 1)
- * | | +------------------------------ Ignored
- * | +--------------------------------- GPCS6
- * +------------------------------------- GP Bus I/O
- */
-#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
-#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
-#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
-#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
-
-/*-----------------------------------------------------------------------
- * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
- * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
- *
- * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
- * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
- * \ / | | | | \----+----/ \-----+------/
- * | | | | | | +---------- Start at 0x10000000
- * | | | | | | 0x11000000
- * | | | | | +----------------------- 16MB Region Size
- * | | | | | ((255 + 1) * 64kB)
- * | | | | +------------------------------ 64kB Page Size
- * | | | +-------------------------------- Writes Enabled
- * | | +---------------------------------- Caching Disabled
- * | +------------------------------------ Execution Enabled
- * +--------------------------------------- ROMCS1
- * ROMCS2
- */
-#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
-#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
-
-/*-----------------------------------------------------------------------
- * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
- * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
- *
- * 010 000 1 00000001111 01100100000000 }- 0x4203d900
- * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
- * \ / \ / | \----+----/ \-----+------/
- * | | | | +---------- Start at 0x19000000
- * | | | | 0x19100000
- * | | | +----------------------- 1MB Region Size
- * | | | ((15 + 1) * 64kB)
- * | | +------------------------------ 64kB Page Size
- * | +--------------------------------- GPCS0
- * | GPCS3
- * +------------------------------------- GP Bus Memory
- */
-#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
-#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
-
-/*-----------------------------------------------------------------------
- * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
- *
- * 010 100 0 00000000 11000000100000000 }- 0x50018100
- * \ / \ / | \---+--/ \-------+-------/
- * | | | | +----------- Start at 0x18100000
- * | | | +------------------------ 4kB Region Size
- * | | | ((0 + 1) * 4kB)
- * | | +------------------------------ 4kB Page Size
- * | +--------------------------------- GPCS4
- * +------------------------------------- GP Bus Memory
- */
-#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index d3eb5969dc99e37c8881a0d99841f78c3851050c..03dfe0af2d02c3fd2943d423b16d50c1e7335a72 100644 (file)
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
#define CONFIG_MACH_DAVINCI_DA850_EVM
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
+#define CONFIG_SOC_DA850 /* TI DA850 SoC */
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
index f8131b1bafdc8fc8d1a23fa5fad4299a45ebe3ab..559e3759deff0d9f5473498cd28b27b96cf7eacf 100644 (file)
#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>
+#include <asm/mach-types.h>
/*
* Display CPU and Board information
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
+/* define to enable boot progress via leds */
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
+ (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+#define CONFIG_SHOW_BOOT_PROGRESS
+#endif
+
/* USB */
#define CONFIG_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#ifdef CONFIG_BOOT_NAND
#define CONFIG_CMD_NAND
#endif
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
+ (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032)
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#endif
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 185faa7ef18c3d1bbb0711c71b48be211213bf64..1f09947706e924fa0ad0173b9bfeccd47521a489 100644 (file)
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_DRIVER_OMAP34XX_I2C
/* RTC */
index e852e3156d084ee0bbe87c401d8276ae36f6d64e..bae4ba0bb53eaa3c8b86afac3ab84d967363dcf0 100644 (file)
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ENV_IS_NOWHERE
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
index eed38c165f0cf9bb259be4970906f76800969b10..d172e56bcfca55f53d81987c6fc9e3036c3b4a28 100644 (file)
# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
#endif
-/* FSL */
-/* #define CONFIG_SYS_FSL_2 */
-/* #define FSL_INTR_2 1 */
-
/*
* memory layout - Example
* CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk
index d0daa455e5243ccbf616c4352a12e414319fe2ca..59255c4e267bd6376b523b459fded7b738c6a81d 100644 (file)
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_I2C_MULTI_BUS 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#define CONFIG_VIDEO_OMAP3 /* DSS Support */
index 2ef3aaa18706d948f743487f9695d983100fffc7..b1f11c01c616ac82b99e6c7e399875eca021accb 100644 (file)
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
/*
* PISMO support
index b2457d0bc6e72c9cb0f54a538c0b037c25245ce4..629118e44b5690691edd1d59416f9b9499685ee6 100644 (file)
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_I2C_MULTI_BUS
/*
index 09a0b2f719203a372009d596edcdd4468a539b65..376a3d031edc78fa7c12ce1ca77c3e1f0c8866f2 100644 (file)
/*
* select serial console configuration
*/
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
-#define CONFIG_SERIAL3 3 /* UART3 */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CONFIG_SERIAL1 1 /* UART1 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
+/* silent console by default */
+#define CONFIG_SYS_DEVICE_NULLDEV 1
+#define CONFIG_SILENT_CONSOLE 1
+
/* USB */
#define CONFIG_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0
-#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
-#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#define CONFIG_I2C_MULTI_BUS 1
/* Environment information */
#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
-#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTDELAY 0
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_STOP_STR "S"
#define CONFIG_EXTRA_ENV_SETTINGS \
+ "silent=true\0" \
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
- "console=ttyO2,115200n8\0" \
+ "console=ttyO0,115200n8\0" \
"mpurate=600\0" \
"vram=12M\0" \
"dvimode=1024x768-24@60\0" \
"defaultdisplay=dvi\0" \
- "fpgafilename=mvbluelynx_x.rbf\0" \
- "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
- "fpga load 0 ${loadaddr} ${filesize}; " \
+ "loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\
+ "/lib/firmware/mvblx/${fpgafilename}; then " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
"fi;\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"omapdss.def_disp=${defaultdisplay} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype} " \
+ "mvfw.fpgavers=${fpgavers} " \
"${cmdline_suffix}\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
"importbootenv=echo Importing environment from mmc ...; " \
index 217f306c0198374d649e109c7d8d4f491e362130..ee888418c59a84779622b9b47f6a88a7c744f706 100644 (file)
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
index b02ec850b7d3a23e772ce3cc7264d61eff0a9d7f..19c6a3d33a0096bec5bae9a8e423c7b828e605f2 100644 (file)
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
index ee4cbd75c1bb77236babe59778c97015842ce4db..b48f21aa3e77205d98632260a973222046b563a3 100644 (file)
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
index a6b48a80ce42c58f8f2ffcd79bbcc7bf84c27f67..27527ce4c67c5579d87190a593704e2559590051 100644 (file)
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
index a32369af3270b0df5eb6bfca83158146a386377e..180cb24f388293b4161e9a1f007689eba0bb4e4b 100644 (file)
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#define CONFIG_I2C_MULTI_BUS 1
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
"source ${loadaddr}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+ "env import -t ${loadaddr} ${filesize}\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc${mmcdev} ...; " \
"run mmcargs; " \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi; " \
+ "if run loadbootenv; then " \
+ "run importbootenv; " \
+ "fi;" \
+ "if test -n ${uenvcmd}; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
"fi; " \
"fi"
index 38c79cfc2b58a00383d4b19c9ba127492df969cf..2edb4aaba955d2b7a58e9168cdc5c37f42a8c6d8 100644 (file)
--- a/include/configs/paz00.h
+++ b/include/configs/paz00.h
#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CONSOLE_SCROLL_LINES 10
+
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
--- /dev/null
+++ b/include/configs/pcm051.h
@@ -0,0 +1,301 @@
+/*
+ * pcm051.h
+ *
+ * Phytec phyCORE-AM335x (pcm051) boards information header
+ *
+ * Copyright (C) 2013 Lemonage Software GmbH
+ * Author Lars Poeschel <poeschel@lemonage.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_PCM051_H
+#define __CONFIG_PCM051_H
+
+#define CONFIG_AM33XX
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
+
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT "U-Boot# "
+#define CONFIG_SYS_NO_FLASH
+#define MACH_TYPE_PCM051 4144 /* Until the next sync */
+#define CONFIG_MACH_TYPE MACH_TYPE_PCM051
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_VERSION_VARIABLE
+
+/* set to negative value for no autoboot */
+#define CONFIG_BOOTDELAY 1
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x80007fc0\0" \
+ "fdtaddr=0x80000000\0" \
+ "rdaddr=0x81000000\0" \
+ "bootfile=uImage\0" \
+ "fdtfile=pcm051.dtb\0" \
+ "console=ttyO0,115200n8\0" \
+ "optargs=\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 ro\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+ "ramrootfstype=ext2\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "bootenv=uEnv.txt\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "ramargs=setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=${ramroot} " \
+ "rootfstype=${ramrootfstype}\0" \
+ "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+ "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+ "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "ramboot=echo Booting from ramdisk ...; " \
+ "run ramargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loaded environment from ${bootenv};" \
+ "run importbootenv;" \
+ "fi;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot;" \
+ "fi;" \
+ "fi;" \
+
+/* Clock Defines */
+#define V_OSCK 25000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK)
+
+#define CONFIG_CMD_ECHO
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/*
+ * memtest works on 8 MB in DRAM after skipping 32MB from
+ * start addr of ram disk
+ */
+#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ + (8 * 1024 * 1024))
+
+#define CONFIG_SYS_LOAD_ADDR 0x80007fc0 /* Default load address */
+#define CONFIG_SYS_HZ 1000 /* 1ms clock */
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_SPI
+#define CONFIG_OMAP3_SPI
+#define CONFIG_MTD_DEVICE
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 24000000
+
+ /* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
+#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
+#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 19) /* 512MiB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
+ GENERATED_GBL_DATA_SIZE)
+ /* Platform/Board specific defs */
+#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CONS_INDEX 1
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK (48000000)
+#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
+#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
+#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
+#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
+#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
+#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
+
+/* I2C Configuration */
+#define CONFIG_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_DRIVER_OMAP24XX_I2C
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+
+#define CONFIG_OMAP_GPIO
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
+4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x402F0400
+#define CONFIG_SPL_MAX_SIZE (101 * 1024)
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING "pcm051 U-Boot SPL"
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+
+/* Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/*
+ * USB configuration
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_MUSB_GADGET
+#define CONFIG_MUSB_PIO_ONLY
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_MUSB_HOST
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
+#define CONFIG_AM335X_USB1
+#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+
+#ifdef CONFIG_MUSB_HOST
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_MUSB_GADGET
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#endif /* CONFIG_MUSB_GADGET */
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR 0
+#define CONFIG_PHY_SMSC
+
+#endif /* ! __CONFIG_PCM051_H */
index 21c76b52743a08d083375a42c520cd01a1c2517e..decf8d9dec855aeef9408cc1905c0ed91be90bcb 100644 (file)
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_FEC_MXC
#define CONFIG_MII
-#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
index d58c24c4aa46883f45f95148b9dd12b3efba5e8e..2c665b8a9dd656ea78e3707362d3268e6a58cce4 100644 (file)
--- a/include/configs/t4qds.h
+++ b/include/configs/t4qds.h
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
-#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
- FTIM0_NOR_TEADC(0x01) | \
- FTIM0_NOR_TEAHC(0x20))
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
+ FTIM0_NOR_TEADC(0x5) | \
+ FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
FTIM1_NOR_TRAD_NOR(0x1A) |\
FTIM1_NOR_TSEQRAD_NOR(0x13))
-#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
- FTIM2_NOR_TCH(0x0E) | \
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
+ FTIM2_NOR_TCH(0x4) | \
FTIM2_NOR_TWPH(0x0E) | \
FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3 0x0
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
| CSPR_V)
-#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024)
#define CONFIG_SYS_CSOR3 0x0
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
index 9f1fb9feef8f9df717d3d130b32d0e866b86d729..2af504baa42f4997651eb8e73846da5ee7d6ea55 100644 (file)
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
diff --git a/include/configs/tec.h b/include/configs/tec.h
index 200cf66647c02dcbdc331d28d2a838d197ea4721..caeb9cd8a85cc76d54f0bdae2bc1d925ed6b8efd 100644 (file)
--- a/include/configs/tec.h
+++ b/include/configs/tec.h
/* High-level configuration options */
#define V_PROMPT "Tegra20 (TEC) # "
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier"
-#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
/* SD/MMC */
#define CONFIG_MMC
"ext2load mmc 0 0x17000000 /boot/uImage;" \
"bootm"
+/* LCD support */
+#define CONFIG_LCD
+#define CONFIG_PWM_TEGRA
+#define CONFIG_VIDEO_TEGRA
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
+
#include "tegra-common-post.h"
#endif /* __CONFIG_H */
index ee40cc2a3e0e26a38d3ddf58bf5f74c01db5c190..f2a70b1a35c87fcaed23f2eace5ded446d8a3f43 100644 (file)
#endif
-/*
- * Memory layout for where various images get loaded by boot scripts:
- *
- * scriptaddr can be pretty much anywhere that doesn't conflict with something
- * else. Put it above BOOTMAPSZ to eliminate conflicts.
- *
- * kernel_addr_r must be within the first 128M of RAM in order for the
- * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
- * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
- * should not overlap that area, or the kernel will have to copy itself
- * somewhere else before decompression. Similarly, the address of any other
- * data passed to the kernel shouldn't overlap the start of RAM. Pushing
- * this up to 16M allows for a sizable kernel to be decompressed below the
- * compressed load address.
- *
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- * the compressed kernel to be up to 16M too.
- *
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
- * for the FDT/DTB to be up to 1M, which is hopefully plenty.
- */
-#define MEM_LAYOUT_ENV_SETTINGS \
- "scriptaddr=0x10000000\0" \
- "kernel_addr_r=0x01000000\0" \
- "fdt_addr_r=0x02000000\0" \
- "ramdisk_addr_r=0x02100000\0" \
-
#ifdef CONFIG_TEGRA_KEYBOARD
#define STDIN_KBD_KBC ",tegra-kbc"
#else
#define STDIN_KBD_USB ""
#endif
+#ifdef CONFIG_VIDEO_TEGRA
+#define STDOUT_LCD ",lcd"
+#else
+#define STDOUT_LCD ""
+#endif
+
#define TEGRA_DEVICE_SETTINGS \
"stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \
- "stdout=serial,lcd\0" \
- "stderr=serial,lcd\0" \
+ "stdout=serial" STDOUT_LCD "\0" \
+ "stderr=serial" STDOUT_LCD "\0" \
+ ""
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA_DEVICE_SETTINGS \
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
--- /dev/null
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TEGRA_COMMON_H
+#define __TEGRA_COMMON_H
+#include <asm/sizes.h>
+#include <linux/stringify.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
+#define CONFIG_TEGRA /* which is a Tegra generic machine */
+#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#include <asm/arch/tegra.h> /* get chip and board defs */
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
+
+/* Environment */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
+
+/*
+ * PllX Configuration
+ */
+#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+
+/* include default commands */
+#include <config_cmd_default.h>
+
+/* remove unused commands */
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration support */
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NFS /* NFS support */
+#undef CONFIG_CMD_NET /* network support */
+
+/* turn on command-line edit/hist/auto */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT V_PROMPT
+/*
+ * Increasing the size of the IO buffer as default nfsargs size is more
+ * than 256 and so it is not possible to edit it
+ */
+#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
+
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
+
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
+
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
+#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_TEGRA_GPIO
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_ENTERRCM
+#define CONFIG_CMD_BOOTZ
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
+ CONFIG_SPL_TEXT_BASE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#endif /* _TEGRA_COMMON_H_ */
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
--- /dev/null
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA114_COMMON_H_
+#define _TEGRA114_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
+#define CONFIG_STACKBASE 0x82800000 /* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE 0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ * the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x90000000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x82000000\0" \
+ "ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE 0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
+#define CONFIG_SPL_STACK 0x800ffffc
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra114/u-boot-spl.lds"
+
+#endif /* _TEGRA114_COMMON_H_ */
index fe07f72260de43ef37cd982fab60fa9ccb9ff0bc..33e5f524f16d4e17dc68c81fe34e978a69e2042b 100644 (file)
* MA 02111-1307 USA
*/
-#ifndef __TEGRA20_COMMON_H
-#define __TEGRA20_COMMON_H
-#include <asm/sizes.h>
-#include <linux/stringify.h>
+#ifndef _TEGRA20_COMMON_H_
+#define _TEGRA20_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
/*
* High Level Configuration Options
*/
-#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
-#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
-#define CONFIG_TEGRA /* which is a Tegra generic machine */
-#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
+#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
-#define CONFIG_SYS_CACHELINE_SIZE 32
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
-#include <asm/arch/tegra.h> /* get chip and board defs */
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
+#define CONFIG_STACKBASE 0x02800000 /* 40MB */
-/* Align LCD to 1MB boundary */
-#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE 0x0010E000
/*
- * Display CPU and Board information
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ * the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x10000000\0" \
+ "kernel_addr_r=0x01000000\0" \
+ "fdt_addr_r=0x02000000\0" \
+ "ramdisk_addr_r=0x02100000\0"
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE 0x00108000
+#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
+#define CONFIG_SPL_STACK 0x000ffffc
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
+
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
#ifdef CONFIG_TEGRA_LP0
#define TEGRA_LP0_ADDR 0x1C406000
#define TEGRA_LP0_SIZE 0x2000
#define TEGRA_LP0_VEC \
- "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
+ "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
"@" __stringify(TEGRA_LP0_ADDR) " "
#else
#define TEGRA_LP0_VEC
#endif
-/* Environment */
-#define CONFIG_ENV_VARS_UBOOT_CONFIG
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
-
-/*
- * PllX Configuration
- */
-#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
-
-/*
- * NS16550 Configuration
- */
-#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX 1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
/*
* This parameter affects a TXFILLTUNING field that controls how much data is
* sent to the latency fifo before it is sent to the wire. Without this
/* Total I2C ports on Tegra20 */
#define TEGRA_I2C_NUM_CONTROLLERS 4
-/* include default commands */
-#include <config_cmd_default.h>
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
-/* remove unused commands */
-#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#undef CONFIG_CMD_FPGA /* FPGA configuration support */
-#undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NFS /* NFS support */
-#undef CONFIG_CMD_NET /* network support */
-
-/* turn on command-line edit/hist/auto */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
-
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
-#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT V_PROMPT
-/*
- * Increasing the size of the IO buffer as default nfsargs size is more
- * than 256 and so it is not possible to edit it
- */
-#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
-
-#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_STACKBASE 0x2800000 /* 40MB */
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
-
-#define CONFIG_SYS_TEXT_BASE 0x0010c000
-#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_TEGRA_GPIO
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_ENTERRCM
-#define CONFIG_CMD_BOOTZ
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_RAM_DEVICE
-#define CONFIG_SPL_BOARD_INIT
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE 0x00108000
-#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
- CONFIG_SPL_TEXT_BASE)
-#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
-#define CONFIG_SPL_STACK 0x000ffffc
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
-
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* Misc utility code */
#define CONFIG_BOUNCE_BUFFER
-#endif /* __TEGRA20_COMMON_H */
+#endif /* _TEGRA20_COMMON_H_ */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
--- /dev/null
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA30_COMMON_H_
+#define _TEGRA30_COMMON_H_
+#include "tegra-common.h"
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
+
+/* Environment information, boards can override if required */
+#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
+#define CONFIG_STACKBASE 0x82800000 /* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_SYS_TEXT_BASE 0x8010E000
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ * else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ * should not overlap that area, or the kernel will have to copy itself
+ * somewhere else before decompression. Similarly, the address of any other
+ * data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ * this up to 16M allows for a sizable kernel to be decompressed below the
+ * compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ * the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+ "scriptaddr=0x90000000\0" \
+ "kernel_addr_r=0x81000000\0" \
+ "fdt_addr_r=0x82000000\0" \
+ "ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE 0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
+#define CONFIG_SPL_STACK 0x800ffffc
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds"
+
+/* Total I2C ports on Tegra30 */
+#define TEGRA_I2C_NUM_CONTROLLERS 5
+
+#endif /* _TEGRA30_COMMON_H_ */
index bcb0350b8c740b747606c5d07ab800fc2b1e414e..1a665ac3ac0b7737fc837ec1838ed3cdb7b7c2c2 100644 (file)
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_SYS_I2C_BUS 0
-#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/* TWL4030 */
diff --git a/include/configs/zynq.h b/include/configs/zynq.h
index 18fd76f47e06283190c96160f0d6200014e0aadd..2989e723e04c6f5633aa80d978570a553096e06b 100644 (file)
--- a/include/configs/zynq.h
+++ b/include/configs/zynq.h
#define CONFIG_ZYNQ_GEM
#define CONFIG_ZYNQ_GEM_BASEADDR0 0xE000B000
+#if defined(CONFIG_ZYNQ_DCC)
+# define CONFIG_ARM_DCC
+# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
+#endif
+
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
diff --git a/include/fat.h b/include/fat.h
index 706cd7a4bd3467444d3b870bad8ac23743a5ad3a..b28c3fd66855e6d559cdea308c481d3995dea8d0 100644 (file)
--- a/include/fat.h
+++ b/include/fat.h
#endif
#endif
-#define TOLOWER(c) if((c) >= 'A' && (c) <= 'Z'){(c)+=('a' - 'A');}
-#define TOUPPER(c) if ((c) >= 'a' && (c) <= 'z') \
- (c) -= ('a' - 'A');
#define START(dent) (FAT2CPU16((dent)->start) \
+ (mydata->fatsize != 32 ? 0 : \
(FAT2CPU16((dent)->starthi) << 16)))
diff --git a/include/fdt.h b/include/fdt.h
index c51212e05b4f41305c30682b61e62b11ecede12d..f9612ed821233aff4ae5419bf57434e55f4007bc 100644 (file)
--- a/include/fdt.h
+++ b/include/fdt.h
#ifndef __ASSEMBLY__
struct fdt_header {
- uint32_t magic; /* magic word FDT_MAGIC */
- uint32_t totalsize; /* total size of DT block */
- uint32_t off_dt_struct; /* offset to structure */
- uint32_t off_dt_strings; /* offset to strings */
- uint32_t off_mem_rsvmap; /* offset to memory reserve map */
- uint32_t version; /* format version */
- uint32_t last_comp_version; /* last compatible version */
+ fdt32_t magic; /* magic word FDT_MAGIC */
+ fdt32_t totalsize; /* total size of DT block */
+ fdt32_t off_dt_struct; /* offset to structure */
+ fdt32_t off_dt_strings; /* offset to strings */
+ fdt32_t off_mem_rsvmap; /* offset to memory reserve map */
+ fdt32_t version; /* format version */
+ fdt32_t last_comp_version; /* last compatible version */
/* version 2 fields below */
- uint32_t boot_cpuid_phys; /* Which physical CPU id we're
+ fdt32_t boot_cpuid_phys; /* Which physical CPU id we're
booting on */
/* version 3 fields below */
- uint32_t size_dt_strings; /* size of the strings block */
+ fdt32_t size_dt_strings; /* size of the strings block */
/* version 17 fields below */
- uint32_t size_dt_struct; /* size of the structure block */
+ fdt32_t size_dt_struct; /* size of the structure block */
};
struct fdt_reserve_entry {
- uint64_t address;
- uint64_t size;
+ fdt64_t address;
+ fdt64_t size;
};
struct fdt_node_header {
- uint32_t tag;
+ fdt32_t tag;
char name[0];
};
struct fdt_property {
- uint32_t tag;
- uint32_t len;
- uint32_t nameoff;
+ fdt32_t tag;
+ fdt32_t len;
+ fdt32_t nameoff;
char data[0];
};
#endif /* !__ASSEMBLY */
#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */
-#define FDT_TAGSIZE sizeof(uint32_t)
+#define FDT_TAGSIZE sizeof(fdt32_t)
#define FDT_BEGIN_NODE 0x1 /* Start node: full name */
#define FDT_END_NODE 0x2 /* End node */
#define FDT_NOP 0x4 /* nop */
#define FDT_END 0x9
-#define FDT_V1_SIZE (7*sizeof(uint32_t))
-#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(uint32_t))
-#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(uint32_t))
+#define FDT_V1_SIZE (7*sizeof(fdt32_t))
+#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t))
+#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t))
#define FDT_V16_SIZE FDT_V3_SIZE
-#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(uint32_t))
+#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t))
/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
#define FDT_RAMDISK_OVERHEAD 0x80
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 4b9f84a24a3dc496fff0dddbcf3bf95fe3549312..2cccc3551db4e584325c9ea50d29285359fc68c6 100644 (file)
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
#ifdef CONFIG_OF_LIBFDT
-#include <fdt.h>
+#include <libfdt.h>
u32 fdt_getprop_u32_default(const void *fdt, const char *path,
const char *prop, const u32 dflt);
void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
void fdt_del_node_and_alias(void *blob, const char *alias);
-u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr);
+u64 fdt_translate_address(void *blob, int node_offset, const __be32 *in_addr);
int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
phys_addr_t compat_off);
int fdt_alloc_phandle(void *blob);
diff --git a/include/fdtdec.h b/include/fdtdec.h
index f77d195630bc088a6d2c82d62f2ee6e3ebb24162..77f244f4171106f1eed6234a0c4b2409eebfb0bc 100644 (file)
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
+ COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
+ COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */
COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */
COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
diff --git a/include/image.h b/include/image.h
index f5adc5035360633024de1b67cfee73f8811f17c8..8e285f9b9ff963877bc954871473d6cdd70a3fd8 100644 (file)
--- a/include/image.h
+++ b/include/image.h
#endif /* USE_HOSTCC */
#if defined(CONFIG_FIT)
-#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#define CONFIG_MD5 /* FIT images need MD5 support */
diff --git a/include/libfdt.h b/include/libfdt.h
index c93ae28833e172c3bca7ee188da1c200f3eb27c5..fc7f75b9ffa60b6bc23f44d39b59c4d0f4b7be3b 100644 (file)
--- a/include/libfdt.h
+++ b/include/libfdt.h
static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset,
const char *name, uint32_t val)
{
- val = cpu_to_fdt32(val);
- return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
+ fdt32_t tmp = cpu_to_fdt32(val);
+ return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
}
/**
static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset,
const char *name, uint64_t val)
{
- val = cpu_to_fdt64(val);
- return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
+ fdt64_t tmp = cpu_to_fdt64(val);
+ return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
}
/**
int fdt_property(void *fdt, const char *name, const void *val, int len);
static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val)
{
- val = cpu_to_fdt32(val);
- return fdt_property(fdt, name, &val, sizeof(val));
+ fdt32_t tmp = cpu_to_fdt32(val);
+ return fdt_property(fdt, name, &tmp, sizeof(tmp));
}
static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val)
{
- val = cpu_to_fdt64(val);
- return fdt_property(fdt, name, &val, sizeof(val));
+ fdt64_t tmp = cpu_to_fdt64(val);
+ return fdt_property(fdt, name, &tmp, sizeof(tmp));
}
static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
{
static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,
uint32_t val)
{
- val = cpu_to_fdt32(val);
- return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
+ fdt32_t tmp = cpu_to_fdt32(val);
+ return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
}
/**
@@ -1189,8 +1189,8 @@ static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,
static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name,
uint64_t val)
{
- val = cpu_to_fdt64(val);
- return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
+ fdt64_t tmp = cpu_to_fdt64(val);
+ return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
}
/**
static inline int fdt_appendprop_u32(void *fdt, int nodeoffset,
const char *name, uint32_t val)
{
- val = cpu_to_fdt32(val);
- return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val));
+ fdt32_t tmp = cpu_to_fdt32(val);
+ return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
}
/**
static inline int fdt_appendprop_u64(void *fdt, int nodeoffset,
const char *name, uint64_t val)
{
- val = cpu_to_fdt64(val);
- return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val));
+ fdt64_t tmp = cpu_to_fdt64(val);
+ return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
}
/**
diff --git a/include/libfdt_env.h b/include/libfdt_env.h
index bf63583d53a9adcea1d9151698b5a9fc03d4e157..3e3defc76ca36068a297dab17623d9525e288ec4 100644 (file)
--- a/include/libfdt_env.h
+++ b/include/libfdt_env.h
#define _LIBFDT_ENV_H
#include "compiler.h"
+#include "linux/types.h"
extern struct fdt_header *working_fdt; /* Pointer to the working fdt */
+typedef __be16 fdt16_t;
+typedef __be32 fdt32_t;
+typedef __be64 fdt64_t;
+
#define fdt32_to_cpu(x) be32_to_cpu(x)
#define cpu_to_fdt32(x) cpu_to_be32(x)
#define fdt64_to_cpu(x) be64_to_cpu(x)
diff --git a/include/serial.h b/include/serial.h
index 14f863ed20ec73f67ed2df791ad2ad4b904b689c..f6bb2b90a1ee196c4a353ab0708e1146c2c139a0 100644 (file)
--- a/include/serial.h
+++ b/include/serial.h
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
- defined(CONFIG_TEGRA20) || defined(CONFIG_SYS_COREBOOT) || \
+ defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \
defined(CONFIG_MICROBLAZE)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
diff --git a/include/stdio_dev.h b/include/stdio_dev.h
index 932d093345e59ade1c175b13fe677dfdcee935dc..9451740e8be4a51071a8e6aa4c94f45d1815ded9 100644 (file)
--- a/include/stdio_dev.h
+++ b/include/stdio_dev.h
struct stdio_dev* stdio_get_by_name(const char* name);
struct stdio_dev* stdio_clone(struct stdio_dev *dev);
-#ifdef CONFIG_ARM_DCC_MULTI
+#ifdef CONFIG_ARM_DCC
int drv_arm_dcc_init(void);
#endif
#ifdef CONFIG_LCD
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 16921e14c9c3ce31b2510cb1f66a16c755d886ef..3ae348dd307bc64aa2ffa8a95d0177d98da7d55b 100644 (file)
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+ COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
+ COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"),
COMPAT(SMSC_LAN9215, "smsc,lan9215"),
COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),
diff --git a/lib/libfdt/fdt.c b/lib/libfdt/fdt.c
index 4157b21efda2eb11585a0e1bf08d94cd8e754a24..387e3544b7e578832eb4f27b443547b92d7e966a 100644 (file)
--- a/lib/libfdt/fdt.c
+++ b/lib/libfdt/fdt.c
uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
{
- const uint32_t *tagp, *lenp;
+ const fdt32_t *tagp, *lenp;
uint32_t tag;
int offset = startoffset;
const char *p;
diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c
index 1933010fd8f170a020ee1ab7cffd282ce2ff00d2..1a461c3e9795150ffe154568e68dc81b70afd77b 100644 (file)
--- a/lib/libfdt/fdt_ro.c
+++ b/lib/libfdt/fdt_ro.c
uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)
{
- const uint32_t *php;
+ const fdt32_t *php;
int len;
/* FIXME: This is a bit sub-optimal, since we potentially scan
diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c
index 5ed23d6f1934699540b60cb437f0c740dc43956c..aba60948416e1cd7a802770f94627089d685446e 100644 (file)
--- a/lib/libfdt/fdt_rw.c
+++ b/lib/libfdt/fdt_rw.c
int nodelen;
int err;
uint32_t tag;
- uint32_t *endtag;
+ fdt32_t *endtag;
FDT_RW_CHECK_HEADER(fdt);
nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
memset(nh->name, 0, FDT_TAGALIGN(namelen+1));
memcpy(nh->name, name, namelen);
- endtag = (uint32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
+ endtag = (fdt32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
*endtag = cpu_to_fdt32(FDT_END_NODE);
return offset;
diff --git a/lib/libfdt/fdt_sw.c b/lib/libfdt/fdt_sw.c
index 55ebebf1eb20e8c7f9200881f99ecf03632db9a3..f422754de9d28df97b99db3506e6b2135dfb4921 100644 (file)
--- a/lib/libfdt/fdt_sw.c
+++ b/lib/libfdt/fdt_sw.c
int fdt_end_node(void *fdt)
{
- uint32_t *en;
+ fdt32_t *en;
FDT_SW_CHECK_HEADER(fdt);
int fdt_finish(void *fdt)
{
char *p = (char *)fdt;
- uint32_t *end;
+ fdt32_t *end;
int oldstroffset, newstroffset;
uint32_t tag;
int offset, nextoffset;
diff --git a/lib/libfdt/fdt_wip.c b/lib/libfdt/fdt_wip.c
index e373677c504d1d854af0151f535ce508b1eeddfc..63e67b78c882b5621d30c6a2214034ba7c40356a 100644 (file)
--- a/lib/libfdt/fdt_wip.c
+++ b/lib/libfdt/fdt_wip.c
static void _fdt_nop_region(void *start, int len)
{
- uint32_t *p;
+ fdt32_t *p;
for (p = start; (char *)p < ((char *)start + len); p++)
*p = cpu_to_fdt32(FDT_NOP);
diff --git a/nand_spl/board/freescale/mpc8313erdb/Makefile b/nand_spl/board/freescale/mpc8313erdb/Makefile
+++ /dev/null
@@ -1,108 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-# (C) Copyright 2008 Freescale Semiconductor
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-NAND_SPL := y
-PAD_TO := 0xfff04000
-
-include $(TOPDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL
-
-SOBJS = start.o ticks.o
-COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \
- time.o cache.o
-
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-$(obj)start.S:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $(obj)start.S
-
-$(obj)nand_boot_fsl_elbc.c:
- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
- $(obj)nand_boot_fsl_elbc.c
-
-$(obj)sdram.c:
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $(obj)sdram.c
-
-$(obj)$(BOARD).c:
- ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $(obj)$(BOARD).c
-
-$(obj)ns16550.c:
- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)nand_init.c:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
-
-$(obj)cache.c:
- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)time.c:
- ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c
-
-$(obj)ticks.S:
- ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
-
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile
index cff2a43d66083a143b911bc0865b43f78c1673ad..f997b5f81fee173e2bb84634762394490eb7092a 100644 (file)
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o ticks.o
-COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \
+COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
time.o cache.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
$(obj)ns16550.c:
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-$(obj)nand_init.c:
- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
+$(obj)spl_minimal.c:
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $(obj)spl_minimal.c
$(obj)cache.c:
ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
index 2a3ddac52d4b471ccc92dcea295cf6f871e8df1a..d967846f74f871a47677566dae726d0ac99aec91 100644 (file)
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o ticks.o
-COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \
+COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
time.o cache.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
@rm -f $@
ln -s $(SRCTREE)/drivers/serial/ns16550.c $@
-$(obj)nand_init.c:
+$(obj)spl_minimal.c:
@rm -f $@
- ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
$(obj)cache.c:
@rm -f $@
diff --git a/spl/Makefile b/spl/Makefile
index d8efad0290c3af1a2ddd36e86883e96b48fc2034..aac614686e801f8613ad9fa81c142583d91fcc65 100644 (file)
--- a/spl/Makefile
+++ b/spl/Makefile
LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o
LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o
LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
+LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o
+LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o
ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
endif
-ifeq ($(SOC),tegra20)
+ifneq ($(CONFIG_TEGRA),)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
diff --git a/tools/fdt_host.h b/tools/fdt_host.h
index 085013e02e7dd24f834daff55445b59f12a32ea0..b08bf866ee49ceb6e5092c5904d6bd3f3ab2be61 100644 (file)
--- a/tools/fdt_host.h
+++ b/tools/fdt_host.h
#define __FDT_HOST_H__
/* Make sure to include u-boot version of libfdt include files */
-#include "../include/fdt.h"
#include "../include/libfdt.h"
#include "../include/fdt_support.h"
diff --git a/tools/imls/imls.c b/tools/imls/imls.c
index b21c505d48d84dcf7bfe840a1a272d3b10ae4728..a982a1378a8ae5bc7e44ee765a33dde02aa44172 100644 (file)
--- a/tools/imls/imls.c
+++ b/tools/imls/imls.c
#endif
#include <sha1.h>
-#include <fdt.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <image.h>
diff --git a/tools/patman/README b/tools/patman/README
index dc3957ce6fd0442639576b59bdb8b0b9c302bae3..1832ebd18326ba47b3292dda10fadc8f46a1fefd 100644 (file)
--- a/tools/patman/README
+++ b/tools/patman/README
in one of your commits, the series will be sent there.
+In Linux this will also call get_maintainer.pl on each of your
+patches automatically.
+
How to use this tool
====================
How to configure it
===================
-For most cases patman will locate and use the file 'doc/git-mailrc' in
-your U-Boot directory. This contains most of the aliases you will need.
+For most cases of using patman for U-Boot developement patman will
+locate and use the file 'doc/git-mailrc' in your U-Boot directory.
+This contains most of the aliases you will need.
+
+For Linux the 'scripts/get_maintainer.pl' handles figuring out where
+to send patches pretty well.
During the first run patman creates a config file for you by taking the default
user name and email address from the global .gitconfig file.
used. Failing that you can put it into your path or ~/bin/checkpatch.pl
+If you want to change the defaults for patman's command-line arguments,
+you can add a [settings] section to your .patman file. This can be used
+for any command line option by referring to the "dest" for the option in
+patman.py. For reference, the useful ones (at the moment) shown below
+(all with the non-default setting):
+
+>>>
+
+[settings]
+ignore_errors: True
+process_tags: False
+verbose: True
+
+<<<
+
+
+If you want to adjust settings (or aliases) that affect just a single
+project you can add a section that looks like [project_settings] or
+[project_alias]. If you want to use tags for your linux work, you could
+do:
+
+>>>
+
+[linux_settings]
+process_tags: True
+
+<<<
+
+
How to run it
=============
will create a patch which is copied to x86, arm, sandbox, mikef, ag and
afleming.
+If you have a cover letter it will get sent to the union of the CC lists of
+all of the other patches.
+
Example Work Flow
=================
index d831087d88b39706b6afee2e70d79ecc8fe434ca..d3a0477bbf1c905078b486d4242e375d4902c9bf 100644 (file)
import gitutil
import os
import re
+import sys
import terminal
def FindCheckPatch():
+ top_level = gitutil.GetTopLevel()
try_list = [
os.getcwd(),
os.path.join(os.getcwd(), '..', '..'),
- os.path.join(gitutil.GetTopLevel(), 'tools'),
+ os.path.join(top_level, 'tools'),
+ os.path.join(top_level, 'scripts'),
'%s/bin' % os.getenv('HOME'),
]
# Look in current dir
if os.path.isfile(fname):
return fname
path = os.path.dirname(path)
- print 'Could not find checkpatch.pl'
- return None
+
+ print >> sys.stderr, ('Cannot find checkpatch.pl - please put it in your ' +
+ '~/bin directory or use --no-check')
+ sys.exit(1)
def CheckPatch(fname, verbose=False):
"""Run checkpatch.pl on a file.
error_count, warning_count, lines = 0, 0, 0
problems = []
chk = FindCheckPatch()
- if not chk:
- raise OSError, ('Cannot find checkpatch.pl - please put it in your ' +
- '~/bin directory')
item = {}
stdout = command.Output(chk, '--no-tree', fname)
#pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE)
diff --git a/tools/patman/get_maintainer.py b/tools/patman/get_maintainer.py
--- /dev/null
@@ -0,0 +1,63 @@
+# Copyright (c) 2012 The Chromium OS Authors.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+import command
+import gitutil
+import os
+
+def FindGetMaintainer():
+ """Look for the get_maintainer.pl script.
+
+ Returns:
+ If the script is found we'll return a path to it; else None.
+ """
+ try_list = [
+ os.path.join(gitutil.GetTopLevel(), 'scripts'),
+ ]
+ # Look in the list
+ for path in try_list:
+ fname = os.path.join(path, 'get_maintainer.pl')
+ if os.path.isfile(fname):
+ return fname
+
+ return None
+
+def GetMaintainer(fname, verbose=False):
+ """Run get_maintainer.pl on a file if we find it.
+
+ We look for get_maintainer.pl in the 'scripts' directory at the top of
+ git. If we find it we'll run it. If we don't find get_maintainer.pl
+ then we fail silently.
+
+ Args:
+ fname: Path to the patch file to run get_maintainer.pl on.
+
+ Returns:
+ A list of email addresses to CC to.
+ """
+ get_maintainer = FindGetMaintainer()
+ if not get_maintainer:
+ if verbose:
+ print "WARNING: Couldn't find get_maintainer.pl"
+ return []
+
+ stdout = command.Output(get_maintainer, '--norolestats', fname)
+ return stdout.splitlines()
index 72d37a0b04e5bd752b107a95c15c700f33ff4164..ca3ba4a03e49a01e40522b5fdd03df5ef514fdbc 100644 (file)
--- a/tools/patman/gitutil.py
+++ b/tools/patman/gitutil.py
Returns:
Git command that was/would be run
+ # For the duration of this doctest pretend that we ran patman with ./patman
+ >>> _old_argv0 = sys.argv[0]
+ >>> sys.argv[0] = './patman'
+
>>> alias = {}
>>> alias['fred'] = ['f.bloggs@napier.co.nz']
>>> alias['john'] = ['j.bloggs@napier.co.nz']
'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \
"f.bloggs@napier.co.nz" --cc "j.bloggs@napier.co.nz" --cc \
"m.poppins@cloud.net" --cc-cmd "./patman --cc-cmd cc-fname" cover p1 p2'
+
+ # Restore argv[0] since we clobbered it.
+ >>> sys.argv[0] = _old_argv0
"""
to = BuildEmailList(series.get('to'), '--to', alias)
if not to:
This test makes sure that we are running tests in the right subdir
- >>> os.path.realpath(os.getcwd()) == \
- os.path.join(GetTopLevel(), 'tools', 'scripts', 'patman')
+ >>> os.path.realpath(os.path.dirname(__file__)) == \
+ os.path.join(GetTopLevel(), 'tools', 'patman')
True
"""
return command.OutputOneLine('git', 'rev-parse', '--show-toplevel')
def Setup():
"""Set up git utils, by reading the alias files."""
- settings.Setup('')
-
# Check for a git alias file also
alias_fname = GetAliasFile()
if alias_fname:
diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index cfe06d08236a820f51b656ced2e4881def5de76b..e049081eae7d9050d91ee5a3b063f6d583417ec3 100755 (executable)
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
import command
import gitutil
import patchstream
+import project
+import settings
import terminal
import test
help='Send patches email even if patch errors are found')
parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run',
default=False, help="Do a try run (create but don't email patches)")
+parser.add_option('-p', '--project', default=project.DetectProject(),
+ help="Project name; affects default option values and "
+ "aliases [default: %default]")
parser.add_option('-s', '--start', dest='start', type='int',
default=0, help='Commit to start creating patches from (0 = HEAD)')
parser.add_option('-t', '--test', action='store_true', dest='test',
default=False, help='Verbose output of errors and warnings')
parser.add_option('--cc-cmd', dest='cc_cmd', type='string', action='store',
default=None, help='Output cc list for patch file (used by git)')
+parser.add_option('--no-check', action='store_false', dest='check_patch',
+ default=True,
+ help="Don't check for patch compliance")
parser.add_option('--no-tags', action='store_false', dest='process_tags',
default=True, help="Don't process subject tags as aliaes")
Create patches from commits in a branch, check them and email them as
specified by tags you place in the commits. Use -n to """
+
+# Parse options twice: first to get the project and second to handle
+# defaults properly (which depends on project).
+(options, args) = parser.parse_args()
+settings.Setup(parser, options.project, '')
(options, args) = parser.parse_args()
# Run our meagre tests
result = unittest.TestResult()
suite.run(result)
- suite = doctest.DocTestSuite('gitutil')
- suite.run(result)
+ for module in ['gitutil', 'settings']:
+ suite = doctest.DocTestSuite(module)
+ suite.run(result)
# TODO: Surely we can just 'print' result?
print result
series.DoChecks()
# Check the patches, and run them through 'git am' just to be sure
- ok = checkpatch.CheckPatches(options.verbose, args)
+ if options.check_patch:
+ ok = checkpatch.CheckPatches(options.verbose, args)
+ else:
+ ok = True
if not gitutil.ApplyPatches(options.verbose, args,
options.count + options.start):
ok = False
+ cc_file = series.MakeCcFile(options.process_tags, cover_fname)
+
# Email the patches out (giving the user time to check / cancel)
cmd = ''
if ok or options.ignore_errors:
- cc_file = series.MakeCcFile(options.process_tags)
cmd = gitutil.EmailPatches(series, cover_fname, args,
options.dry_run, cc_file)
- os.remove(cc_file)
# For a dry run, just show our actions as a sanity check
if options.dry_run:
series.ShowActions(args, cmd, options.process_tags)
+
+ os.remove(cc_file)
diff --git a/tools/patman/project.py b/tools/patman/project.py
--- /dev/null
+++ b/tools/patman/project.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 The Chromium OS Authors.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+import os.path
+
+import gitutil
+
+def DetectProject():
+ """Autodetect the name of the current project.
+
+ This looks for signature files/directories that are unlikely to exist except
+ in the given project.
+
+ Returns:
+ The name of the project, like "linux" or "u-boot". Returns "unknown"
+ if we can't detect the project.
+ """
+ top_level = gitutil.GetTopLevel()
+
+ if os.path.exists(os.path.join(top_level, "include", "u-boot")):
+ return "u-boot"
+ elif os.path.exists(os.path.join(top_level, "kernel")):
+ return "linux"
+
+ return "unknown"
diff --git a/tools/patman/series.py b/tools/patman/series.py
index d2971f48983afe05f259be47284360442cbac552..6c5c5702e84bf82ad9eaf0b51e62b75d7f9fabeb 100644 (file)
--- a/tools/patman/series.py
+++ b/tools/patman/series.py
# MA 02111-1307 USA
#
+import itertools
import os
+import get_maintainer
import gitutil
import terminal
self.notes = []
self.changes = {}
+ # Written in MakeCcFile()
+ # key: name of patch file
+ # value: list of email addresses
+ self._generated_cc = {}
+
# These make us more like a dictionary
def __setattr__(self, name, value):
self[name] = value
for upto in range(len(args)):
commit = self.commits[upto]
print col.Color(col.GREEN, ' %s' % args[upto])
- cc_list = []
- if process_tags:
- cc_list += gitutil.BuildEmailList(commit.tags)
- cc_list += gitutil.BuildEmailList(commit.cc_list)
+ cc_list = list(self._generated_cc[commit.patch])
# Skip items in To list
if 'to' in self:
print 'Prefix:\t ', self.get('prefix')
if self.cover:
print 'Cover: %d lines' % len(self.cover)
+ all_ccs = itertools.chain(*self._generated_cc.values())
+ for email in set(all_ccs):
+ print ' Cc: ',email
if cmd:
print 'Git command: %s' % cmd
str = 'Change log exists, but no version is set'
print col.Color(col.RED, str)
- def MakeCcFile(self, process_tags):
+ def MakeCcFile(self, process_tags, cover_fname):
"""Make a cc file for us to use for per-commit Cc automation
+ Also stores in self._generated_cc to make ShowActions() faster.
+
Args:
process_tags: Process tags as if they were aliases
+ cover_fname: If non-None the name of the cover letter.
Return:
Filename of temp file created
"""
# Look for commit tags (of the form 'xxx:' at the start of the subject)
fname = '/tmp/patman.%d' % os.getpid()
fd = open(fname, 'w')
+ all_ccs = []
for commit in self.commits:
list = []
if process_tags:
list += gitutil.BuildEmailList(commit.tags)
list += gitutil.BuildEmailList(commit.cc_list)
+ list += get_maintainer.GetMaintainer(commit.patch)
+ all_ccs += list
print >>fd, commit.patch, ', '.join(list)
+ self._generated_cc[commit.patch] = list
+
+ if cover_fname:
+ print >>fd, cover_fname, ', '.join(set(all_ccs))
fd.close()
return fname
index 4dda17bf516d15ebab877f2d1e1f61b13bfe5cc8..084d1b80e525d097dad1f0a809b8d389c794b9de 100644 (file)
--- a/tools/patman/settings.py
+++ b/tools/patman/settings.py
import command
import gitutil
+"""Default settings per-project.
+
+These are used by _ProjectConfigParser. Settings names should match
+the "dest" of the option parser from patman.py.
+"""
+_default_settings = {
+ "u-boot": {},
+ "linux": {
+ "process_tags": "False",
+ }
+}
+
+class _ProjectConfigParser(ConfigParser.SafeConfigParser):
+ """ConfigParser that handles projects.
+
+ There are two main goals of this class:
+ - Load project-specific default settings.
+ - Merge general default settings/aliases with project-specific ones.
+
+ # Sample config used for tests below...
+ >>> import StringIO
+ >>> sample_config = '''
+ ... [alias]
+ ... me: Peter P. <likesspiders@example.com>
+ ... enemies: Evil <evil@example.com>
+ ...
+ ... [sm_alias]
+ ... enemies: Green G. <ugly@example.com>
+ ...
+ ... [sm2_alias]
+ ... enemies: Doc O. <pus@example.com>
+ ...
+ ... [settings]
+ ... am_hero: True
+ ... '''
+
+ # Check to make sure that bogus project gets general alias.
+ >>> config = _ProjectConfigParser("zzz")
+ >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> config.get("alias", "enemies")
+ 'Evil <evil@example.com>'
+
+ # Check to make sure that alias gets overridden by project.
+ >>> config = _ProjectConfigParser("sm")
+ >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> config.get("alias", "enemies")
+ 'Green G. <ugly@example.com>'
+
+ # Check to make sure that settings get merged with project.
+ >>> config = _ProjectConfigParser("linux")
+ >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> sorted(config.items("settings"))
+ [('am_hero', 'True'), ('process_tags', 'False')]
+
+ # Check to make sure that settings works with unknown project.
+ >>> config = _ProjectConfigParser("unknown")
+ >>> config.readfp(StringIO.StringIO(sample_config))
+ >>> sorted(config.items("settings"))
+ [('am_hero', 'True')]
+ """
+ def __init__(self, project_name):
+ """Construct _ProjectConfigParser.
+
+ In addition to standard SafeConfigParser initialization, this also loads
+ project defaults.
+
+ Args:
+ project_name: The name of the project.
+ """
+ self._project_name = project_name
+ ConfigParser.SafeConfigParser.__init__(self)
+
+ # Update the project settings in the config based on
+ # the _default_settings global.
+ project_settings = "%s_settings" % project_name
+ if not self.has_section(project_settings):
+ self.add_section(project_settings)
+ project_defaults = _default_settings.get(project_name, {})
+ for setting_name, setting_value in project_defaults.iteritems():
+ self.set(project_settings, setting_name, setting_value)
+
+ def get(self, section, option, *args, **kwargs):
+ """Extend SafeConfigParser to try project_section before section.
+
+ Args:
+ See SafeConfigParser.
+ Returns:
+ See SafeConfigParser.
+ """
+ try:
+ return ConfigParser.SafeConfigParser.get(
+ self, "%s_%s" % (self._project_name, section), option,
+ *args, **kwargs
+ )
+ except (ConfigParser.NoSectionError, ConfigParser.NoOptionError):
+ return ConfigParser.SafeConfigParser.get(
+ self, section, option, *args, **kwargs
+ )
+
+ def items(self, section, *args, **kwargs):
+ """Extend SafeConfigParser to add project_section to section.
+
+ Args:
+ See SafeConfigParser.
+ Returns:
+ See SafeConfigParser.
+ """
+ project_items = []
+ has_project_section = False
+ top_items = []
+
+ # Get items from the project section
+ try:
+ project_items = ConfigParser.SafeConfigParser.items(
+ self, "%s_%s" % (self._project_name, section), *args, **kwargs
+ )
+ has_project_section = True
+ except ConfigParser.NoSectionError:
+ pass
+
+ # Get top-level items
+ try:
+ top_items = ConfigParser.SafeConfigParser.items(
+ self, section, *args, **kwargs
+ )
+ except ConfigParser.NoSectionError:
+ # If neither section exists raise the error on...
+ if not has_project_section:
+ raise
+
+ item_dict = dict(top_items)
+ item_dict.update(project_items)
+ return item_dict.items()
+
def ReadGitAliases(fname):
"""Read a git alias file. This is in the form used by git:
print >>f, "[alias]\nme: %s <%s>" % (name, email)
f.close();
-def Setup(config_fname=''):
+def _UpdateDefaults(parser, config):
+ """Update the given OptionParser defaults based on config.
+
+ We'll walk through all of the settings from the parser
+ For each setting we'll look for a default in the option parser.
+ If it's found we'll update the option parser default.
+
+ The idea here is that the .patman file should be able to update
+ defaults but that command line flags should still have the final
+ say.
+
+ Args:
+ parser: An instance of an OptionParser whose defaults will be
+ updated.
+ config: An instance of _ProjectConfigParser that we will query
+ for settings.
+ """
+ defaults = parser.get_default_values()
+ for name, val in config.items('settings'):
+ if hasattr(defaults, name):
+ default_val = getattr(defaults, name)
+ if isinstance(default_val, bool):
+ val = config.getboolean('settings', name)
+ elif isinstance(default_val, int):
+ val = config.getint('settings', name)
+ parser.set_default(name, val)
+ else:
+ print "WARNING: Unknown setting %s" % name
+
+def Setup(parser, project_name, config_fname=''):
"""Set up the settings module by reading config files.
Args:
+ parser: The parser to update
+ project_name: Name of project that we're working on; we'll look
+ for sections named "project_section" as well.
config_fname: Config filename to read ('' for default)
"""
- settings = ConfigParser.SafeConfigParser()
+ config = _ProjectConfigParser(project_name)
if config_fname == '':
config_fname = '%s/.patman' % os.getenv('HOME')
print "No config file found ~/.patman\nCreating one...\n"
CreatePatmanConfigFile(config_fname)
- settings.read(config_fname)
+ config.read(config_fname)
- for name, value in settings.items('alias'):
+ for name, value in config.items('alias'):
alias[name] = value.split(',')
+ _UpdateDefaults(parser, config)
# These are the aliases we understand, indexed by alias. Each member is a list.
alias = {}
+
+if __name__ == "__main__":
+ import doctest
+
+ doctest.testmod()
diff --git a/tools/patman/test.py b/tools/patman/test.py
index cf42480a6508e267df6df3ca34efe9ee3847de57..f801cedc7b4a528f12f59cb3ed9fbf9afb1156e7 100644 (file)
--- a/tools/patman/test.py
+++ b/tools/patman/test.py
--- a/README
+++ b/README
@@ -2026,6 +2026,17 @@ The following options need to be configured:
- example, some LED's) on your board. At the moment,
- the following checkpoints are implemented:
+ example, some LED's) on your board. At the moment,
+ the following checkpoints are implemented:
+- Time boot progress
+ CONFIG_BOOTSTAGE
+ You can add calls to bootstage_mark() to set time markers.
+
- Standalone program support:
- CONFIG_STANDALONE_LOAD_ADDR
+ CONFIG_STANDALONE_LOAD_ADDR
diff --git a/common/bootstage.c b/common/bootstage.c
new file mode 100644