powerpc/mpc85xx: Add T4240 SoC

Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index c5982dbe01a6aebb959887257914ac03f4b3a883..5440809e9cb5535456bd62d18f6a16e151e1dab5 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -67,6 +67,7 @@ COBJS-$(CONFIG_PPC_P3041)     += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5040)      += ddr-gen3.o
+COBJS-$(CONFIG_PPC_T4240)      += ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)                += ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)   += ether_fcc.o
@@ -82,6 +83,7 @@ COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
+COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
 
 COBJS-$(CONFIG_QE)     += qe_io.o
 COBJS-$(CONFIG_CPM2)   += serial_scc.o
@@ -114,6 +116,7 @@ COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
 COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
+COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
 
 COBJS  = $(COBJS-y)
 COBJS  += cpu.o

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
new file mode 100644 (file)
index 0000000..a8f16b1
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+       /* dqrr liodn, frame data liodn, liodn off, sdest */
+       SET_QP_INFO(1, 27, 1, 0),
+       SET_QP_INFO(2, 28, 1, 0),
+       SET_QP_INFO(3, 29, 1, 1),
+       SET_QP_INFO(4, 30, 1, 1),
+       SET_QP_INFO(5, 31, 1, 2),
+       SET_QP_INFO(6, 32, 1, 2),
+       SET_QP_INFO(7, 33, 1, 3),
+       SET_QP_INFO(8, 34, 1, 3),
+       SET_QP_INFO(9, 35, 1, 4),
+       SET_QP_INFO(10, 36, 1, 4),
+       SET_QP_INFO(11, 37, 1, 5),
+       SET_QP_INFO(12, 38, 1, 5),
+       SET_QP_INFO(13, 39, 1, 6),
+       SET_QP_INFO(14, 40, 1, 6),
+       SET_QP_INFO(15, 41, 1, 7),
+       SET_QP_INFO(16, 42, 1, 7),
+       SET_QP_INFO(17, 43, 1, 8),
+       SET_QP_INFO(18, 44, 1, 8),
+       SET_QP_INFO(19, 45, 1, 9),
+       SET_QP_INFO(20, 46, 1, 9),
+       SET_QP_INFO(21, 47, 1, 10),
+       SET_QP_INFO(22, 48, 1, 10),
+       SET_QP_INFO(23, 49, 1, 11),
+       SET_QP_INFO(24, 50, 1, 11),
+       SET_QP_INFO(65, 89, 1, 0),
+       SET_QP_INFO(66, 90, 1, 0),
+       SET_QP_INFO(67, 91, 1, 1),
+       SET_QP_INFO(68, 92, 1, 1),
+       SET_QP_INFO(69, 93, 1, 2),
+       SET_QP_INFO(70, 94, 1, 2),
+       SET_QP_INFO(71, 95, 1, 3),
+       SET_QP_INFO(72, 96, 1, 3),
+       SET_QP_INFO(73, 97, 1, 4),
+       SET_QP_INFO(74, 98, 1, 4),
+       SET_QP_INFO(75, 99, 1, 5),
+       SET_QP_INFO(76, 100, 1, 5),
+       SET_QP_INFO(77, 101, 1, 6),
+       SET_QP_INFO(78, 102, 1, 6),
+       SET_QP_INFO(79, 103, 1, 7),
+       SET_QP_INFO(80, 104, 1, 7),
+       SET_QP_INFO(81, 105, 1, 8),
+       SET_QP_INFO(82, 106, 1, 8),
+       SET_QP_INFO(83, 107, 1, 9),
+       SET_QP_INFO(84, 108, 1, 9),
+       SET_QP_INFO(85, 109, 1, 10),
+       SET_QP_INFO(86, 110, 1, 10),
+       SET_QP_INFO(87, 111, 1, 11),
+       SET_QP_INFO(88, 112, 1, 11),
+       SET_QP_INFO(25, 51, 1, 0),
+       SET_QP_INFO(26, 52, 1, 0),
+};
+#endif
+
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+       SET_SRIO_LIODN_1(1, 307),
+       SET_SRIO_LIODN_1(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+       SET_QMAN_LIODN(62),
+       SET_BMAN_LIODN(63),
+#endif
+
+       SET_SDHC_LIODN(1, 552),
+
+       SET_PME_LIODN(117),
+
+       SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+       SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+
+       SET_SATA_LIODN(1, 555),
+       SET_SATA_LIODN(2, 556),
+
+       SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+       SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+       SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+       SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+
+       SET_DMA_LIODN(1, 147),
+       SET_DMA_LIODN(2, 227),
+
+       SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+       SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+       SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+       SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+#ifdef CONFIG_SYS_PMAN
+       SET_PMAN_LIODN(1, 513),
+       SET_PMAN_LIODN(2, 514),
+       SET_PMAN_LIODN(3, 515),
+#endif
+
+       /* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+       SET_FMAN_RX_1G_LIODN(1, 0, 88),
+       SET_FMAN_RX_1G_LIODN(1, 1, 89),
+       SET_FMAN_RX_1G_LIODN(1, 2, 90),
+       SET_FMAN_RX_1G_LIODN(1, 3, 91),
+       SET_FMAN_RX_1G_LIODN(1, 4, 92),
+       SET_FMAN_RX_1G_LIODN(1, 5, 93),
+       SET_FMAN_RX_10G_LIODN(1, 0, 94),
+       SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+       SET_FMAN_RX_1G_LIODN(2, 0, 88),
+       SET_FMAN_RX_1G_LIODN(2, 1, 89),
+       SET_FMAN_RX_1G_LIODN(2, 2, 90),
+       SET_FMAN_RX_1G_LIODN(2, 3, 91),
+       SET_FMAN_RX_1G_LIODN(2, 4, 92),
+       SET_FMAN_RX_1G_LIODN(2, 5, 93),
+       SET_FMAN_RX_10G_LIODN(2, 0, 94),
+       SET_FMAN_RX_10G_LIODN(2, 1, 95),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+       SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+       SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+       SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+       SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+       SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+       SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+       SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+       SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+       SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+       SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+       SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+       SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+       SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+       SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+       SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+       SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+       /* Set RMan block 0-3 liodn offset */
+       SET_RMAN_LIODN(0, 678),
+       SET_RMAN_LIODN(1, 679),
+       SET_RMAN_LIODN(2, 680),
+       SET_RMAN_LIODN(3, 681),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+#ifdef CONFIG_SYS_DPAA_DCE
+       [FSL_HW_PORTAL_DCE]  = SET_LIODN_BASE_2(618, 694),
+#endif
+       [FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+       [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#if (CONFIG_SYS_NUM_FMAN == 2)
+       [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069),
+#endif
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+       [FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(770, 846),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+       [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};

diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
new file mode 100644 (file)
index 0000000..102defa
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+       u32 protocol;
+       u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+       /* SerDes 1 */
+       {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+               XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+               XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+               XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+       {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+       {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+               HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+       {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+       {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+               SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+       {38, {NONE, NONE, QSGMII_FM1_B, NONE,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+               SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+       /* SerDes 2 */
+       {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC10, XAUI_FM2_MAC10,
+               XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
+       {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
+               HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+       {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
+               HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+       {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {38, {NONE, NONE, QSGMII_FM2_B, NONE,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+               SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+               NONE, NONE, QSGMII_FM1_A, NONE}},
+       {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+               XFI_FM2_MAC10, XFI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+               XFI_FM2_MAC10, XFI_FM2_MAC9,
+               SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+               SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+       {}
+};
+static struct serdes_config serdes3_cfg_tbl[] = {
+       /* SerDes 3 */
+       {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+       {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+       {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+       {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+       {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+       {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+       {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               PCIE2, PCIE2, PCIE2, PCIE2}},
+       {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               PCIE2, PCIE2, PCIE2, PCIE2}},
+       {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1}},
+       {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1}},
+       {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1}},
+       {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+               SRIO1, SRIO1, SRIO1, SRIO1}},
+       {}
+};
+static struct serdes_config serdes4_cfg_tbl[] = {
+       /* SerDes 4 */
+       {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+       {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+       {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+       {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+       {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}},
+       {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}},
+       {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+       {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+       {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
+       {}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
+       serdes1_cfg_tbl,
+       serdes2_cfg_tbl,
+       serdes3_cfg_tbl,
+       serdes4_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+       struct serdes_config *ptr;
+
+       if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+               return 0;
+
+       ptr = serdes_cfg_tbl[serdes];
+       while (ptr->protocol) {
+               if (ptr->protocol == cfg)
+                       return ptr->lanes[lane];
+               ptr++;
+       }
+       return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+       int i;
+       struct serdes_config *ptr;
+
+       if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+               return 0;
+
+       ptr = serdes_cfg_tbl[serdes];
+       while (ptr->protocol) {
+               if (ptr->protocol == prtcl)
+                       break;
+               ptr++;
+       }
+
+       if (!ptr->protocol)
+               return 0;
+
+       for (i = 0; i < SRDS_MAX_LANES; i++) {
+               if (ptr->lanes[i] != NONE)
+                       return 1;
+       }
+
+       return 0;
+}

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index fb78784345bd8dbf7f2318d212a209f5f8cbfea8..4d96d1b107498e764de5f3a255ce88000057d3cf 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -75,6 +75,8 @@ struct cpu_type cpu_type_list [] = {
        CPU_TYPE_ENTRY(P5020, P5020, 2),
        CPU_TYPE_ENTRY(P5021, P5021, 2),
        CPU_TYPE_ENTRY(P5040, P5040, 4),
+       CPU_TYPE_ENTRY(T4240, T4240, 0),
+       CPU_TYPE_ENTRY(T4120, T4120, 0),
        CPU_TYPE_ENTRY(BSC9130, 9130, 1),
        CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 #elif defined(CONFIG_MPC86xx)

diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index e7ff59a1ca963aa06eb8574630135ee649f7e024..d4f8ecee9b75b54eb8fd6317931c8c40efef67a2 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -34,8 +34,13 @@
 #define SRIO_LCSBA1CSR 0x60000000
 
 #if defined(CONFIG_FSL_CORENET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+       #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
+       #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
+#else
        #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
        #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
+#endif
        #define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
        #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC85xx)
@@ -236,7 +241,13 @@ void srio_init(void)
 {
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
        int srio1_used = 0, srio2_used = 0;
+       u32 *devdisr;
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+       devdisr = &gur->devdisr3;
+#else
+       devdisr = &gur->devdisr;
+#endif
        if (is_serdes_configured(SRIO1)) {
                set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
                                law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
@@ -273,16 +284,16 @@ void srio_init(void)
 #ifdef CONFIG_FSL_CORENET
        /* On FSL_CORENET devices we can disable individual ports */
        if (!srio1_used)
-               setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
+               setbits_be32(devdisr, _DEVDISR_SRIO1);
        if (!srio2_used)
-               setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
+               setbits_be32(devdisr, _DEVDISR_SRIO2);
 #endif
 
        /* neither port is used - disable everything */
        if (!srio1_used && !srio2_used) {
-               setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
-               setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
-               setbits_be32(&gur->devdisr, _DEVDISR_RMU);
+               setbits_be32(devdisr, _DEVDISR_SRIO1);
+               setbits_be32(devdisr, _DEVDISR_SRIO2);
+               setbits_be32(devdisr, _DEVDISR_RMU);
        }
 }
 

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index a61d315be65b449392bfbde5730903d7c63da436..cfa5448b5eb9242ea2b709b73590fb5fd34a363e 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -482,6 +482,34 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+#elif defined(CONFIG_PPC_T4240)
+#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
+#define CONFIG_MAX_CPUS                        12
+#define CONFIG_SYS_FSL_NUM_CC_PLLS     5
+#define CONFIG_SYS_FSL_NUM_LAWS                32
+#define CONFIG_SYS_FSL_SRDS_3
+#define CONFIG_SYS_FSL_SRDS_4
+#define CONFIG_SYS_FSL_SEC_COMPAT      4
+#define CONFIG_SYS_NUM_FMAN            2
+#define CONFIG_SYS_NUM_FM1_DTSEC       8
+#define CONFIG_SYS_NUM_FM1_10GEC       2
+#define CONFIG_SYS_NUM_FM2_DTSEC       8
+#define CONFIG_SYS_NUM_FM2_10GEC       2
+#define CONFIG_NUM_DDR_CONTROLLERS     3
+#define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
+#define CONFIG_SYS_FM_MURAM_SIZE       0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV       16
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS  2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
+
 #else
 #error Processor type not defined for this platform
 #endif

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 51f02fcb3d83aa3e4ebfc19fc19a0919d24fb4d8..5001f6eba2027e53fee39ac6d1bc2b126ac58589 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1689,6 +1689,72 @@ typedef struct ccsr_gur {
        u32     alt_pmuxcr;     /* Alt function signal multiplex control */
        u8      res6[12];
        u32     devdisr;        /* Device disable control */
+       u32     devdisr2;       /* Device disable control 2 */
+       u32     devdisr3;       /* Device disable control 3 */
+       u32     devdisr4;       /* Device disable control 4 */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+       u32     devdisr5;       /* Device disable control 5 */
+#define FSL_CORENET_DEVDISR_PBL        0x80000000
+#define FSL_CORENET_DEVDISR_PMAN       0x40000000
+#define FSL_CORENET_DEVDISR_ESDHC      0x20000000
+#define FSL_CORENET_DEVDISR_DMA1       0x00800000
+#define FSL_CORENET_DEVDISR_DMA2       0x00400000
+#define FSL_CORENET_DEVDISR_USB1       0x00080000
+#define FSL_CORENET_DEVDISR_USB2       0x00040000
+#define FSL_CORENET_DEVDISR_SATA1      0x00008000
+#define FSL_CORENET_DEVDISR_SATA2      0x00004000
+#define FSL_CORENET_DEVDISR_PME        0x00000800
+#define FSL_CORENET_DEVDISR_SEC        0x00000200
+#define FSL_CORENET_DEVDISR_RMU        0x00000080
+#define FSL_CORENET_DEVDISR_DCE        0x00000040
+#define FSL_CORENET_DEVDISR2_DTSEC1_1  0x80000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2  0x40000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3  0x20000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4  0x10000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5  0x08000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_6  0x04000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_9  0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
+#define FSL_CORENET_DEVDISR2_10GEC1_1  0x00800000
+#define FSL_CORENET_DEVDISR2_10GEC1_2  0x00400000
+#define FSL_CORENET_DEVDISR2_DTSEC2_1  0x00080000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2  0x00040000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3  0x00020000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4  0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5  0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_6  0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_9  0x00000800
+#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
+#define FSL_CORENET_DEVDISR2_10GEC2_1  0x00000800
+#define FSL_CORENET_DEVDISR2_10GEC2_2  0x00000400
+#define FSL_CORENET_DEVDISR2_FM1       0x00000080
+#define FSL_CORENET_DEVDISR2_FM2       0x00000040
+#define FSL_CORENET_DEVDISR3_PCIE1     0x80000000
+#define FSL_CORENET_DEVDISR3_PCIE2     0x40000000
+#define FSL_CORENET_DEVDISR3_PCIE3     0x20000000
+#define FSL_CORENET_DEVDISR3_PCIE4     0x10000000
+#define FSL_CORENET_DEVDISR3_SRIO1     0x08000000
+#define FSL_CORENET_DEVDISR3_SRIO2     0x04000000
+#define FSL_CORENET_DEVDISR3_QMAN      0x00080000
+#define FSL_CORENET_DEVDISR3_BMAN      0x00040000
+#define FSL_CORENET_DEVDISR3_LA1       0x00008000
+#define FSL_CORENET_DEVDISR4_I2C1      0x80000000
+#define FSL_CORENET_DEVDISR4_I2C2      0x40000000
+#define FSL_CORENET_DEVDISR4_DUART1    0x20000000
+#define FSL_CORENET_DEVDISR4_DUART2    0x10000000
+#define FSL_CORENET_DEVDISR4_ESPI      0x08000000
+#define FSL_CORENET_DEVDISR5_DDR1      0x80000000
+#define FSL_CORENET_DEVDISR5_DDR2      0x40000000
+#define FSL_CORENET_DEVDISR5_DDR3      0x20000000
+#define FSL_CORENET_DEVDISR5_CPC1      0x08000000
+#define FSL_CORENET_DEVDISR5_CPC2      0x04000000
+#define FSL_CORENET_DEVDISR5_CPC3      0x02000000
+#define FSL_CORENET_DEVDISR5_IFC       0x00800000
+#define FSL_CORENET_DEVDISR5_GPIO      0x00400000
+#define FSL_CORENET_DEVDISR5_DBG       0x00200000
+#define FSL_CORENET_DEVDISR5_NAL       0x00100000
+#define FSL_CORENET_NUM_DEVDISR                5
+#else
 #define FSL_CORENET_DEVDISR_PCIE1      0x80000000
 #define FSL_CORENET_DEVDISR_PCIE2      0x40000000
 #define FSL_CORENET_DEVDISR_PCIE3      0x20000000
@@ -1714,7 +1780,6 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR_I2C2       0x00000010
 #define FSL_CORENET_DEVDISR_DUART1     0x00000002
 #define FSL_CORENET_DEVDISR_DUART2     0x00000001
-       u32     devdisr2;       /* Device disable control 2 */
 #define FSL_CORENET_DEVDISR2_PME       0x80000000
 #define FSL_CORENET_DEVDISR2_SEC       0x40000000
 #define FSL_CORENET_DEVDISR2_QMBM      0x08000000
@@ -1733,8 +1798,8 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC2_4  0x00001000
 #define FSL_CORENET_DEVDISR2_DTSEC2_5  0x00000800
 #define FSL_CORENET_NUM_DEVDISR                2
-       u8      res7[8];
        u32     powmgtcsr;      /* Power management status & control */
+#endif
        u8      res8[12];
        u32     coredisru;      /* uppper portion for support of 64 cores */
        u32     coredisrl;      /* lower portion for support of 64 cores */
@@ -1761,6 +1826,7 @@ typedef struct ccsr_gur {
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT   16
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK    0x3f
+#if defined(CONFIG_PPC_T4240)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  26
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL                0x00fe0000
@@ -1769,6 +1835,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT  11
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL                0x000000f8
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT  3
+#endif
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1        0x00800000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2        0x00400000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1        0x00200000
@@ -1821,6 +1888,15 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII        0x00000000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
+#endif
+#if defined(CONFIG_PPC_T4240)
+#define FSL_CORENET_RCWSR13_EC1                        0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII       0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO               0x40000000
+#define FSL_CORENET_RCWSR13_EC2                        0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII       0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII       0x08000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO               0x10000000
 #endif
        u8      res18[192];
        u32     scratchrw[4];   /* Scratch Read/Write */
@@ -2798,10 +2874,17 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET          0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET         0x130000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET     0x1e0000
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET                0x240000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET                0x250000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET                0x260000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET                0x270000
+#else
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET                0x200000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET                0x201000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET                0x202000
 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET                0x203000
+#endif
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET         0x210000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET         0x211000
 #define CONFIG_SYS_MPC85xx_USB_OFFSET          CONFIG_SYS_MPC85xx_USB1_OFFSET

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index fd0160a2d1e96f2f0444048348fbefb754f2524b..5bc0da6df1eedb28dbbf58c5c530e12262cb540d 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1097,6 +1097,8 @@
 #define SVR_P5020      0x822000
 #define SVR_P5021      0X820500
 #define SVR_P5040      0x820400
+#define SVR_T4240      0x824000
+#define SVR_T4120      0x824001
 
 #define SVR_8610       0x80A000
 #define SVR_8641       0x809000

diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index cc573547557e037345bfd2a69e70955c320bec2e..73f64ad45a73e8df28e9403ca200a9ac4b405c67 100644 (file)
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_PPC_P2041) += p5020.o
 COBJS-$(CONFIG_PPC_P3041) += p5020.o
 COBJS-$(CONFIG_PPC_P4080) += p4080.o
 COBJS-$(CONFIG_PPC_P5020) += p5020.o
+COBJS-$(CONFIG_PPC_T4240) += t4240.o
 endif
 
 COBJS  := $(COBJS-y)

diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index 736b8b958296bc6656f9a6ebc1d01c40b3ea216b..ae389b88422f2e88b6817355cd3758676928ba60 100644 (file)
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -38,6 +38,15 @@ struct fm_eth_info fm_info[] = {
 #if (CONFIG_SYS_NUM_FM1_DTSEC >= 5)
        FM_DTSEC_INFO_INITIALIZER(1, 5),
 #endif
+#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6)
+       FM_DTSEC_INFO_INITIALIZER(1, 6),
+#endif
+#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7)
+       FM_DTSEC_INFO_INITIALIZER(1, 9),
+#endif
+#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8)
+       FM_DTSEC_INFO_INITIALIZER(1, 10),
+#endif
 #if (CONFIG_SYS_NUM_FM2_DTSEC >= 1)
        FM_DTSEC_INFO_INITIALIZER(2, 1),
 #endif
@@ -53,6 +62,15 @@ struct fm_eth_info fm_info[] = {
 #if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
        FM_DTSEC_INFO_INITIALIZER(2, 5),
 #endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6)
+       FM_DTSEC_INFO_INITIALIZER(2, 6),
+#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7)
+       FM_DTSEC_INFO_INITIALIZER(2, 9),
+#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8)
+       FM_DTSEC_INFO_INITIALIZER(2, 10),
+#endif
 #if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
        FM_TGEC_INFO_INITIALIZER(1, 1),
 #endif

diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
new file mode 100644 (file)
index 0000000..48c530c
--- /dev/null
+++ b/drivers/net/fm/t4240.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *     Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+u32 port_to_devdisr[] = {
+       [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
+       [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
+       [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
+       [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
+       [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
+       [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
+       [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
+       [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
+       [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
+       [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
+       [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
+       [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
+       [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
+       [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
+       [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
+       [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
+       [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
+       [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
+       [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
+       [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 devdisr2 = in_be32(&gur->devdisr2);
+
+       return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+       setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+       ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+       if (is_device_disabled(port))
+               return PHY_INTERFACE_MODE_NONE;
+
+       if ((port == FM1_10GEC1 || port == FM1_10GEC2)
+                       && (is_serdes_configured(XAUI_FM1)))
+               return PHY_INTERFACE_MODE_XGMII;
+
+       if ((port == FM2_10GEC1 || port == FM2_10GEC2)
+                       && (is_serdes_configured(XAUI_FM2)))
+               return PHY_INTERFACE_MODE_XGMII;
+
+#define FSL_CORENET_RCWSR13_EC1                        0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII       0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO               0x40000000
+#define FSL_CORENET_RCWSR13_EC2                        0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII       0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII       0x08000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO               0x10000000
+       /* handle RGMII first */
+       if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+               FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
+               return PHY_INTERFACE_MODE_RGMII;
+
+       if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+               FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
+               return PHY_INTERFACE_MODE_RGMII;
+
+       if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+               FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
+               return PHY_INTERFACE_MODE_RGMII;
+       switch (port) {
+       case FM1_DTSEC1:
+       case FM1_DTSEC2:
+       case FM1_DTSEC3:
+       case FM1_DTSEC4:
+       case FM1_DTSEC5:
+       case FM1_DTSEC6:
+       case FM1_DTSEC9:
+       case FM1_DTSEC10:
+               if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+                       return PHY_INTERFACE_MODE_SGMII;
+               break;
+       case FM2_DTSEC1:
+       case FM2_DTSEC2:
+       case FM2_DTSEC3:
+       case FM2_DTSEC4:
+       case FM2_DTSEC5:
+       case FM2_DTSEC6:
+       case FM2_DTSEC9:
+       case FM2_DTSEC10:
+               if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
+                       return PHY_INTERFACE_MODE_SGMII;
+               break;
+       default:
+               return PHY_INTERFACE_MODE_NONE;
+       }
+
+       return PHY_INTERFACE_MODE_NONE;
+}

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 86ccbe7ee891a07d58dd8702ad8721f3345f8363..e8eb9d6db77c6dbb734aa4861ebdfa847abf4b7c 100644 (file)
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -666,10 +666,17 @@ int fsl_configure_pcie(struct fsl_pci_info *info,
 }
 
 #if defined(CONFIG_FSL_CORENET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+       #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
+       #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
+       #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
+       #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
+#else
        #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
        #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
        #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
        #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
+#endif
        #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC85xx)
        #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
@@ -749,34 +756,42 @@ int fsl_pcie_init_board(int busno)
 {
        struct fsl_pci_info pci_info;
        ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
-       u32 devdisr = in_be32(&gur->devdisr);
+       u32 devdisr;
+       u32 *addr;
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+       addr = &gur->devdisr3;
+#else
+       addr = &gur->devdisr;
+#endif
+       devdisr = in_be32(addr);
 
 #ifdef CONFIG_PCIE1
        SET_STD_PCIE_INFO(pci_info, 1);
        busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
 #else
-       setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
+       setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
 #endif
 
 #ifdef CONFIG_PCIE2
        SET_STD_PCIE_INFO(pci_info, 2);
        busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
 #else
-       setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
+       setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
 #endif
 
 #ifdef CONFIG_PCIE3
        SET_STD_PCIE_INFO(pci_info, 3);
        busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
 #else
-       setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */
+       setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
 #endif
 
 #ifdef CONFIG_PCIE4
        SET_STD_PCIE_INFO(pci_info, 4);
        busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
 #else
-       setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */
+       setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
 #endif
 
        return busno;

diff --git a/include/fm_eth.h b/include/fm_eth.h
index e56541df1b727a997391fdc24a051e81209de965..5d80e4962ed3b7277870a8c88aebef5be50ca7bd 100644 (file)
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -30,13 +30,21 @@ enum fm_port {
        FM1_DTSEC3,
        FM1_DTSEC4,
        FM1_DTSEC5,
+       FM1_DTSEC6,
+       FM1_DTSEC9,
+       FM1_DTSEC10,
        FM1_10GEC1,
+       FM1_10GEC2,
        FM2_DTSEC1,
        FM2_DTSEC2,
        FM2_DTSEC3,
        FM2_DTSEC4,
        FM2_DTSEC5,
+       FM2_DTSEC6,
+       FM2_DTSEC9,
+       FM2_DTSEC10,
        FM2_10GEC1,
+       FM2_10GEC2,
        NUM_FM_PORTS,
 };