Merge remote-tracking branch 'u-boot/master' into u-boot-arm-merged
authorAllen Martin <amartin@nvidia.com>
Wed, 19 Dec 2012 21:02:36 +0000 (13:02 -0800)
committerAllen Martin <amartin@nvidia.com>
Wed, 19 Dec 2012 21:02:36 +0000 (13:02 -0800)
Conflicts:
README
arch/arm/cpu/armv7/exynos/clock.c
board/samsung/universal_c210/universal.c
drivers/misc/Makefile
drivers/power/power_fsl.c
include/configs/mx35pdk.h
include/configs/mx53loco.h
include/configs/seaboard.h

40 files changed:
1  2 
MAINTAINERS
Makefile
README
arch/arm/cpu/armv7/exynos/clock.c
arch/arm/cpu/armv7/exynos/pinmux.c
arch/arm/include/asm/arch-exynos/cpu.h
board/freescale/mx35pdk/mx35pdk.c
board/samsung/trats/trats.c
board/samsung/universal_c210/universal.c
boards.cfg
common/Makefile
common/lcd.c
common/main.c
drivers/misc/Makefile
drivers/mmc/tegra_mmc.c
drivers/power/power_fsl.c
drivers/video/Makefile
include/configs/mx28evk.h
include/configs/mx31pdk.h
include/configs/mx35pdk.h
include/configs/mx51_efikamx.h
include/configs/mx51evk.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx6qarm2.h
include/configs/mx6qsabre_common.h
include/configs/mx6qsabrelite.h
include/configs/s5pc210_universal.h
include/configs/seaboard.h
include/configs/smdk5250.h
include/configs/tegra-common-post.h
include/configs/tegra20-common.h
include/configs/trats.h
include/configs/ventana.h
include/configs/vision2.h
include/fdtdec.h
include/lcd.h
include/power/max8998_pmic.h
lib/fdtdec.c
spl/Makefile

diff --cc MAINTAINERS
Simple merge
diff --cc Makefile
Simple merge
diff --cc README
index 037513a1340c1a250aa3ec02ca7cbc6ad5f09236,f386041140e1f3b4fcc4464301a74abe71ffdbe7..653ef6aa4a55d57686165e56eeec847dcd40b3f1
--- 1/README
--- 2/README
+++ b/README
@@@ -1469,22 -1486,16 +1486,30 @@@ CBFS (Coreboot Filesystem) suppor
                Normally display is black on white background; define
                CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
  
 +              CONFIG_LCD_ALIGNMENT
 +
 +              Normally the LCD is page-aligned (tyically 4KB). If this is
 +              defined then the LCD will be aligned to this value instead.
 +              For ARM it is sometimes useful to use MMU_SECTION_SIZE
 +              here, since it is cheaper to change data cache settings on
 +              a per-section basis.
 +
 +              CONFIG_CONSOLE_SCROLL_LINES
 +
 +              When the console need to be scrolled, this is the number of
 +              lines to scroll by. It defaults to 1. Increasing this makes
 +              the console jump but can help speed up operation when scrolling
 +              is slow.
 +
+               CONFIG_LCD_BMP_RLE8
+               Support drawing of RLE8-compressed bitmaps on the LCD.
+               CONFIG_I2C_EDID
+               Enables an 'i2c edid' command which can read EDID
+               information over I2C from an attached LCD display.
 -
  - Splash Screen Support: CONFIG_SPLASH_SCREEN
  
                If this option is set, the environment is checked for
index fe61f88af4954015b14c478ffa08c53bfc2fcd4b,21e45d2e828cb2913666cd7ec0358ab2aee7471f..c6c66814e5b516d2c3b7e2cd796cd7f1adab5c8c
@@@ -718,207 -732,19 +718,221 @@@ static unsigned long exynos5_get_i2c_cl
        return aclk_66;
  }
  
 +int exynos5_set_epll_clk(unsigned long rate)
 +{
 +      unsigned int epll_con, epll_con_k;
 +      unsigned int i;
 +      unsigned int lockcnt;
 +      unsigned int start;
 +      struct exynos5_clock *clk =
 +              (struct exynos5_clock *)samsung_get_base_clock();
 +
 +      epll_con = readl(&clk->epll_con0);
 +      epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
 +                      EPLL_CON0_LOCK_DET_EN_SHIFT) |
 +              EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
 +              EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
 +              EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
 +
 +      for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
 +              if (exynos5_epll_div[i].freq_out == rate)
 +                      break;
 +      }
 +
 +      if (i == ARRAY_SIZE(exynos5_epll_div))
 +              return -1;
 +
 +      epll_con_k = exynos5_epll_div[i].k_dsm << 0;
 +      epll_con |= exynos5_epll_div[i].en_lock_det <<
 +                              EPLL_CON0_LOCK_DET_EN_SHIFT;
 +      epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
 +      epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
 +      epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
 +
 +      /*
 +       * Required period ( in cycles) to genarate a stable clock output.
 +       * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
 +       * frequency input (as per spec)
 +       */
 +      lockcnt = 3000 * exynos5_epll_div[i].p_div;
 +
 +      writel(lockcnt, &clk->epll_lock);
 +      writel(epll_con, &clk->epll_con0);
 +      writel(epll_con_k, &clk->epll_con1);
 +
 +      start = get_timer(0);
 +
 +       while (!(readl(&clk->epll_con0) &
 +                      (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
 +              if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
 +                      debug("%s: Timeout waiting for EPLL lock\n", __func__);
 +                      return -1;
 +              }
 +      }
 +      return 0;
 +}
 +
 +void exynos5_set_i2s_clk_source(void)
 +{
 +      struct exynos5_clock *clk =
 +              (struct exynos5_clock *)samsung_get_base_clock();
 +
 +      clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
 +                      (CLK_SRC_SCLK_EPLL));
 +}
 +
 +int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
 +                                      unsigned int dst_frq)
 +{
 +      struct exynos5_clock *clk =
 +              (struct exynos5_clock *)samsung_get_base_clock();
 +      unsigned int div;
 +
 +      if ((dst_frq == 0) || (src_frq == 0)) {
 +              debug("%s: Invalid requency input for prescaler\n", __func__);
 +              debug("src frq = %d des frq = %d ", src_frq, dst_frq);
 +              return -1;
 +      }
 +
 +      div = (src_frq / dst_frq);
 +      if (div > AUDIO_1_RATIO_MASK) {
 +              debug("%s: Frequency ratio is out of range\n", __func__);
 +              debug("src frq = %d des frq = %d ", src_frq, dst_frq);
 +              return -1;
 +      }
 +      clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
 +                              (div & AUDIO_1_RATIO_MASK));
 +      return 0;
 +}
 +
 +/**
 + * Linearly searches for the most accurate main and fine stage clock scalars
 + * (divisors) for a specified target frequency and scalar bit sizes by checking
 + * all multiples of main_scalar_bits values. Will always return scalars up to or
 + * slower than target.
 + *
 + * @param main_scalar_bits    Number of main scalar bits, must be > 0 and < 32
 + * @param fine_scalar_bits    Number of fine scalar bits, must be > 0 and < 32
 + * @param input_freq          Clock frequency to be scaled in Hz
 + * @param target_freq         Desired clock frequency in Hz
 + * @param best_fine_scalar    Pointer to store the fine stage divisor
 + *
 + * @return best_main_scalar   Main scalar for desired frequency or -1 if none
 + * found
 + */
 +static int clock_calc_best_scalar(unsigned int main_scaler_bits,
 +      unsigned int fine_scalar_bits, unsigned int input_rate,
 +      unsigned int target_rate, unsigned int *best_fine_scalar)
 +{
 +      int i;
 +      int best_main_scalar = -1;
 +      unsigned int best_error = target_rate;
 +      const unsigned int cap = (1 << fine_scalar_bits) - 1;
 +      const unsigned int loops = 1 << main_scaler_bits;
 +
 +      debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
 +                      target_rate, cap);
 +
 +      assert(best_fine_scalar != NULL);
 +      assert(main_scaler_bits <= fine_scalar_bits);
 +
 +      *best_fine_scalar = 1;
 +
 +      if (input_rate == 0 || target_rate == 0)
 +              return -1;
 +
 +      if (target_rate >= input_rate)
 +              return 1;
 +
 +      for (i = 1; i <= loops; i++) {
 +              const unsigned int effective_div = max(min(input_rate / i /
 +                                                      target_rate, cap), 1);
 +              const unsigned int effective_rate = input_rate / i /
 +                                                      effective_div;
 +              const int error = target_rate - effective_rate;
 +
 +              debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
 +                              effective_rate, error);
 +
 +              if (error >= 0 && error <= best_error) {
 +                      best_error = error;
 +                      best_main_scalar = i;
 +                      *best_fine_scalar = effective_div;
 +              }
 +      }
 +
 +      return best_main_scalar;
 +}
 +
 +static int exynos5_set_spi_clk(enum periph_id periph_id,
 +                                      unsigned int rate)
 +{
 +      struct exynos5_clock *clk =
 +              (struct exynos5_clock *)samsung_get_base_clock();
 +      int main;
 +      unsigned int fine;
 +      unsigned shift, pre_shift;
 +      unsigned mask = 0xff;
 +      u32 *reg;
 +
 +      main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
 +      if (main < 0) {
 +              debug("%s: Cannot set clock rate for periph %d",
 +                              __func__, periph_id);
 +              return -1;
 +      }
 +      main = main - 1;
 +      fine = fine - 1;
 +
 +      switch (periph_id) {
 +      case PERIPH_ID_SPI0:
 +              reg = &clk->div_peric1;
 +              shift = 0;
 +              pre_shift = 8;
 +              break;
 +      case PERIPH_ID_SPI1:
 +              reg = &clk->div_peric1;
 +              shift = 16;
 +              pre_shift = 24;
 +              break;
 +      case PERIPH_ID_SPI2:
 +              reg = &clk->div_peric2;
 +              shift = 0;
 +              pre_shift = 8;
 +              break;
 +      case PERIPH_ID_SPI3:
 +              reg = &clk->sclk_div_isp;
 +              shift = 0;
 +              pre_shift = 4;
 +              break;
 +      case PERIPH_ID_SPI4:
 +              reg = &clk->sclk_div_isp;
 +              shift = 12;
 +              pre_shift = 16;
 +              break;
 +      default:
 +              debug("%s: Unsupported peripheral ID %d\n", __func__,
 +                    periph_id);
 +              return -1;
 +      }
 +      clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
 +      clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
 +
 +      return 0;
++
+ static unsigned long exynos4_get_i2c_clk(void)
+ {
+       struct exynos4_clock *clk =
+               (struct exynos4_clock *)samsung_get_base_clock();
+       unsigned long sclk, aclk_100;
+       unsigned int ratio;
+       sclk = get_pll_clk(APLL);
+       ratio = (readl(&clk->div_top)) >> 4;
+       ratio &= 0xf;
+       aclk_100 = sclk / (ratio + 1);
+       return aclk_100;
  }
  
  unsigned long get_pll_clk(int pllreg)
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index afe3bb0aeb81eb38a0e1dad8c5d06770eab0cc2b,36a047217c57cbdac1b07196fbb137bf0eb7f2d1..1e67dea2ae248037b67b1d61be6e7a80e5f1a445
  #include <asm/arch/adc.h>
  #include <asm/arch/gpio.h>
  #include <asm/arch/mmc.h>
 +#include <asm/arch/pinmux.h>
 +#include <pmic.h>
 +#include <usb/s3c_udc.h>
 +#include <asm/arch/cpu.h>
 +#include <max8998_pmic.h>
 +#include <asm/arch/watchdog.h>
 +#include <libtizen.h>
 +#include <ld9040.h>
+ #include <power/pmic.h>
+ #include <usb/s3c_udc.h>
+ #include <asm/arch/cpu.h>
+ #include <power/max8998_pmic.h>
  
  DECLARE_GLOBAL_DATA_PTR;
  
diff --cc boards.cfg
Simple merge
diff --cc common/Makefile
Simple merge
diff --cc common/lcd.c
Simple merge
diff --cc common/main.c
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index c8d4c8d9ecf6e429470485738da6385075e96915,651f88f850a0690bc26f15693051ddfee31e16f2..af4663dd259e651ba026453103dbcf26222792ce
  
  #include <common.h>
  #include <spi.h>
- #include <pmic.h>
+ #include <power/pmic.h>
  #include <fsl_pmic.h>
+ #include <errno.h>
  
- #if defined(CONFIG_PMIC_SPI)
 +#if defined(CONFIG_PMIC_FSL_MC13892)
 +#define FSL_PMIC_I2C_LENGTH   3
 +#elif defined(CONFIG_PMIC_FSL_MC34704)
 +#define FSL_PMIC_I2C_LENGTH   1
 +#endif
 +
+ #if defined(CONFIG_POWER_SPI)
  static u32 pmic_spi_prepare_tx(u32 reg, u32 *val, u32 write)
  {
        return (write << 31) | (reg << 25) | (*val & 0x00FFFFFF);
@@@ -56,13 -56,13 +62,13 @@@ int pmic_init(unsigned char bus
        p->hw.spi.bitlen = CONFIG_FSL_PMIC_BITLEN;
        p->hw.spi.flags = SPI_XFER_BEGIN | SPI_XFER_END;
        p->hw.spi.prepare_tx = pmic_spi_prepare_tx;
- #elif defined(CONFIG_PMIC_I2C)
+ #elif defined(CONFIG_POWER_I2C)
        p->interface = PMIC_I2C;
        p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR;
 -      p->hw.i2c.tx_num = 3;
 -      p->bus = bus;
 +      p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH;
 +      p->bus = I2C_PMIC;
  #else
- #error "You must select CONFIG_PMIC_SPI or CONFIG_PMIC_I2C"
+ #error "You must select CONFIG_POWER_SPI or CONFIG_PMIC_I2C"
  #endif
  
        return 0;
index b3207c83c3cfc3089c4cbe8fa359f864b29e797c,cc3022a2c73a9e8c6578b8ac99951ae50976633a..170a358b5283849207827f21d7eb49dc419d9acf
@@@ -37,9 -37,9 +37,10 @@@ COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos
  COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
  COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o
  COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 +COBJS-$(CONFIG_LD9040) += ld9040.o
  COBJS-$(CONFIG_SED156X) += sed156x.o
  COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
+ COBJS-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
  COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
  COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
  COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
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index c472075c9adcf9189b85efe02360b0f670b41c44,1916b85e2837f06760cf32cf03a310d549e54aed..a0af3eeb26f2783b64b6eca380e0c6894170be77
  #define CONFIG_SYS_I2C_SPEED            100000
  
  /* PMIC Configs */
- #define CONFIG_PMIC
- #define CONFIG_PMIC_I2C
- #define CONFIG_PMIC_FSL
+ #define CONFIG_POWER
+ #define CONFIG_POWER_I2C
+ #define CONFIG_POWER_FSL
  #define CONFIG_SYS_FSL_PMIC_I2C_ADDR    8
 +#define CONFIG_PMIC_FSL_MC13892
  #define CONFIG_RTC_MC13XXX
  
  /* MMC Configs */
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index c2d1c66215f3ffa3d563af6f5a740e143cbcc548,ab10bd0abc7e57a24e2115eb3fd3698899016dd6..de0c777819b2b4a41d18dbd3188a611df2390306
  #define CONFIG_TEGRA_KEYBOARD
  #define CONFIG_KEYBOARD
  
- #undef TEGRA_DEVICE_SETTINGS
- #define TEGRA_DEVICE_SETTINGS "stdin=serial,tegra-kbc\0" \
-                               "stdout=serial,lcd\0" \
-                               "stderr=serial,lcd\0"
+ /* USB keyboard */
+ #define CONFIG_USB_KEYBOARD
  
 -#include "tegra-common-post.h"
 +/* LCD support */
 +#define CONFIG_LCD
 +#define CONFIG_PWM_TEGRA
 +#define CONFIG_VIDEO_TEGRA
 +#define LCD_BPP                               LCD_COLOR16
 +#define CONFIG_SYS_WHITE_ON_BLACK
 +#define CONFIG_CONSOLE_SCROLL_LINES   10
  
  /* NAND support */
  #define CONFIG_CMD_NAND
index e412da8c9d8f7e18a568a64f678850a6616f166f,39a347af84afce85cffc03f0b5fe2f558079c318..9ee462f0ca9cf7be1622a3e3d83e1c65cde7de65
  #define CONFIG_I2C_MULTI_BUS
  #define CONFIG_MAX_I2C_NUM    8
  #define CONFIG_SYS_I2C_SLAVE    0x0
+ #define CONFIG_I2C_EDID
  
 +/* PMIC */
 +#define CONFIG_PMIC
 +#define CONFIG_PMIC_I2C
 +#define CONFIG_PMIC_MAX77686
 +
 +/* SPI */
 +#define CONFIG_ENV_IS_IN_SPI_FLASH
 +#define CONFIG_SPI_FLASH
 +
 +#ifdef CONFIG_SPI_FLASH
 +#define CONFIG_EXYNOS_SPI
 +#define CONFIG_CMD_SF
 +#define CONFIG_CMD_SPI
 +#define CONFIG_SPI_FLASH_WINBOND
 +#define CONFIG_SF_DEFAULT_MODE                SPI_MODE_0
 +#define CONFIG_SF_DEFAULT_SPEED               50000000
 +#define EXYNOS5_SPI_NUM_CONTROLLERS   5
 +#endif
 +
 +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
 +#define CONFIG_ENV_SPI_MODE   SPI_MODE_0
 +#define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
 +#define CONFIG_ENV_SPI_BUS    1
 +#define CONFIG_ENV_SPI_MAX_HZ 50000000
 +#endif
 +
  /* Ethernet Controllor Driver */
  #ifdef CONFIG_CMD_NET
  #define CONFIG_SMC911X
index 2d0d61dc9d4a91dc229f1d3f88983ae6d4dd7347,6f310bee601328b3eab4e492e1c9cbe5b1a6ca80..ee40cc2a3e0e26a38d3ddf58bf5f74c01db5c190
        "fdt_addr_r=0x02000000\0" \
        "ramdisk_addr_r=0x02100000\0" \
  
 -      "stdout=serial\0" \
 -      "stderr=serial\0" \
+ #ifdef CONFIG_TEGRA_KEYBOARD
+ #define STDIN_KBD_KBC ",tegra-kbc"
+ #else
+ #define STDIN_KBD_KBC ""
+ #endif
+ #ifdef CONFIG_USB_KEYBOARD
+ #define STDIN_KBD_USB ",usbkbd"
+ #define CONFIG_SYS_USB_EVENT_POLL
+ #define CONFIG_PREBOOT                        "usb start"
+ #else
+ #define STDIN_KBD_USB ""
+ #endif
+ #define TEGRA_DEVICE_SETTINGS \
+       "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB "\0" \
++      "stdout=serial,lcd\0" \
++      "stderr=serial,lcd\0" \
  #define CONFIG_EXTRA_ENV_SETTINGS \
        TEGRA_DEVICE_SETTINGS \
        MEM_LAYOUT_ENV_SETTINGS \
Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
diff --cc include/lcd.h
Simple merge
Simple merge
diff --cc lib/fdtdec.c
Simple merge
diff --cc spl/Makefile
Simple merge