Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 14 Jan 2013 16:00:02 +0000 (17:00 +0100)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 14 Jan 2013 16:00:02 +0000 (17:00 +0100)
144 files changed:
MAINTAINERS
Makefile
README
arch/arm/cpu/arm1136/start.S
arch/arm/cpu/arm1176/start.S
arch/arm/cpu/arm720t/start.S
arch/arm/cpu/arm920t/start.S
arch/arm/cpu/arm925t/start.S
arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
arch/arm/cpu/arm926ejs/kirkwood/mpp.c
arch/arm/cpu/arm926ejs/start.S
arch/arm/cpu/arm946es/start.S
arch/arm/cpu/arm_intcm/start.S
arch/arm/cpu/armv7/exynos/clock.c
arch/arm/cpu/armv7/exynos/pinmux.c
arch/arm/cpu/armv7/start.S
arch/arm/cpu/ixp/start.S
arch/arm/cpu/pxa/start.S
arch/arm/cpu/s3c44b0/start.S
arch/arm/cpu/sa1100/start.S
arch/arm/dts/exynos5250.dtsi [new file with mode: 0644]
arch/arm/include/asm/arch-at91/at91sam9x5.h
arch/arm/include/asm/arch-exynos/clk.h
arch/arm/include/asm/arch-exynos/clock.h
arch/arm/include/asm/arch-exynos/cpu.h
arch/arm/include/asm/arch-exynos/dp_info.h
arch/arm/include/asm/arch-exynos/gpio.h
arch/arm/include/asm/arch-exynos/mipi_dsim.h
arch/arm/include/asm/arch-exynos/periph.h
arch/arm/include/asm/arch-exynos/pinmux.h
arch/arm/include/asm/arch-exynos/sromc.h
arch/arm/include/asm/arch-kirkwood/cpu.h
arch/arm/include/asm/arch-kirkwood/mpp.h
arch/arm/include/asm/global_data.h
arch/arm/lib/Makefile
arch/arm/lib/board.c
arch/arm/lib/cache-cp15.c
arch/arm/lib/crt0.S [new file with mode: 0644]
arch/m68k/lib/board.c
arch/sh/include/asm/cpu_sh4.h
arch/sh/include/asm/cpu_sh7752.h [new file with mode: 0644]
board/LaCie/net2big_v2/net2big_v2.c
board/LaCie/netspace_v2/netspace_v2.c
board/LaCie/wireless_space/Makefile [new file with mode: 0644]
board/LaCie/wireless_space/kwbimage.cfg [new file with mode: 0644]
board/LaCie/wireless_space/wireless_space.c [new file with mode: 0644]
board/Marvell/dreamplug/dreamplug.c
board/Marvell/guruplug/guruplug.c
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
board/Marvell/openrd/openrd.c
board/Marvell/rd6281a/rd6281a.c
board/Marvell/sheevaplug/sheevaplug.c
board/Seagate/dockstar/dockstar.c
board/atmel/at91sam9x5ek/at91sam9x5ek.c
board/buffalo/lsxl/lsxl.c
board/cloudengines/pogo_e02/pogo_e02.c
board/cm_t35/cm_t35.c
board/d-link/dns325/dns325.c
board/h2200/h2200.c
board/iomega/iconnect/iconnect.c
board/karo/tk71/tk71.c
board/keymile/common/common.c
board/keymile/km_arm/km_arm.c
board/keymile/km_arm/kwbimage-memphis.cfg
board/keymile/km_arm/kwbimage.cfg
board/keymile/km_arm/kwbimage_128M16_1.cfg
board/keymile/km_arm/kwbimage_256M8_1.cfg
board/raidsonic/ib62x0/ib62x0.c
board/renesas/sh7752evb/Makefile [new file with mode: 0644]
board/renesas/sh7752evb/lowlevel_init.S [new file with mode: 0644]
board/renesas/sh7752evb/sh7752evb.c [new file with mode: 0644]
board/renesas/sh7752evb/spi-boot.c [new file with mode: 0644]
board/renesas/sh7752evb/u-boot.lds [new file with mode: 0644]
board/samsung/dts/exynos5250-smdk5250.dts [new file with mode: 0644]
board/samsung/smdk5250/smdk5250.c
board/samsung/trats/trats.c
boards.cfg
common/cmd_bootm.c
common/cmd_mem.c
common/cmd_setexpr.c
common/cmd_sf.c
common/cmd_sound.c
common/cmd_version.c
common/usb.c
common/usb_hub.c
common/usb_storage.c
doc/README.sh7752evb [new file with mode: 0644]
doc/README.usb
doc/device-tree-bindings/exynos/isp-spi.txt [new file with mode: 0644]
doc/device-tree-bindings/exynos/sound.txt [new file with mode: 0644]
drivers/i2c/s3c24x0_i2c.c
drivers/i2c/s3c24x0_i2c.h
drivers/mtd/cfi_flash.c
drivers/mtd/nand/Makefile
drivers/mtd/nand/fsl_ifc_nand.c
drivers/net/phy/mv88e61xx.c
drivers/net/phy/mv88e61xx.h
drivers/power/pmic/pmic_max77686.c
drivers/serial/ns16550.c
drivers/serial/serial_sh.h
drivers/sound/sound.c
drivers/sound/wm8994.c
drivers/sound/wm8994.h
drivers/spi/atmel_spi.c
drivers/spi/exynos_spi.c
drivers/spi/kirkwood_spi.c
drivers/usb/gadget/g_dnl.c
drivers/usb/gadget/pxa25x_udc.c
drivers/usb/host/ehci-exynos.c
drivers/usb/host/ohci-at91.c
drivers/video/exynos_dp.c
drivers/video/exynos_fb.c
drivers/video/exynos_fimd.c
include/common.h
include/config_cmd_all.h
include/configs/at91sam9x5ek.h
include/configs/cm_t35.h
include/configs/coreboot.h
include/configs/eb_cpu5282.h
include/configs/exynos5250-dt.h [new file with mode: 0644]
include/configs/h2200.h
include/configs/igep00x0.h
include/configs/km/keymile-common.h
include/configs/lsxl.h
include/configs/mv-common.h
include/configs/sh7752evb.h [new file with mode: 0644]
include/configs/smdk5250.h
include/configs/socfpga_cyclone5.h
include/configs/trats.h
include/configs/wireless_space.h [new file with mode: 0644]
include/env_callback.h
include/fdtdec.h
include/flash.h
include/i2c.h
include/netdev.h
include/sound.h
include/twl4030.h
include/usb.h
lib/asm-offsets.c
lib/fdtdec.c
nand_spl/board/freescale/mx31pdk/Makefile
nand_spl/board/karo/tx25/Makefile
tools/env/fw_env.c
tools/env/fw_env_main.c

index 36b47b741ad2f63cef57856cd58ff99d4d9b827b..28c052d7a0e32500a400876c6af473f26c9eaa55 100644 (file)
@@ -1203,6 +1203,7 @@ Mark Jonas <mark.jonas@de.bosch.com>
 Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
 
        MS7720SE        SH7720
+       R0P77520000RZ   SH7752
        R0P77570030RL   SH7757
        R0P77850011RL   SH7785
 
index a7b6cd1cbad361ecfa6f71faff567ebae86c449d..e1b9384d808b3a832c4de20a2f17e669eaeda701 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -24,7 +24,7 @@
 VERSION = 2013
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc2
+EXTRAVERSION = -rc3
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -869,7 +869,7 @@ clobber:    tidy
        @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
        @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
        @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
-       @rm -f $(obj)MLO
+       @rm -f $(obj)MLO MLO.byteswap
        @rm -f $(obj)SPL
        @rm -f $(obj)tools/xway-swap-bytes
        @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
diff --git a/README b/README
index 653ef6aa4a55d57686165e56eeec847dcd40b3f1..8707bf2d7c4510872feaf5e527c230d0919e28bb 100644 (file)
--- a/README
+++ b/README
@@ -616,6 +616,14 @@ The following options need to be configured:
                boot loader that has already initialized the UART.  Define this
                variable to flush the UART at init time.
 
+               CONFIG_SYS_NS16550_BROKEN_TEMT
+
+               16550 UART set the Transmitter Empty (TEMT) Bit when all output
+               has finished and the transmitter is totally empty. U-Boot waits
+               for this bit to be set to initialize the serial console. On some
+               broken platforms this bit is not set in SPL making U-Boot to
+               hang while waiting for TEMT. Define this option to avoid it.
+
 
 - Console Interface:
                Depending on board, define exactly one serial port
@@ -849,6 +857,7 @@ The following options need to be configured:
                CONFIG_CMD_LOADS          loads
                CONFIG_CMD_MD5SUM         print md5 message digest
                                          (requires CONFIG_CMD_MEMORY and CONFIG_MD5)
+               CONFIG_CMD_MEMINFO      * Display detailed memory information
                CONFIG_CMD_MEMORY         md, mm, nm, mw, cp, cmp, crc, base,
                                          loop, loopw, mtest
                CONFIG_CMD_MISC           Misc functions like sleep etc
@@ -2378,6 +2387,15 @@ CBFS (Coreboot Filesystem) support
                run-time determined information about the hardware to the
                environment.  These will be named board_name, board_rev.
 
+               CONFIG_DELAY_ENVIRONMENT
+
+               Normally the environment is loaded when the board is
+               intialised so that it is available to U-Boot. This inhibits
+               that so that the environment is not available until
+               explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL
+               this is instead controlled by the value of
+               /config/load-environment.
+
 - DataFlash Support:
                CONFIG_HAS_DATAFLASH
 
@@ -2404,6 +2422,11 @@ CBFS (Coreboot Filesystem) support
                CONFIG_SF_DEFAULT_MODE          (see include/spi.h)
                CONFIG_SF_DEFAULT_SPEED         in Hz
 
+               CONFIG_CMD_SF_TEST
+
+               Define this option to include a destructive SPI flash
+               test ('sf test').
+
 - SystemACE Support:
                CONFIG_SYSTEMACE
 
@@ -3448,6 +3471,16 @@ use the "saveenv" command to store a valid environment.
                space for already greatly restricted images, including but not
                limited to NAND_SPL configurations.
 
+- CONFIG_DISPLAY_BOARDINFO
+               Display information about the board that U-Boot is running on
+               when U-Boot starts up. The board function checkboard() is called
+               to do this.
+
+- CONFIG_DISPLAY_BOARDINFO_LATE
+               Similar to the previous option, but display this information
+               later, once stdio is running and output goes to the LCD, if
+               present.
+
 Low Level (hardware related) configuration options:
 ---------------------------------------------------
 
index 5d3b4c2299ef05659066c2f259205274a5c4710e..a067b8a1868182f33e6b9e11a980d19ae004186d 100644 (file)
@@ -165,13 +165,7 @@ next:
        bl  cpu_init_crit
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -188,14 +182,10 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _image_copy_end_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -245,7 +235,15 @@ fixnext:
        add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
        cmp     r2, r3
        blo     fixloop
-       b       clear_bss
+       bx      lr
+
+#endif
+
+relocate_done:
+
+       bx      lr
+
+#ifndef CONFIG_SPL_BUILD
 
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
@@ -253,54 +251,13 @@ _rel_dyn_end_ofs:
        .word __rel_dyn_end - _start
 _dynsym_start_ofs:
        .word __dynsym_start - _start
-#endif
 
-clear_bss:
-#ifdef CONFIG_SPL_BUILD
-       /* No relocation for SPL */
-       ldr     r0, =__bss_start
-       ldr     r1, =__bss_end__
-#else
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
 #endif
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
 
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-       ldr     r0, _nand_boot_ofs
-       mov     pc, r0
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
 
-_nand_boot_ofs:
-       .word nand_boot
-#else
-jump_2_ram:
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
-       mov     pc, lr
-
-_board_init_r_ofs:
-       .word board_init_r - _start
-#endif
+       bx      lr
 
 /*
  *************************************************************************
index 667a0e0c48631b1f34c5fec04d1e994abae390ae..40df4b161428dd3343ba0eb8730908a98bdd1720 100644 (file)
@@ -224,12 +224,7 @@ skip_tcmdisable:
         */
        bl      lowlevel_init           /* go setup pll,mux,memory */
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -246,14 +241,10 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -343,49 +334,9 @@ mmu_enable:
 skip_hw_init:
 #endif
 
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-#ifndef CONFIG_NAND_SPL
-       bl coloured_LED_init
-       bl red_led_on
-#endif
-#endif
+relocate_done:
 
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-       ldr     pc, _nand_boot
-
-_nand_boot: .word nand_boot
-#else
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
-       mov     pc, lr
-
-_board_init_r_ofs:
-       .word board_init_r - _start
-#endif
+       bx      lr
 
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
@@ -399,6 +350,11 @@ _mmu_table_base:
        .word mmu_table
 #endif
 
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       mov     pc, lr
+
 #ifndef CONFIG_NAND_SPL
 /*
  * we assume that cache operation is done before. (eg. cleanup_before_linux())
index c2a7763fff00a2b4e974dacf7b31b144641c6e2c..771d3869c157969f4fdb2039d01bf176e7a79fe7 100644 (file)
@@ -147,12 +147,7 @@ reset:
        bl      cpu_init_crit
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -169,14 +164,10 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -228,43 +219,10 @@ fixnext:
        blo     fixloop
 #endif
 
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-
-       bl coloured_LED_init
-       bl red_led_on
-#endif
+relocate_done:
 
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
        mov     pc, lr
 
-_board_init_r_ofs:
-       .word board_init_r - _start
-
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
 _rel_dyn_end_ofs:
@@ -272,6 +230,11 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
        .word __dynsym_start - _start
 
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       mov     pc, lr
+
 /*
  *************************************************************************
  *
index 14c9156c084aebacdebb12ce0fa44e07cd940627..511d21d3344eec1f68b835b85a66584d6f261173 100644 (file)
@@ -182,12 +182,7 @@ copyex:
        bl      cpu_init_crit
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -204,14 +199,10 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -263,51 +254,10 @@ fixnext:
        blo     fixloop
 #endif
 
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-
-       bl coloured_LED_init
-       bl red_led_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-       ldr     r0, _nand_boot_ofs
-       mov     pc, r0
+relocate_done:
 
-_nand_boot_ofs:
-       .word nand_boot
-#else
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
        mov     pc, lr
 
-_board_init_r_ofs:
-       .word board_init_r - _start
-#endif
-
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
 _rel_dyn_end_ofs:
@@ -315,6 +265,11 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
        .word __dynsym_start - _start
 
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       mov     pc, lr
+
 /*
  *************************************************************************
  *
index 3a483f6caef858e76aa7b89ce1ad8accb5dc2db7..e8d6d71c1701613e7781846c6ecfe25d57ee0b1e 100644 (file)
 #include <config.h>
 #include <version.h>
 
-#if defined(CONFIG_OMAP1510)
-#include <./configs/omap1510.h>
-#endif
-
 /*
  *************************************************************************
  *
@@ -176,12 +172,7 @@ poll1:
        bl  cpu_init_crit
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -198,14 +189,10 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -257,51 +244,10 @@ fixnext:
        blo     fixloop
 #endif
 
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-
-       bl coloured_LED_init
-       bl red_led_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-       ldr     r0, _nand_boot_ofs
-       mov     pc, r0
+relocate_done:
 
-_nand_boot_ofs:
-       .word nand_boot
-#else
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
        mov     pc, lr
 
-_board_init_r_ofs:
-       .word board_init_r - _start
-#endif
-
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
 _rel_dyn_end_ofs:
@@ -309,6 +255,11 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
        .word __dynsym_start - _start
 
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       mov     pc, lr
+
 /*
  *************************************************************************
  *
index 93485523b585077e48a9ca03a6d163f80ed5f77e..0448c0b133b99e254d6c8a373ba731c19e933717 100644 (file)
@@ -193,6 +193,19 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 }
 #endif
 
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+void at91_uhp_hw_init(void)
+{
+       /* Enable VBus on UHP ports */
+       at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */
+       at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */
+#if defined(CONFIG_USB_OHCI_NEW)
+       /* port C is OHCI only */
+       at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */
+#endif
+}
+#endif
+
 #ifdef CONFIG_MACB
 void at91_macb_hw_init(void)
 {
index 03eb2de520f72bbf555d62fd643c6bc7151d061f..0ba6f098cb6b2c6486dc1a79375a6482634327f9 100644 (file)
@@ -31,7 +31,7 @@ static u32 kirkwood_variant(void)
 #define MPP_CTRL(i)    (KW_MPP_BASE + (i* 4))
 #define MPP_NR_REGS    (1 + MPP_MAX/8)
 
-void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save)
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save)
 {
        u32 mpp_ctrl[MPP_NR_REGS];
        unsigned int variant_mask;
index 2188f7e35d1df8de3bce8d9ccadea6e60bc89b46..66a8b654bdf465d9fc1ad711de4925ca42006c8c 100644 (file)
 #include <common.h>
 #include <version.h>
 
-#if defined(CONFIG_OMAP1610)
-#include <./configs/omap1510.h>
-#elif defined(CONFIG_OMAP730)
-#include <./configs/omap730.h>
-#endif
-
 /*
  *************************************************************************
  *
@@ -198,20 +192,7 @@ reset:
        bl      cpu_init_crit
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-#else
-#ifdef CONFIG_SPL_BUILD
-       ldr     sp, =(CONFIG_SPL_STACK)
-#else
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-#endif
-#endif
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -229,15 +210,11 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        sub     r9, r6, r0              /* r9 <- relocation offset */
        cmp     r0, r6
-       moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       moveq   r9, #0                  /* no relocation. offset(r9) = 0 */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -289,56 +266,9 @@ fixnext:
        blo     fixloop
 #endif
 
-clear_bss:
-#ifdef CONFIG_SPL_BUILD
-       /* No relocation for SPL */
-       ldr     r0, =__bss_start
-       ldr     r1, =__bss_end__
-#else
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-#endif
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-
-#ifndef CONFIG_SPL_BUILD
-       bl coloured_LED_init
-       bl red_led_on
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-       ldr     r0, _nand_boot_ofs
-       mov     pc, r0
+relocate_done:
 
-_nand_boot_ofs:
-       .word nand_boot
-#else
-       ldr     r0, _board_init_r_ofs
-       ldr     r1, _TEXT_BASE
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
-       mov     pc, lr
-
-_board_init_r_ofs:
-       .word board_init_r - _start
-#endif
+       bx      lr
 
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
@@ -346,8 +276,14 @@ _rel_dyn_end_ofs:
        .word __rel_dyn_end - _start
 _dynsym_start_ofs:
        .word __dynsym_start - _start
+
 #endif
 
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       bx      lr
+
 /*
  *************************************************************************
  *
index 30e21835cc8759c6947ab1e46fc367f6a728e2f0..a7a98a4e58a94b0a5e4515f66119d13c0a0a39c6 100644 (file)
@@ -147,12 +147,7 @@ reset:
        bl      cpu_init_crit
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -169,14 +164,10 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -228,46 +219,10 @@ fixnext:
        blo     fixloop
 #endif
 
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-       ldr     pc, _nand_boot
+relocate_done:
 
-_nand_boot: .word nand_boot
-#else
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
        mov     pc, lr
 
-_board_init_r_ofs:
-       .word board_init_r - _start
-#endif
-
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
 _rel_dyn_end_ofs:
@@ -275,6 +230,11 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
        .word __dynsym_start - _start
 
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       mov     pc, lr
+
 /*
  *************************************************************************
  *
index a133d19bc88f863c6b5c036133ff3eec7d548fba..c189849fa844775b4cfa9234291aca9ff39f53b6 100644 (file)
@@ -143,12 +143,7 @@ reset:
        bl      cpu_init_crit
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -165,14 +160,10 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -224,50 +215,9 @@ fixnext:
        blo     fixloop
 #endif
 
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-
-       bl coloured_LED_init
-       bl red_led_on
-#endif
+relocate_done:
 
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_NAND_SPL
-       ldr     r0, _nand_boot_ofs
-       mov     pc, r0
-
-_nand_boot_ofs:
-       .word nand_boot
-#else
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
-       mov     pc, lr
-
-_board_init_r_ofs:
-       .word board_init_r - _start
-#endif
+       bx      lr
 
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
@@ -276,6 +226,11 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
        .word __dynsym_start - _start
 
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       mov     pc, lr
+
 /*
  *************************************************************************
  *
index 74599798c435ff84ee4e05117c13936e57351ed7..956427c9ebbfe9dd9a9ed8b763ecd25c7f75482e 100644 (file)
@@ -112,6 +112,36 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
        return exynos_get_pll_clk(pllreg, r, k);
 }
 
+/* exynos4x12: return pll clock frequency */
+static unsigned long exynos4x12_get_pll_clk(int pllreg)
+{
+       struct exynos4x12_clock *clk =
+               (struct exynos4x12_clock *)samsung_get_base_clock();
+       unsigned long r, k = 0;
+
+       switch (pllreg) {
+       case APLL:
+               r = readl(&clk->apll_con0);
+               break;
+       case MPLL:
+               r = readl(&clk->mpll_con0);
+               break;
+       case EPLL:
+               r = readl(&clk->epll_con0);
+               k = readl(&clk->epll_con1);
+               break;
+       case VPLL:
+               r = readl(&clk->vpll_con0);
+               k = readl(&clk->vpll_con1);
+               break;
+       default:
+               printf("Unsupported PLL (%d)\n", pllreg);
+               return 0;
+       }
+
+       return exynos_get_pll_clk(pllreg, r, k);
+}
+
 /* exynos5: return pll clock frequency */
 static unsigned long exynos5_get_pll_clk(int pllreg)
 {
@@ -193,6 +223,28 @@ static unsigned long exynos4_get_arm_clk(void)
        return armclk;
 }
 
+/* exynos4x12: return ARM clock frequency */
+static unsigned long exynos4x12_get_arm_clk(void)
+{
+       struct exynos4x12_clock *clk =
+               (struct exynos4x12_clock *)samsung_get_base_clock();
+       unsigned long div;
+       unsigned long armclk;
+       unsigned int core_ratio;
+       unsigned int core2_ratio;
+
+       div = readl(&clk->div_cpu0);
+
+       /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
+       core_ratio = (div >> 0) & 0x7;
+       core2_ratio = (div >> 28) & 0x7;
+
+       armclk = get_pll_clk(APLL) / (core_ratio + 1);
+       armclk /= (core2_ratio + 1);
+
+       return armclk;
+}
+
 /* exynos5: return ARM clock frequency */
 static unsigned long exynos5_get_arm_clk(void)
 {
@@ -258,6 +310,20 @@ static unsigned long exynos4_get_pwm_clk(void)
        return pclk;
 }
 
+/* exynos4x12: return pwm clock frequency */
+static unsigned long exynos4x12_get_pwm_clk(void)
+{
+       unsigned long pclk, sclk;
+       unsigned int ratio;
+
+       sclk = get_pll_clk(MPLL);
+       ratio = 8;
+
+       pclk = sclk / (ratio + 1);
+
+       return pclk;
+}
+
 /* exynos5: return pwm clock frequency */
 static unsigned long exynos5_get_pwm_clk(void)
 {
@@ -326,6 +392,51 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
        return uclk;
 }
 
+/* exynos4x12: return uart clock frequency */
+static unsigned long exynos4x12_get_uart_clk(int dev_index)
+{
+       struct exynos4x12_clock *clk =
+               (struct exynos4x12_clock *)samsung_get_base_clock();
+       unsigned long uclk, sclk;
+       unsigned int sel;
+       unsigned int ratio;
+
+       /*
+        * CLK_SRC_PERIL0
+        * UART0_SEL [3:0]
+        * UART1_SEL [7:4]
+        * UART2_SEL [8:11]
+        * UART3_SEL [12:15]
+        * UART4_SEL [16:19]
+        */
+       sel = readl(&clk->src_peril0);
+       sel = (sel >> (dev_index << 2)) & 0xf;
+
+       if (sel == 0x6)
+               sclk = get_pll_clk(MPLL);
+       else if (sel == 0x7)
+               sclk = get_pll_clk(EPLL);
+       else if (sel == 0x8)
+               sclk = get_pll_clk(VPLL);
+       else
+               return 0;
+
+       /*
+        * CLK_DIV_PERIL0
+        * UART0_RATIO [3:0]
+        * UART1_RATIO [7:4]
+        * UART2_RATIO [8:11]
+        * UART3_RATIO [12:15]
+        * UART4_RATIO [16:19]
+        */
+       ratio = readl(&clk->div_peril0);
+       ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+       uclk = sclk / (ratio + 1);
+
+       return uclk;
+}
+
 /* exynos5: return uart clock frequency */
 static unsigned long exynos5_get_uart_clk(int dev_index)
 {
@@ -373,6 +484,100 @@ static unsigned long exynos5_get_uart_clk(int dev_index)
        return uclk;
 }
 
+static unsigned long exynos4_get_mmc_clk(int dev_index)
+{
+       struct exynos4_clock *clk =
+               (struct exynos4_clock *)samsung_get_base_clock();
+       unsigned long uclk, sclk;
+       unsigned int sel, ratio, pre_ratio;
+       int shift;
+
+       sel = readl(&clk->src_fsys);
+       sel = (sel >> (dev_index << 2)) & 0xf;
+
+       if (sel == 0x6)
+               sclk = get_pll_clk(MPLL);
+       else if (sel == 0x7)
+               sclk = get_pll_clk(EPLL);
+       else if (sel == 0x8)
+               sclk = get_pll_clk(VPLL);
+       else
+               return 0;
+
+       switch (dev_index) {
+       case 0:
+       case 1:
+               ratio = readl(&clk->div_fsys1);
+               pre_ratio = readl(&clk->div_fsys1);
+               break;
+       case 2:
+       case 3:
+               ratio = readl(&clk->div_fsys2);
+               pre_ratio = readl(&clk->div_fsys2);
+               break;
+       case 4:
+               ratio = readl(&clk->div_fsys3);
+               pre_ratio = readl(&clk->div_fsys3);
+               break;
+       default:
+               return 0;
+       }
+
+       if (dev_index == 1 || dev_index == 3)
+               shift = 16;
+
+       ratio = (ratio >> shift) & 0xf;
+       pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+       uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+       return uclk;
+}
+
+static unsigned long exynos5_get_mmc_clk(int dev_index)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       unsigned long uclk, sclk;
+       unsigned int sel, ratio, pre_ratio;
+       int shift;
+
+       sel = readl(&clk->src_fsys);
+       sel = (sel >> (dev_index << 2)) & 0xf;
+
+       if (sel == 0x6)
+               sclk = get_pll_clk(MPLL);
+       else if (sel == 0x7)
+               sclk = get_pll_clk(EPLL);
+       else if (sel == 0x8)
+               sclk = get_pll_clk(VPLL);
+       else
+               return 0;
+
+       switch (dev_index) {
+       case 0:
+       case 1:
+               ratio = readl(&clk->div_fsys1);
+               pre_ratio = readl(&clk->div_fsys1);
+               break;
+       case 2:
+       case 3:
+               ratio = readl(&clk->div_fsys2);
+               pre_ratio = readl(&clk->div_fsys2);
+               break;
+       default:
+               return 0;
+       }
+
+       if (dev_index == 1 || dev_index == 3)
+               shift = 16;
+
+       ratio = (ratio >> shift) & 0xf;
+       pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
+       uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
+
+       return uclk;
+}
+
 /* exynos4: set the mmc clock */
 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
@@ -381,6 +586,38 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
        unsigned int addr;
        unsigned int val;
 
+       /*
+        * CLK_DIV_FSYS1
+        * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+        * CLK_DIV_FSYS2
+        * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+        * CLK_DIV_FSYS3
+        * MMC4_PRE_RATIO [15:8]
+        */
+       if (dev_index < 2) {
+               addr = (unsigned int)&clk->div_fsys1;
+       }  else if (dev_index == 4) {
+               addr = (unsigned int)&clk->div_fsys3;
+               dev_index -= 4;
+       } else {
+               addr = (unsigned int)&clk->div_fsys2;
+               dev_index -= 2;
+       }
+
+       val = readl(addr);
+       val &= ~(0xff << ((dev_index << 4) + 8));
+       val |= (div & 0xff) << ((dev_index << 4) + 8);
+       writel(val, addr);
+}
+
+/* exynos4x12: set the mmc clock */
+static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
+{
+       struct exynos4x12_clock *clk =
+               (struct exynos4x12_clock *)samsung_get_base_clock();
+       unsigned int addr;
+       unsigned int val;
+
        /*
         * CLK_DIV_FSYS1
         * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
@@ -603,7 +840,7 @@ void exynos5_set_lcd_clk(void)
         */
        cfg = readl(&clk->src_disp1_0);
        cfg &= ~(0xf);
-       cfg |= 0x8;
+       cfg |= 0x6;
        writel(cfg, &clk->src_disp1_0);
 
        /*
@@ -940,16 +1177,22 @@ unsigned long get_pll_clk(int pllreg)
 {
        if (cpu_is_exynos5())
                return exynos5_get_pll_clk(pllreg);
-       else
+       else {
+               if (proid_is_exynos4412())
+                       return exynos4x12_get_pll_clk(pllreg);
                return exynos4_get_pll_clk(pllreg);
+       }
 }
 
 unsigned long get_arm_clk(void)
 {
        if (cpu_is_exynos5())
                return exynos5_get_arm_clk();
-       else
+       else {
+               if (proid_is_exynos4412())
+                       return exynos4x12_get_arm_clk();
                return exynos4_get_arm_clk();
+       }
 }
 
 unsigned long get_i2c_clk(void)
@@ -968,24 +1211,41 @@ unsigned long get_pwm_clk(void)
 {
        if (cpu_is_exynos5())
                return exynos5_get_pwm_clk();
-       else
+       else {
+               if (proid_is_exynos4412())
+                       return exynos4x12_get_pwm_clk();
                return exynos4_get_pwm_clk();
+       }
 }
 
 unsigned long get_uart_clk(int dev_index)
 {
        if (cpu_is_exynos5())
                return exynos5_get_uart_clk(dev_index);
-       else
+       else {
+               if (proid_is_exynos4412())
+                       return exynos4x12_get_uart_clk(dev_index);
                return exynos4_get_uart_clk(dev_index);
+       }
+}
+
+unsigned long get_mmc_clk(int dev_index)
+{
+       if (cpu_is_exynos5())
+               return exynos5_get_mmc_clk(dev_index);
+       else
+               return exynos4_get_mmc_clk(dev_index);
 }
 
 void set_mmc_clk(int dev_index, unsigned int div)
 {
        if (cpu_is_exynos5())
                exynos5_set_mmc_clk(dev_index, div);
-       else
+       else {
+               if (proid_is_exynos4412())
+                       exynos4x12_set_mmc_clk(dev_index, div);
                exynos4_set_mmc_clk(dev_index, div);
+       }
 }
 
 unsigned long get_lcd_clk(void)
index 20a4b8414a9f5aff3d6a93844f1f8e2f6045706e..bd499b47614ca2b1af126642931fa627d14f45ca 100644 (file)
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/sromc.h>
@@ -370,6 +371,43 @@ static void exynos4_i2c_config(int peripheral, int flags)
        }
 }
 
+static int exynos4_mmc_config(int peripheral, int flags)
+{
+       struct exynos4_gpio_part2 *gpio2 =
+               (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
+       struct s5p_gpio_bank *bank, *bank_ext;
+       int i;
+
+       switch (peripheral) {
+       case PERIPH_ID_SDMMC0:
+               bank = &gpio2->k0;
+               bank_ext = &gpio2->k1;
+               break;
+       case PERIPH_ID_SDMMC2:
+               bank = &gpio2->k2;
+               bank_ext = &gpio2->k3;
+               break;
+       default:
+               return -1;
+       }
+       for (i = 0; i < 7; i++) {
+               if (i == 2)
+                       continue;
+               s5p_gpio_cfg_pin(bank, i,  GPIO_FUNC(0x2));
+               s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+               s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+       }
+       if (flags & PINMUX_FLAG_8BIT_MODE) {
+               for (i = 3; i < 7; i++) {
+                       s5p_gpio_cfg_pin(bank_ext, i,  GPIO_FUNC(0x3));
+                       s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_NONE);
+                       s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+               }
+       }
+
+       return 0;
+}
+
 static int exynos4_pinmux_config(int peripheral, int flags)
 {
        switch (peripheral) {
@@ -383,6 +421,14 @@ static int exynos4_pinmux_config(int peripheral, int flags)
        case PERIPH_ID_I2C7:
                exynos4_i2c_config(peripheral, flags);
                break;
+       case PERIPH_ID_SDMMC0:
+       case PERIPH_ID_SDMMC2:
+               return exynos4_mmc_config(peripheral, flags);
+       case PERIPH_ID_SDMMC1:
+       case PERIPH_ID_SDMMC3:
+       case PERIPH_ID_SDMMC4:
+               printf("SDMMC device %d not implemented\n", peripheral);
+               return -1;
        default:
                debug("%s: invalid peripheral %d", __func__, peripheral);
                return -1;
@@ -402,3 +448,31 @@ int exynos_pinmux_config(int peripheral, int flags)
                return -1;
        }
 }
+
+#ifdef CONFIG_OF_CONTROL
+static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
+{
+       int err;
+       u32 cell[3];
+
+       err = fdtdec_get_int_array(blob, node, "interrupts", cell,
+                                       ARRAY_SIZE(cell));
+       if (err)
+               return PERIPH_ID_NONE;
+
+       /* check for invalid peripheral id */
+       if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
+               return cell[1];
+
+       debug(" invalid peripheral id\n");
+       return PERIPH_ID_NONE;
+}
+
+int pinmux_decode_periph_id(const void *blob, int node)
+{
+       if (cpu_is_exynos5())
+               return  exynos5_pinmux_decode_periph_id(blob, node);
+       else
+               return PERIPH_ID_NONE;
+}
+#endif
index 7df97c5a3a663a88c01e68ffcfb7b91e4bbcc6b8..dcc1f831bc814a2b47fd034815091561859b7000 100644 (file)
@@ -155,12 +155,7 @@ reset:
        bl      cpu_init_crit
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -177,14 +172,10 @@ ENTRY(relocate_code)
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _image_copy_end_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -233,34 +224,22 @@ fixnext:
        add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
        cmp     r2, r3
        blo     fixloop
-       b       clear_bss
+
+relocate_done:
+
+       bx      lr
+
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
 _rel_dyn_end_ofs:
        .word __rel_dyn_end - _start
 _dynsym_start_ofs:
        .word __dynsym_start - _start
+ENDPROC(relocate_code)
 
-clear_bss:
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
+#endif
 
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-jump_2_ram:
+ENTRY(c_runtime_cpu_setup)
 /*
  * If I-cache is enabled invalidate it
  */
@@ -279,20 +258,9 @@ jump_2_ram:
        mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
 #endif /* !Tegra20 */
 
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
-       mov     pc, lr
-
-_board_init_r_ofs:
-       .word board_init_r - _start
-ENDPROC(relocate_code)
-#endif
+       bx      lr
+
+ENDPROC(c_runtime_cpu_setup)
 
 /*************************************************************************
  *
index c12f1a7db8a5bb99c78ccaaf7f7ef4bd53245704..efb5a400cf67cc9c2732af97714a751b4c2c5c07 100644 (file)
@@ -245,12 +245,7 @@ reset:
        orr     r0,r0,#0x13
        msr     cpsr,r0
 
-/* Set initial stackpointer in SDRAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -267,14 +262,10 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -326,42 +317,9 @@ fixnext:
        blo     fixloop
 #endif
 
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-
-       bl coloured_LED_init
-       bl red_led_on
-#endif
+relocate_done:
 
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
-       mov     pc, lr
-
-_board_init_r_ofs:
-       .word board_init_r - _start
+       bx      lr
 
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
@@ -370,6 +328,11 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
        .word __dynsym_start - _start
 
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       bx      lr
+
 /****************************************************************************/
 /*                                                                         */
 /* Interrupt handling                                                      */
index 536cf5c9748824aee06097f1304e92ab7f557305..72af869704000bad2cf7fa542bb0c249a4a89718 100644 (file)
@@ -164,12 +164,7 @@ reset:
        bl      lock_cache_for_stack
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0, =0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 #ifndef CONFIG_SPL_BUILD
@@ -186,10 +181,6 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
 /* Disable the Dcache RAM lock for stack now */
 #ifdef CONFIG_CPU_PXA25X
        bl      cpu_init_crit
@@ -198,7 +189,7 @@ stack_setup:
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -250,48 +241,9 @@ fixnext:
        blo     fixloop
 #endif
 
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-#endif /* #ifndef CONFIG_SPL_BUILD */
+relocate_done:
 
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-#ifdef CONFIG_ONENAND_SPL
-       ldr     r0, _onenand_boot_ofs
-       mov     pc, r0
-
-_onenand_boot_ofs:
-       .word onenand_boot
-#else
-jump_2_ram:
-       ldr     r0, _board_init_r_ofs
-       ldr     r1, _TEXT_BASE
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
-       mov     pc, lr
-
-_board_init_r_ofs:
-       .word board_init_r - _start
-#endif
+       bx      lr
 
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
@@ -299,7 +251,14 @@ _rel_dyn_end_ofs:
        .word __rel_dyn_end - _start
 _dynsym_start_ofs:
        .word __dynsym_start - _start
+
 #endif
+
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       bx      lr
+
 /*
  *************************************************************************
  *
index 323b923f13da6003785247ab9324205238c883fe..4528c91983837cea91bcb254fa9ee34104a46be1 100644 (file)
@@ -128,12 +128,7 @@ reset:
        bl      lowlevel_init
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -150,14 +145,10 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -209,42 +200,9 @@ fixnext:
        blo     fixloop
 #endif
 
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-
-       bl coloured_LED_init
-       bl red_led_on
-#endif
+relocate_done:
 
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
-       mov     pc, lr
-
-_board_init_r_ofs:
-       .word board_init_r - _start
+       bx      lr
 
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
@@ -253,6 +211,11 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
        .word __dynsym_start - _start
 
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       bx      lr
+
 /*
  *************************************************************************
  *
index 1ea92d14567a86ea728c3fc623816935a0455f88..3144299afef81c256223311259351998f27f9251 100644 (file)
@@ -132,12 +132,7 @@ reset:
        bl      cpu_init_crit
 #endif
 
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
+       bl      _main
 
 /*------------------------------------------------------------------------------*/
 
@@ -154,14 +149,10 @@ relocate_code:
        mov     r5, r1  /* save addr of gd */
        mov     r6, r2  /* save addr of destination */
 
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
        adr     r0, _start
        cmp     r0, r6
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
+       beq     relocate_done           /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
@@ -213,40 +204,10 @@ fixnext:
        blo     fixloop
 #endif
 
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-#endif
+relocate_done:
 
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
        mov     pc, lr
 
-_board_init_r_ofs:
-       .word board_init_r - _start
-
 _rel_dyn_start_ofs:
        .word __rel_dyn_start - _start
 _rel_dyn_end_ofs:
@@ -254,6 +215,11 @@ _rel_dyn_end_ofs:
 _dynsym_start_ofs:
        .word __dynsym_start - _start
 
+       .globl  c_runtime_cpu_setup
+c_runtime_cpu_setup:
+
+       mov     pc, lr
+
 /*
  *************************************************************************
  *
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
new file mode 100644 (file)
index 0000000..ed8c8dd
--- /dev/null
@@ -0,0 +1,154 @@
+/*
+ * SAMSUNG EXYNOS5250 SoC device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
+ * EXYNOS5250 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
+ * additional nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/include/ "skeleton.dtsi"
+
+/ {
+       compatible = "samsung,exynos5250";
+
+       sromc@12250000 {
+               compatible = "samsung,exynos-sromc";
+               reg = <0x12250000 0x20>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       i2c@12c60000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12C60000 0x100>;
+               interrupts = <0 56 0>;
+       };
+
+       i2c@12c70000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12C70000 0x100>;
+               interrupts = <0 57 0>;
+       };
+
+       i2c@12c80000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12C80000 0x100>;
+               interrupts = <0 58 0>;
+       };
+
+       i2c@12c90000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12C90000 0x100>;
+               interrupts = <0 59 0>;
+       };
+
+       i2c@12ca0000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12CA0000 0x100>;
+               interrupts = <0 60 0>;
+       };
+
+       i2c@12cb0000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12CB0000 0x100>;
+               interrupts = <0 61 0>;
+       };
+
+       i2c@12cc0000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12CC0000 0x100>;
+               interrupts = <0 62 0>;
+       };
+
+       i2c@12cd0000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,s3c2440-i2c";
+               reg = <0x12CD0000 0x100>;
+               interrupts = <0 63 0>;
+       };
+
+       sound@12d60000 {
+               compatible = "samsung,exynos-sound";
+               reg = <0x12d60000 0x20>;
+       };
+
+       spi@12d20000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos-spi";
+               reg = <0x12d20000 0x30>;
+               interrupts = <0 68 0>;
+       };
+
+       spi@12d30000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos-spi";
+               reg = <0x12d30000 0x30>;
+               interrupts = <0 69 0>;
+       };
+
+       spi@12d40000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos-spi";
+               reg = <0x12d40000 0x30>;
+               clock-frequency = <50000000>;
+               interrupts = <0 70 0>;
+        };
+
+       spi@131a0000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos-spi";
+               reg = <0x131a0000 0x30>;
+               interrupts = <0 129 0>;
+       };
+
+       spi@131b0000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "samsung,exynos-spi";
+               reg = <0x131b0000 0x30>;
+               interrupts = <0 130 0>;
+       };
+
+       ehci@12110000 {
+               compatible = "samsung,exynos-ehci";
+               reg = <0x12110000 0x100>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               phy {
+                       compatible = "samsung,exynos-usb-phy";
+                       reg = <0x12130000 0x100>;
+               };
+       };
+
+};
index 0e728c96dcffca718b7bca409de2fa0f1ea8ff2e..de0f1b1923e60258c528724789365fd5c174acda 100644 (file)
 #define ATMEL_PIO_PORTS         4
 #define CPU_HAS_PIO3
 #define PIO_SCDR_DIV            (0x3fff <<  0)  /* Slow Clock Divider Mask */
+#define ATMEL_PMC_UHP          AT91SAM926x_PMC_UHP
+#define ATMEL_ID_UHP           ATMEL_ID_UHPHS
 
 /*
  * at91sam9x5 specific prototypes
index cd12323509a844c26c5de4c539b46bc854856d91..1935b0b5b899d86f96c218c90a44526cc71fcfb1 100644 (file)
@@ -34,6 +34,7 @@ unsigned long get_arm_clk(void);
 unsigned long get_i2c_clk(void);
 unsigned long get_pwm_clk(void);
 unsigned long get_uart_clk(int dev_index);
+unsigned long get_mmc_clk(int dev_index);
 void set_mmc_clk(int dev_index, unsigned int div);
 unsigned long get_lcd_clk(void);
 void set_lcd_clk(void);
index ff6781aae45a41e616f81e5d5816f32a66e57ec2..9b56b4e51bf09d1b8c8783f8d4d201fc4650e682 100644 (file)
@@ -251,6 +251,282 @@ struct exynos4_clock {
        unsigned int    div_iem_l1;
 };
 
+struct exynos4x12_clock {
+       unsigned char   res1[0x4200];
+       unsigned int    src_leftbus;
+       unsigned char   res2[0x1fc];
+       unsigned int    mux_stat_leftbus;
+       unsigned char   res3[0xfc];
+       unsigned int    div_leftbus;
+       unsigned char   res4[0xfc];
+       unsigned int    div_stat_leftbus;
+       unsigned char   res5[0x1fc];
+       unsigned int    gate_ip_leftbus;
+       unsigned char   res6[0x12c];
+       unsigned int    gate_ip_image;
+       unsigned char   res7[0xcc];
+       unsigned int    clkout_leftbus;
+       unsigned int    clkout_leftbus_div_stat;
+       unsigned char   res8[0x37f8];
+       unsigned int    src_rightbus;
+       unsigned char   res9[0x1fc];
+       unsigned int    mux_stat_rightbus;
+       unsigned char   res10[0xfc];
+       unsigned int    div_rightbus;
+       unsigned char   res11[0xfc];
+       unsigned int    div_stat_rightbus;
+       unsigned char   res12[0x1fc];
+       unsigned int    gate_ip_rightbus;
+       unsigned char   res13[0x15c];
+       unsigned int    gate_ip_perir;
+       unsigned char   res14[0x9c];
+       unsigned int    clkout_rightbus;
+       unsigned int    clkout_rightbus_div_stat;
+       unsigned char   res15[0x3608];
+       unsigned int    epll_lock;
+       unsigned char   res16[0xc];
+       unsigned int    vpll_lock;
+       unsigned char   res17[0xec];
+       unsigned int    epll_con0;
+       unsigned int    epll_con1;
+       unsigned int    epll_con2;
+       unsigned char   res18[0x4];
+       unsigned int    vpll_con0;
+       unsigned int    vpll_con1;
+       unsigned int    vpll_con2;
+       unsigned char   res19[0xe4];
+       unsigned int    src_top0;
+       unsigned int    src_top1;
+       unsigned char   res20[0x8];
+       unsigned int    src_cam;
+       unsigned int    src_tv;
+       unsigned int    src_mfc;
+       unsigned int    src_g3d;
+       unsigned char   res21[0x4];
+       unsigned int    src_lcd;
+       unsigned int    src_isp;
+       unsigned int    src_maudio;
+       unsigned int    src_fsys;
+       unsigned char   res22[0xc];
+       unsigned int    src_peril0;
+       unsigned int    src_peril1;
+       unsigned int    src_cam1;
+       unsigned char   res23[0xb4];
+       unsigned int    src_mask_top;
+       unsigned char   res24[0xc];
+       unsigned int    src_mask_cam;
+       unsigned int    src_mask_tv;
+       unsigned char   res25[0xc];
+       unsigned int    src_mask_lcd;
+       unsigned int    src_mask_isp;
+       unsigned int    src_mask_maudio;
+       unsigned int    src_mask_fsys;
+       unsigned char   res26[0xc];
+       unsigned int    src_mask_peril0;
+       unsigned int    src_mask_peril1;
+       unsigned char   res27[0xb8];
+       unsigned int    mux_stat_top0;
+       unsigned int    mux_stat_top1;
+       unsigned char   res28[0x10];
+       unsigned int    mux_stat_mfc;
+       unsigned int    mux_stat_g3d;
+       unsigned char   res29[0x28];
+       unsigned int    mux_stat_cam1;
+       unsigned char   res30[0xb4];
+       unsigned int    div_top;
+       unsigned char   res31[0xc];
+       unsigned int    div_cam;
+       unsigned int    div_tv;
+       unsigned int    div_mfc;
+       unsigned int    div_g3d;
+       unsigned char   res32[0x4];
+       unsigned int    div_lcd;
+       unsigned int    div_isp;
+       unsigned int    div_maudio;
+       unsigned int    div_fsys0;
+       unsigned int    div_fsys1;
+       unsigned int    div_fsys2;
+       unsigned int    div_fsys3;
+       unsigned int    div_peril0;
+       unsigned int    div_peril1;
+       unsigned int    div_peril2;
+       unsigned int    div_peril3;
+       unsigned int    div_peril4;
+       unsigned int    div_peril5;
+       unsigned int    div_cam1;
+       unsigned char   res33[0x14];
+       unsigned int    div2_ratio;
+       unsigned char   res34[0x8c];
+       unsigned int    div_stat_top;
+       unsigned char   res35[0xc];
+       unsigned int    div_stat_cam;
+       unsigned int    div_stat_tv;
+       unsigned int    div_stat_mfc;
+       unsigned int    div_stat_g3d;
+       unsigned char   res36[0x4];
+       unsigned int    div_stat_lcd;
+       unsigned int    div_stat_isp;
+       unsigned int    div_stat_maudio;
+       unsigned int    div_stat_fsys0;
+       unsigned int    div_stat_fsys1;
+       unsigned int    div_stat_fsys2;
+       unsigned int    div_stat_fsys3;
+       unsigned int    div_stat_peril0;
+       unsigned int    div_stat_peril1;
+       unsigned int    div_stat_peril2;
+       unsigned int    div_stat_peril3;
+       unsigned int    div_stat_peril4;
+       unsigned int    div_stat_peril5;
+       unsigned int    div_stat_cam1;
+       unsigned char   res37[0x14];
+       unsigned int    div2_stat;
+       unsigned char   res38[0x29c];
+       unsigned int    gate_ip_cam;
+       unsigned int    gate_ip_tv;
+       unsigned int    gate_ip_mfc;
+       unsigned int    gate_ip_g3d;
+       unsigned char   res39[0x4];
+       unsigned int    gate_ip_lcd;
+       unsigned int    gate_ip_isp;
+       unsigned char   res40[0x4];
+       unsigned int    gate_ip_fsys;
+       unsigned char   res41[0x8];
+       unsigned int    gate_ip_gps;
+       unsigned int    gate_ip_peril;
+       unsigned char   res42[0xc];
+       unsigned char   res43[0x4];
+       unsigned char   res44[0xc];
+       unsigned int    gate_block;
+       unsigned char   res45[0x8c];
+       unsigned int    clkout_cmu_top;
+       unsigned int    clkout_cmu_top_div_stat;
+       unsigned char   res46[0x3600];
+       unsigned int    mpll_lock;
+       unsigned char   res47[0xfc];
+       unsigned int    mpll_con0;
+       unsigned int    mpll_con1;
+       unsigned char   res48[0xf0];
+       unsigned int    src_dmc;
+       unsigned char   res49[0xfc];
+       unsigned int    src_mask_dmc;
+       unsigned char   res50[0xfc];
+       unsigned int    mux_stat_dmc;
+       unsigned char   res51[0xfc];
+       unsigned int    div_dmc0;
+       unsigned int    div_dmc1;
+       unsigned char   res52[0xf8];
+       unsigned int    div_stat_dmc0;
+       unsigned int    div_stat_dmc1;
+       unsigned char   res53[0xf8];
+       unsigned int    gate_bus_dmc0;
+       unsigned int    gate_bus_dmc1;
+       unsigned char   res54[0x1f8];
+       unsigned int    gate_ip_dmc0;
+       unsigned int    gate_ip_dmc1;
+       unsigned char   res55[0xf8];
+       unsigned int    clkout_cmu_dmc;
+       unsigned int    clkout_cmu_dmc_div_stat;
+       unsigned char   res56[0x5f8];
+       unsigned int    dcgidx_map0;
+       unsigned int    dcgidx_map1;
+       unsigned int    dcgidx_map2;
+       unsigned char   res57[0x14];
+       unsigned int    dcgperf_map0;
+       unsigned int    dcgperf_map1;
+       unsigned char   res58[0x18];
+       unsigned int    dvcidx_map;
+       unsigned char   res59[0x1c];
+       unsigned int    freq_cpu;
+       unsigned int    freq_dpm;
+       unsigned char   res60[0x18];
+       unsigned int    dvsemclk_en;
+       unsigned int    maxperf;
+       unsigned char   res61[0x8];
+       unsigned int    dmc_freq_ctrl;
+       unsigned int    dmc_pause_ctrl;
+       unsigned int    dddrphy_lock_ctrl;
+       unsigned int    c2c_state;
+       unsigned char   res62[0x2f60];
+       unsigned int    apll_lock;
+       unsigned char   res63[0x8];
+       unsigned char   res64[0xf4];
+       unsigned int    apll_con0;
+       unsigned int    apll_con1;
+       unsigned char   res65[0xf8];
+       unsigned int    src_cpu;
+       unsigned char   res66[0x1fc];
+       unsigned int    mux_stat_cpu;
+       unsigned char   res67[0xfc];
+       unsigned int    div_cpu0;
+       unsigned int    div_cpu1;
+       unsigned char   res68[0xf8];
+       unsigned int    div_stat_cpu0;
+       unsigned int    div_stat_cpu1;
+       unsigned char   res69[0x2f8];
+       unsigned int    clk_gate_ip_cpu;
+       unsigned char   res70[0xfc];
+       unsigned int    clkout_cmu_cpu;
+       unsigned int    clkout_cmu_cpu_div_stat;
+       unsigned char   res71[0x5f8];
+       unsigned int    armclk_stopctrl;
+       unsigned int    atclk_stopctrl;
+       unsigned char   res72[0x10];
+       unsigned char   res73[0x8];
+       unsigned int    pwr_ctrl;
+       unsigned int    pwr_ctrl2;
+       unsigned char   res74[0xd8];
+       unsigned int    apll_con0_l8;
+       unsigned int    apll_con0_l7;
+       unsigned int    apll_con0_l6;
+       unsigned int    apll_con0_l5;
+       unsigned int    apll_con0_l4;
+       unsigned int    apll_con0_l3;
+       unsigned int    apll_con0_l2;
+       unsigned int    apll_con0_l1;
+       unsigned int    iem_control;
+       unsigned char   res75[0xdc];
+       unsigned int    apll_con1_l8;
+       unsigned int    apll_con1_l7;
+       unsigned int    apll_con1_l6;
+       unsigned int    apll_con1_l5;
+       unsigned int    apll_con1_l4;
+       unsigned int    apll_con1_l3;
+       unsigned int    apll_con1_l2;
+       unsigned int    apll_con1_l1;
+       unsigned char   res76[0xe0];
+       unsigned int    div_iem_l8;
+       unsigned int    div_iem_l7;
+       unsigned int    div_iem_l6;
+       unsigned int    div_iem_l5;
+       unsigned int    div_iem_l4;
+       unsigned int    div_iem_l3;
+       unsigned int    div_iem_l2;
+       unsigned int    div_iem_l1;
+       unsigned char   res77[0xe0];
+       unsigned int    l2_status;
+       unsigned char   res78[0xc];
+       unsigned int    cpu_status;
+       unsigned char   res79[0xc];
+       unsigned int    ptm_status;
+       unsigned char   res80[0x2edc];
+       unsigned int    div_isp0;
+       unsigned int    div_isp1;
+       unsigned char   res81[0xf8];
+       unsigned int    div_stat_isp0;
+       unsigned int    div_stat_isp1;
+       unsigned char   res82[0x3f8];
+       unsigned int    gate_ip_isp0;
+       unsigned int    gate_ip_isp1;
+       unsigned char   res83[0x1f8];
+       unsigned int    clkout_cmu_isp;
+       unsigned int    clkout_cmu_ispd_div_stat;
+       unsigned char   res84[0xf8];
+       unsigned int    cmu_isp_spar0;
+       unsigned int    cmu_isp_spar1;
+       unsigned int    cmu_isp_spar2;
+       unsigned int    cmu_isp_spar3;
+};
+
 struct exynos5_clock {
        unsigned int    apll_lock;
        unsigned char   res1[0xfc];
index f06af2eb8592597944aa3b7393396545b9c45541..eb3442235378fd7e8b29d2ef84bfee1c35871d56 100644 (file)
@@ -27,7 +27,7 @@
 #define EXYNOS_CPU_NAME                        "Exynos"
 #define EXYNOS4_ADDR_BASE              0x10000000
 
-/* EXYNOS4 */
+/* EXYNOS4 Common*/
 #define EXYNOS4_I2C_SPACING            0x10000
 
 #define EXYNOS4_GPIO_PART3_BASE                0x03860000
 #define EXYNOS4_DP_BASE                        DEVICE_NOT_AVAILABLE
 #define EXYNOS4_SPI_ISP_BASE           DEVICE_NOT_AVAILABLE
 
-/* EXYNOS5 */
+/* EXYNOS4X12 */
+#define EXYNOS4X12_GPIO_PART3_BASE     0x03860000
+#define EXYNOS4X12_PRO_ID              0x10000000
+#define EXYNOS4X12_SYSREG_BASE         0x10010000
+#define EXYNOS4X12_POWER_BASE          0x10020000
+#define EXYNOS4X12_SWRESET             0x10020400
+#define EXYNOS4X12_USBPHY_CONTROL      0x10020704
+#define EXYNOS4X12_CLOCK_BASE          0x10030000
+#define EXYNOS4X12_SYSTIMER_BASE       0x10050000
+#define EXYNOS4X12_WATCHDOG_BASE       0x10060000
+#define EXYNOS4X12_DMC0_BASE           0x10600000
+#define EXYNOS4X12_DMC1_BASE           0x10610000
+#define EXYNOS4X12_GPIO_PART4_BASE     0x106E0000
+#define EXYNOS4X12_GPIO_PART2_BASE     0x11000000
+#define EXYNOS4X12_GPIO_PART1_BASE     0x11400000
+#define EXYNOS4X12_FIMD_BASE           0x11C00000
+#define EXYNOS4X12_MIPI_DSIM_BASE      0x11C80000
+#define EXYNOS4X12_USBOTG_BASE         0x12480000
+#define EXYNOS4X12_MMC_BASE            0x12510000
+#define EXYNOS4X12_SROMC_BASE          0x12570000
+#define EXYNOS4X12_USB_HOST_EHCI_BASE  0x12580000
+#define EXYNOS4X12_USBPHY_BASE         0x125B0000
+#define EXYNOS4X12_UART_BASE           0x13800000
+#define EXYNOS4X12_I2C_BASE            0x13860000
+#define EXYNOS4X12_PWMTIMER_BASE       0x139D0000
+
+#define EXYNOS4X12_ADC_BASE            DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DP_BASE             DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_MODEM_BASE          DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASE            DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASE            DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASE                DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 Common*/
 #define EXYNOS5_I2C_SPACING            0x10000
 
 #define EXYNOS5_GPIO_PART4_BASE                0x03860000
@@ -154,17 +187,20 @@ static inline int proid_is_##type(void)                   \
 }
 
 IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 
 #define SAMSUNG_BASE(device, base)                             \
 static inline unsigned int samsung_get_base_##device(void)     \
 {                                                              \
-       if (cpu_is_exynos4())                                   \
+       if (cpu_is_exynos4()) {                                 \
+               if (proid_is_exynos4412())                      \
+                       return EXYNOS4X12_##base;               \
                return EXYNOS4_##base;                          \
-       else if (cpu_is_exynos5())                              \
+       } else if (cpu_is_exynos5()) {                          \
                return EXYNOS5_##base;                          \
-       else                                                    \
-               return 0;                                       \
+       }                                                       \
+       return 0;                                               \
 }
 
 SAMSUNG_BASE(adc, ADC_BASE)
index 35694980fad075504ca4c14ddf26260876578fae..102b709bd76315d779c5c337c84990e691888bac 100644 (file)
@@ -211,4 +211,6 @@ unsigned int exynos_init_dp(void)
 }
 #endif
 
+void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
+
 #endif /* _DP_INFO_H */
index 4db8fd640e0f78006d040f5abe53c1100585269f..cfe10246c53d6f0e1339de8fb1faf199e225d5b8 100644 (file)
@@ -79,6 +79,67 @@ struct exynos4_gpio_part3 {
        struct s5p_gpio_bank z;
 };
 
+struct exynos4x12_gpio_part1 {
+       struct s5p_gpio_bank a0;
+       struct s5p_gpio_bank a1;
+       struct s5p_gpio_bank b;
+       struct s5p_gpio_bank c0;
+       struct s5p_gpio_bank c1;
+       struct s5p_gpio_bank d0;
+       struct s5p_gpio_bank d1;
+       struct s5p_gpio_bank res1[0x5];
+       struct s5p_gpio_bank f0;
+       struct s5p_gpio_bank f1;
+       struct s5p_gpio_bank f2;
+       struct s5p_gpio_bank f3;
+       struct s5p_gpio_bank res2[0x2];
+       struct s5p_gpio_bank j0;
+       struct s5p_gpio_bank j1;
+};
+
+struct exynos4x12_gpio_part2 {
+       struct s5p_gpio_bank res1[0x2];
+       struct s5p_gpio_bank k0;
+       struct s5p_gpio_bank k1;
+       struct s5p_gpio_bank k2;
+       struct s5p_gpio_bank k3;
+       struct s5p_gpio_bank l0;
+       struct s5p_gpio_bank l1;
+       struct s5p_gpio_bank l2;
+       struct s5p_gpio_bank y0;
+       struct s5p_gpio_bank y1;
+       struct s5p_gpio_bank y2;
+       struct s5p_gpio_bank y3;
+       struct s5p_gpio_bank y4;
+       struct s5p_gpio_bank y5;
+       struct s5p_gpio_bank y6;
+       struct s5p_gpio_bank res2[0x3];
+       struct s5p_gpio_bank m0;
+       struct s5p_gpio_bank m1;
+       struct s5p_gpio_bank m2;
+       struct s5p_gpio_bank m3;
+       struct s5p_gpio_bank m4;
+       struct s5p_gpio_bank res3[0x48];
+       struct s5p_gpio_bank x0;
+       struct s5p_gpio_bank x1;
+       struct s5p_gpio_bank x2;
+       struct s5p_gpio_bank x3;
+};
+
+struct exynos4x12_gpio_part3 {
+       struct s5p_gpio_bank z;
+};
+
+struct exynos4x12_gpio_part4 {
+       struct s5p_gpio_bank v0;
+       struct s5p_gpio_bank v1;
+       struct s5p_gpio_bank res1[0x1];
+       struct s5p_gpio_bank v2;
+       struct s5p_gpio_bank v3;
+       struct s5p_gpio_bank res2[0x1];
+       struct s5p_gpio_bank v4;
+};
+
 struct exynos5_gpio_part1 {
        struct s5p_gpio_bank a0;
        struct s5p_gpio_bank a1;
@@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
            - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
          * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
 
+#define exynos4x12_gpio_part1_get_nr(bank, pin) \
+       ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
+                              EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
+           - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+         * GPIO_PER_BANK) + pin)
+
+#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
+                           / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part2_get_nr(bank, pin) \
+       (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
+                               EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
+           - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
+         * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
+
+#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
+                           / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part3_get_nr(bank, pin) \
+       (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
+                               EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
+           - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
+         * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
+
 #define exynos5_gpio_part1_get_nr(bank, pin) \
        ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
                               EXYNOS5_GPIO_PART1_BASE)->bank)) \
index 9a7cbeb599057b9285754489ac35d8c7ad472471..c1c9a3578ae40cfe62c9f1a180a4f5b561a20eab 100644 (file)
@@ -358,7 +358,14 @@ struct mipi_dsim_lcd_driver {
        void    (*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
 };
 
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
 int exynos_mipi_dsi_init(void);
+#else
+static inline int exynos_mipi_dsi_init(void)
+{
+       return 0;
+}
+#endif
 
 /*
  * register mipi_dsim_lcd_driver object defined by lcd panel driver
index 13abd2d703a58d7dacb42dd533aff3b4a6c0a8bf..89bcdfc0cc3ffec97abd7edbc9e3382d65503443 100644 (file)
 #define __ASM_ARM_ARCH_PERIPH_H
 
 /*
- * Peripherals requiring clock/pinmux configuration. List will
+ * Peripherals required for pinmux configuration. List will
  * grow with support for more devices getting added.
+ * Numbering based on interrupt table.
  *
  */
 enum periph_id {
-       PERIPH_ID_I2C0,
+       PERIPH_ID_UART0 = 51,
+       PERIPH_ID_UART1,
+       PERIPH_ID_UART2,
+       PERIPH_ID_UART3,
+       PERIPH_ID_I2C0 = 56,
        PERIPH_ID_I2C1,
        PERIPH_ID_I2C2,
        PERIPH_ID_I2C3,
@@ -38,22 +43,24 @@ enum periph_id {
        PERIPH_ID_I2C5,
        PERIPH_ID_I2C6,
        PERIPH_ID_I2C7,
-       PERIPH_ID_I2S1,
-       PERIPH_ID_SDMMC0,
+       PERIPH_ID_SPI0 = 68,
+       PERIPH_ID_SPI1,
+       PERIPH_ID_SPI2,
+       PERIPH_ID_SDMMC0 = 75,
        PERIPH_ID_SDMMC1,
        PERIPH_ID_SDMMC2,
        PERIPH_ID_SDMMC3,
-       PERIPH_ID_SDMMC4,
-       PERIPH_ID_SROMC,
-       PERIPH_ID_SPI0,
-       PERIPH_ID_SPI1,
-       PERIPH_ID_SPI2,
+       PERIPH_ID_I2S1 = 99,
+
+       /* Since following peripherals do
+        * not have shared peripheral interrupts (SPIs)
+        * they are numbered arbitiraly after the maximum
+        * SPIs Exynos has (128)
+        */
+       PERIPH_ID_SROMC = 128,
        PERIPH_ID_SPI3,
        PERIPH_ID_SPI4,
-       PERIPH_ID_UART0,
-       PERIPH_ID_UART1,
-       PERIPH_ID_UART2,
-       PERIPH_ID_UART3,
+       PERIPH_ID_SDMMC4,
 
        PERIPH_ID_COUNT,
        PERIPH_ID_NONE = -1,
index 10ea736c7dd3a2091515bd4a938195b5aaee7dd4..014eebc75d97919aa85b8eef593ceeb15a9e9e4f 100644 (file)
@@ -55,4 +55,12 @@ enum {
  */
 int exynos_pinmux_config(int peripheral, int flags);
 
+/**
+ * Decode the peripheral id using the interrpt numbers.
+ *
+ * @param blob  Device tree blob
+ * @param node  FDT I2C node to find
+ * @return peripheral id if ok, PERIPH_ID_NONE on error
+ */
+int pinmux_decode_periph_id(const void *blob, int node);
 #endif
index f616bcb37bc0c1782e10d7255ac577a9983d9a77..dc6aae2c50c413f10b43061c8ec3b8f08559c8b1 100644 (file)
@@ -48,4 +48,22 @@ struct s5p_sromc {
 /* Configure the Band Width and Bank Control Regs for required SROMC Bank */
 void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
 
+enum {
+       FDT_SROM_PMC,
+       FDT_SROM_TACP,
+       FDT_SROM_TAH,
+       FDT_SROM_TCOH,
+       FDT_SROM_TACC,
+       FDT_SROM_TCOS,
+       FDT_SROM_TACS,
+
+       FDT_SROM_TIMING_COUNT,
+};
+
+struct fdt_sromc {
+       u8 bank;        /* srom bank number */
+       u8 width;       /* bus width in bytes */
+       unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
+};
+
 #endif /* __ASM_ARCH_SROMC_H_ */
index 57bfe8e78b1081ed9e627335ad6e8619d9b93ebd..009a6bb8f3f2cd4af353ef56e2bf68938f9538ac 100644 (file)
@@ -33,7 +33,7 @@
                        | (attr << 8) | (kw_winctrl_calcsize(size) << 16))
 
 #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x)     \
-               ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
+               ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
 
 #define KW_REG_PCIE_DEVID              (KW_REG_PCIE_BASE + 0x00)
 #define KW_REG_PCIE_REVID              (KW_REG_PCIE_BASE + 0x08)
index 8ceea7bb886ee127a5d803586205e4d07be8fc18..48d1477fff77069215458a91b3d1d0eacee39815 100644 (file)
 
 #define MPP_MAX                        49
 
-void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save);
+void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save);
 
 #endif
index 2b9af938068ed1e30e264bf65510104859ff5d2f..41a26edfb54d597d905d591a565053f8b70b0966 100644 (file)
@@ -73,6 +73,7 @@ typedef       struct  global_data {
        unsigned long   reloc_off;
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
        unsigned long   tlb_addr;
+       unsigned long   tlb_size;
 #endif
        const void      *fdt_blob;      /* Our device tree, NULL if none */
        void            **jt;           /* jump table */
index 3422ac1c5fc3213d735ae9f69a9481c65dacb4e5..57111afd90c1427fd8a0b27b137c25857102ef1d 100644 (file)
@@ -36,18 +36,21 @@ GLSOBJS     += _umodsi3.o
 
 GLCOBJS        += div0.o
 
+SOBJS-y += crt0.o
+
 ifndef CONFIG_SPL_BUILD
 COBJS-y        += board.o
 COBJS-y        += bootm.o
 COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
-COBJS-y        += interrupts.o
-COBJS-y        += reset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
 SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
 else
 COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o
 endif
 
+COBJS-y        += interrupts.o
+COBJS-y        += reset.o
+
 COBJS-y        += cache.o
 COBJS-y        += cache-cp15.o
 
index e0cb6353a3feb95fc35734875d53e16b633c3cd7..cfe32cc926d502e470d23ec092f827e29c91cf0f 100644 (file)
@@ -40,6 +40,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <environment.h>
 #include <malloc.h>
 #include <stdio_dev.h>
 #include <version.h>
@@ -231,14 +232,22 @@ int __power_init_board(void)
 int power_init_board(void)
        __attribute__((weak, alias("__power_init_board")));
 
+       /* Record the board_init_f() bootstage (after arch_cpu_init()) */
+static int mark_bootstage(void)
+{
+       bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
+
+       return 0;
+}
+
 init_fnc_t *init_sequence[] = {
        arch_cpu_init,          /* basic arch cpu dependent setup */
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-       board_early_init_f,
-#endif
+       mark_bootstage,
 #ifdef CONFIG_OF_CONTROL
        fdtdec_check_fdt,
+#endif
+#if defined(CONFIG_BOARD_EARLY_INIT_F)
+       board_early_init_f,
 #endif
        timer_init,             /* initialize timer */
 #ifdef CONFIG_BOARD_POSTCLK_INIT
@@ -277,13 +286,6 @@ void board_init_f(ulong bootflag)
        void *new_fdt = NULL;
        size_t fdt_size = 0;
 
-       bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
-
-       /* Pointer is writable since we allocated a register for it */
-       gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
-       /* compiler optimization barrier needed for GCC >= 3.4 */
-       __asm__ __volatile__("": : :"memory");
-
        memset((void *)gd, 0, sizeof(gd_t));
 
        gd->mon_len = _bss_end_ofs;
@@ -353,13 +355,14 @@ void board_init_f(ulong bootflag)
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
        /* reserve TLB table */
-       addr -= (4096 * 4);
+       gd->tlb_size = 4096 * 4;
+       addr -= gd->tlb_size;
 
        /* round down to next 64 kB limit */
        addr &= ~(0x10000 - 1);
 
        gd->tlb_addr = addr;
-       debug("TLB table at: %08lx\n", addr);
+       debug("TLB table from %08lx to %08lx\n", addr, addr + gd->tlb_size);
 #endif
 
        /* round down to next 4 kB limit */
@@ -465,10 +468,6 @@ void board_init_f(ulong bootflag)
                gd->fdt_blob = new_fdt;
        }
        memcpy(id, (void *)gd, sizeof(gd_t));
-
-       relocate_code(addr_sp, id, addr);
-
-       /* NOTREACHED - relocate_code() does not return */
 }
 
 #if !defined(CONFIG_SYS_NO_FLASH)
@@ -476,7 +475,38 @@ static char *failed = "*** failed ***\n";
 #endif
 
 /*
- ************************************************************************
+ * Tell if it's OK to load the environment early in boot.
+ *
+ * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see
+ * if this is OK (defaulting to saying it's not OK).
+ *
+ * NOTE: Loading the environment early can be a bad idea if security is
+ *       important, since no verification is done on the environment.
+ *
+ * @return 0 if environment should not be loaded, !=0 if it is ok to load
+ */
+static int should_load_env(void)
+{
+#ifdef CONFIG_OF_CONTROL
+       return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 0);
+#elif defined CONFIG_DELAY_ENVIRONMENT
+       return 0;
+#else
+       return 1;
+#endif
+}
+
+#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) && defined(CONFIG_OF_CONTROL)
+static void display_fdt_model(const void *blob)
+{
+       const char *model;
+
+       model = (char *)fdt_getprop(blob, 0, "model", NULL);
+       printf("Model: %s\n", model ? model : "<unknown>");
+}
+#endif
+
+/************************************************************************
  *
  * This is the next part if the initialization sequence: we are now
  * running from RAM and have a "normal" C environment, i. e. global
@@ -493,8 +523,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
        ulong flash_size;
 #endif
 
-       gd = id;
-
        gd->flags |= GD_FLG_RELOC;      /* tell others: relocation done */
        bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
 
@@ -571,8 +599,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #endif
 
 #ifdef CONFIG_GENERIC_MMC
-       puts("MMC:   ");
-       mmc_initialize(gd->bd);
+       puts("MMC:   ");
+       mmc_initialize(gd->bd);
 #endif
 
 #ifdef CONFIG_HAS_DATAFLASH
@@ -581,7 +609,10 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #endif
 
        /* initialize environment */
-       env_relocate();
+       if (should_load_env())
+               env_relocate();
+       else
+               set_default_env(NULL);
 
 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
        arm_pci_init();
@@ -598,6 +629,15 @@ void board_init_r(gd_t *id, ulong dest_addr)
 
        console_init_r();       /* fully init console as a device */
 
+#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
+# ifdef CONFIG_OF_CONTROL
+       /* Put this here so it appears on the LCD, now it is ready */
+       display_fdt_model(gd->fdt_blob);
+# else
+       checkboard();
+# endif
+#endif
+
 #if defined(CONFIG_ARCH_MISC_INIT)
        /* miscellaneous arch dependent initialisations */
        arch_misc_init();
index 6edf815d4d7b85f9b6197260b9b870acb01b586f..1cab27c22629fe5bd034d8278efa8d09e36f7378 100644 (file)
@@ -153,8 +153,11 @@ static void cache_disable(uint32_t cache_bit)
                        return;
                /* if disabling data cache, disable mmu too */
                cache_bit |= CR_M;
-               flush_dcache_all();
        }
+       reg = get_cr();
+       cp_delay();
+       if (cache_bit == (CR_C | CR_M))
+               flush_dcache_all();
        set_cr(reg & ~cache_bit);
 }
 #endif
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
new file mode 100644 (file)
index 0000000..4f60958
--- /dev/null
@@ -0,0 +1,173 @@
+/*
+ *  crt0 - C-runtime startup Code for ARM U-Boot
+ *
+ *  Copyright (c) 2012  Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+
+/*
+ * This file handles the target-independent stages of the U-Boot
+ * start-up where a C runtime environment is needed. Its entry point
+ * is _main and is branched into from the target's start.S file.
+ *
+ * _main execution sequence is:
+ *
+ * 1. Set up initial environment for calling board_init_f().
+ *    This environment only provides a stack and a place to store
+ *    the GD ('global data') structure, both located in some readily
+ *    available RAM (SRAM, locked cache...). In this context, VARIABLE
+ *    global data, initialized or not (BSS), are UNAVAILABLE; only
+ *    CONSTANT initialized data are available.
+ *
+ * 2. Call board_init_f(). This function prepares the hardware for
+ *    execution from system RAM (DRAM, DDR...) As system RAM may not
+ *    be available yet, , board_init_f() must use the current GD to
+ *    store any data which must be passed on to later stages. These
+ *    data include the relocation destination, the future stack, and
+ *    the future GD location.
+ *
+ * (the following applies only to non-SPL builds)
+ *
+ * 3. Set up intermediate environment where the stack and GD are the
+ *    ones allocated by board_init_f() in system RAM, but BSS and
+ *    initialized non-const data are still not available.
+ *
+ * 4. Call relocate_code(). This function relocates U-Boot from its
+ *    current location into the relocation destination computed by
+ *    board_init_f().
+ *
+ * 5. Set up final environment for calling board_init_r(). This
+ *    environment has BSS (initialized to 0), initialized non-const
+ *    data (initialized to their intended value), and stack in system
+ *    RAM. GD has retained values set by board_init_f(). Some CPUs
+ *    have some work left to do at this point regarding memory, so
+ *    call c_runtime_cpu_setup.
+ *
+ * 6. Branch to either nand_boot() or board_init_r().
+ */
+
+/*
+ * declare nand_boot() or board_init_r() to jump to at end of crt0
+ */
+
+#if defined(CONFIG_NAND_SPL)
+
+.globl nand_boot
+
+#elif ! defined(CONFIG_SPL_BUILD)
+
+.globl board_init_r
+
+#endif
+
+/*
+ * start and end of BSS
+ */
+
+.globl __bss_start
+.globl __bss_end__
+
+/*
+ * entry point of crt0 sequence
+ */
+
+.global _main
+
+_main:
+
+/*
+ * Set up initial C runtime environment and call board_init_f(0).
+ */
+
+#if defined(CONFIG_NAND_SPL)
+       /* deprecated, use instead CONFIG_SPL_BUILD */
+       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+       ldr     sp, =(CONFIG_SPL_STACK)
+#else
+       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
+       bic     sp, sp, #7      /* 8-byte alignment for ABI compliance */
+       sub     sp, #GD_SIZE    /* allocate one GD above SP */
+       bic     sp, sp, #7      /* 8-byte alignment for ABI compliance */
+       mov     r8, sp          /* GD is above SP */
+       mov     r0, #0
+       bl      board_init_f
+
+#if ! defined(CONFIG_SPL_BUILD)
+
+/*
+ * Set up intermediate environment (new sp and gd) and call
+ * relocate_code(addr_sp, gd, addr_moni). Trick here is that
+ * we'll return 'here' but relocated.
+ */
+
+       ldr     sp, [r8, #GD_START_ADDR_SP]     /* r8 = gd->start_addr_sp */
+       bic     sp, sp, #7      /* 8-byte alignment for ABI compliance */
+       ldr     r8, [r8, #GD_BD]                /* r8 = gd->bd */
+       sub     r8, r8, #GD_SIZE                /* new GD is below bd */
+
+       adr     lr, here
+       ldr     r0, [r8, #GD_RELOC_OFF]         /* lr = gd->start_addr_sp */
+       add     lr, lr, r0
+       ldr     r0, [r8, #GD_START_ADDR_SP]     /* r0 = gd->start_addr_sp */
+       mov     r1, r8                          /* r1 = gd */
+       ldr     r2, [r8, #GD_RELOCADDR]         /* r2 = gd->relocaddr */
+       b       relocate_code
+here:
+
+/* Set up final (full) environment */
+
+       bl      c_runtime_cpu_setup     /* we still call old routine here */
+
+       ldr     r0, =__bss_start        /* this is auto-relocated! */
+       ldr     r1, =__bss_end__        /* this is auto-relocated! */
+
+       mov     r2, #0x00000000         /* prepare zero to clear BSS */
+
+clbss_l:cmp    r0, r1                  /* while not at end of BSS */
+       strlo   r2, [r0]                /* clear 32-bit BSS word */
+       addlo   r0, r0, #4              /* move to next */
+       blo     clbss_l
+
+       bl coloured_LED_init
+       bl red_led_on
+
+#if defined(CONFIG_NAND_SPL)
+
+       /* call _nand_boot() */
+       ldr     pc, =nand_boot
+
+#else
+
+       /* call board_init_r(gd_t *id, ulong dest_addr) */
+       mov     r0, r8                  /* gd_t */
+       ldr     r1, [r8, #GD_RELOCADDR] /* dest_addr */
+       /* call board_init_r */
+       ldr     pc, =board_init_r       /* this is auto-relocated! */
+
+#endif
+
+       /* we should not return here. */
+
+#endif
index 794b8679fefe2696bef4a8857f5b6d036b0c8882..e934cb6c25f5d49eebcb50b8535d1e74ae6f7e92 100644 (file)
@@ -402,14 +402,14 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
        gd->flags |= GD_FLG_RELOC;      /* tell others: relocation done */
 
-       serial_initialize();
-
        debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
 
        WATCHDOG_RESET ();
 
        gd->reloc_off =  dest_addr - CONFIG_SYS_MONITOR_BASE;
 
+       serial_initialize();
+
        monitor_flash_len = (ulong)&__init_end - dest_addr;
 
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
index f1f49fe7fae69c9655c946cb01e43df5ee37f703..af5c56f21e6dc71ef51cf7ce7d2a5f100d4de31d 100644 (file)
@@ -48,6 +48,8 @@
 # include <asm/cpu_sh7724.h>
 #elif defined (CONFIG_CPU_SH7734)
 # include <asm/cpu_sh7734.h>
+#elif defined (CONFIG_CPU_SH7752)
+# include <asm/cpu_sh7752.h>
 #elif defined (CONFIG_CPU_SH7757)
 # include <asm/cpu_sh7757.h>
 #elif defined (CONFIG_CPU_SH7763)
diff --git a/arch/sh/include/asm/cpu_sh7752.h b/arch/sh/include/asm/cpu_sh7752.h
new file mode 100644 (file)
index 0000000..f0ad0e8
--- /dev/null
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CPU_SH7752_H_
+#define _ASM_CPU_SH7752_H_
+
+#define CCR            0xFF00001C
+#define WTCNT          0xFFCC0000
+#define CCR_CACHE_INIT 0x0000090b
+#define CACHE_OC_NUM_WAYS      1
+
+#ifndef __ASSEMBLY__           /* put C only stuff in this section */
+/* MMU */
+struct mmu_regs {
+       unsigned int    reserved[4];
+       unsigned int    mmucr;
+};
+#define MMU_BASE       ((struct mmu_regs *)0xff000000)
+
+/* Watchdog */
+#define WTCSR0         0xffcc0002
+#define WRSTCSR_R      0xffcc0003
+#define WRSTCSR_W      0xffcc0002
+#define WTCSR_PREFIX           0xa500
+#define WRSTCSR_PREFIX         0x6900
+#define WRSTCSR_WOVF_PREFIX    0x9600
+
+/* SCIF */
+#define SCIF0_BASE     0xfe4b0000      /* The real name is SCIF2 */
+#define SCIF1_BASE     0xfe4c0000      /* The real name is SCIF3 */
+#define SCIF2_BASE     0xfe4d0000      /* The real name is SCIF4 */
+
+/* TMU0 */
+#define TMU_BASE        0xFE430000
+
+/* ETHER, GETHER MAC address */
+struct ether_mac_regs {
+       unsigned int    reserved[114];
+       unsigned int    mahr;
+       unsigned int    reserved2;
+       unsigned int    malr;
+};
+#define GETHER0_MAC_BASE       ((struct ether_mac_regs *)0xfee0400)
+#define GETHER1_MAC_BASE       ((struct ether_mac_regs *)0xfee0c00)
+#define ETHER0_MAC_BASE                ((struct ether_mac_regs *)0xfef0000)
+#define ETHER1_MAC_BASE                ((struct ether_mac_regs *)0xfef0800)
+
+/* GETHER */
+struct gether_control_regs {
+       unsigned int    gbecont;
+};
+#define GETHER_CONTROL_BASE    ((struct gether_control_regs *)0xffc10100)
+#define GBECONT_RMII1          0x00020000
+#define GBECONT_RMII0          0x00010000
+
+/* SerMux */
+struct sermux_regs {
+       unsigned char   smr0;
+       unsigned char   smr1;
+       unsigned char   smr2;
+       unsigned char   smr3;
+       unsigned char   smr4;
+       unsigned char   smr5;
+};
+#define SERMUX_BASE    ((struct sermux_regs *)0xfe470000)
+
+
+/* USB0/1 */
+struct usb_common_regs {
+       unsigned short  reserved[129];
+       unsigned short  suspmode;
+};
+#define USB0_COMMON_BASE       ((struct usb_common_regs *)0xfe450000)
+#define USB1_COMMON_BASE       ((struct usb_common_regs *)0xfe4f0000)
+
+struct usb0_phy_regs {
+       unsigned short  reset;
+       unsigned short  reserved[4];
+       unsigned short  portsel;
+};
+#define USB0_PHY_BASE          ((struct usb0_phy_regs *)0xfe5f0000)
+
+struct usb1_port_regs {
+       unsigned int    port1sel;
+       unsigned int    reserved;
+       unsigned int    usb1intsts;
+};
+#define USB1_PORT_BASE         ((struct usb1_port_regs *)0xfe4f2000)
+
+struct usb1_alignment_regs {
+       unsigned int    ehcidatac;      /* 0xfe4fe018 */
+       unsigned int    reserved[63];
+       unsigned int    ohcidatac;
+};
+#define USB1_ALIGNMENT_BASE    ((struct usb1_alignment_regs *)0xfe4fe018)
+
+/* GPIO */
+struct gpio_regs {
+       unsigned short  pacr;
+       unsigned short  pbcr;
+       unsigned short  pccr;
+       unsigned short  pdcr;
+       unsigned short  pecr;
+       unsigned short  pfcr;
+       unsigned short  pgcr;
+       unsigned short  phcr;
+       unsigned short  picr;
+       unsigned short  pjcr;
+       unsigned short  pkcr;
+       unsigned short  plcr;
+       unsigned short  pmcr;
+       unsigned short  pncr;
+       unsigned short  pocr;
+       unsigned short  reserved;
+       unsigned short  pqcr;
+       unsigned short  prcr;
+       unsigned short  pscr;
+       unsigned short  ptcr;
+       unsigned short  pucr;
+       unsigned short  pvcr;
+       unsigned short  pwcr;
+       unsigned short  pxcr;
+       unsigned short  pycr;
+       unsigned short  pzcr;
+       unsigned char   padr;
+       unsigned char   reserved_a;
+       unsigned char   pbdr;
+       unsigned char   reserved_b;
+       unsigned char   pcdr;
+       unsigned char   reserved_c;
+       unsigned char   pddr;
+       unsigned char   reserved_d;
+       unsigned char   pedr;
+       unsigned char   reserved_e;
+       unsigned char   pfdr;
+       unsigned char   reserved_f;
+       unsigned char   pgdr;
+       unsigned char   reserved_g;
+       unsigned char   phdr;
+       unsigned char   reserved_h;
+       unsigned char   pidr;
+       unsigned char   reserved_i;
+       unsigned char   pjdr;
+       unsigned char   reserved_j;
+       unsigned char   pkdr;
+       unsigned char   reserved_k;
+       unsigned char   pldr;
+       unsigned char   reserved_l;
+       unsigned char   pmdr;
+       unsigned char   reserved_m;
+       unsigned char   pndr;
+       unsigned char   reserved_n;
+       unsigned char   podr;
+       unsigned char   reserved_o;
+       unsigned char   ppdr;
+       unsigned char   reserved_p;
+       unsigned char   pqdr;
+       unsigned char   reserved_q;
+       unsigned char   prdr;
+       unsigned char   reserved_r;
+       unsigned char   psdr;
+       unsigned char   reserved_s;
+       unsigned char   ptdr;
+       unsigned char   reserved_t;
+       unsigned char   pudr;
+       unsigned char   reserved_u;
+       unsigned char   pvdr;
+       unsigned char   reserved_v;
+       unsigned char   pwdr;
+       unsigned char   reserved_w;
+       unsigned char   pxdr;
+       unsigned char   reserved_x;
+       unsigned char   pydr;
+       unsigned char   reserved_y;
+       unsigned char   pzdr;
+       unsigned char   reserved_z;
+       unsigned short  ncer;
+       unsigned short  ncmcr;
+       unsigned short  nccsr;
+       unsigned char   reserved2[2];
+       unsigned short  psel0;          /* +0x70 */
+       unsigned short  psel1;
+       unsigned short  psel2;
+       unsigned short  psel3;
+       unsigned short  psel4;
+       unsigned short  psel5;
+       unsigned short  psel6;
+       unsigned short  reserved3[2];
+       unsigned short  psel7;
+};
+#define GPIO_BASE      ((struct gpio_regs *)0xffec0000)
+
+#endif /* ifndef __ASSEMBLY__ */
+#endif /* _ASM_CPU_SH7752_H_ */
index 0e06c29153dfefc89059845c1c054656963a81bd..e524f3511d2691b0ccaef26840c85b7885e01005 100644 (file)
@@ -39,7 +39,7 @@ int board_early_init_f(void)
                        NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_SPI_SCn,
                MPP1_SPI_MOSI,
                MPP2_SPI_SCK,
index 101a80a70ab9a0eed2c792dc9c2121674b115a1b..0aa5345ddcc8040ecff6e0948e0a2b3c93dc89a6 100644 (file)
@@ -39,7 +39,7 @@ int board_early_init_f(void)
                        NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_SPI_SCn,
                MPP1_SPI_MOSI,
                MPP2_SPI_SCK,
diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile
new file mode 100644 (file)
index 0000000..b43c3d3
--- /dev/null
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := $(BOARD).o ../common/common.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg
new file mode 100644 (file)
index 0000000..0daf5b5
--- /dev/null
@@ -0,0 +1,82 @@
+#
+# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
+#
+# Based on netspace_v2 kwbimage.cfg:
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM      nand    # Boot from NAND flash
+NAND_PAGE_SIZE 800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Values taken from image original LaCie U-Boot header dump!
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30     # DDR Configuration register
+
+DATA 0xFFD01404 0x37743000     # DDR Controller Control Low
+
+DATA 0xFFD01408 0x11012228     # DDR Timing (Low) (active cycles value +1)
+
+DATA 0xFFD0140C 0x00000A19     #  DDR Timing (High)
+
+DATA 0xFFD01410 0x0000CCCC     #  DDR Address Control
+
+DATA 0xFFD01414 0x00000000     #  DDR Open Pages Control
+
+DATA 0xFFD01418 0x00000000     #  DDR Operation
+
+DATA 0xFFD0141C 0x00000662     #  DDR Mode
+
+DATA 0xFFD01420 0x00000004     #  DDR Extended Mode
+
+DATA 0xFFD01424 0x0000F07F     #  DDR Controller Control High
+
+DATA 0xFFD01428 0x00096630     # DDR2 ODT Read Timing (default values)
+
+DATA 0xFFD0147C 0x00009663     # DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01504 0x0FFFFFF1     # CS[0]n Size
+DATA 0xFFD01508 0x00000000     # CS[1]n Base address to 0x0
+DATA 0xFFD0150C 0x00000000     # CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000     # CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000     # CS[3]n Size, window disabled
+DATA 0xFFD01494 0x00120012     #  DDR ODT Control (Low)
+DATA 0xFFD01498 0x00000000     #  DDR ODT Control (High)
+DATA 0xFFD0149C 0x0000E40F     # CPU ODT Control
+DATA 0xFFD01480 0x00000001     # DDR Initialization Control
+DATA 0xFFD20134 0x66666666
+DATA 0xFFD20138 0x66666666
+DATA 0xFFD10000 0x01112222
+DATA 0xFFD1000C 0x00000000
+DATA 0xFFD10104 0x00000000
+DATA 0xFFD10100 0x40000000
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c
new file mode 100644 (file)
index 0000000..2080658
--- /dev/null
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+ *
+ * Based on Kirkwood support:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+#include "../common/common.h"
+#include "netdev.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPIO configuration: start FAN at low speed, USB and HDD */
+
+#define WIRELESS_SPACE_OE_LOW          0xFF006808
+#define WIRELESS_SPACE_OE_HIGH         0x0000F989
+#define WIRELESS_SPACE_OE_VAL_LOW      0x00010080
+#define WIRELESS_SPACE_OE_VAL_HIGH     0x00000240
+
+#define WIRELESS_SPACE_REAR_BUTTON     13
+#define WIRELESS_SPACE_FRONT_BUTTON    43
+
+const u32 kwmpp_config[] = {
+       MPP0_NF_IO2,
+       MPP1_NF_IO3,
+       MPP2_NF_IO4,
+       MPP3_NF_IO5,
+       MPP4_NF_IO6,
+       MPP5_NF_IO7,
+       MPP6_SYSRST_OUTn,
+       MPP7_GPO,               /* Fan speed (bit 1) */
+       MPP8_TW_SDA,
+       MPP9_TW_SCK,
+       MPP10_UART0_TXD,
+       MPP11_UART0_RXD,
+       MPP13_GPIO,             /* Red led */
+       MPP14_GPIO,             /* USB fuse */
+       MPP15_SATA0_ACTn,
+       MPP16_GPIO,             /* SATA 0 power */
+       MPP17_GPIO,             /* SATA 1 power */
+       MPP18_NF_IO0,
+       MPP19_NF_IO1,
+       MPP20_GE1_0,            /* Gigabit Ethernet 1 */
+       MPP21_GE1_1,
+       MPP22_GE1_2,
+       MPP23_GE1_3,
+       MPP24_GE1_4,
+       MPP25_GE1_5,
+       MPP26_GE1_6,
+       MPP27_GE1_7,
+       MPP28_GE1_8,
+       MPP29_GE1_9,
+       MPP30_GE1_10,
+       MPP31_GE1_11,
+       MPP32_GE1_12,
+       MPP33_GE1_13,
+       MPP34_GE1_14,
+       MPP35_GE1_15,
+       MPP36_GPIO,             /* Fan speed (bit 2) */
+       MPP37_GPIO,             /* Fan speed (bit 0) */
+       MPP38_GPIO,             /* Fan power */
+       MPP39_GPIO,             /* Fan rotation fail */
+       MPP40_GPIO,             /* Ethernet switch link */
+       MPP41_GPIO,             /* USB enable host vbus */
+       MPP42_GPIO,             /* LED clock control */
+       MPP43_GPIO,             /* WPS button (0=Pushed, 1=Released) */
+       MPP44_GPIO,             /* Red LED on/off */
+       MPP45_GPIO,             /* Red LED timer blink (on=off=100ms) */
+       MPP46_GPIO,             /* Green LED on/off */
+       MPP47_GPIO,             /* LED (blue, green) SATA activity blink */
+       MPP48_GPIO,             /* Blue LED on/off */
+       0
+};
+
+struct mv88e61xx_config swcfg = {
+       .name = "egiga0",
+       .vlancfg = MV88E61XX_VLANCFG_ROUTER,
+       .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
+       .led_init = MV88E61XX_LED_INIT_EN,
+       .mdip = MV88E61XX_MDIP_NOCHANGE,
+       .portstate = MV88E61XX_PORTSTT_FORWARDING,
+       .cpuport = 0x20,
+       .ports_enabled = 0x3F,
+};
+
+int board_early_init_f(void)
+{
+       /* Gpio configuration */
+       kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH,
+                       WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH);
+
+       /* Multi-Purpose Pins Functionality configuration */
+       kirkwood_mpp_conf(kwmpp_config, NULL);
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* Machine number */
+       gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+       /* Boot parameters address */
+       gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+       return 0;
+}
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
+       if (!getenv("ethaddr")) {
+               uchar mac[6];
+               if (lacie_read_mac_address(mac) == 0)
+                       eth_setenv_enetaddr("ethaddr", mac);
+       }
+#endif
+       return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and initialize PHY */
+void reset_phy(void)
+{
+       /* configure switch on egiga0 */
+       mv88e61xx_switch_initialize(&swcfg);
+}
+#endif
+
+#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD)
+/* Return GPIO button status */
+static int
+do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+       if (strcmp(argv[1], "button") == 0) {
+               if (strcmp(argv[2], "rear") == 0)
+                       /* invert GPIO result for intuitive while/until use */
+                       return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON);
+               else if (strcmp(argv[2], "front") == 0)
+                       return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON);
+               else
+                       return -1;
+       } else {
+               return -1;
+       }
+}
+
+U_BOOT_CMD(ws, 3, 0, do_ws,
+          "Return GPIO button status 0=off 1=on",
+          "- ws button rear|front: test buttons' states\n"
+);
+#endif
index d6497aaa07e6ff104dbaad34c85a6f5ae0171188..0caf34ff0a8f195f8a893ef93e07d566ccf97cf8 100644 (file)
@@ -46,7 +46,7 @@ int board_early_init_f(void)
                        DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_SPI_SCn,           /* SPI Flash */
                MPP1_SPI_MOSI,
                MPP2_SPI_SCK,
index f5c1c3cfd908318a4405c45cde90eeef3738a7c4..3a52ab2744472d365948b60d13ac0bb783f8b0f5 100644 (file)
@@ -43,7 +43,7 @@ int board_early_init_f(void)
                        GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_NF_IO2,
                MPP1_NF_IO3,
                MPP2_NF_IO4,
index 43852f6b24f1a04a5397c988f40578b30bf1f57b..fb57faa52bf3fe2e62c9d4d3fec85e331d422993 100644 (file)
@@ -45,7 +45,7 @@ int board_early_init_f(void)
                        MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_SPI_SCn,
                MPP1_SPI_MOSI,
                MPP2_SPI_SCK,
index d48f05a0488ade209a5df311b2175dfb2a3da7f0..c59a32611c6866999de713c46b20e45c1892ecb4 100644 (file)
@@ -48,7 +48,7 @@ int board_early_init_f(void)
                        OPENRD_OE_LOW, OPENRD_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_NF_IO2,
                MPP1_NF_IO3,
                MPP2_NF_IO4,
index 1fd7677dcb589cb26d60c11978b43936eb87b720..adaa6a1a696394a926133e056ab39eeb05f7d0d8 100644 (file)
@@ -44,7 +44,7 @@ int board_early_init_f(void)
                        RD6281A_OE_LOW, RD6281A_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_NF_IO2,
                MPP1_NF_IO3,
                MPP2_NF_IO4,
index 688d3086d4d3f3296b82e4e45a464788f2f92619..16efe645d1a69f7e938ddc6b8abde4fb99ccd747 100644 (file)
@@ -43,7 +43,7 @@ int board_early_init_f(void)
                        SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_NF_IO2,
                MPP1_NF_IO3,
                MPP2_NF_IO4,
index fc88520b2d15eea8d852a8db47392075c885d6f2..4f1f899b903e7607a92a9f018f6c25b491e0b2b8 100644 (file)
@@ -47,7 +47,7 @@ int board_early_init_f(void)
                        DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_NF_IO2,
                MPP1_NF_IO3,
                MPP2_NF_IO4,
index edb088680d000838288d84f9cff0bd48433cd9b8..8773e6fd3994c68e27aa968110ea363124fd9d2c 100644 (file)
@@ -295,6 +295,9 @@ int board_init(void)
        at91_macb_hw_init();
 #endif
 
+#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI)
+       at91_uhp_hw_init();
+#endif
 #ifdef CONFIG_LCD
        at91sam9x5ek_lcd_hw_init();
 #endif
index 57776fb077400599fbc30333c58baede3b30bb35..83eea04cbcb90dcccc72ab587026b98cf727b7f3 100644 (file)
@@ -49,9 +49,8 @@
  * you can do this only with a working network connection. Therefore, a random
  * ethernet address is generated if none is set and a DHCP request is sent.
  * After a successful DHCP response is received, the network settings are
- * configured and the ncip parameter is set to the serverip. Eg. for a working
- * resuce mode, you should set 'next-server' to the host where the netconsole
- * client is started.
+ * configured and the ncip is unset. Therefore, all netconsole packets are
+ * broadcasted.
  * Additionally, the bootsource is set to 'rescue'.
  */
 
@@ -76,7 +75,7 @@ int board_early_init_f(void)
         * Multi-Purpose Pins Functionality configuration
         * These strappings are taken from the original vendor uboot port.
         */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_SPI_SCn,
                MPP1_SPI_MOSI,
                MPP2_SPI_SCK,
index bac9ce55a88363352b1ed0dc088bd8f19deca8e3..3b1c8ec2adde3a3a45726ec7d8e326183fbbade3 100644 (file)
@@ -45,7 +45,7 @@ int board_early_init_f(void)
                        POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_NF_IO2,
                MPP1_NF_IO3,
                MPP2_NF_IO4,
index 6c2e95b1d4d5a7e1627d17208d449019f9a49ace..edbb941985c103e8d18ab2069471f7bd6ef95fa2 100644 (file)
@@ -32,6 +32,7 @@
 #include <netdev.h>
 #include <net.h>
 #include <i2c.h>
+#include <usb.h>
 #include <twl4030.h>
 #include <linux/compiler.h>
 
@@ -41,6 +42,8 @@
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-types.h>
+#include <asm/ehci-omap.h>
+#include <asm/gpio.h>
 
 #include "eeprom.h"
 
@@ -260,6 +263,36 @@ static void cm_t3x_set_common_muxconf(void)
        MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA6*/
        MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)); /*HSUSB0_DATA7*/
 
+       /* USB EHCI */
+       MUX_VAL(CP(ETK_D0_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT0*/
+       MUX_VAL(CP(ETK_D1_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT1*/
+       MUX_VAL(CP(ETK_D2_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT2*/
+       MUX_VAL(CP(ETK_D7_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT3*/
+       MUX_VAL(CP(ETK_D4_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT4*/
+       MUX_VAL(CP(ETK_D5_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT5*/
+       MUX_VAL(CP(ETK_D6_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT6*/
+       MUX_VAL(CP(ETK_D3_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DT7*/
+       MUX_VAL(CP(ETK_D8_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_DIR*/
+       MUX_VAL(CP(ETK_D9_ES2),         (IEN  | PTD | EN  | M3)); /*HSUSB1_NXT*/
+       MUX_VAL(CP(ETK_CTL_ES2),        (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
+       MUX_VAL(CP(ETK_CLK_ES2),        (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
+
+       MUX_VAL(CP(ETK_D14_ES2),        (IEN  | PTD | EN  | M3)); /*HSUSB2_DT0*/
+       MUX_VAL(CP(ETK_D15_ES2),        (IEN  | PTD | EN  | M3)); /*HSUSB2_DT1*/
+       MUX_VAL(CP(MCSPI1_CS3),         (IEN  | PTD | EN  | M3)); /*HSUSB2_DT2*/
+       MUX_VAL(CP(MCSPI2_CS1),         (IEN  | PTD | EN  | M3)); /*HSUSB2_DT3*/
+       MUX_VAL(CP(MCSPI2_SIMO),        (IEN  | PTD | EN  | M3)); /*HSUSB2_DT4*/
+       MUX_VAL(CP(MCSPI2_SOMI),        (IEN  | PTD | EN  | M3)); /*HSUSB2_DT5*/
+       MUX_VAL(CP(MCSPI2_CS0),         (IEN  | PTD | EN  | M3)); /*HSUSB2_DT6*/
+       MUX_VAL(CP(MCSPI2_CLK),         (IEN  | PTD | EN  | M3)); /*HSUSB2_DT7*/
+       MUX_VAL(CP(ETK_D12_ES2),        (IEN  | PTD | EN  | M3)); /*HSUSB2_DIR*/
+       MUX_VAL(CP(ETK_D13_ES2),        (IEN  | PTD | EN  | M3)); /*HSUSB2_NXT*/
+       MUX_VAL(CP(ETK_D10_ES2),        (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
+       MUX_VAL(CP(ETK_D11_ES2),        (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
+
+       /* SB_T35_USB_HUB_RESET_GPIO */
+       MUX_VAL(CP(CAM_WEN),            (IDIS | PTD | DIS | M4)); /*GPIO_167*/
+
        /* I2C1 */
        MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)); /*I2C1_SCL*/
        MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)); /*I2C1_SDA*/
@@ -461,3 +494,47 @@ void __weak get_board_serial(struct tag_serialnr *serialnr)
        serialnr->low = 0;
        serialnr->high = 0;
 };
+
+#ifdef CONFIG_USB_EHCI_OMAP
+struct omap_usbhs_board_data usbhs_bdata = {
+       .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+       .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+       .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+#define SB_T35_USB_HUB_RESET_GPIO      167
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+       u8 val;
+       int offset;
+
+       if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
+               printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
+                               SB_T35_USB_HUB_RESET_GPIO);
+               return -1;
+       }
+
+       gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
+       udelay(10);
+       gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
+       udelay(1000);
+
+       offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
+       twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, offset);
+       /* Set GPIO6 and GPIO7 of TPS65930 as output */
+       val |= 0xC0;
+       twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, val, offset);
+       offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
+       /* Take both PHYs out of reset */
+       twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, 0xC0, offset);
+       udelay(1);
+
+       return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+       return omap_ehci_hcd_stop();
+}
+
+#endif /* CONFIG_USB_EHCI_OMAP */
index 11260fe5f68ded64f248094fd69f4204ecf3d61c..41879017e82cdf10465d0f8fff24abced4705346 100644 (file)
@@ -44,7 +44,7 @@ int board_early_init_f(void)
                        DNS325_OE_LOW, DNS325_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_NF_IO2,
                MPP1_NF_IO3,
                MPP2_NF_IO4,
index 30763061c724bfa701add15fafee34419242b819..720b06e4ce8f91c4e820af304cdd1f04faecb384 100644 (file)
 #include <asm/arch/pxa.h>
 #include <asm/arch/pxa-regs.h>
 #include <asm/io.h>
+#include <usb.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+int board_eth_init(bd_t *bis)
+{
+       usb_eth_initialize(bis);
+       return 0;
+}
+
 int board_init(void)
 {
        /* We have RAM, disable cache */
@@ -36,6 +43,10 @@ int board_init(void)
        /* adress of boot parameters */
        gd->bd->bi_boot_params = 0xa0000100;
 
+       /* Let host see that device is disconnected */
+       udc_disconnect();
+       mdelay(500);
+
        return 0;
 }
 
index 8cfb4e6620dade4577bca5c1e02d3944d3d3fc65..c54c95d28886bb702afca0419e33d7932dc0af79 100644 (file)
@@ -41,7 +41,7 @@ int board_early_init_f(void)
                        ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_NF_IO2,
                MPP1_NF_IO3,
                MPP2_NF_IO4,
index 96410d77d60ae5c195752418f102ced0a5ec2f0f..7a4e7b3286a207aca0fa4339b6ea60a90a1c4461 100644 (file)
@@ -47,7 +47,7 @@ int board_early_init_f(void)
                        TK71_OE_LOW, TK71_OE_HIGH);
 
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_NF_IO2,
                MPP1_NF_IO3,
                MPP2_NF_IO4,
index a90f1124fbee8444c0380658f6f1b08e4070f320..6f407b78f259f35805f6a78f1159550530483561 100644 (file)
@@ -121,7 +121,7 @@ int i2c_make_abort(void)
 {
 
 #if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD)
-       immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
+       immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
        i2c8260_t *i2c  = (i2c8260_t *)&immap->im_i2c;
 
        /*
index 0c4dddc617328f7ba5a4999bd3828c2c1025129a..eda9199bbe9f499e9c49301709007fd68708cbc1 100644 (file)
@@ -54,7 +54,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define MASK_RBI_DEFECT_16     0x01
 
 /* Multi-Purpose Pins Functionality configuration */
-u32 kwmpp_config[] = {
+static const u32 kwmpp_config[] = {
        MPP0_NF_IO2,
        MPP1_NF_IO3,
        MPP2_NF_IO4,
@@ -193,15 +193,6 @@ void set_bootcount_addr(void)
 
 int misc_init_r(void)
 {
-       char *str;
-       int mach_type;
-
-       str = getenv("mach_type");
-       if (str != NULL) {
-               mach_type = simple_strtoul(str, NULL, 10);
-               printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
-               gd->bd->bi_arch_number = mach_type;
-       }
 #if defined(CONFIG_KM_MGCOGE3UN)
        char *wait_for_ne;
        wait_for_ne = getenv("waitforne");
@@ -258,11 +249,6 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-       /*
-        * arch number of board
-        */
-       gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD;
-
        /* address of boot parameters */
        gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
 
index 6df2ad79029d8971cb9babae28448809e20d8f02..5aa0de2528d152db61b843669c8a4232e71a30b2 100644 (file)
@@ -55,9 +55,9 @@ DATA 0xFFD10008 0x00001100    # MPP Control 2 Register
 DATA 0xFFD100E0 0x1B1B1B1B     # IO Configuration 0 Register
 DATA 0xFFD20134 0x66666666     # L2 RAM Timing 0 Register
 DATA 0xFFD20138 0x66666666     # L2 RAM Timing 1 Register
-DATA 0xFFD20154 0x00000200     # CPU RAM Management Control3 Register
-DATA 0xFFD2014C 0x00001C00     # CPU RAM Management Control1 Register
-DATA 0xFFD20148 0x00000001     # CPU RAM Management Control0 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 #Dram initalization
 DATA 0xFFD01400 0x430004E0     # SDRAM Configuration Register
index b2f51936f4debff917a3c2c4f843c6b4a0fbb00f..e5e9942c1aa11ae76d8915fb8e5ac8fc88244885 100644 (file)
@@ -52,9 +52,9 @@ DATA 0xFFD10008 0x00001100    # MPP Control 2 Register
 DATA 0xFFD100E0 0x1B1B1B1B     # IO Configuration 0 Register
 DATA 0xFFD20134 0x66666666     # L2 RAM Timing 0 Register
 DATA 0xFFD20138 0x66666666     # L2 RAM Timing 1 Register
-DATA 0xFFD20154 0x00000200     # CPU RAM Management Control3 Register
-DATA 0xFFD2014C 0x00001C00     # CPU RAM Management Control1 Register
-DATA 0xFFD20148 0x00000001     # CPU RAM Management Control0 Register
+
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 #Dram initalization
 DATA 0xFFD01400 0x43000400     # SDRAM Configuration Register
index bcce9073f6f8f8490287649ee1dd1dfda55d98a5..5de8df70fd6607403bd1c21512b9fe0815c98723 100644 (file)
@@ -98,29 +98,8 @@ DATA 0xFFD20138 0x66666666   # L2 RAM Timing 1 Register
 # bit 19-18: 1, ECC RAM WTC RAM0
 # bit 31-20: ???,Reserve
 
-DATA 0xFFD20154 0x00000200     # CPU RAM Management Control3 Register
-# bit 23-0:  0x000200, Addr Config tuning
-# bit 31-24: 0,        Reserved
-
-# ??? Missing register # CPU RAM Management Control2 Register
-
-DATA 0xFFD2014C 0x00001C00     # CPU RAM Management Control1 Register
-# bit 15-0:  0x1C00, Opmux Tuning
-# bit 31-16: 0,      Pc Dp Tuning
-
-DATA 0xFFD20148 0x00000001     # CPU RAM Management Control0 Register
-# bit 1-0:   1, addr clk tune
-# bit 3-2:   0, reserved
-# bit 5-4:   0, dtcmp clk tune
-# bit 7-6:   0, reserved
-# bit 9-8:   0, macdrv clk tune
-# bit 11-10: 0, opmuxgm2 clk tune
-# bit 15-14: 0, rf clk tune
-# bit 17-16: 0, rfbypass clk tune
-# bit 19-18: 0, pc dp clk tune
-# bit 23-20: 0, icache clk tune
-# bit 27:24: 0, dcache clk tune
-# bit 31:28: 0, regfile tunin
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 # SDRAM initalization
 DATA 0xFFD01400 0x430004E0     # SDRAM Configuration Register
index 3e1237bbe31b1d2f7f67cbf5ff2c4cbce7c56393..d0a09f61d2d963df49e911c9cd69fa38b951c1d3 100644 (file)
@@ -100,29 +100,8 @@ DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
 # bit 19-18: 1, ECC RAM WTC RAM0
 # bit 31-20: ?,Reserved
 
-DATA 0xFFD20154 0x00000200     # CPU RAM Management Control3 Register
-# bit 23-0:  0x000200, Addr Config tuning
-# bit 31-24: 0,        Reserved
-
-# ??? Missing register # CPU RAM Management Control2 Register
-
-DATA 0xFFD2014C 0x00001C00     # CPU RAM Management Control1 Register
-# bit 15-0:  0x1C00, Opmux Tuning
-# bit 31-16: 0,      Pc Dp Tuning
-
-DATA 0xFFD20148 0x00000001     # CPU RAM Management Control0 Register
-# bit 1-0:   1, addr clk tune
-# bit 3-2:   0, reserved
-# bit 5-4:   0, dtcmp clk tune
-# bit 7-6:   0, reserved
-# bit 9-8:   0, macdrv clk tune
-# bit 11-10: 0, opmuxgm2 clk tune
-# bit 15-14: 0, rf clk tune
-# bit 17-16: 0, rfbypass clk tune
-# bit 19-18: 0, pc dp clk tune
-# bit 23-20: 0, icache clk tune
-# bit 27:24: 0, dcache clk tune
-# bit 31:28: 0, regfile tunin
+# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
+# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
 
 # SDRAM initalization
 DATA 0xFFD01400 0x430004E0     # SDRAM Configuration Register
index 5f0f3961d319ad2ab037403e26b243f2debe43c3..cf4ca51fcb479405cff2996a7ab0b853498517d5 100644 (file)
@@ -45,7 +45,7 @@ int board_early_init_f(void)
        /* Set SATA activity LEDs to default off */
        writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
        /* Multi-Purpose Pins Functionality configuration */
-       u32 kwmpp_config[] = {
+       static const u32 kwmpp_config[] = {
                MPP0_NF_IO2,
                MPP1_NF_IO3,
                MPP2_NF_IO4,
diff --git a/board/renesas/sh7752evb/Makefile b/board/renesas/sh7752evb/Makefile
new file mode 100644 (file)
index 0000000..196c992
--- /dev/null
@@ -0,0 +1,36 @@
+#
+# Copyright (C) 2012  Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := sh7752evb.o spi-boot.o
+SOBJS  := lowlevel_init.o
+
+$(LIB):        $(obj).depend $(COBJS) $(SOBJS)
+       $(call cmd_link_o_target, $(COBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/renesas/sh7752evb/lowlevel_init.S b/board/renesas/sh7752evb/lowlevel_init.S
new file mode 100644 (file)
index 0000000..73c8ac4
--- /dev/null
@@ -0,0 +1,460 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+.macro or32, addr, data
+       mov.l \addr, r1
+       mov.l \data, r0
+       mov.l @r1, r2
+       or    r2, r0
+       mov.l r0, @r1
+.endm
+
+.macro wait_DBCMD
+       mov.l   DBWAIT_A, r0
+       mov.l   @r0, r1
+.endm
+
+       .global lowlevel_init
+       .section        .spiboot1.text
+       .align  2
+
+lowlevel_init:
+       /*------- GPIO -------*/
+       write16 PDCR_A, PDCR_D          ! SPI0
+       write16 PGCR_A, PGCR_D          ! SPI0, GETHER MDIO gate(PTG1)
+       write16 PJCR_A, PJCR_D          ! SCIF4
+       write16 PTCR_A, PTCR_D          ! STATUS
+       write16 PSEL1_A, PSEL1_D        ! SPI0
+       write16 PSEL2_A, PSEL2_D        ! SPI0
+       write16 PSEL5_A, PSEL5_D        ! STATUS
+
+       bra     exit_gpio
+       nop
+
+       .align  2
+
+/*------- GPIO -------*/
+PDCR_A:                .long   0xffec0006
+PGCR_A:                .long   0xffec000c
+PJCR_A:                .long   0xffec0012
+PTCR_A:                .long   0xffec0026
+PSEL1_A:       .long   0xffec0072
+PSEL2_A:       .long   0xffec0074
+PSEL5_A:       .long   0xffec007a
+
+PDCR_D:                .long   0x0000
+PGCR_D:                .long   0x0004
+PJCR_D:                .long   0x0000
+PTCR_D:                .long   0x0000
+PSEL1_D:       .long   0x0000
+PSEL2_D:       .long   0x3000
+PSEL5_D:       .long   0x0ffc
+
+       .align  2
+
+exit_gpio:
+       mov     #0, r14
+       mova    2f, r0
+       mov.l   PC_MASK, r1
+       tst     r0, r1
+       bf      2f
+
+       bra     exit_pmb
+       nop
+
+       .align  2
+
+/* If CPU runs on SDRAM (PC=0x5???????) or not. */
+PC_MASK:       .long   0x20000000
+
+2:
+       mov     #1, r14
+
+       mov.l   EXPEVT_A, r0
+       mov.l   @r0, r0
+       mov.l   EXPEVT_POWER_ON_RESET, r1
+       cmp/eq  r0, r1
+       bt      1f
+
+       /*
+        * If EXPEVT value is manual reset or tlb multipul-hit,
+        * initialization of DDR3IF is not necessary.
+        */
+       bra     exit_ddr
+       nop
+
+1:
+       /*------- Reset -------*/
+       write32 MRSTCR0_A, MRSTCR0_D
+       write32 MRSTCR1_A, MRSTCR1_D
+
+       /* For Core Reset */
+       mov.l   DBACEN_A, r0
+       mov.l   @r0, r0
+       cmp/eq  #0, r0
+       bt      3f
+
+       /*
+        * If DBACEN == 1(DBSC was already enabled), we have to avoid the
+        * initialization of DDR3-SDRAM.
+        */
+       bra     exit_ddr
+       nop
+
+3:
+       /*------- DDR3IF -------*/
+       /* oscillation stabilization time */
+       wait_timer      WAIT_OSC_TIME
+
+       /* step 3 */
+       write32 DBCMD_A, DBCMD_RSTL_VAL
+       wait_timer      WAIT_30US
+
+       /* step 4 */
+       write32 DBCMD_A, DBCMD_PDEN_VAL
+
+       /* step 5 */
+       write32 DBKIND_A, DBKIND_D
+
+       /* step 6 */
+       write32 DBCONF_A, DBCONF_D
+       write32 DBTR0_A, DBTR0_D
+       write32 DBTR1_A, DBTR1_D
+       write32 DBTR2_A, DBTR2_D
+       write32 DBTR3_A, DBTR3_D
+       write32 DBTR4_A, DBTR4_D
+       write32 DBTR5_A, DBTR5_D
+       write32 DBTR6_A, DBTR6_D
+       write32 DBTR7_A, DBTR7_D
+       write32 DBTR8_A, DBTR8_D
+       write32 DBTR9_A, DBTR9_D
+       write32 DBTR10_A, DBTR10_D
+       write32 DBTR11_A, DBTR11_D
+       write32 DBTR12_A, DBTR12_D
+       write32 DBTR13_A, DBTR13_D
+       write32 DBTR14_A, DBTR14_D
+       write32 DBTR15_A, DBTR15_D
+       write32 DBTR16_A, DBTR16_D
+       write32 DBTR17_A, DBTR17_D
+       write32 DBTR18_A, DBTR18_D
+       write32 DBTR19_A, DBTR19_D
+       write32 DBRNK0_A, DBRNK0_D
+
+       /* step 7 */
+       write32 DBPDCNT3_A, DBPDCNT3_D
+
+       /* step 8 */
+       write32 DBPDCNT1_A, DBPDCNT1_D
+       write32 DBPDCNT2_A, DBPDCNT2_D
+       write32 DBPDLCK_A, DBPDLCK_D
+       write32 DBPDRGA_A, DBPDRGA_D
+       write32 DBPDRGD_A, DBPDRGD_D
+
+       /* step 9 */
+       wait_timer      WAIT_30US
+
+       /* step 10 */
+       write32 DBPDCNT0_A, DBPDCNT0_D
+
+       /* step 11 */
+       wait_timer      WAIT_30US
+       wait_timer      WAIT_30US
+
+       /* step 12 */
+       write32 DBCMD_A, DBCMD_WAIT_VAL
+       wait_DBCMD
+
+       /* step 13 */
+       write32 DBCMD_A, DBCMD_RSTH_VAL
+       wait_DBCMD
+
+       /* step 14 */
+       write32 DBCMD_A, DBCMD_WAIT_VAL
+       write32 DBCMD_A, DBCMD_WAIT_VAL
+       write32 DBCMD_A, DBCMD_WAIT_VAL
+       write32 DBCMD_A, DBCMD_WAIT_VAL
+
+       /* step 15 */
+       write32 DBCMD_A, DBCMD_PDXT_VAL
+
+       /* step 16 */
+       write32 DBCMD_A, DBCMD_MRS2_VAL
+
+       /* step 17 */
+       write32 DBCMD_A, DBCMD_MRS3_VAL
+
+       /* step 18 */
+       write32 DBCMD_A, DBCMD_MRS1_VAL
+
+       /* step 19 */
+       write32 DBCMD_A, DBCMD_MRS0_VAL
+
+       /* step 20 */
+       write32 DBCMD_A, DBCMD_ZQCL_VAL
+
+       write32 DBCMD_A, DBCMD_REF_VAL
+       write32 DBCMD_A, DBCMD_REF_VAL
+       wait_DBCMD
+
+       /* step 21 */
+       write32 DBADJ0_A, DBADJ0_D
+       write32 DBADJ1_A, DBADJ1_D
+       write32 DBADJ2_A, DBADJ2_D
+
+       /* step 22 */
+       write32 DBRFCNF0_A, DBRFCNF0_D
+       write32 DBRFCNF1_A, DBRFCNF1_D
+       write32 DBRFCNF2_A, DBRFCNF2_D
+
+       /* step 23 */
+       write32 DBCALCNF_A, DBCALCNF_D
+
+       /* step 24 */
+       write32 DBRFEN_A, DBRFEN_D
+       write32 DBCMD_A, DBCMD_SRXT_VAL
+
+       /* step 25 */
+       write32 DBACEN_A, DBACEN_D
+
+       /* step 26 */
+       wait_DBCMD
+
+       bra     exit_ddr
+       nop
+
+       .align 2
+
+EXPEVT_A:              .long   0xff000024
+EXPEVT_POWER_ON_RESET: .long   0x00000000
+
+/*------- Reset -------*/
+MRSTCR0_A:     .long   0xffd50030
+MRSTCR0_D:     .long   0xfe1ffe7f
+MRSTCR1_A:     .long   0xffd50034
+MRSTCR1_D:     .long   0xfff3ffff
+
+/*------- DDR3IF -------*/
+DBCMD_A:       .long   0xfe800018
+DBKIND_A:      .long   0xfe800020
+DBCONF_A:      .long   0xfe800024
+DBTR0_A:       .long   0xfe800040
+DBTR1_A:       .long   0xfe800044
+DBTR2_A:       .long   0xfe800048
+DBTR3_A:       .long   0xfe800050
+DBTR4_A:       .long   0xfe800054
+DBTR5_A:       .long   0xfe800058
+DBTR6_A:       .long   0xfe80005c
+DBTR7_A:       .long   0xfe800060
+DBTR8_A:       .long   0xfe800064
+DBTR9_A:       .long   0xfe800068
+DBTR10_A:      .long   0xfe80006c
+DBTR11_A:      .long   0xfe800070
+DBTR12_A:      .long   0xfe800074
+DBTR13_A:      .long   0xfe800078
+DBTR14_A:      .long   0xfe80007c
+DBTR15_A:      .long   0xfe800080
+DBTR16_A:      .long   0xfe800084
+DBTR17_A:      .long   0xfe800088
+DBTR18_A:      .long   0xfe80008c
+DBTR19_A:      .long   0xfe800090
+DBRNK0_A:      .long   0xfe800100
+DBPDCNT0_A:    .long   0xfe800200
+DBPDCNT1_A:    .long   0xfe800204
+DBPDCNT2_A:    .long   0xfe800208
+DBPDCNT3_A:    .long   0xfe80020c
+DBPDLCK_A:     .long   0xfe800280
+DBPDRGA_A:     .long   0xfe800290
+DBPDRGD_A:     .long   0xfe8002a0
+DBADJ0_A:      .long   0xfe8000c0
+DBADJ1_A:      .long   0xfe8000c4
+DBADJ2_A:      .long   0xfe8000c8
+DBRFCNF0_A:    .long   0xfe8000e0
+DBRFCNF1_A:    .long   0xfe8000e4
+DBRFCNF2_A:    .long   0xfe8000e8
+DBCALCNF_A:    .long   0xfe8000f4
+DBRFEN_A:      .long   0xfe800014
+DBACEN_A:      .long   0xfe800010
+DBWAIT_A:      .long   0xfe80001c
+
+WAIT_OSC_TIME: .long   6000
+WAIT_30US:     .long   13333
+
+DBCMD_RSTL_VAL:        .long   0x20000000
+DBCMD_PDEN_VAL:        .long   0x1000d73c
+DBCMD_WAIT_VAL:        .long   0x0000d73c
+DBCMD_RSTH_VAL:        .long   0x2100d73c
+DBCMD_PDXT_VAL:        .long   0x110000c8
+DBCMD_MRS0_VAL:        .long   0x28000930
+DBCMD_MRS1_VAL:        .long   0x29000004
+DBCMD_MRS2_VAL:        .long   0x2a000008
+DBCMD_MRS3_VAL:        .long   0x2b000000
+DBCMD_ZQCL_VAL:        .long   0x03000200
+DBCMD_REF_VAL: .long   0x0c000000
+DBCMD_SRXT_VAL:        .long   0x19000000
+DBKIND_D:      .long   0x00000007
+DBCONF_D:      .long   0x0f030a01
+DBTR0_D:       .long   0x00000007
+DBTR1_D:       .long   0x00000006
+DBTR2_D:       .long   0x00000000
+DBTR3_D:       .long   0x00000007
+DBTR4_D:       .long   0x00070007
+DBTR5_D:       .long   0x0000001b
+DBTR6_D:       .long   0x00000014
+DBTR7_D:       .long   0x00000005
+DBTR8_D:       .long   0x00000015
+DBTR9_D:       .long   0x00000006
+DBTR10_D:      .long   0x00000008
+DBTR11_D:      .long   0x00000007
+DBTR12_D:      .long   0x0000000e
+DBTR13_D:      .long   0x00000056
+DBTR14_D:      .long   0x00000006
+DBTR15_D:      .long   0x00000004
+DBTR16_D:      .long   0x00150002
+DBTR17_D:      .long   0x000c0017
+DBTR18_D:      .long   0x00000200
+DBTR19_D:      .long   0x00000040
+DBRNK0_D:      .long   0x00000001
+DBPDCNT0_D:    .long   0x00000001
+DBPDCNT1_D:    .long   0x00000001
+DBPDCNT2_D:    .long   0x00000000
+DBPDCNT3_D:    .long   0x00004010
+DBPDLCK_D:     .long   0x0000a55a
+DBPDRGA_D:     .long   0x00000028
+DBPDRGD_D:     .long   0x00017100
+
+DBADJ0_D:      .long   0x00000000
+DBADJ1_D:      .long   0x00000000
+DBADJ2_D:      .long   0x18061806
+DBRFCNF0_D:    .long   0x000001ff
+DBRFCNF1_D:    .long   0x08001000
+DBRFCNF2_D:    .long   0x00000000
+DBCALCNF_D:    .long   0x0000ffff
+DBRFEN_D:      .long   0x00000001
+DBACEN_D:      .long   0x00000001
+
+       .align 2
+exit_ddr:
+#if defined(CONFIG_SH_32BIT)
+       /*------- set PMB -------*/
+       write32 PASCR_A,        PASCR_29BIT_D
+       write32 MMUCR_A,        MMUCR_D
+
+       /*****************************************************************
+        * ent  virt            phys            v       sz      c       wt
+        * 0    0xa0000000      0x00000000      1       128M    0       1
+        * 1    0xa8000000      0x48000000      1       128M    0       1
+        * 5    0x88000000      0x48000000      1       128M    1       1
+        */
+       write32 PMB_ADDR_SPIBOOT_A,     PMB_ADDR_SPIBOOT_D
+       write32 PMB_DATA_SPIBOOT_A,     PMB_DATA_SPIBOOT_D
+       write32 PMB_ADDR_DDR_C1_A,      PMB_ADDR_DDR_C1_D
+       write32 PMB_DATA_DDR_C1_A,      PMB_DATA_DDR_C1_D
+       write32 PMB_ADDR_DDR_N1_A,      PMB_ADDR_DDR_N1_D
+       write32 PMB_DATA_DDR_N1_A,      PMB_DATA_DDR_N1_D
+
+       write32 PMB_ADDR_ENTRY2,        PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY3,        PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY4,        PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY6,        PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY7,        PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY8,        PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY9,        PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY10,       PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY11,       PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY12,       PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY13,       PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY14,       PMB_ADDR_NOT_USE_D
+       write32 PMB_ADDR_ENTRY15,       PMB_ADDR_NOT_USE_D
+
+       write32 PASCR_A,        PASCR_INIT
+       mov.l   DUMMY_ADDR, r0
+       icbi    @r0
+#endif /* if defined(CONFIG_SH_32BIT) */
+
+exit_pmb:
+       /* CPU is running on ILRAM? */
+       mov     r14, r0
+       tst     #1, r0
+       bt      1f
+
+       mov.l   _stack_ilram, r15
+       mov.l   _spiboot_main, r0
+100:   bsrf    r0
+       nop
+
+       .align  2
+_spiboot_main: .long   (spiboot_main - (100b + 4))
+_stack_ilram:  .long   0xe5204000
+
+1:
+       write32 CCR_A,  CCR_D
+
+       rts
+        nop
+
+       .align 2
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_SPIBOOT_A:    .long   PMB_ADDR_BASE(0)
+PMB_ADDR_DDR_N1_A:     .long   PMB_ADDR_BASE(1)
+PMB_ADDR_DDR_C1_A:     .long   PMB_ADDR_BASE(5)
+PMB_ADDR_ENTRY2:       .long   PMB_ADDR_BASE(2)
+PMB_ADDR_ENTRY3:       .long   PMB_ADDR_BASE(3)
+PMB_ADDR_ENTRY4:       .long   PMB_ADDR_BASE(4)
+PMB_ADDR_ENTRY6:       .long   PMB_ADDR_BASE(6)
+PMB_ADDR_ENTRY7:       .long   PMB_ADDR_BASE(7)
+PMB_ADDR_ENTRY8:       .long   PMB_ADDR_BASE(8)
+PMB_ADDR_ENTRY9:       .long   PMB_ADDR_BASE(9)
+PMB_ADDR_ENTRY10:      .long   PMB_ADDR_BASE(10)
+PMB_ADDR_ENTRY11:      .long   PMB_ADDR_BASE(11)
+PMB_ADDR_ENTRY12:      .long   PMB_ADDR_BASE(12)
+PMB_ADDR_ENTRY13:      .long   PMB_ADDR_BASE(13)
+PMB_ADDR_ENTRY14:      .long   PMB_ADDR_BASE(14)
+PMB_ADDR_ENTRY15:      .long   PMB_ADDR_BASE(15)
+
+PMB_ADDR_SPIBOOT_D:    .long   mk_pmb_addr_val(0xa0)
+PMB_ADDR_DDR_C1_D:     .long   mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_N1_D:     .long   mk_pmb_addr_val(0xa8)
+PMB_ADDR_NOT_USE_D:    .long   0x00000000
+
+PMB_DATA_SPIBOOT_A:    .long   PMB_DATA_BASE(0)
+PMB_DATA_DDR_N1_A:     .long   PMB_DATA_BASE(1)
+PMB_DATA_DDR_C1_A:     .long   PMB_DATA_BASE(5)
+
+/*                                             ppn   ub v s1 s0  c  wt */
+PMB_DATA_SPIBOOT_D:    .long   mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_C1_D:     .long   mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D:     .long   mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+
+PASCR_A:               .long   0xff000070
+DUMMY_ADDR:            .long   0xa0000000
+PASCR_29BIT_D:         .long   0x00000000
+PASCR_INIT:            .long   0x80000080
+MMUCR_A:               .long   0xff000010
+MMUCR_D:               .long   0x00000004      /* clear ITLB */
+#endif /* CONFIG_SH_32BIT */
+
+CCR_A:         .long   CCR
+CCR_D:         .long   CCR_CACHE_INIT
diff --git a/board/renesas/sh7752evb/sh7752evb.c b/board/renesas/sh7752evb/sh7752evb.c
new file mode 100644 (file)
index 0000000..e996593
--- /dev/null
@@ -0,0 +1,330 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/mmc.h>
+#include <spi_flash.h>
+
+int checkboard(void)
+{
+       puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
+
+       return 0;
+}
+
+static void init_gpio(void)
+{
+       struct gpio_regs *gpio = GPIO_BASE;
+       struct sermux_regs *sermux = SERMUX_BASE;
+
+       /* GPIO */
+       writew(0x0000, &gpio->pacr);    /* GETHER */
+       writew(0x0001, &gpio->pbcr);    /* INTC */
+       writew(0x0000, &gpio->pccr);    /* PWMU, INTC */
+       writew(0xeaff, &gpio->pecr);    /* GPIO */
+       writew(0x0000, &gpio->pfcr);    /* WDT */
+       writew(0x0000, &gpio->phcr);    /* SPI1 */
+       writew(0x0000, &gpio->picr);    /* SDHI */
+       writew(0x0003, &gpio->pkcr);    /* SerMux */
+       writew(0x0000, &gpio->plcr);    /* SerMux */
+       writew(0x0000, &gpio->pmcr);    /* RIIC */
+       writew(0x0000, &gpio->pncr);    /* USB, SGPIO */
+       writew(0x0000, &gpio->pocr);    /* SGPIO */
+       writew(0xd555, &gpio->pqcr);    /* GPIO */
+       writew(0x0000, &gpio->prcr);    /* RIIC */
+       writew(0x0000, &gpio->pscr);    /* RIIC */
+       writeb(0x00, &gpio->pudr);
+       writew(0x5555, &gpio->pucr);    /* Debug LED */
+       writew(0x0000, &gpio->pvcr);    /* RSPI */
+       writew(0x0000, &gpio->pwcr);    /* EVC */
+       writew(0x0000, &gpio->pxcr);    /* LBSC */
+       writew(0x0000, &gpio->pycr);    /* LBSC */
+       writew(0x0000, &gpio->pzcr);    /* eMMC */
+       writew(0xfe00, &gpio->psel0);
+       writew(0xff00, &gpio->psel3);
+       writew(0x771f, &gpio->psel4);
+       writew(0x00ff, &gpio->psel6);
+       writew(0xfc00, &gpio->psel7);
+
+       writeb(0x10, &sermux->smr0);    /* SMR0: SerMux mode 0 */
+}
+
+static void init_usb_phy(void)
+{
+       struct usb_common_regs *common0 = USB0_COMMON_BASE;
+       struct usb_common_regs *common1 = USB1_COMMON_BASE;
+       struct usb0_phy_regs *phy = USB0_PHY_BASE;
+       struct usb1_port_regs *port = USB1_PORT_BASE;
+       struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
+
+       writew(0x0100, &phy->reset);            /* set reset */
+       /* port0 = USB0, port1 = USB1 */
+       writew(0x0002, &phy->portsel);
+       writel(0x0001, &port->port1sel);        /* port1 = Host */
+       writew(0x0111, &phy->reset);            /* clear reset */
+
+       writew(0x4000, &common0->suspmode);
+       writew(0x4000, &common1->suspmode);
+
+#if defined(__LITTLE_ENDIAN)
+       writel(0x00000000, &align->ehcidatac);
+       writel(0x00000000, &align->ohcidatac);
+#endif
+}
+
+static void init_gether_mdio(void)
+{
+       struct gpio_regs *gpio = GPIO_BASE;
+
+       writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
+       writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
+}
+
+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
+{
+       struct ether_mac_regs *ether;
+       unsigned char mac[6];
+       unsigned long val;
+
+       eth_parse_enetaddr(mac_string, mac);
+
+       if (!channel)
+               ether = GETHER0_MAC_BASE;
+       else
+               ether = GETHER1_MAC_BASE;
+
+       val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+       writel(val, &ether->mahr);
+       val = (mac[4] << 8) | mac[5];
+       writel(val, &ether->malr);
+}
+
+/*****************************************************************
+ * This PMB must be set on this timing. The lowlevel_init is run on
+ * Area 0(phys 0x00000000), so we have to map it.
+ *
+ * The new PMB table is following:
+ * ent virt            phys            v       sz      c       wt
+ * 0   0xa0000000      0x40000000      1       128M    0       1
+ * 1   0xa8000000      0x48000000      1       128M    0       1
+ * 2   0xb0000000      0x50000000      1       128M    0       1
+ * 3   0xb8000000      0x58000000      1       128M    0       1
+ * 4   0x80000000      0x40000000      1       128M    1       1
+ * 5   0x88000000      0x48000000      1       128M    1       1
+ * 6   0x90000000      0x50000000      1       128M    1       1
+ * 7   0x98000000      0x58000000      1       128M    1       1
+ */
+static void set_pmb_on_board_init(void)
+{
+       struct mmu_regs *mmu = MMU_BASE;
+
+       /* clear ITLB */
+       writel(0x00000004, &mmu->mmucr);
+
+       /* delete PMB for SPIBOOT */
+       writel(0, PMB_ADDR_BASE(0));
+       writel(0, PMB_DATA_BASE(0));
+
+       /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+       /*                      ppn  ub v s1 s0  c  wt */
+       writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
+       writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
+       writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
+       writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
+       writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
+       writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
+       writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
+       writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
+       writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
+       writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
+       writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
+       writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
+}
+
+int board_init(void)
+{
+       init_gpio();
+       set_pmb_on_board_init();
+
+       init_usb_phy();
+       init_gether_mdio();
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+
+       gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+       printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+
+       return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       struct gpio_regs *gpio = GPIO_BASE;
+
+       writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
+       writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
+       udelay(1);
+       writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
+       udelay(200);
+
+       return mmcif_mmc_init();
+}
+
+static int get_sh_eth_mac_raw(unsigned char *buf, int size)
+{
+       struct spi_flash *spi;
+       int ret;
+
+       spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+       if (spi == NULL) {
+               printf("%s: spi_flash probe failed.\n", __func__);
+               return 1;
+       }
+
+       ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
+       if (ret) {
+               printf("%s: spi_flash read failed.\n", __func__);
+               spi_flash_free(spi);
+               return 1;
+       }
+       spi_flash_free(spi);
+
+       return 0;
+}
+
+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
+{
+       memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
+               SH7752EVB_ETHERNET_MAC_SIZE);
+       mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
+
+       return 0;
+}
+
+static void init_ethernet_mac(void)
+{
+       char mac_string[64];
+       char env_string[64];
+       int i;
+       unsigned char *buf;
+
+       buf = malloc(256);
+       if (!buf) {
+               printf("%s: malloc failed.\n", __func__);
+               return;
+       }
+       get_sh_eth_mac_raw(buf, 256);
+
+       /* Gigabit Ethernet */
+       for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
+               get_sh_eth_mac(i, mac_string, buf);
+               if (i == 0)
+                       setenv("ethaddr", mac_string);
+               else {
+                       sprintf(env_string, "eth%daddr", i);
+                       setenv(env_string, mac_string);
+               }
+               set_mac_to_sh_giga_eth_register(i, mac_string);
+       }
+
+       free(buf);
+}
+
+int board_late_init(void)
+{
+       init_ethernet_mac();
+
+       return 0;
+}
+
+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+       int i, ret;
+       char mac_string[256];
+       struct spi_flash *spi;
+       unsigned char *buf;
+
+       if (argc != 3) {
+               buf = malloc(256);
+               if (!buf) {
+                       printf("%s: malloc failed.\n", __func__);
+                       return 1;
+               }
+
+               get_sh_eth_mac_raw(buf, 256);
+
+               /* print current MAC address */
+               for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
+                       get_sh_eth_mac(i, mac_string, buf);
+                       printf("GETHERC ch%d = %s\n", i, mac_string);
+               }
+               free(buf);
+               return 0;
+       }
+
+       /* new setting */
+       memset(mac_string, 0xff, sizeof(mac_string));
+       sprintf(mac_string, "%s\t%s",
+               argv[1], argv[2]);
+
+       /* write MAC data to SPI rom */
+       spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+       if (!spi) {
+               printf("%s: spi_flash probe failed.\n", __func__);
+               return 1;
+       }
+
+       ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
+                               SH7752EVB_SPI_SECTOR_SIZE);
+       if (ret) {
+               printf("%s: spi_flash erase failed.\n", __func__);
+               return 1;
+       }
+
+       ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
+                               sizeof(mac_string), mac_string);
+       if (ret) {
+               printf("%s: spi_flash write failed.\n", __func__);
+               spi_flash_free(spi);
+               return 1;
+       }
+       spi_flash_free(spi);
+
+       puts("The writing of the MAC address to SPI ROM was completed.\n");
+
+       return 0;
+}
+
+U_BOOT_CMD(
+       write_mac,      3,      1,      do_write_mac,
+       "write MAC address for GETHERC",
+       "[GETHERC ch0] [GETHERC ch1]\n"
+);
diff --git a/board/renesas/sh7752evb/spi-boot.c b/board/renesas/sh7752evb/spi-boot.c
new file mode 100644 (file)
index 0000000..91565d4
--- /dev/null
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License.  See the file "COPYING.LIB" in the main
+ * directory of this archive for more details.
+ */
+
+#include <common.h>
+
+#define CONFIG_RAM_BOOT_PHYS   CONFIG_SYS_TEXT_BASE
+#define CONFIG_SPI_ADDR                0x00000000
+#define CONFIG_SPI_LENGTH      CONFIG_SYS_MONITOR_LEN
+#define CONFIG_RAM_BOOT                CONFIG_SYS_TEXT_BASE
+
+#define SPIWDMADR      0xFE001018
+#define SPIWDMCNTR     0xFE001020
+#define SPIDMCOR       0xFE001028
+#define SPIDMINTSR     0xFE001188
+#define SPIDMINTMR     0xFE001190
+
+#define SPIDMINTSR_DMEND       0x00000004
+
+#define TBR    0xFE002000
+#define RBR    0xFE002000
+
+#define CR1    0xFE002008
+#define CR2    0xFE002010
+#define CR3    0xFE002018
+#define CR4    0xFE002020
+
+/* CR1 */
+#define SPI_TBE                0x80
+#define SPI_TBF                0x40
+#define SPI_RBE                0x20
+#define SPI_RBF                0x10
+#define SPI_PFONRD     0x08
+#define SPI_SSDB       0x04
+#define SPI_SSD                0x02
+#define SPI_SSA                0x01
+
+/* CR2 */
+#define SPI_RSTF       0x80
+#define SPI_LOOPBK     0x40
+#define SPI_CPOL       0x20
+#define SPI_CPHA       0x10
+#define SPI_L1M0       0x08
+
+/* CR4 */
+#define SPI_TBEI       0x80
+#define SPI_TBFI       0x40
+#define SPI_RBEI       0x20
+#define SPI_RBFI       0x10
+#define SPI_SpiS0      0x02
+#define SPI_SSS                0x01
+
+#define spi_write(val, addr)   (*(volatile unsigned long *)(addr)) = val
+#define spi_read(addr)         (*(volatile unsigned long *)(addr))
+
+/* M25P80 */
+#define M25_READ       0x03
+
+#define __uses_spiboot2        __attribute__((section(".spiboot2.text")))
+static void __uses_spiboot2 spi_reset(void)
+{
+       int timeout = 0x00100000;
+
+       /* Make sure the last transaction is finalized */
+       spi_write(0x00, CR3);
+       spi_write(0x02, CR1);
+       while (!(spi_read(CR4) & SPI_SpiS0)) {
+               if (timeout-- < 0)
+                       break;
+       }
+       spi_write(0x00, CR1);
+
+       spi_write(spi_read(CR2) | SPI_RSTF, CR2);       /* fifo reset */
+       spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
+
+       spi_write(0, SPIDMCOR);
+}
+
+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
+                                          unsigned long len)
+{
+       spi_write(M25_READ, TBR);
+       spi_write((addr >> 16) & 0xFF, TBR);
+       spi_write((addr >> 8) & 0xFF, TBR);
+       spi_write(addr & 0xFF, TBR);
+
+       spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
+       spi_write((unsigned long)buf, SPIWDMADR);
+       spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
+       spi_write(1, SPIDMCOR);
+
+       spi_write(0xff, CR3);
+       spi_write(spi_read(CR1) | SPI_SSDB, CR1);
+       spi_write(spi_read(CR1) | SPI_SSA, CR1);
+
+       while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
+               ;
+
+       /* Nagate SP0-SS0 */
+       spi_write(0, CR1);
+}
+
+void __uses_spiboot2 spiboot_main(void)
+{
+       void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
+
+       spi_reset();
+       spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
+                       CONFIG_SPI_LENGTH);
+
+       _start();
+}
diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds
new file mode 100644 (file)
index 0000000..28449b6
--- /dev/null
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * Copyright (C) 2012
+ * Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+       /*
+        * entry and reloct_dst will be provided via ldflags
+        */
+       . = .;
+
+       PROVIDE (_ftext = .);
+       PROVIDE (_fcode = .);
+       PROVIDE (_start = .);
+
+       .text :
+       {
+               KEEP(arch/sh/cpu/sh4/start.o            (.text))
+               *(.spiboot1.text)
+               *(.spiboot2.text)
+               . = ALIGN(8192);
+               common/env_embedded.o   (.ppcenv)
+               . = ALIGN(8192);
+               common/env_embedded.o   (.ppcenvr)
+               . = ALIGN(8192);
+               *(.text)
+               . = ALIGN(4);
+       } =0xFF
+       PROVIDE (_ecode = .);
+       .rodata :
+       {
+               *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+               . = ALIGN(4);
+       }
+       PROVIDE (_etext = .);
+
+
+       PROVIDE (_fdata = .);
+       .data :
+       {
+               *(.data)
+               . = ALIGN(4);
+       }
+       PROVIDE (_edata = .);
+
+       PROVIDE (_fgot = .);
+       .got :
+       {
+               *(.got)
+               . = ALIGN(4);
+       }
+       PROVIDE (_egot = .);
+
+       .u_boot_list : {
+               #include <u-boot.lst>
+       }
+
+       PROVIDE (reloc_dst_end = .);
+       /* _reloc_dst_end = .; */
+
+       PROVIDE (bss_start = .);
+       PROVIDE (__bss_start = .);
+       .bss (NOLOAD) :
+       {
+               *(.bss)
+               . = ALIGN(4);
+       }
+       PROVIDE (bss_end = .);
+
+       PROVIDE (__bss_end__ = .);
+}
diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts
new file mode 100644 (file)
index 0000000..cbfab6f
--- /dev/null
@@ -0,0 +1,69 @@
+/*
+ * SAMSUNG SMDK5250 board device tree source
+ *
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ *             http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+/include/ ARCH_CPU_DTS
+
+/ {
+       model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
+       compatible = "samsung,smdk5250", "samsung,exynos5250";
+
+       aliases {
+               i2c0 = "/i2c@12c60000";
+               i2c1 = "/i2c@12c70000";
+               i2c2 = "/i2c@12c80000";
+               i2c3 = "/i2c@12c90000";
+               i2c4 = "/i2c@12ca0000";
+               i2c5 = "/i2c@12cb0000";
+               i2c6 = "/i2c@12cc0000";
+               i2c7 = "/i2c@12cd0000";
+               spi0 = "/spi@12d20000";
+               spi1 = "/spi@12d30000";
+               spi2 = "/spi@12d40000";
+               spi3 = "/spi@131a0000";
+               spi4 = "/spi@131b0000";
+       };
+
+       sromc@12250000 {
+               bank = <1>;
+               srom-timing = <1 9 12 1 6 1 1>;
+               width = <2>;
+               lan@5000000 {
+                       compatible = "smsc,lan9215", "smsc,lan";
+                       reg = <0x5000000 0x100>;
+                       phy-mode = "mii";
+               };
+       };
+
+       sound@12d60000 {
+               samsung,i2s-epll-clock-frequency = <192000000>;
+               samsung,i2s-sampling-rate = <48000>;
+               samsung,i2s-bits-per-sample = <16>;
+               samsung,i2s-channels = <2>;
+               samsung,i2s-lr-clk-framesize = <256>;
+               samsung,i2s-bit-clk-framesize = <32>;
+               samsung,codec-type = "wm8994";
+       };
+
+       i2c@12c70000 {
+               soundcodec@1a {
+                       reg = <0x1a>;
+                       compatible = "wolfson,wm8994-codec";
+               };
+       };
+
+       i2c@12c60000 {
+               pmic@9 {
+                       reg = <0x9>;
+                       compatible = "maxim,max77686_pmic";
+               };
+       };
+};
index 9c926d6ecf2e9ae6f1db1bc390633b6cf3cb14d0..7a5f132ebb753a8519834b1e995f9810d414daf9 100644 (file)
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/io.h>
 #include <i2c.h>
+#include <lcd.h>
 #include <netdev.h>
 #include <spi.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
 #include <asm/arch/sromc.h>
+#include <asm/arch/dp_info.h>
 #include <power/pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_SMC911X
-static int smc9115_pre_init(void)
+#ifdef CONFIG_USB_EHCI_EXYNOS
+int board_usb_vbus_init(void)
 {
-       u32 smc_bw_conf, smc_bc_conf;
-       int err;
-
-       /* Ethernet needs data bus width of 16 bits */
-       smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
-                       | SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
+       struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
+                                               samsung_get_base_gpio_part1();
 
-       smc_bc_conf = SROMC_BC_TACS(0x01) | SROMC_BC_TCOS(0x01)
-                       | SROMC_BC_TACC(0x06) | SROMC_BC_TCOH(0x01)
-                       | SROMC_BC_TAH(0x0C)  | SROMC_BC_TACP(0x09)
-                       | SROMC_BC_PMC(0x01);
+       /* Enable VBUS power switch */
+       s5p_gpio_direction_output(&gpio1->x2, 6, 1);
 
-       /* Select and configure the SROMC bank */
-       err = exynos_pinmux_config(PERIPH_ID_SROMC,
-                               CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT);
-       if (err) {
-               debug("SROMC not configured\n");
-               return err;
-       }
+       /* VBUS turn ON time */
+       mdelay(3);
 
-       s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
        return 0;
 }
 #endif
@@ -67,6 +59,9 @@ int board_init(void)
        gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 #ifdef CONFIG_EXYNOS_SPI
        spi_init();
+#endif
+#ifdef CONFIG_USB_EHCI_EXYNOS
+       board_usb_vbus_init();
 #endif
        return 0;
 }
@@ -122,12 +117,94 @@ void dram_init_banksize(void)
                                                        PHYS_SDRAM_8_SIZE);
 }
 
+#ifdef CONFIG_OF_CONTROL
+static int decode_sromc(const void *blob, struct fdt_sromc *config)
+{
+       int err;
+       int node;
+
+       node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC);
+       if (node < 0) {
+               debug("Could not find SROMC node\n");
+               return node;
+       }
+
+       config->bank = fdtdec_get_int(blob, node, "bank", 0);
+       config->width = fdtdec_get_int(blob, node, "width", 2);
+
+       err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing,
+                       FDT_SROM_TIMING_COUNT);
+       if (err < 0) {
+               debug("Could not decode SROMC configuration\n");
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       return 0;
+}
+#endif
+
 int board_eth_init(bd_t *bis)
 {
 #ifdef CONFIG_SMC911X
-       if (smc9115_pre_init())
+       u32 smc_bw_conf, smc_bc_conf;
+       struct fdt_sromc config;
+       fdt_addr_t base_addr;
+       int node;
+
+#ifdef CONFIG_OF_CONTROL
+       node = decode_sromc(gd->fdt_blob, &config);
+       if (node < 0) {
+               debug("%s: Could not find sromc configuration\n", __func__);
+               return 0;
+       }
+       node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
+       if (node < 0) {
+               debug("%s: Could not find lan9215 configuration\n", __func__);
+               return 0;
+       }
+
+       /* We now have a node, so any problems from now on are errors */
+       base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
+       if (base_addr == FDT_ADDR_T_NONE) {
+               debug("%s: Could not find lan9215 address\n", __func__);
+               return -1;
+       }
+#else
+       /* Non-FDT configuration - bank number and timing parameters*/
+       config.bank = CONFIG_ENV_SROM_BANK;
+       config.width = 2;
+
+       config.timing[FDT_SROM_TACS] = 0x01;
+       config.timing[FDT_SROM_TCOS] = 0x01;
+       config.timing[FDT_SROM_TACC] = 0x06;
+       config.timing[FDT_SROM_TCOH] = 0x01;
+       config.timing[FDT_SROM_TAH] = 0x0C;
+       config.timing[FDT_SROM_TACP] = 0x09;
+       config.timing[FDT_SROM_PMC] = 0x01;
+       base_addr = CONFIG_SMC911X_BASE;
+#endif
+
+       /* Ethernet needs data bus width of 16 bits */
+       if (config.width != 2) {
+               debug("%s: Unsupported bus width %d\n", __func__,
+                       config.width);
                return -1;
-       return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+       }
+       smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
+                       | SROMC_BYTE_ENABLE(config.bank);
+
+       smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS])   |\
+                       SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
+                       SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
+                       SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
+                       SROMC_BC_TAH(config.timing[FDT_SROM_TAH])   |\
+                       SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
+                       SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
+
+       /* Select and configure the SROMC bank */
+       exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
+       s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
+       return smc911x_initialize(0, base_addr);
 #endif
        return 0;
 }
@@ -188,24 +265,6 @@ static int board_uart_init(void)
        return 0;
 }
 
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-static int board_i2c_init(void)
-{
-       int i, err;
-
-       for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
-               err = exynos_pinmux_config((PERIPH_ID_I2C0 + i),
-                                               PINMUX_FLAG_NONE);
-               if (err) {
-                       debug("I2C%d not configured\n", (PERIPH_ID_I2C0 + i));
-                       return err;
-               }
-       }
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-       return 0;
-}
-#endif
-
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
@@ -216,8 +275,104 @@ int board_early_init_f(void)
                return err;
        }
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
-       err = board_i2c_init();
+       board_i2c_init(gd->fdt_blob);
 #endif
        return err;
 }
 #endif
+
+#ifdef CONFIG_LCD
+void cfg_lcd_gpio(void)
+{
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+       /* For Backlight */
+       s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
+       s5p_gpio_set_value(&gpio1->b2, 0, 1);
+
+       /* LCD power on */
+       s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
+       s5p_gpio_set_value(&gpio1->x1, 5, 1);
+
+       /* Set Hotplug detect for DP */
+       s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
+}
+
+vidinfo_t panel_info = {
+       .vl_freq        = 60,
+       .vl_col         = 2560,
+       .vl_row         = 1600,
+       .vl_width       = 2560,
+       .vl_height      = 1600,
+       .vl_clkp        = CONFIG_SYS_LOW,
+       .vl_hsp         = CONFIG_SYS_LOW,
+       .vl_vsp         = CONFIG_SYS_LOW,
+       .vl_dp          = CONFIG_SYS_LOW,
+       .vl_bpix        = 4,    /* LCD_BPP = 2^4, for output conosle on LCD */
+
+       /* wDP panel timing infomation */
+       .vl_hspw        = 32,
+       .vl_hbpd        = 80,
+       .vl_hfpd        = 48,
+
+       .vl_vspw        = 6,
+       .vl_vbpd        = 37,
+       .vl_vfpd        = 3,
+       .vl_cmd_allow_len = 0xf,
+
+       .win_id         = 3,
+       .cfg_gpio       = cfg_lcd_gpio,
+       .backlight_on   = NULL,
+       .lcd_power_on   = NULL,
+       .reset_lcd      = NULL,
+       .dual_lcd_enabled = 0,
+
+       .init_delay     = 0,
+       .power_on_delay = 0,
+       .reset_delay    = 0,
+       .interface_mode = FIMD_RGB_INTERFACE,
+       .dp_enabled     = 1,
+};
+
+static struct edp_device_info edp_info = {
+       .disp_info = {
+               .h_res = 2560,
+               .h_sync_width = 32,
+               .h_back_porch = 80,
+               .h_front_porch = 48,
+               .v_res = 1600,
+               .v_sync_width  = 6,
+               .v_back_porch = 37,
+               .v_front_porch = 3,
+               .v_sync_rate = 60,
+       },
+       .lt_info = {
+               .lt_status = DP_LT_NONE,
+       },
+       .video_info = {
+               .master_mode = 0,
+               .bist_mode = DP_DISABLE,
+               .bist_pattern = NO_PATTERN,
+               .h_sync_polarity = 0,
+               .v_sync_polarity = 0,
+               .interlaced = 0,
+               .color_space = COLOR_RGB,
+               .dynamic_range = VESA,
+               .ycbcr_coeff = COLOR_YCBCR601,
+               .color_depth = COLOR_8,
+       },
+};
+
+static struct exynos_dp_platform_data dp_platform_data = {
+       .phy_enable     = set_dp_phy_ctrl,
+       .edp_dev_info   = &edp_info,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+       vid->rgb_mode   = MODE_RGB_P,
+
+       exynos_set_dp_platform_data(&dp_platform_data);
+}
+#endif
index 472402942442da0c16e2d530e33c89e36fed7927..88d193de280437a0f566a2e27be21e3a7c930109 100644 (file)
@@ -67,7 +67,7 @@ struct s3c_plat_otg_data s5pc210_otg_data;
 
 int board_init(void)
 {
-       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+       gd->bd->bi_boot_params = CONFIG_SYS_SPL_ARGS_ADDR;
 
        check_hw_revision();
        printf("HW Revision:\t0x%x\n", board_rev);
index 388e4a4461d2bb6b8403ae7d8730e743197c4bf7..e4b0d44fa7825d9b4ffd2dd863d451dec5385b9d 100644 (file)
@@ -99,6 +99,7 @@ at91sam9m10g45ek_nandflash   arm         arm926ejs   at91sam9m10g45ek    atmel
 at91sam9rlek_dataflash       arm         arm926ejs   at91sam9rlek        atmel          at91        at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH
 at91sam9rlek_nandflash       arm         arm926ejs   at91sam9rlek        atmel          at91        at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
 at91sam9x5ek_nandflash       arm         arm926ejs   at91sam9x5ek        atmel          at91        at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH
+at91sam9x5ek_dataflash       arm         arm926ejs   at91sam9x5ek        atmel          at91        at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH
 at91sam9x5ek_spiflash        arm         arm926ejs   at91sam9x5ek        atmel          at91        at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH
 at91sam9x5ek_mmc             arm         arm926ejs   at91sam9x5ek        atmel          at91        at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC
 at91sam9xeek_dataflash_cs0   arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0
@@ -171,6 +172,7 @@ netspace_lite_v2             arm         arm926ejs   netspace_v2         LaCie
 netspace_max_v2              arm         arm926ejs   netspace_v2         LaCie          kirkwood       lacie_kw:NETSPACE_MAX_V2
 netspace_mini_v2             arm         arm926ejs   netspace_v2         LaCie          kirkwood       lacie_kw:NETSPACE_MINI_V2
 netspace_v2                  arm         arm926ejs   netspace_v2         LaCie          kirkwood       lacie_kw:NETSPACE_V2
+wireless_space               arm         arm926ejs   wireless_space      LaCie          kirkwood
 dreamplug                    arm         arm926ejs   -                   Marvell        kirkwood
 guruplug                     arm         arm926ejs   -                   Marvell        kirkwood
 mv88f6281gtw_ge              arm         arm926ejs   -                   Marvell        kirkwood
@@ -375,8 +377,8 @@ M5235EVB                     m68k        mcf523x     m5235evb            freesca
 M5235EVB_Flash32             m68k        mcf523x     m5235evb            freescale      -           M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000
 cobra5272                    m68k        mcf52x2     cobra5272           -
 idmr                         m68k        mcf52x2
-eb_cpu5282                   m68k        mcf52x2     eb_cpu5282          BuS            -           eb_cpu5282:SYS_TEXT_BASE=0xFF000000
-eb_cpu5282_internal          m68k        mcf52x2     eb_cpu5282          BuS            -           eb_cpu5282:SYS_TEXT_BASE=0xF0000000
+eb_cpu5282                   m68k        mcf52x2     eb_cpu5282          BuS            -           eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400
+eb_cpu5282_internal          m68k        mcf52x2     eb_cpu5282          BuS            -           eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418
 TASREG                       m68k        mcf52x2     tasreg              esd
 M5208EVBE                    m68k        mcf52x2     m5208evbe           freescale
 M5249EVB                     m68k        mcf52x2     m5249evb            freescale
@@ -1091,6 +1093,7 @@ ecovec                       sh          sh4         ecovec              renesas
 MigoR                        sh          sh4         MigoR               renesas        -
 r2dplus                      sh          sh4         r2dplus             renesas        -
 r7780mp                      sh          sh4         r7780mp             renesas        -
+sh7752evb                    sh          sh4         sh7752evb           renesas        -
 sh7757lcr                    sh          sh4         sh7757lcr           renesas        -
 sh7763rdp                    sh          sh4         sh7763rdp           renesas        -
 sh7785lcr                    sh          sh4         sh7785lcr           renesas        -
index f7595c0311955b58acffa6efd2b19a209576ec48..1b8a8c15610f68954643f967081d61ca8eee0e74 100644 (file)
@@ -592,12 +592,18 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_NEEDS_MANUAL_RELOC
        static int relocated = 0;
 
-       /* relocate boot function table */
        if (!relocated) {
                int i;
+
+               /* relocate boot function table */
                for (i = 0; i < ARRAY_SIZE(boot_os); i++)
                        if (boot_os[i] != NULL)
                                boot_os[i] += gd->reloc_off;
+
+               /* relocate names of sub-command table */
+               for (i = 0; i < ARRAY_SIZE(cmd_bootm_sub); i++)
+                       cmd_bootm_sub[i].name += gd->reloc_off;
+
                relocated = 1;
        }
 #endif
index 4d64cfffde8040bb397f373d52b63fb927f27cee..0f3ffc84ff568f5f8f01c94fd75f316d4d5cc6ad 100644 (file)
@@ -33,6 +33,9 @@
 #include <dataflash.h>
 #endif
 #include <watchdog.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 static int mod_mem(cmd_tbl_t *, int, int, int, char * const []);
 
@@ -1203,6 +1206,22 @@ U_BOOT_CMD(
 
 #endif
 
+#ifdef CONFIG_CMD_MEMINFO
+__weak void board_show_dram(ulong size)
+{
+       puts("DRAM:  ");
+       print_size(size, "\n");
+}
+
+static int do_mem_info(cmd_tbl_t *cmdtp, int flag, int argc,
+                      char * const argv[])
+{
+       board_show_dram(gd->ram_size);
+
+       return 0;
+}
+#endif
+
 U_BOOT_CMD(
        base,   2,      1,      do_mem_base,
        "print or set address offset",
@@ -1243,3 +1262,11 @@ U_BOOT_CMD(
        "[.b, .w, .l] address value delay(ms)"
 );
 #endif /* CONFIG_MX_CYCLIC */
+
+#ifdef CONFIG_CMD_MEMINFO
+U_BOOT_CMD(
+       meminfo,        3,      1,      do_mem_info,
+       "display memory information",
+       ""
+);
+#endif
index 7b140deea398b32e3a0be83b2349580be0ee8dcb..5a042951da568b49f45d56f7840eedc190e72402 100644 (file)
@@ -57,12 +57,22 @@ static int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        int w;
 
        /* Validate arguments */
-       if ((argc != 5) || (strlen(argv[3]) != 1))
+       if (argc != 5 && argc != 3)
+               return CMD_RET_USAGE;
+       if (argc == 5 && strlen(argv[3]) != 1)
                return CMD_RET_USAGE;
 
        w = cmd_get_data_size(argv[0], 4);
 
        a = get_arg(argv[2], w);
+
+       if (argc == 3) {
+               sprintf(buf, "%lx", a);
+               setenv(argv[1], buf);
+
+               return 0;
+       }
+
        b = get_arg(argv[4], w);
 
        switch (argv[3][0]) {
@@ -87,8 +97,11 @@ static int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 U_BOOT_CMD(
        setexpr, 5, 0, do_setexpr,
        "set environment variable as the result of eval expression",
-       "[.b, .w, .l] name value1 <op> value2\n"
+       "[.b, .w, .l] name [*]value1 <op> [*]value2\n"
        "    - set environment variable 'name' to the result of the evaluated\n"
        "      express specified by <op>.  <op> can be &, |, ^, +, -, *, /, %\n"
-       "      size argument is only meaningful if value1 and/or value2 are memory addresses"
+       "      size argument is only meaningful if value1 and/or value2 are\n"
+       "      memory addresses (*)\n"
+       "setexpr[.b, .w, .l] name *value\n"
+       "    - load a memory address into a variable"
 );
index 5ac1d0c4c1ef4ef9cc34b30b3e056b2a76744beb..b1753587d3c92f1273e66acab040bad9efca5761 100644 (file)
@@ -5,6 +5,7 @@
  * Licensed under the GPL-2 or later.
  */
 
+#include <div64.h>
 #include <common.h>
 #include <malloc.h>
 #include <spi_flash.h>
@@ -67,6 +68,23 @@ static int sf_parse_len_arg(char *arg, ulong *len)
        return 1;
 }
 
+/**
+ * This function takes a byte length and a delta unit of time to compute the
+ * approximate bytes per second
+ *
+ * @param len          amount of bytes currently processed
+ * @param start_ms     start time of processing in ms
+ * @return bytes per second if OK, 0 on error
+ */
+static ulong bytes_per_second(unsigned int len, ulong start_ms)
+{
+       /* less accurate but avoids overflow */
+       if (len >= ((unsigned int) -1) / 1024)
+               return len / (max(get_timer(start_ms) / 1024, 1));
+       else
+               return 1024 * len / max(get_timer(start_ms), 1);
+}
+
 static int do_spi_flash_probe(int argc, char * const argv[])
 {
        unsigned int bus = CONFIG_SF_DEFAULT_BUS;
@@ -167,11 +185,26 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,
        const char *end = buf + len;
        size_t todo;            /* number of bytes to do in this pass */
        size_t skipped = 0;     /* statistics */
+       const ulong start_time = get_timer(0);
+       size_t scale = 1;
+       const char *start_buf = buf;
+       ulong delta;
 
+       if (end - buf >= 200)
+               scale = (end - buf) / 100;
        cmp_buf = malloc(flash->sector_size);
        if (cmp_buf) {
+               ulong last_update = get_timer(0);
+
                for (; buf < end && !err_oper; buf += todo, offset += todo) {
                        todo = min(end - buf, flash->sector_size);
+                       if (get_timer(last_update) > 100) {
+                               printf("   \rUpdating, %zu%% %lu B/s",
+                                       100 - (end - buf) / scale,
+                                       bytes_per_second(buf - start_buf,
+                                                        start_time));
+                               last_update = get_timer(0);
+                       }
                        err_oper = spi_flash_update_block(flash, offset, todo,
                                        buf, cmp_buf, &skipped);
                }
@@ -179,12 +212,17 @@ static int spi_flash_update(struct spi_flash *flash, u32 offset,
                err_oper = "malloc";
        }
        free(cmp_buf);
+       putc('\r');
        if (err_oper) {
                printf("SPI flash failed in %s step\n", err_oper);
                return 1;
        }
-       printf("%zu bytes written, %zu bytes skipped\n", len - skipped,
-              skipped);
+
+       delta = get_timer(start_time);
+       printf("%zu bytes written, %zu bytes skipped", len - skipped,
+               skipped);
+       printf(" in %ld.%lds, speed %ld B/s\n",
+               delta / 1000, delta % 1000, bytes_per_second(len, start_time));
 
        return 0;
 }
@@ -275,6 +313,161 @@ static int do_spi_flash_erase(int argc, char * const argv[])
        return 0;
 }
 
+#ifdef CONFIG_CMD_SF_TEST
+enum {
+       STAGE_ERASE,
+       STAGE_CHECK,
+       STAGE_WRITE,
+       STAGE_READ,
+
+       STAGE_COUNT,
+};
+
+static char *stage_name[STAGE_COUNT] = {
+       "erase",
+       "check",
+       "write",
+       "read",
+};
+
+struct test_info {
+       int stage;
+       int bytes;
+       unsigned base_ms;
+       unsigned time_ms[STAGE_COUNT];
+};
+
+static void show_time(struct test_info *test, int stage)
+{
+       uint64_t speed; /* KiB/s */
+       int bps;        /* Bits per second */
+
+       speed = (long long)test->bytes * 1000;
+       do_div(speed, test->time_ms[stage] * 1024);
+       bps = speed * 8;
+
+       printf("%d %s: %d ticks, %d KiB/s %d.%03d Mbps\n", stage,
+              stage_name[stage], test->time_ms[stage],
+              (int)speed, bps / 1000, bps % 1000);
+}
+
+static void spi_test_next_stage(struct test_info *test)
+{
+       test->time_ms[test->stage] = get_timer(test->base_ms);
+       show_time(test, test->stage);
+       test->base_ms = get_timer(0);
+       test->stage++;
+}
+
+/**
+ * Run a test on the SPI flash
+ *
+ * @param flash                SPI flash to use
+ * @param buf          Source buffer for data to write
+ * @param len          Size of data to read/write
+ * @param offset       Offset within flash to check
+ * @param vbuf         Verification buffer
+ * @return 0 if ok, -1 on error
+ */
+static int spi_flash_test(struct spi_flash *flash, char *buf, ulong len,
+                          ulong offset, char *vbuf)
+{
+       struct test_info test;
+       int i;
+
+       printf("SPI flash test:\n");
+       memset(&test, '\0', sizeof(test));
+       test.base_ms = get_timer(0);
+       test.bytes = len;
+       if (spi_flash_erase(flash, offset, len)) {
+               printf("Erase failed\n");
+               return -1;
+       }
+       spi_test_next_stage(&test);
+
+       if (spi_flash_read(flash, offset, len, vbuf)) {
+               printf("Check read failed\n");
+               return -1;
+       }
+       for (i = 0; i < len; i++) {
+               if (vbuf[i] != 0xff) {
+                       printf("Check failed at %d\n", i);
+                       print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0);
+                       return -1;
+               }
+       }
+       spi_test_next_stage(&test);
+
+       if (spi_flash_write(flash, offset, len, buf)) {
+               printf("Write failed\n");
+               return -1;
+       }
+       memset(vbuf, '\0', len);
+       spi_test_next_stage(&test);
+
+       if (spi_flash_read(flash, offset, len, vbuf)) {
+               printf("Read failed\n");
+               return -1;
+       }
+       spi_test_next_stage(&test);
+
+       for (i = 0; i < len; i++) {
+               if (buf[i] != vbuf[i]) {
+                       printf("Verify failed at %d, good data:\n", i);
+                       print_buffer(i, buf + i, 1, min(len - i, 0x40), 0);
+                       printf("Bad data:\n");
+                       print_buffer(i, vbuf + i, 1, min(len - i, 0x40), 0);
+                       return -1;
+               }
+       }
+       printf("Test passed\n");
+       for (i = 0; i < STAGE_COUNT; i++)
+               show_time(&test, i);
+
+       return 0;
+}
+
+static int do_spi_flash_test(int argc, char * const argv[])
+{
+       unsigned long offset;
+       unsigned long len;
+       char *buf = (char *)CONFIG_SYS_TEXT_BASE;
+       char *endp;
+       char *vbuf;
+       int ret;
+
+       offset = simple_strtoul(argv[1], &endp, 16);
+       if (*argv[1] == 0 || *endp != 0)
+               return -1;
+       len = simple_strtoul(argv[2], &endp, 16);
+       if (*argv[2] == 0 || *endp != 0)
+               return -1;
+
+       vbuf = malloc(len);
+       if (!vbuf) {
+               printf("Cannot allocate memory\n");
+               return 1;
+       }
+       buf = malloc(len);
+       if (!buf) {
+               free(vbuf);
+               printf("Cannot allocate memory\n");
+               return 1;
+       }
+
+       memcpy(buf, (char *)CONFIG_SYS_TEXT_BASE, len);
+       ret = spi_flash_test(flash, buf, len, offset, vbuf);
+       free(vbuf);
+       free(buf);
+       if (ret) {
+               printf("Test failed\n");
+               return 1;
+       }
+
+       return 0;
+}
+#endif /* CONFIG_CMD_SF_TEST */
+
 static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        const char *cmd;
@@ -304,6 +497,10 @@ static int do_spi_flash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[
                ret = do_spi_flash_read_write(argc, argv);
        else if (strcmp(cmd, "erase") == 0)
                ret = do_spi_flash_erase(argc, argv);
+#ifdef CONFIG_CMD_SF_TEST
+       else if (!strcmp(cmd, "test"))
+               ret = do_spi_flash_test(argc, argv);
+#endif
        else
                ret = -1;
 
@@ -315,6 +512,13 @@ usage:
        return CMD_RET_USAGE;
 }
 
+#ifdef CONFIG_CMD_SF_TEST
+#define SF_TEST_HELP "\nsf test offset len             " \
+               "- run a very basic destructive test"
+#else
+#define SF_TEST_HELP
+#endif
+
 U_BOOT_CMD(
        sf,     5,      1,      do_spi_flash,
        "SPI flash sub-system",
@@ -328,4 +532,5 @@ U_BOOT_CMD(
        "                                 `+len' round up `len' to block size\n"
        "sf update addr offset len      - erase and write `len' bytes from memory\n"
        "                                 at `addr' to flash at `offset'"
+       SF_TEST_HELP
 );
index 459d1ebaf2cc00ea61974c0d7675115199b5eb2b..cfca9dd136b37072c82fc21ed27524eeb5ed9b19 100644 (file)
@@ -33,7 +33,7 @@ static int do_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 {
        int ret;
 
-       ret = sound_init();
+       ret = sound_init(gd->fdt_blob);
        if (ret) {
                printf("Initialise Audio driver failed\n");
                return CMD_RET_FAILURE;
index ab4c560ae094e1dffabe5c85404d5dd6fb90466c..e8f40d3ed189b3308c66a61e40f46f6a465aab2a 100644 (file)
@@ -25,6 +25,9 @@
 #include <command.h>
 #include <version.h>
 #include <linux/compiler.h>
+#ifdef CONFIG_SYS_COREBOOT
+#include <asm/arch/sysinfo.h>
+#endif
 
 const char __weak version_string[] = U_BOOT_VERSION_STRING;
 
@@ -37,7 +40,9 @@ static int do_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef LD_VERSION_STRING
        puts(LD_VERSION_STRING "\n");
 #endif
-
+#ifdef CONFIG_SYS_COREBOOT
+       printf("coreboot-%s (%s)\n", lib_sysinfo.version, lib_sysinfo.build);
+#endif
        return 0;
 }
 
index ac9b4ca8d58bfe8dd3cd941c7fb094a4b9d819e7..6fc0fc1c0ec75fe34f100cbfb03b207628b32885 100644 (file)
@@ -805,6 +805,18 @@ struct usb_device *usb_alloc_new_device(void *controller)
        return &usb_dev[dev_index - 1];
 }
 
+/*
+ * Free the newly created device node.
+ * Called in error cases where configuring a newly attached
+ * device fails for some reason.
+ */
+void usb_free_device(void)
+{
+       dev_index--;
+       USB_PRINTF("Freeing device node: %d\n", dev_index);
+       memset(&usb_dev[dev_index], 0, sizeof(struct usb_device));
+       usb_dev[dev_index].devnum = -1;
+}
 
 /*
  * By the time we get here, the device has gotten a new device ID
index e4a120120dc23d068686d0e69e6d8248f9b35308..b5eeb62fbe55ecab41fe74abd3dea5209695a01f 100644 (file)
@@ -259,6 +259,8 @@ void usb_hub_port_connect_change(struct usb_device *dev, int port)
        /* Run it through the hoops (find a driver, etc) */
        if (usb_new_device(usb)) {
                /* Woops, disable the port */
+               usb_free_device();
+               dev->children[port] = NULL;
                USB_HUB_PRINTF("hub: disabling port %d\n", port + 1);
                usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_ENABLE);
        }
@@ -396,14 +398,37 @@ static int usb_hub_configure(struct usb_device *dev)
        for (i = 0; i < dev->maxchild; i++) {
                ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
                unsigned short portstatus, portchange;
+               int ret;
+               ulong start = get_timer(0);
+
+               /*
+                * Wait for (whichever finishes first)
+                *  - A maximum of 10 seconds
+                *    This is a purely observational value driven by connecting
+                *    a few broken pen drives and taking the max * 1.5 approach
+                *  - connection_change and connection state to report same
+                *    state
+                */
+               do {
+                       ret = usb_get_port_status(dev, i + 1, portsts);
+                       if (ret < 0) {
+                               USB_HUB_PRINTF("get_port_status failed\n");
+                               break;
+                       }
+
+                       portstatus = le16_to_cpu(portsts->wPortStatus);
+                       portchange = le16_to_cpu(portsts->wPortChange);
+
+                       if ((portchange & USB_PORT_STAT_C_CONNECTION) ==
+                               (portstatus & USB_PORT_STAT_CONNECTION))
+                               break;
+
+                       mdelay(100);
+               } while (get_timer(start) < CONFIG_SYS_HZ * 10);
 
-               if (usb_get_port_status(dev, i + 1, portsts) < 0) {
-                       USB_HUB_PRINTF("get_port_status failed\n");
+               if (ret < 0)
                        continue;
-               }
 
-               portstatus = le16_to_cpu(portsts->wPortStatus);
-               portchange = le16_to_cpu(portsts->wPortChange);
                USB_HUB_PRINTF("Port %d Status %X Change %X\n",
                                i + 1, portstatus, portchange);
 
index 2d92ee1bb3e95c5af8e6cc66ddcfa1c4aa61bac8..fb322b4015fe0ba2ea72d82a1f7171ae7bfee2e3 100644 (file)
@@ -970,6 +970,16 @@ static int usb_test_unit_ready(ccb *srb, struct us_data *ss)
                        return 0;
                }
                usb_request_sense(srb, ss);
+               /*
+                * Check the Key Code Qualifier, if it matches
+                * "Not Ready - medium not present"
+                * (the sense Key equals 0x2 and the ASC is 0x3a)
+                * return immediately as the medium being absent won't change
+                * unless there is a user action.
+                */
+               if ((srb->sense_buf[2] == 0x02) &&
+                   (srb->sense_buf[12] == 0x3a))
+                       return -1;
                mdelay(100);
        } while (retries--);
 
diff --git a/doc/README.sh7752evb b/doc/README.sh7752evb
new file mode 100644 (file)
index 0000000..c1fb54c
--- /dev/null
@@ -0,0 +1,67 @@
+========================================
+Renesas R0P7752C00000RZ board
+========================================
+
+This board specification:
+=========================
+
+The R0P7752C00000RZ(board config name:sh7752evb) has the following device:
+
+ - SH7752 (SH-4A)
+ - DDR3-SDRAM 512MB
+ - SPI ROM 8MB
+ - Gigabit Ethernet controllers
+ - eMMC 4GB
+
+
+Configuration for This board:
+=============================
+
+You can select the configuration as follows:
+
+ - make sh7752evb_config
+
+
+This board specific command:
+============================
+
+This board has the following its specific command:
+
+ - write_mac
+
+
+1. write_mac
+
+You can write MAC address to SPI ROM.
+
+ Usage 1) Write MAC address
+
+   write_mac [GETHERC ch0] [GETHERC ch1]
+
+       For example)
+        => write_mac 74:90:50:00:33:9e 74:90:50:00:33:9f
+               *) We have to input the command as a single line
+                  (without carriage return)
+               *) We have to reset after input the command.
+
+ Usage 2) Show current data
+
+   write_mac
+
+       For example)
+               => write_mac
+               GETHERC ch0 = 74:90:50:00:33:9e
+               GETHERC ch1 = 74:90:50:00:33:9f
+
+
+Update SPI ROM:
+============================
+
+1. Copy u-boot image to RAM area.
+2. Probe SPI device.
+   => sf probe 0
+   SF: Detected MX25L6405D with page size 64KiB, total 8 MiB
+3. Erase SPI ROM.
+   => sf erase 0 80000
+4. Write u-boot image to SPI ROM.
+   => sf write 0x48000000 0 80000
index ef1d6ba36608f596c3c4a0d7643331d7fa767687..b4c3ef52247fe6470f42d6ae204b59ea01fbabd1 100644 (file)
@@ -63,7 +63,7 @@ Common USB Commands:
 Storage USB Commands:
 - usb scan:        scans the USB for storage devices.The USB must be
                    running for this command (usb start)
-- usb device [dev]: show or set current USB staorage device
+- usb device [dev]: show or set current USB storage device
 - usb part [dev]:   print partition table of one or all USB storage
                    devices
 - usb read addr blk# cnt:
diff --git a/doc/device-tree-bindings/exynos/isp-spi.txt b/doc/device-tree-bindings/exynos/isp-spi.txt
new file mode 100644 (file)
index 0000000..b8086e8
--- /dev/null
@@ -0,0 +1,22 @@
+Exynos ISP SPI Subsystem
+
+The device node for ISP SPI subsytem.
+Since Peripheral id in EXYNOS is decoded based on Interrupts, currently
+ISP SPI have no individual interrupts hence we add ad dummy interrupt node
+which will have a value beyond the maximum number of interrupts exynos5 can
+support.
+
+Required properties :
+ - compatible : Should be "samsung,exynos-spi" for spi.
+ - reg : Base adrress of the the subsystem.
+ - interrupts : A value which is beyond the maximum number of interrupts
+exynos5 can support.
+
+Example:
+spi@131a0000 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       compatible = "samsung,exynos-spi";
+       reg = <0x131a0000 0x30>;
+       interrupts = <0 129 0>;
+};
diff --git a/doc/device-tree-bindings/exynos/sound.txt b/doc/device-tree-bindings/exynos/sound.txt
new file mode 100644 (file)
index 0000000..98d1798
--- /dev/null
@@ -0,0 +1,27 @@
+Exynos Sound Subsystem
+
+The device node for sound subsytem which contains codec and i2s block
+that is a part of Exynos5250
+
+Required properties :
+ - compatible : Should be "samsung,exynos-sound" for sound
+ - samsung,i2s-epll-clock-frequency : epll clock output frequency in Hz
+ - samsung,i2s-sampling-rate : sampling rate, default is 48000
+ - samsung,i2s-bits-per-sample : sample width, defalut is 16 bit
+ - samsung,i2s-channels : nummber of channels, default is 2
+ - samsung,i2s-lr-clk-framesize : lr clock frame size
+ - samsung,i2s-bit-clk-framesize : bit clock frame size
+ - samsung,codec-type : sound codec type
+
+Example:
+
+sound@12d60000 {
+       compatible = "samsung,exynos-sound"
+       samsung,i2s-epll-clock-frequency = <192000000>;
+       samsung,i2s-sampling-rate = <48000>;
+       samsung,i2s-bits-per-sample = <16>;
+       samsung,i2s-channels = <2>;
+       samsung,i2s-lr-clk-framesize = <256>;
+       samsung,i2s-bit-clk-framesize = <32>;
+       samsung,codec-type = "wm8994";
+};
index 90d297a28422ac9a4c7e568bfe1bd2edc2f26dff..769a2ba5ba32bd77a492647900bc86e5626f89d4 100644 (file)
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 #include <asm/arch/clk.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/pinmux.h>
 #else
 #include <asm/arch/s3c24x0_cpu.h>
 #endif
 #define I2C_TIMEOUT 1          /* 1 second */
 
 
-static unsigned int g_current_bus;     /* Stores Current I2C Bus */
+/*
+ * For SPL boot some boards need i2c before SDRAM is initialised so force
+ * variables to live in SRAM
+ */
+static unsigned int g_current_bus __attribute__((section(".data")));
+#ifdef CONFIG_OF_CONTROL
+static int i2c_busses __attribute__((section(".data")));
+static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
+                       __attribute__((section(".data")));
+#endif
 
 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
 static int GetI2CSDA(void)
@@ -512,4 +523,76 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
                (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
                 len) != 0);
 }
+
+#ifdef CONFIG_OF_CONTROL
+void board_i2c_init(const void *blob)
+{
+       int node_list[CONFIG_MAX_I2C_NUM];
+       int count, i;
+
+       count = fdtdec_find_aliases_for_id(blob, "i2c",
+               COMPAT_SAMSUNG_S3C2440_I2C, node_list,
+               CONFIG_MAX_I2C_NUM);
+
+       for (i = 0; i < count; i++) {
+               struct s3c24x0_i2c_bus *bus;
+               int node = node_list[i];
+
+               if (node <= 0)
+                       continue;
+               bus = &i2c_bus[i];
+               bus->regs = (struct s3c24x0_i2c *)
+                       fdtdec_get_addr(blob, node, "reg");
+               bus->id = pinmux_decode_periph_id(blob, node);
+               bus->node = node;
+               bus->bus_num = i2c_busses++;
+               exynos_pinmux_config(bus->id, 0);
+       }
+}
+
+static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
+{
+       if (bus_idx < i2c_busses)
+               return &i2c_bus[bus_idx];
+
+       debug("Undefined bus: %d\n", bus_idx);
+       return NULL;
+}
+
+int i2c_get_bus_num_fdt(int node)
+{
+       int i;
+
+       for (i = 0; i < i2c_busses; i++) {
+               if (node == i2c_bus[i].node)
+                       return i;
+       }
+
+       debug("%s: Can't find any matched I2C bus\n", __func__);
+       return -1;
+}
+
+int i2c_reset_port_fdt(const void *blob, int node)
+{
+       struct s3c24x0_i2c_bus *i2c;
+       int bus;
+
+       bus = i2c_get_bus_num_fdt(node);
+       if (bus < 0) {
+               debug("could not get bus for node %d\n", node);
+               return -1;
+       }
+
+       i2c = get_bus(bus);
+       if (!i2c) {
+               debug("get_bus() failed for node node %d\n", node);
+               return -1;
+       }
+
+       i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+       return 0;
+}
+#endif
+
 #endif /* CONFIG_HARD_I2C */
index 2dd4b06a23270ec27ec776f3a8bcef620bb8ed2e..a56d749dec0adcc3c767552a4d3487211e751dfb 100644 (file)
@@ -30,4 +30,11 @@ struct s3c24x0_i2c {
        u32     iicds;
        u32     iiclc;
 };
+
+struct s3c24x0_i2c_bus {
+       int node;       /* device tree node */
+       int bus_num;    /* i2c bus number */
+       struct s3c24x0_i2c *regs;
+       int id;
+};
 #endif /* _S3C24X0_I2C_H */
index b2dfc5369dde405baf170756af6b0347e8904b1e..60dbb7864f2b40476e7dab9a03930aa89dc50158 100644 (file)
@@ -1128,7 +1128,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
                                                AMD_CMD_ERASE_START);
                                flash_unlock_seq (info, sect);
                                flash_write_cmd (info, sect, 0,
-                                                AMD_CMD_ERASE_SECTOR);
+                                                info->cmd_erase_sector);
                                break;
 #ifdef CONFIG_FLASH_CFI_LEGACY
                        case CFI_CMDSET_AMD_LEGACY:
@@ -1247,6 +1247,8 @@ void flash_print_info (flash_info_t * info)
                printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
                info->device_id2);
        }
+       if ((info->vendor == CFI_CMDSET_AMD_STANDARD) && (info->legacy_unlock))
+               printf("\n  Advanced Sector Protection (PPB) enabled");
        printf ("\n  Erase timeout: %ld ms, write timeout: %ld ms\n",
                info->erase_blk_tout,
                info->write_tout);
@@ -1425,13 +1427,18 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
        return flash_write_cfiword (info, wp, cword);
 }
 
+static inline int manufact_match(flash_info_t *info, u32 manu)
+{
+       return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16);
+}
+
 /*-----------------------------------------------------------------------
  */
 #ifdef CONFIG_SYS_FLASH_PROTECTION
 
 static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot)
 {
-       if (info->manufacturer_id == ((INTEL_MANUFACT & FLASH_VENDMASK) >> 16)
+       if (manufact_match(info, INTEL_MANUFACT)
            && info->device_id == NUMONYX_256MBIT) {
                /*
                 * see errata called
@@ -1488,8 +1495,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
                case CFI_CMDSET_AMD_EXTENDED:
                case CFI_CMDSET_AMD_STANDARD:
                        /* U-Boot only checks the first byte */
-                       if (info->manufacturer_id ==
-                           ((ATM_MANUFACT & FLASH_VENDMASK) >> 16)) {
+                       if (manufact_match(info, ATM_MANUFACT)) {
                                if (prot) {
                                        flash_unlock_seq (info, 0);
                                        flash_write_cmd (info, 0,
@@ -1507,8 +1513,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
                                                        0, ATM_CMD_UNLOCK_SECT);
                                }
                        }
-                       if (info->manufacturer_id ==
-                           ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) {
+                       if (info->legacy_unlock) {
                                int flag = disable_interrupts();
                                int lock_flag;
 
@@ -1733,18 +1738,15 @@ static void cmdset_amd_read_jedec_ids(flash_info_t *info)
 static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
 {
        info->cmd_reset = AMD_CMD_RESET;
+       info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR;
 
        cmdset_amd_read_jedec_ids(info);
        flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
 
 #ifdef CONFIG_SYS_FLASH_PROTECTION
-       if (info->ext_addr && info->manufacturer_id ==
-           ((AMD_MANUFACT & FLASH_VENDMASK) >> 16)) {
-               ushort spus;
-
-               /* read sector protect/unprotect scheme */
-               spus = flash_read_uchar(info, info->ext_addr + 9);
-               if (spus == 0x8)
+       if (info->ext_addr) {
+               /* read sector protect/unprotect scheme (at 0x49) */
+               if (flash_read_uchar(info, info->ext_addr + 9) == 0x8)
                        info->legacy_unlock = 1;
        }
 #endif
@@ -2003,6 +2005,25 @@ static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
        }
 }
 
+static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry)
+{
+       /*
+        * SST, for many recent nor parallel flashes, says they are
+        * CFI-conformant. This is not true, since qry struct.
+        * reports a std. AMD command set (0x0002), while SST allows to
+        * erase two different sector sizes for the same memory.
+        * 64KB sector (SST call it block)  needs 0x30 to be erased.
+        * 4KB  sector (SST call it sector) needs 0x50 to be erased.
+        * Since CFI query detect the 4KB number of sectors, users expects
+        * a sector granularity of 4KB, and it is here set.
+        */
+       if (info->device_id == 0x5D23 || /* SST39VF3201B */
+           info->device_id == 0x5C23) { /* SST39VF3202B */
+               /* set sector granularity to 4KB */
+               info->cmd_erase_sector=0x50;
+       }
+}
+
 /*
  * The following code cannot be run from FLASH!
  *
@@ -2081,6 +2102,9 @@ ulong flash_get_size (phys_addr_t base, int banknum)
                case 0x0020:
                        flash_fixup_stm(info, &qry);
                        break;
+               case 0x00bf: /* SST */
+                       flash_fixup_sst(info, &qry);
+                       break;
                }
 
                debug ("manufacturer is %d\n", info->vendor);
@@ -2158,6 +2182,27 @@ ulong flash_get_size (phys_addr_t base, int banknum)
                                                             FLASH_OFFSET_PROTECT,
                                                             FLASH_STATUS_PROTECT);
                                        break;
+                               case CFI_CMDSET_AMD_EXTENDED:
+                               case CFI_CMDSET_AMD_STANDARD:
+                                       if (!info->legacy_unlock) {
+                                               /* default: not protected */
+                                               info->protect[sect_cnt] = 0;
+                                               break;
+                                       }
+
+                                       /* Read protection (PPB) from sector */
+                                       flash_write_cmd(info, 0, 0,
+                                                       info->cmd_reset);
+                                       flash_unlock_seq(info, 0);
+                                       flash_write_cmd(info, 0,
+                                                       info->addr_unlock1,
+                                                       FLASH_CMD_READ_ID);
+                                       info->protect[sect_cnt] =
+                                               flash_isset(
+                                                       info, sect_cnt,
+                                                       FLASH_OFFSET_PROTECT,
+                                                       FLASH_STATUS_PROTECT);
+                                       break;
                                default:
                                        /* default: not protected */
                                        info->protect[sect_cnt] = 0;
index 2c3812c3bab20d3ea762c9f2a61d3ea2107ef984..c77c0c4f0f6eec10c34ce5e3b17d495b6531026f 100644 (file)
@@ -79,6 +79,10 @@ COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
 
+else  # minimal SPL drivers
+
+COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
+
 endif # drivers
 endif # nand
 
index 0878bece675bd3267d044919dbf0c870d966042b..b13d8a9303a9bea0410c0d9e039926366d5ab7c4 100644 (file)
@@ -391,7 +391,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
                        timing = IFC_FIR_OP_RBCD;
 
                out_be32(&ifc->ifc_nand.nand_fir0,
-                               (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
+                               (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
                                (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
                                (timing << IFC_NAND_FIR0_OP2_SHIFT));
                out_be32(&ifc->ifc_nand.nand_fcr0,
@@ -758,7 +758,7 @@ static void fsl_ifc_sram_init(void)
 
        /* READID */
        out_be32(&ifc->ifc_nand.nand_fir0,
-                       (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
+                       (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
                        (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
                        (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
        out_be32(&ifc->ifc_nand.nand_fcr0,
index 483a920fcaeee1432263389390c850bd2a7c21f2..e8da66d63f6949ce168746590a5050c80d67ee98 100644 (file)
 #include <netdev.h>
 #include "mv88e61xx.h"
 
+/*
+ * Uncomment either of the following line for local debug control;
+ * otherwise global debug control will apply.
+ */
+
+/* #undef DEBUG */
+/* #define DEBUG */
+
 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
 /* Chip Address mode
  * The Switch support two modes of operation
@@ -52,7 +60,8 @@ static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
        return 0;
 }
 
-static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
+static void mv88e61xx_switch_write(char *name, u32 phy_adr,
+       u32 reg_ofs, u16 data)
 {
        u16 mii_dev_addr;
 
@@ -70,7 +79,8 @@ static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
                                                                         15));
 }
 
-static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
+static void mv88e61xx_switch_read(char *name, u32 phy_adr,
+       u32 reg_ofs, u16 *data)
 {
        u16 mii_dev_addr;
 
@@ -90,110 +100,51 @@ static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
 }
 #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
 
-static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig,
-                                      u32 max_prtnum, u32 ports_ofs)
-{
-       u32 prt;
-       u16 reg;
-       char *name = swconfig->name;
-       u32 cpu_port = swconfig->cpuport;
-       u32 port_mask = swconfig->ports_enabled;
-       enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg;
-
-       /* be sure all ports are disabled */
-       for (prt = 0; prt < max_prtnum; prt++) {
-               RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, &reg);
-               reg &= ~0x3;
-               WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg);
-
-               if (!(cpu_port & (1 << prt)))
-                       continue;
-               /* Set CPU port VID to 0x1 */
-               RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, &reg);
-               reg &= ~0xfff;
-               reg |= 0x1;
-               WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg);
-       }
-
-       /* Setting  Port default priority for all ports to zero */
-       for (prt = 0; prt < max_prtnum; prt++) {
-               RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, &reg);
-               reg &= ~0xc000;
-               WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg);
-       }
-       /* Setting VID and VID map for all ports except CPU port */
-       for (prt = 0; prt < max_prtnum; prt++) {
-               /* only for enabled ports */
-               if ((1 << prt) & port_mask) {
-                       /* skip CPU port */
-                       if ((1 << prt) & cpu_port) {
-                               /*
-                                * Set Vlan map table for cpu_port to see
-                                * all ports
-                                */
-                               RD_PHY(name, (ports_ofs + prt),
-                                      MV88E61XX_PRT_VMAP_REG, &reg);
-                               reg &= ~((1 << max_prtnum) - 1);
-                               reg |= port_mask & ~(1 << prt);
-                               WR_PHY(name, (ports_ofs + prt),
-                                      MV88E61XX_PRT_VMAP_REG, reg);
-                       } else {
-
-                               /*
-                                *  set Ports VLAN Mapping.
-                                *      port prt <--> cpu_port VLAN #prt+1.
-                                */
-                               RD_PHY(name, ports_ofs + prt,
-                                      MV88E61XX_PRT_VID_REG, &reg);
-                               reg &= ~0x0fff;
-                               reg |= (prt + 1);
-                               WR_PHY(name, ports_ofs + prt,
-                                      MV88E61XX_PRT_VID_REG, reg);
-
-                               RD_PHY(name, ports_ofs + prt,
-                                      MV88E61XX_PRT_VMAP_REG, &reg);
-                               if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) {
-                                       /*
-                                        * all any port can send frames to all other ports
-                                        * ref: sec 3.2.1.1 of datasheet
-                                        */
-                                       reg |= 0x03f;
-                                       reg &= ~(1 << prt);
-                               } else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) {
-                                       /*
-                                        * all other ports can send frames to CPU port only
-                                        * ref: sec 3.2.1.2 of datasheet
-                                        */
-                                       reg &= ~((1 << max_prtnum) - 1);
-                                       reg |= cpu_port;
-                               }
-                               WR_PHY(name, ports_ofs + prt,
-                                      MV88E61XX_PRT_VMAP_REG, reg);
-                       }
-               }
-       }
+/*
+ * Convenience macros for switch device/port reads/writes
+ * These macros output valid 'mv88e61xx' U_BOOT_CMDs
+ */
 
-       /*
-        * enable only appropriate ports to forwarding mode
-        * and disable the others
-        */
-       for (prt = 0; prt < max_prtnum; prt++) {
-               if ((1 << prt) & port_mask) {
-                       RD_PHY(name, ports_ofs + prt,
-                              MV88E61XX_PRT_CTRL_REG, &reg);
-                       reg |= 0x3;
-                       WR_PHY(name, ports_ofs + prt,
-                              MV88E61XX_PRT_CTRL_REG, reg);
-               } else {
-                       /* Disable port */
-                       RD_PHY(name, ports_ofs + prt,
-                              MV88E61XX_PRT_CTRL_REG, &reg);
-                       reg &= ~0x3;
-                       WR_PHY(name, ports_ofs + prt,
-                              MV88E61XX_PRT_CTRL_REG, reg);
-               }
-       }
+#ifndef DEBUG
+#define WR_SWITCH_REG wr_switch_reg
+#define RD_SWITCH_REG rd_switch_reg
+#define WR_SWITCH_PORT_REG(n, p, r, d) \
+       WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
+#define RD_SWITCH_PORT_REG(n, p, r, d) \
+       RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
+#else
+static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
+{
+       printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
+               name, dev_adr, reg_ofs, data);
+       wr_switch_reg(name, dev_adr, reg_ofs, data);
 }
+static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
+{
+       rd_switch_reg(name, dev_adr, reg_ofs, data);
+       printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
+               name, dev_adr, reg_ofs, *data);
+}
+static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
+       u16 data)
+{
+       printf("mv88e61xx %s port %02x reg %02x write %04x\n",
+               name, prt_adr, reg_ofs, data);
+       wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+}
+static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
+       u16 *data)
+{
+       rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+       printf("mv88e61xx %s port %02x reg %02x read %04x\n",
+               name, prt_adr, reg_ofs, *data);
+}
+#endif
+
+/*
+ * Local functions to read/write registers on the switch PHYs.
+ * NOTE! This goes through switch, not direct miiphy, writes and reads!
+ */
 
 /*
  * Make sure SMIBusy bit cleared before another
@@ -204,7 +155,7 @@ static int mv88e61xx_busychk(char *name)
        u16 reg = 0;
        u32 timeout = MV88E61XX_PHY_TIMEOUT;
        do {
-               RD_PHY(name, MV88E61XX_GLB2REG_DEVADR,
+               rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR,
                       MV88E61XX_PHY_CMD, &reg);
                if (timeout-- == 0) {
                        printf("SMI busy timeout\n");
@@ -214,34 +165,110 @@ static int mv88e61xx_busychk(char *name)
        return 0;
 }
 
+static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy,
+       u32 reg, u16 data)
+{
+       /* write switch data reg then cmd reg then check completion */
+       wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA,
+               data);
+       wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
+               (MV88E61XX_PHY_WRITE_CMD | (phy << 5)  | reg));
+       return mv88e61xx_busychk(name);
+}
+
+static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy,
+       u32 reg, u16 *data)
+{
+       /* write switch cmd reg, check for completion */
+       wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
+               (MV88E61XX_PHY_READ_CMD | (phy << 5)  | reg));
+       if (mv88e61xx_busychk(name))
+               return -1;
+       /* read switch data reg and return success */
+       rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data);
+       return 0;
+}
+
+/*
+ * Convenience macros for switch PHY reads/writes
+ */
+
+#ifndef DEBUG
+#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write
+#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read
+#else
+static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr,
+       u32 reg_ofs, u16 data)
+{
+       int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data);
+       if (r)
+               printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n",
+                       name, phy_adr, reg_ofs);
+       else
+               printf("mv88e61xx %s phy %02x reg %02x write %04x\n",
+                       name, phy_adr, reg_ofs, data);
+       return r;
+}
+static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_a