Merge remote-tracking branch 'u-boot-ti/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 3 Nov 2012 09:05:22 +0000 (10:05 +0100)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 3 Nov 2012 09:05:22 +0000 (10:05 +0100)
663 files changed:
.gitignore
CREDITS
MAINTAINERS
Makefile
README
arch/arm/cpu/arm1136/mx35/generic.c
arch/arm/cpu/arm720t/cpu.c
arch/arm/cpu/arm720t/interrupts.c
arch/arm/cpu/arm720t/lpc2292/flash.c [deleted file]
arch/arm/cpu/arm720t/lpc2292/iap_entry.S [deleted file]
arch/arm/cpu/arm720t/lpc2292/mmc.c [deleted file]
arch/arm/cpu/arm720t/lpc2292/mmc_hw.c [deleted file]
arch/arm/cpu/arm720t/lpc2292/mmc_hw.h [deleted file]
arch/arm/cpu/arm720t/lpc2292/spi.c [deleted file]
arch/arm/cpu/arm720t/s3c4510b/cache.c [deleted file]
arch/arm/cpu/arm720t/start.S
arch/arm/cpu/arm720t/tegra-common/spl.c
arch/arm/cpu/arm920t/ep93xx/u-boot.lds
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
arch/arm/cpu/armv7/mx5/clock.c
arch/arm/cpu/armv7/mx5/lowlevel_init.S
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
arch/arm/cpu/ixp/u-boot.lds
arch/arm/cpu/tegra20-common/emc.c
arch/arm/cpu/u-boot.lds
arch/arm/imx-common/cmd_bmode.c
arch/arm/imx-common/iomux-v3.c
arch/arm/include/asm/arch-arm720t/hardware.h
arch/arm/include/asm/arch-arm720t/netarm_dma_module.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_eni_module.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_eth_module.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_gen_module.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_mem_module.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_registers.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_ser_module.h [deleted file]
arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h [deleted file]
arch/arm/include/asm/arch-lpc2292/spi.h [deleted file]
arch/arm/include/asm/arch-mx25/imx-regs.h
arch/arm/include/asm/arch-mx35/clock.h
arch/arm/include/asm/arch-mx35/lowlevel_macro.S
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/mx6x_pins.h
arch/arm/include/asm/arch-mx6/mxc_hdmi.h [new file with mode: 0644]
arch/arm/include/asm/arch-s3c4510b/hardware.h [deleted file]
arch/arm/include/asm/arch-tegra20/spl.h [new file with mode: 0644]
arch/arm/include/asm/global_data.h
arch/arm/include/asm/imx-common/iomux-v3.h
arch/arm/include/asm/u-boot.h
arch/arm/lib/board.c
arch/avr32/cpu/u-boot.lds
arch/avr32/include/asm/global_data.h
arch/avr32/include/asm/u-boot.h
arch/avr32/lib/board.c
arch/blackfin/cpu/u-boot.lds
arch/blackfin/include/asm/global_data.h
arch/blackfin/include/asm/u-boot.h
arch/blackfin/lib/board.c
arch/m68k/cpu/mcf5227x/cpu_init.c
arch/m68k/cpu/mcf5227x/start.S
arch/m68k/cpu/mcf523x/start.S
arch/m68k/cpu/mcf52x2/start.S
arch/m68k/cpu/mcf532x/start.S
arch/m68k/cpu/mcf5445x/config.mk
arch/m68k/cpu/mcf5445x/cpu.c
arch/m68k/cpu/mcf5445x/cpu_init.c
arch/m68k/cpu/mcf5445x/speed.c
arch/m68k/cpu/mcf5445x/start.S
arch/m68k/cpu/mcf547x_8x/start.S
arch/m68k/include/asm/cache.h
arch/m68k/include/asm/global_data.h
arch/m68k/include/asm/immap.h
arch/m68k/include/asm/immap_5441x.h [new file with mode: 0644]
arch/m68k/include/asm/m5441x.h [new file with mode: 0644]
arch/m68k/include/asm/u-boot.h
arch/m68k/lib/board.c
arch/microblaze/cpu/u-boot.lds
arch/microblaze/include/asm/global_data.h
arch/microblaze/include/asm/u-boot.h
arch/mips/cpu/mips32/au1x00/Makefile
arch/mips/cpu/mips32/au1x00/au1x00_ide.c [moved from board/bmw/m48t59y.h with 59% similarity]
arch/mips/cpu/mips32/au1x00/au1x00_serial.c
arch/mips/cpu/mips32/cache.S
arch/mips/cpu/mips32/cpu.c
arch/mips/cpu/mips32/incaip/asc_serial.c
arch/mips/cpu/mips64/Makefile [moved from arch/arm/cpu/arm720t/lpc2292/Makefile with 69% similarity]
arch/mips/cpu/mips64/cache.S [new file with mode: 0644]
arch/mips/cpu/mips64/config.mk [new file with mode: 0644]
arch/mips/cpu/mips64/cpu.c [new file with mode: 0644]
arch/mips/cpu/mips64/interrupts.c [moved from drivers/net/netarm_eth.h with 52% similarity]
arch/mips/cpu/mips64/start.S [new file with mode: 0644]
arch/mips/cpu/mips64/time.c [new file with mode: 0644]
arch/mips/cpu/xburst/cpu.c
arch/mips/cpu/xburst/jz_serial.c
arch/mips/cpu/xburst/start.S
arch/mips/include/asm/addrspace.h
arch/mips/include/asm/asm.h
arch/mips/include/asm/cacheops.h
arch/mips/include/asm/global_data.h
arch/mips/include/asm/io.h
arch/mips/include/asm/posix_types.h
arch/mips/include/asm/u-boot.h
arch/mips/lib/board.c
arch/nds32/cpu/n1213/u-boot.lds
arch/nds32/include/asm/global_data.h
arch/nds32/include/asm/u-boot.h
arch/nds32/lib/board.c
arch/nios2/cpu/u-boot.lds
arch/nios2/include/asm/global_data.h
arch/nios2/include/asm/u-boot.h
arch/openrisc/include/asm/global_data.h
arch/openrisc/include/asm/u-boot.h
arch/powerpc/cpu/74xx_7xx/u-boot.lds
arch/powerpc/cpu/mpc512x/u-boot.lds
arch/powerpc/cpu/mpc5xx/serial.c
arch/powerpc/cpu/mpc5xx/u-boot.lds
arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
arch/powerpc/cpu/mpc5xxx/u-boot.lds
arch/powerpc/cpu/mpc8220/u-boot.lds
arch/powerpc/cpu/mpc8220/uart.c
arch/powerpc/cpu/mpc824x/cpu_init.c
arch/powerpc/cpu/mpc824x/start.S
arch/powerpc/cpu/mpc824x/u-boot.lds
arch/powerpc/cpu/mpc8260/serial_scc.c
arch/powerpc/cpu/mpc8260/serial_smc.c
arch/powerpc/cpu/mpc8260/u-boot.lds
arch/powerpc/cpu/mpc83xx/cpu.c
arch/powerpc/cpu/mpc83xx/cpu_init.c
arch/powerpc/cpu/mpc83xx/speed.c
arch/powerpc/cpu/mpc83xx/u-boot.lds
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/b4860_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/b4860_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
arch/powerpc/cpu/mpc85xx/liodn.c
arch/powerpc/cpu/mpc85xx/mp.c
arch/powerpc/cpu/mpc85xx/mp.h
arch/powerpc/cpu/mpc85xx/p5040_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/p5040_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/portals.c
arch/powerpc/cpu/mpc85xx/release.S
arch/powerpc/cpu/mpc85xx/serial_scc.c
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc85xx/t4240_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/t4240_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/tlb.c
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
arch/powerpc/cpu/mpc85xx/u-boot.lds
arch/powerpc/cpu/mpc86xx/fdt.c
arch/powerpc/cpu/mpc86xx/mp.c
arch/powerpc/cpu/mpc86xx/u-boot.lds
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
arch/powerpc/cpu/mpc8xxx/ddr/main.c
arch/powerpc/cpu/mpc8xxx/ddr/options.c
arch/powerpc/cpu/mpc8xxx/ddr/util.c
arch/powerpc/cpu/mpc8xxx/fdt.c
arch/powerpc/cpu/mpc8xxx/srio.c
arch/powerpc/cpu/ppc4xx/u-boot.lds
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_ddr_sdram.h
arch/powerpc/include/asm/fsl_fman.h
arch/powerpc/include/asm/fsl_liodn.h
arch/powerpc/include/asm/fsl_memac.h [new file with mode: 0644]
arch/powerpc/include/asm/fsl_portals.h
arch/powerpc/include/asm/fsl_serdes.h
arch/powerpc/include/asm/global_data.h
arch/powerpc/include/asm/immap_83xx.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/immap_qe.h
arch/powerpc/include/asm/mp.h
arch/powerpc/include/asm/mpc85xx_gpio.h
arch/powerpc/include/asm/processor.h
arch/powerpc/include/asm/u-boot.h
arch/powerpc/lib/Makefile
arch/powerpc/lib/board.c
arch/powerpc/lib/ide.c [new file with mode: 0644]
arch/powerpc/lib/ide.h [moved from arch/arm/include/asm/arch-lpc2292/hardware.h with 71% similarity]
arch/sandbox/cpu/u-boot.lds
arch/sandbox/include/asm/global_data.h
arch/sh/cpu/sh2/u-boot.lds
arch/sh/cpu/sh3/u-boot.lds
arch/sh/cpu/sh4/u-boot.lds
arch/sh/include/asm/global_data.h
arch/sh/include/asm/u-boot.h
arch/sparc/cpu/leon2/serial.c
arch/sparc/cpu/leon3/serial.c
arch/sparc/include/asm/global_data.h
arch/sparc/include/asm/u-boot.h
arch/sparc/lib/board.c
arch/x86/cpu/u-boot.lds
arch/x86/include/asm/global_data.h
board/BuS/eb_cpu5282/u-boot.lds
board/CarMediaLab/flea3/lowlevel_init.S
board/LEOX/elpt860/u-boot.lds
board/Marvell/common/serial.c
board/RPXClassic/u-boot.lds
board/RPXClassic/u-boot.lds.debug
board/RPXlite/u-boot.lds
board/RPXlite/u-boot.lds.debug
board/RPXlite_dw/u-boot.lds
board/RPXlite_dw/u-boot.lds.debug
board/RRvision/u-boot.lds
board/actux1/u-boot.lds
board/actux2/u-boot.lds
board/actux3/u-boot.lds
board/adder/u-boot.lds
board/ait/cam_enc_4xx/u-boot-spl.lds
board/altera/nios2-generic/u-boot.lds
board/amcc/acadia/u-boot-nand.lds
board/amcc/bamboo/u-boot-nand.lds
board/amcc/canyonlands/u-boot-nand.lds
board/amcc/kilauea/u-boot-nand.lds
board/amcc/sequoia/u-boot-nand.lds
board/amcc/sequoia/u-boot-ram.lds
board/astro/mcf5373l/u-boot.lds
board/atmel/at91sam9x5ek/at91sam9x5ek.c
board/avionic-design/medcom-wide/Makefile
board/avionic-design/plutux/Makefile
board/avionic-design/tec/Makefile
board/bmw/Makefile [deleted file]
board/bmw/README [deleted file]
board/bmw/bmw.c [deleted file]
board/bmw/bmw.h [deleted file]
board/bmw/early_init.S [deleted file]
board/bmw/flash.c [deleted file]
board/bmw/m48t59y.c [deleted file]
board/bmw/ns16550.c [deleted file]
board/bmw/ns16550.h [deleted file]
board/bmw/serial.c [deleted file]
board/c2mon/u-boot.lds
board/c2mon/u-boot.lds.debug
board/cobra5272/u-boot.lds
board/cogent/serial.c
board/cogent/u-boot.lds
board/cogent/u-boot.lds.debug
board/compal/paz00/Makefile
board/compulab/trimslice/Makefile
board/cpc45/Makefile
board/cpc45/cpc45.c
board/cpc45/ide.c [new file with mode: 0644]
board/cray/L1/u-boot.lds.debug
board/dave/PPChameleonEVB/u-boot.lds
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
board/davinci/da8xxevm/u-boot-spl-hawk.lds
board/dbau1x00/u-boot.lds
board/dvlhost/u-boot.lds
board/eltec/mhpc/u-boot.lds
board/eltec/mhpc/u-boot.lds.debug
board/emk/top860/u-boot.lds
board/ep88x/u-boot.lds
board/esd/cpci750/ide.c
board/esd/cpci750/serial.c
board/esd/dasa_sim/u-boot.lds
board/esd/pmc440/u-boot-nand.lds
board/esd/tasreg/u-boot.lds
board/esg/ima3-mx53/ima3-mx53.c
board/esteem192e/u-boot.lds
board/etx094/u-boot.lds
board/evb64260/serial.c
board/evb64260/u-boot.lds
board/fads/u-boot.lds
board/flagadm/u-boot.lds
board/flagadm/u-boot.lds.debug
board/freescale/common/Makefile
board/freescale/common/qixis.c
board/freescale/common/qixis.h
board/freescale/common/vsc3316_3308.c [new file with mode: 0644]
board/freescale/common/vsc3316_3308.h [new file with mode: 0644]
board/freescale/m5208evbe/u-boot.lds
board/freescale/m52277evb/u-boot.lds
board/freescale/m5235evb/u-boot.lds
board/freescale/m5249evb/u-boot.lds
board/freescale/m5253demo/u-boot.lds
board/freescale/m5253evbe/u-boot.lds
board/freescale/m5271evb/u-boot.lds
board/freescale/m5272c3/u-boot.lds
board/freescale/m5275evb/u-boot.lds
board/freescale/m5282evb/u-boot.lds
board/freescale/m53017evb/u-boot.lds
board/freescale/m5329evb/u-boot.lds
board/freescale/m5373evb/u-boot.lds
board/freescale/m54418twr/Makefile [moved from board/sx1/Makefile with 85% similarity]
board/freescale/m54418twr/config.mk [moved from board/bmw/config.mk with 73% similarity]
board/freescale/m54418twr/m54418twr.c [new file with mode: 0644]
board/freescale/m54418twr/u-boot.lds [new file with mode: 0644]
board/freescale/m54451evb/u-boot.lds
board/freescale/m54455evb/u-boot.lds
board/freescale/m547xevb/u-boot.lds
board/freescale/m548xevb/u-boot.lds
board/freescale/mx31ads/u-boot.lds
board/freescale/mx35pdk/lowlevel_init.S
board/freescale/mx35pdk/mx35pdk.c
board/freescale/mx35pdk/mx35pdk.h
board/freescale/mx51evk/mx51evk.c
board/freescale/mx53ard/mx53ard.c
board/freescale/mx53evk/mx53evk.c
board/freescale/mx53loco/mx53loco.c
board/freescale/mx53smd/mx53smd.c
board/freescale/mx6qarm2/mx6qarm2.c
board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6qsabrelite/mx6qsabrelite.c
board/freescale/mx6qsabresd/mx6qsabresd.c
board/freescale/t4qds/Makefile [moved from board/sbc8560/Makefile with 81% similarity]
board/freescale/t4qds/ddr.c [new file with mode: 0644]
board/freescale/t4qds/eth.c [new file with mode: 0644]
board/freescale/t4qds/law.c [new file with mode: 0644]
board/freescale/t4qds/pci.c [new file with mode: 0644]
board/freescale/t4qds/t4240qds_qixis.h [new file with mode: 0644]
board/freescale/t4qds/t4qds.c [new file with mode: 0644]
board/freescale/t4qds/t4qds.h [new file with mode: 0644]
board/freescale/t4qds/tlb.c [new file with mode: 0644]
board/gaisler/gr_cpci_ax2000/u-boot.lds
board/gaisler/gr_ep2s60/u-boot.lds
board/gaisler/gr_xc3s_1500/u-boot.lds
board/gaisler/grsim/u-boot.lds
board/gaisler/grsim_leon2/u-boot.lds
board/gen860t/u-boot-flashenv.lds
board/gen860t/u-boot.lds
board/genesi/mx51_efikamx/efikamx.c
board/genietv/u-boot.lds
board/genietv/u-boot.lds.debug
board/hermes/u-boot.lds
board/hermes/u-boot.lds.debug
board/hymod/u-boot.lds
board/hymod/u-boot.lds.debug
board/icu862/u-boot.lds
board/icu862/u-boot.lds.debug
board/idmr/u-boot.lds
board/incaip/u-boot.lds
board/ip860/u-boot.lds
board/ip860/u-boot.lds.debug
board/ivm/ivm.c
board/ivm/u-boot.lds
board/ivm/u-boot.lds.debug
board/keymile/km83xx/km83xx.c
board/kmc/kzm9g/kzm9g.c
board/korat/u-boot-F7FC.lds
board/kup/kup4k/u-boot.lds
board/kup/kup4k/u-boot.lds.debug
board/kup/kup4x/u-boot.lds
board/kup/kup4x/u-boot.lds.debug
board/lantec/u-boot.lds
board/lantec/u-boot.lds.debug
board/linkstation/ide.c
board/lubbock/lubbock.c
board/lwmon/u-boot.lds
board/lwmon/u-boot.lds.debug
board/manroland/uc100/u-boot.lds
board/matrix_vision/mvsmr/u-boot.lds
board/mbx8xx/u-boot.lds
board/mbx8xx/u-boot.lds.debug
board/micronas/vct/u-boot.lds
board/mousse/u-boot.lds
board/mousse/u-boot.lds.ram
board/mousse/u-boot.lds.rom
board/mpl/pip405/u-boot.lds.debug
board/mvblue/u-boot.lds
board/netphone/u-boot.lds
board/netphone/u-boot.lds.debug
board/netta/u-boot.lds
board/netta/u-boot.lds.debug
board/netta2/u-boot.lds
board/netta2/u-boot.lds.debug
board/netvia/u-boot.lds
board/netvia/u-boot.lds.debug
board/nvidia/common/Makefile
board/nvidia/common/common.mk [new file with mode: 0644]
board/nvidia/dts/tegra20-harmony.dts
board/nvidia/dts/tegra20-whistler.dts
board/nvidia/harmony/harmony.c
board/nvidia/seaboard/seaboard.c
board/nx823/u-boot.lds
board/nx823/u-boot.lds.debug
board/openrisc/openrisc-generic/u-boot.lds
board/palmtc/palmtc.c
board/pb1x00/u-boot.lds
board/pcippc2/fpga_serial.c
board/pcippc2/fpga_serial.h
board/pcippc2/pcippc2.c
board/pcs440ep/pcs440ep.c
board/prodrive/p3mx/serial.c
board/pxa255_idp/pxa_idp.c
board/qemu-mips/config.mk [deleted file]
board/qemu-mips/u-boot.lds
board/qi/qi_lb60/u-boot.lds
board/quantum/u-boot.lds
board/r360mpi/u-boot.lds
board/rbc823/u-boot.lds
board/renesas/sh7757lcr/u-boot.lds
board/rsdproto/u-boot.lds
board/samsung/origen/lowlevel_init.S
board/samsung/origen/origen_setup.h
board/samsung/smdk5250/smdk5250-uboot-spl.lds
board/samsung/smdk6400/u-boot-nand.lds
board/sandburst/karef/u-boot.lds.debug
board/sandburst/metrobox/u-boot.lds.debug
board/sandpoint/u-boot.lds
board/sbc8560/README [deleted file]
board/sbc8560/ddr.c [deleted file]
board/sbc8560/law.c [deleted file]
board/sbc8560/sbc8560.c [deleted file]
board/sbc8560/tlb.c [deleted file]
board/siemens/IAD210/u-boot.lds
board/sixnet/u-boot.lds
board/snmc/qs850/u-boot.lds
board/snmc/qs860t/u-boot.lds
board/spc1920/u-boot.lds
board/spd8xx/u-boot.lds
board/spd8xx/u-boot.lds.debug
board/stx/stxxtc/u-boot.lds
board/stx/stxxtc/u-boot.lds.debug
board/svm_sc8xx/u-boot.lds
board/sx1/config.mk [deleted file]
board/sx1/lowlevel_init.S [deleted file]
board/sx1/sx1.c [deleted file]
board/ti/omap2420h4/omap2420h4.c
board/toradex/colibri_t20-common/colibri_t20-common.c [new file with mode: 0644]
board/toradex/colibri_t20-common/colibri_t20-common.h [new file with mode: 0644]
board/toradex/colibri_t20_iris/Makefile [new file with mode: 0644]
board/toradex/colibri_t20_iris/colibri_t20_iris.c [new file with mode: 0644]
board/toradex/dts/tegra20-colibri_t20_iris.dts [new file with mode: 0644]
board/tqc/tqm8xx/u-boot.lds
board/trizepsiv/conxs.c
board/ttcontrol/vision2/vision2.c
board/v37/u-boot.lds
board/vpac270/u-boot-spl.lds
board/w7o/u-boot.lds.debug
board/westel/amx860/u-boot.lds
board/westel/amx860/u-boot.lds.debug
board/xes/xpedite1000/u-boot.lds.debug
boards.cfg
common/Makefile
common/bouncebuf.c [new file with mode: 0644]
common/cmd_bdinfo.c
common/cmd_cbfs.c [new file with mode: 0644]
common/cmd_fdt.c
common/cmd_help.c
common/cmd_i2c.c
common/cmd_ide.c
common/cmd_nvedit.c
common/command.c
common/env_common.c
common/env_embedded.c
common/image.c
common/iomux.c
common/spl/spl.c
common/usb.c
common/usb_storage.c
config.mk
disk/part.c
disk/part_dos.c
disk/part_efi.c
disk/part_efi.h
doc/DocBook/Makefile
doc/DocBook/linker_lists.tmpl [new file with mode: 0644]
doc/DocBook/stdio.tmpl [new file with mode: 0644]
doc/README.VSC3316-3308 [new file with mode: 0644]
doc/README.commands
doc/README.fsl-ddr
doc/README.m54418twr [new file with mode: 0644]
doc/README.mpc85xx-spin-table [new file with mode: 0644]
doc/README.scrapyard
doc/README.t4240qds [new file with mode: 0644]
doc/driver-model/UDM-serial.txt
drivers/i2c/sh_i2c.c
drivers/i2c/soft_i2c.c
drivers/input/i8042.c
drivers/input/input.c
drivers/mmc/Makefile
drivers/mmc/dw_mmc.c [new file with mode: 0644]
drivers/mmc/fsl_esdhc.c
drivers/mmc/gen_atmel_mci.c
drivers/mmc/mmc.c
drivers/mmc/mmc_spi.c
drivers/mmc/mxsmmc.c
drivers/mmc/pxa_mmc.c [deleted file]
drivers/mmc/s5p_sdhci.c
drivers/mmc/sdhci.c
drivers/mtd/nand/tegra_nand.c
drivers/net/Makefile
drivers/net/fm/Makefile
drivers/net/fm/eth.c
drivers/net/fm/init.c
drivers/net/fm/memac.c [new file with mode: 0644]
drivers/net/fm/memac_phy.c [new file with mode: 0644]
drivers/net/fm/t4240.c [new file with mode: 0644]
drivers/net/mcfmii.c
drivers/net/netarm_eth.c [deleted file]
drivers/pci/fsl_pci_init.c
drivers/qe/qe.c
drivers/serial/Makefile
drivers/serial/altera_jtag_uart.c
drivers/serial/altera_uart.c
drivers/serial/atmel_usart.c
drivers/serial/lpc32xx_hsuart.c
drivers/serial/mcfuart.c
drivers/serial/ns9750_serial.c
drivers/serial/opencores_yanu.c
drivers/serial/s3c4510b_uart.c [deleted file]
drivers/serial/s3c4510b_uart.h [deleted file]
drivers/serial/s3c64xx.c
drivers/serial/serial.c
drivers/serial/serial_clps7111.c [deleted file]
drivers/serial/serial_imx.c
drivers/serial/serial_ixp.c
drivers/serial/serial_ks8695.c
drivers/serial/serial_lpc2292.c [deleted file]
drivers/serial/serial_mxc.c
drivers/serial/serial_netarm.c [deleted file]
drivers/serial/serial_pl01x.c
drivers/serial/serial_s3c44b0.c
drivers/serial/serial_sa1100.c
drivers/serial/serial_sh.c
drivers/spi/fsl_espi.c
drivers/usb/host/ehci-fsl.c
drivers/video/mxc_ipuv3_fb.c
examples/standalone/mips64.lds [new file with mode: 0644]
examples/standalone/sparc.lds
fs/Makefile
fs/cbfs/Makefile [moved from arch/arm/cpu/arm720t/s3c4510b/Makefile with 76% similarity]
fs/cbfs/cbfs.c [new file with mode: 0644]
fs/fat/fat.c
fs/fat/fat_write.c
helper.mk [new file with mode: 0644]
include/atmel_mci.h
include/bouncebuf.h [new file with mode: 0644]
include/cbfs.h [new file with mode: 0644]
include/clps7111.h [deleted file]
include/command.h
include/config_phylib_all_drivers.h
include/configs/BMW.h [deleted file]
include/configs/CPC45.h
include/configs/ICU862.h
include/configs/IVML24.h
include/configs/IVMS8.h
include/configs/KUP4K.h
include/configs/KUP4X.h
include/configs/M54418TWR.h [new file with mode: 0644]
include/configs/MBX.h
include/configs/MPC8308RDB.h
include/configs/NETTA.h
include/configs/NSCU.h
include/configs/P3041DS.h
include/configs/P4080DS.h
include/configs/P5020DS.h
include/configs/R360MPI.h
include/configs/RPXClassic.h
include/configs/RPXlite.h
include/configs/RPXlite_DW.h
include/configs/RRvision.h
include/configs/SBC8540.h [deleted file]
include/configs/SPD823TS.h
include/configs/SX1.h [deleted file]
include/configs/T4240QDS.h [new file with mode: 0644]
include/configs/TK885D.h
include/configs/TQM823L.h
include/configs/TQM823M.h
include/configs/TQM850L.h
include/configs/TQM850M.h
include/configs/TQM855L.h
include/configs/TQM855M.h
include/configs/TQM860L.h
include/configs/TQM860M.h
include/configs/TQM862L.h
include/configs/TQM862M.h
include/configs/TQM866M.h
include/configs/TQM885D.h
include/configs/apx4devkit.h
include/configs/at91sam9x5ek.h
include/configs/atc.h
include/configs/c2mon.h
include/configs/colibri_t20_iris.h [new file with mode: 0644]
include/configs/coreboot.h
include/configs/corenet_ds.h
include/configs/harmony.h
include/configs/km/km8309-common.h [new file with mode: 0644]
include/configs/km/km8321-common.h
include/configs/km/km83xx-common.h
include/configs/kzm9g.h
include/configs/lubbock.h
include/configs/lwmon.h
include/configs/m28evk.h
include/configs/mpc8308_p1m.h
include/configs/mx25pdk.h
include/configs/mx28evk.h
include/configs/mx51evk.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx6qarm2.h
include/configs/mx6qsabre_common.h
include/configs/mx6qsabreauto.h
include/configs/mx6qsabrelite.h
include/configs/mx6qsabresd.h
include/configs/palmtc.h
include/configs/pxa255_idp.h
include/configs/qemu-mips.h
include/configs/qemu-mips64.h [new file with mode: 0644]
include/configs/quantum.h
include/configs/sbc8560.h [deleted file]
include/configs/seaboard.h
include/configs/suvd3.h
include/configs/svm_sc8xx.h
include/configs/t4qds.h [new file with mode: 0644]
include/configs/tegra-common-post.h
include/configs/tegra20-common.h
include/configs/trizepsiv.h
include/configs/uc100.h
include/configs/virtlab2.h
include/dwmmc.h [new file with mode: 0644]
include/e500.h
include/env_default.h [new file with mode: 0644]
include/flash.h
include/fm_eth.h
include/fsl_esdhc.h
include/fsl_mdio.h
include/i8042.h
include/ide.h
include/image.h
include/input.h
include/ipu_pixfmt.h
include/libfdt.h
include/linker_lists.h [new file with mode: 0644]
include/mpc83xx.h
include/sdhci.h
include/serial.h
lib/libfdt/Makefile
lib/libfdt/fdt_empty_tree.c [new file with mode: 0644]
lib/libfdt/fdt_rw.c
nand_spl/board/freescale/mpc8536ds/Makefile
nand_spl/board/freescale/mpc8569mds/Makefile
nand_spl/board/freescale/mpc8572ds/Makefile
nand_spl/board/freescale/mx31pdk/Makefile
nand_spl/board/freescale/mx31pdk/u-boot.lds
nand_spl/board/freescale/p1010rdb/Makefile
nand_spl/board/freescale/p1023rds/Makefile
nand_spl/board/freescale/p1_p2_rdb/Makefile
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
nand_spl/board/karo/tx25/Makefile
nand_spl/board/karo/tx25/u-boot.lds
nand_spl/board/samsung/smdk6400/u-boot.lds
spl/.gitignore
spl/Makefile
tools/env/fw_env.c
tools/imximage.c
tools/imximage.h
tools/patman/gitutil.py
tools/patman/patchstream.py

index d91e91b1e652dcac5a91e5f653e7d08e763e1d1c..1ac43f2825666d93f2f611e86ab2f735777bf83f 100644 (file)
@@ -38,6 +38,7 @@
 /u-boot.sha1
 /u-boot.dis
 /u-boot.lds
+/u-boot.lst
 /u-boot.ubl
 /u-boot.ais
 /u-boot.dtb
diff --git a/CREDITS b/CREDITS
index fa9a14ebdd0f84eecbcf8423a93b3e375f907a1e..7c1458f51df42be7923dbd4ca9104e2f503ff409 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -79,11 +79,6 @@ N: Oliver Brown
 E: obrown@adventnetworks.com
 D: Port to the gw8260 board
 
-N: Curt Brune
-E: curt@cucy.com
-D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
-W: http://www.cucy.com
-
 N: Jonathan De Bruyne
 E: jonathan.debruyne@siemens.atea.be
 D: Port to Siemens IAD210 board
index f4625c3f053f371c05ac495f64e653bf831b6852..12fa853cac9f948f4c72903ff016953a8a62cfea 100644 (file)
@@ -214,9 +214,7 @@ Siddarth Gore <gores@marvell.com>
 Paul Gortmaker <paul.gortmaker@windriver.com>
 
        sbc8349         MPC8349
-       sbc8540         MPC8540
        sbc8548         MPC8548
-       sbc8560         MPC8560
        sbc8641d        MPC8641D
 
 Frank Gottschling <fgottschling@eltec.de>
@@ -908,6 +906,10 @@ Michal Simek <monstr@monstr.eu>
 
        zynq            ARM ARMV7 (Zynq SoC)
 
+Lucas Stach <dev@lynxeye.de>
+
+       colibri_t20_iris        Tegra20 (ARM7 & A9 Dual Core)
+
 Nick Thompson <nick.thompson@gefanuc.com>
 
        da830evm        ARM926EJS (DA830/OMAP-L137)
index 08eecbbbcdff22746e2febc856c8045f600ec6b6..216ad02e05af532f6951ed5f75ee9f3a41f62bd0 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -260,7 +260,8 @@ LIBS-y += drivers/net/npe/libnpe.o
 endif
 LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
 LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/cramfs/libcramfs.o \
+LIBS-y += fs/cbfs/libcbfs.o \
+       fs/cramfs/libcramfs.o \
        fs/ext4/libext4fs.o \
        fs/fat/libfat.o \
        fs/fdos/libfdos.o \
@@ -514,17 +515,18 @@ $(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
 
 ifeq ($(SOC),tegra20)
 ifeq ($(CONFIG_OF_SEPARATE),y)
-$(obj)u-boot-dtb-tegra.bin:    $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(obj)u-boot.dtb
-               $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-               cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(obj)u-boot.dtb > $@
-               rm $(obj)spl/u-boot-spl-pad.bin
+nodtb=dtb
+dtbfile=$(obj)u-boot.dtb
 else
-$(obj)u-boot-nodtb-tegra.bin:  $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+nodtb=nodtb
+dtbfile=
+endif
+
+$(obj)u-boot-$(nodtb)-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(dtbfile)
                $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
-               cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
+               cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(dtbfile) > $@
                rm $(obj)spl/u-boot-spl-pad.bin
 endif
-endif
 
 ifeq ($(CONFIG_SANDBOX),y)
 GEN_UBOOT = \
@@ -533,9 +535,10 @@ GEN_UBOOT = \
                        $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
 else
 GEN_UBOOT = \
-               UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
-               sed  -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
-               cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__OBJS) \
+               UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+               sed  -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
+               cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+                       $$UNDEF_LST $(__OBJS) \
                        --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
                        -Map u-boot.map -o u-boot
 endif
@@ -568,8 +571,12 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot
 $(LDSCRIPT):   depend
                $(MAKE) -C $(dir $@) $(notdir $@)
 
-$(obj)u-boot.lds: $(LDSCRIPT)
-               $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates u-boot.lst,
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
+$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
+               $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
 
 nand_spl:      $(TIMESTAMP_FILE) $(VERSION_FILE) depend
                $(MAKE) -C nand_spl/board/$(BOARDDIR) all
@@ -748,20 +755,6 @@ $(obj).boards.depend:      boards.cfg
 lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
 ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
 
-#========================================================================
-# ARM
-#========================================================================
-
-SX1_stdout_serial_config \
-SX1_config:            unconfig
-       @mkdir -p $(obj)include
-       @if [ "$(findstring _stdout_serial_, $@)" ] ; then \
-               echo "#undef CONFIG_STDOUT_USBTTY" >> $(obj)include/config.h ; \
-       else \
-               echo "#define CONFIG_STDOUT_USBTTY" >> $(obj)include/config.h ; \
-       fi;
-       @$(MKCONFIG) -n $@ SX1 arm arm925t sx1
-
 #########################################################################
 ## ARM1176 Systems
 #########################################################################
@@ -808,6 +801,7 @@ clean:
               $(obj)board/matrix_vision/*/bootscript.img                 \
               $(obj)board/voiceblue/eeprom                               \
               $(obj)u-boot.lds                                           \
+              $(obj)include/u-boot.lst                                   \
               $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]          \
               $(obj)arch/blackfin/cpu/init.{lds,elf}
        @rm -f $(obj)include/bmp_logo.h
@@ -841,8 +835,10 @@ clobber:   tidy
        @rm -f $(obj)u-boot.dtb
        @rm -f $(obj)u-boot.sb
        @rm -f $(obj)u-boot.spr
-       @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
-       @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
+       @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
+       @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
+       @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
+       @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
        @rm -f $(obj)MLO
        @rm -f $(obj)tools/xway-swap-bytes
        @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
diff --git a/README b/README
index 61e2e1ffc7952935ee150b1397483befeff21e6a..2572add57303c5596d87d740f63edd4a494c48e9 100644 (file)
--- a/README
+++ b/README
@@ -363,6 +363,12 @@ The following options need to be configured:
                ICache only when Code runs from RAM.
 
 - 85xx CPU Options:
+               CONFIG_SYS_PPC64
+
+               Specifies that the core is a 64-bit PowerPC implementation (implements
+               the "64" category of the Power ISA). This is necessary for ePAPR
+               compliance, among other possible reasons.
+
                CONFIG_SYS_FSL_TBCLK_DIV
 
                Defines the core time base clock divider ratio compared to the
@@ -1088,7 +1094,7 @@ The following options need to be configured:
                CONFIG_CALXEDA_XGMAC
                Support for the Calxeda XGMAC device
 
-               CONFIG_DRIVER_LAN91C96
+               CONFIG_LAN91C96
                Support for SMSC's LAN91C96 chips.
 
                        CONFIG_LAN91C96_BASE
@@ -1098,7 +1104,7 @@ The following options need to be configured:
                        CONFIG_LAN91C96_USE_32_BIT
                        Define this to enable 32 bit addressing
 
-               CONFIG_DRIVER_SMC91111
+               CONFIG_SMC91111
                Support for SMSC's LAN91C111 chip
 
                        CONFIG_SMC91111_BASE
@@ -1320,6 +1326,13 @@ The following options need to be configured:
                This will also enable the command "fatwrite" enabling the
                user to write files to FAT.
 
+CBFS (Coreboot Filesystem) support
+               CONFIG_CMD_CBFS
+
+               Define this to enable support for reading from a Coreboot
+               filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
+               and cbfsload.
+
 - Keyboard Support:
                CONFIG_ISA_KEYBOARD
 
index 7dc1a8ec58482fe03d46935d67593d83d06e8310..41e9639d9c4cd92cfcaded97a12c5d448f75a7dd 100644 (file)
@@ -361,8 +361,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                return get_ipg_per_clk();
        case MXC_UART_CLK:
                return imx_get_uartclk();
-       case MXC_ESDHC_CLK:
+       case MXC_ESDHC1_CLK:
                return mxc_get_peri_clock(ESDHC1_CLK);
+       case MXC_ESDHC2_CLK:
+               return mxc_get_peri_clock(ESDHC2_CLK);
+       case MXC_ESDHC3_CLK:
+               return mxc_get_peri_clock(ESDHC3_CLK);
        case MXC_USB_CLK:
                return mxc_get_main_clock(USB_CLK);
        case MXC_FEC_CLK:
@@ -472,7 +476,13 @@ int cpu_mmc_init(bd_t *bis)
 int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
 #endif
        return 0;
 }
index ce7b3c9c24e1ac45e3f84ba46fc4b447aa726dd5..820614e0ea6da3c63d43c4421fa99af37921949f 100644 (file)
  */
 
 /*
- * CPU specific code
+ * cleanup_before_linux() - Prepare the CPU to jump to Linux
+ *
+ * This function is called just before we call Linux, it
+ * prepares the processor for linux
  */
-
-#include <common.h>
-#include <command.h>
-#include <clps7111.h>
-#include <asm/hardware.h>
-#include <asm/system.h>
-
-int cleanup_before_linux (void)
+int cleanup_before_linux(void)
 {
-       /*
-        * this function is called just before we call linux
-        * it prepares the processor for linux
-        *
-        * we turn off caches etc ...
-        * and we set the CPU-speed to 73 MHz - see start.S for details
-        */
-
-#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
-       disable_interrupts ();
-       /* Nothing more needed */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* No cleanup before linux for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_TEGRA)
-       /* No cleanup before linux for tegra as yet */
-#else
-#error No cleanup_before_linux() defined for this CPU type
-#endif
        return 0;
 }
index c2f898f2cc9bcec6f1da84796551749cd8bb133d..623a24b65175cfda34afd305ff1858dfb95f90ba 100644 (file)
  */
 
 #include <common.h>
-#include <clps7111.h>
-#include <asm/proc-armv/ptrace.h>
-#include <asm/hardware.h>
-
-#ifndef CONFIG_NETARM
-/* we always count down the max. */
-#define TIMER_LOAD_VAL 0xffff
-/* macro to read the 16 bit timer */
-#define READ_TIMER (IO_TC1D & 0xffff)
-
-#ifdef CONFIG_LPC2292
-#undef READ_TIMER
-#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
-#endif
-
-#else
-#define IRQEN  (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
-#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
-#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
-#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
-#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
-#endif
-
-#ifdef CONFIG_S3C4510B
-/* require interrupts for the S3C4510B */
-# ifndef CONFIG_USE_IRQ
-#  error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
-# else
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-# endif
-#endif /* CONFIG_S3C4510B */
 
 #ifdef CONFIG_USE_IRQ
 void do_irq (struct pt_regs *pt_regs)
 {
-#if defined(CONFIG_S3C4510B)
-       unsigned int pending;
-
-       while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
-               IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
-
-               /* clear pending interrupt */
-               PUT_REG( REG_INTPEND, (1<<(pending>>2)));
-       }
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* No do_irq() for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-
-    void (*pfnct)(void);
-
-    pfnct = (void (*)(void))VICVectAddr;
-
-    (*pfnct)();
-#else
-#error do_irq() not defined for this CPU type
-#endif
-}
-#endif
-
-#ifdef CONFIG_S3C4510B
-static void default_isr( void *data) {
-       printf ("default_isr():  called for IRQ %d\n", (int)data);
-}
-
-static void timer_isr( void *data) {
-       unsigned int *pTime = (unsigned int *)data;
-
-       (*pTime)++;
-       if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
-               /* toggle LED 0 */
-               PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
-       }
-
 }
 #endif
 
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* Use IntegratorAP routines in board/integratorap.c */
-#else
-
+#if defined(CONFIG_TEGRA)
 static ulong timestamp;
 static ulong lastdec;
 
-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
-int arch_interrupt_init (void)
-{
-       int i;
-
-       /* install default interrupt handlers */
-       for ( i = 0; i < N_IRQS; i++) {
-               IRQ_HANDLER[i].m_data = (void *)i;
-               IRQ_HANDLER[i].m_func = default_isr;
-       }
-
-       /* configure interrupts for IRQ mode */
-       PUT_REG( REG_INTMODE, 0x0);
-       /* clear any pending interrupts */
-       PUT_REG( REG_INTPEND, 0x1FFFFF);
-
-       lastdec = 0;
-
-       /* install interrupt handler for timer */
-       IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
-       IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
-
-       return 0;
-}
-#endif
-
 int timer_init (void)
 {
-#if defined(CONFIG_NETARM)
-       /* disable all interrupts */
-       IRQEN = 0;
-
-       /* operate timer 2 in non-prescale mode */
-       TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
-                   NETARM_GEN_TCTL_ENABLE |
-                   NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
-
-       /* set timer 2 counter */
-       lastdec = TIMER_LOAD_VAL;
-#elif defined(CONFIG_S3C4510B)
-       /* configure free running timer 0 */
-       PUT_REG( REG_TMOD, 0x0);
-       /* Stop timer 0 */
-       CLR_REG( REG_TMOD, TM0_RUN);
-
-       /* Configure for interval mode */
-       CLR_REG( REG_TMOD, TM1_TOGGLE);
-
-       /*
-        * Load Timer data register with count down value.
-        * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
-        */
-       PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
-
-       /*
-        * Enable global interrupt
-        * Enable timer0 interrupt
-        */
-       CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
-
-       /* Start timer */
-       SET_REG( REG_TMOD, TM0_RUN);
-#elif defined(CONFIG_LPC2292)
-       PUT32(T0IR, 0);         /* disable all timer0 interrupts */
-       PUT32(T0TCR, 0);        /* disable timer0 */
-       PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
-       PUT32(T0MCR, 0);
-       PUT32(T0TC, 0);
-       PUT32(T0TCR, 1);        /* enable timer0 */
-
-#elif defined(CONFIG_TEGRA)
        /* No timer routines for tegra as yet */
        lastdec = 0;
-#else
-#error No timer_init() defined for this CPU type
-#endif
        timestamp = 0;
 
-       return (0);
-}
-
-#endif /* ! IntegratorAP */
-
-/*
- * timer without interrupts
- */
-
-
-#if defined(CONFIG_NETARM) || defined(CONFIG_LPC2292)
-
-ulong get_timer (ulong base)
-{
-       return get_timer_masked () - base;
-}
-
-void __udelay (unsigned long usec)
-{
-       ulong tmo;
-
-       tmo = usec / 1000;
-       tmo *= CONFIG_SYS_HZ;
-       tmo /= 1000;
-
-       tmo += get_timer (0);
-
-       while (get_timer_masked () < tmo)
-#ifdef CONFIG_LPC2292
-               /* GJ - not sure whether this is really needed or a misunderstanding */
-               __asm__ __volatile__(" nop");
-#else
-               /*NOP*/;
-#endif
-}
-
-ulong get_timer_masked (void)
-{
-       ulong now = READ_TIMER;
-
-       if (lastdec >= now) {
-               /* normal mode */
-               timestamp += lastdec - now;
-       } else {
-               /* we have an overflow ... */
-               timestamp += lastdec + TIMER_LOAD_VAL - now;
-       }
-       lastdec = now;
-
-       return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-       ulong tmo;
-       ulong endtime;
-       signed long diff;
-
-       if (usec >= 1000) {
-               tmo = usec / 1000;
-               tmo *= CONFIG_SYS_HZ;
-               tmo /= 1000;
-       } else {
-               tmo = usec * CONFIG_SYS_HZ;
-               tmo /= (1000*1000);
-       }
-
-       endtime = get_timer_masked () + tmo;
-
-       do {
-               ulong now = get_timer_masked ();
-               diff = endtime - now;
-       } while (diff >= 0);
-}
-
-#elif defined(CONFIG_S3C4510B)
-
-ulong get_timer (ulong base)
-{
-       return timestamp - base;
-}
-
-void __udelay (unsigned long usec)
-{
-       u32 ticks;
-
-       ticks = (usec * CONFIG_SYS_HZ) / 1000000;
-
-       ticks += get_timer (0);
-
-       while (get_timer (0) < ticks)
-               /*NOP*/;
-
+       return 0;
 }
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* No timer routines for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_TEGRA)
-       /* No timer routines for tegra as yet */
-#else
-#error Timer routines not defined for this CPU type
 #endif
diff --git a/arch/arm/cpu/arm720t/lpc2292/flash.c b/arch/arm/cpu/arm720t/lpc2292/flash.c
deleted file mode 100644 (file)
index 3d2dc32..0000000
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
- *
- * Modified to remove all but the IAP-command related code by
- * Gary Jennejohn <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-/* IAP commands use 32 bytes at the top of CPU internal sram, we
-   use 512 bytes below that */
-#define COPY_BUFFER_LOCATION 0x40003de0
-
-#define IAP_LOCATION 0x7ffffff1
-#define IAP_CMD_PREPARE 50
-#define IAP_CMD_COPY 51
-#define IAP_CMD_ERASE 52
-#define IAP_CMD_CHECK 53
-#define IAP_CMD_ID 54
-#define IAP_CMD_VERSION 55
-#define IAP_CMD_COMPARE 56
-
-#define IAP_RET_CMD_SUCCESS 0
-
-static unsigned long command[5];
-static unsigned long result[2];
-
-extern void iap_entry(unsigned long * command, unsigned long * result);
-
-/*-----------------------------------------------------------------------
- *
- */
-static int get_flash_sector(flash_info_t * info, ulong flash_addr)
-{
-       int i;
-
-       for(i = 1; i < (info->sector_count); i++) {
-               if (flash_addr < (info->start[i]))
-                       break;
-       }
-
-       return (i-1);
-}
-
-/*-----------------------------------------------------------------------
- * This function assumes that flash_addr is aligned on 512 bytes boundary
- * in flash. This function also assumes that prepare have been called
- * for the sector in question.
- */
-int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
-{
-       int first_sector;
-       int last_sector;
-
-       first_sector = get_flash_sector(info, flash_addr);
-       last_sector = get_flash_sector(info, flash_addr + 512 - 1);
-
-       /* prepare sectors for write */
-       command[0] = IAP_CMD_PREPARE;
-       command[1] = first_sector;
-       command[2] = last_sector;
-       iap_entry(command, result);
-       if (result[0] != IAP_RET_CMD_SUCCESS) {
-               printf("IAP prepare failed\n");
-               return ERR_PROG_ERROR;
-       }
-
-       command[0] = IAP_CMD_COPY;
-       command[1] = flash_addr;
-       command[2] = COPY_BUFFER_LOCATION;
-       command[3] = 512;
-       command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
-       iap_entry(command, result);
-       if (result[0] != IAP_RET_CMD_SUCCESS) {
-               printf("IAP copy failed\n");
-               return 1;
-       }
-
-       return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-       int flag;
-       int prot;
-       int sect;
-
-       prot = 0;
-       for (sect = s_first; sect <= s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-       if (prot)
-               return ERR_PROTECTED;
-
-
-       flag = disable_interrupts();
-
-       printf ("Erasing %d sectors starting at sector %2d.\n"
-       "This make take some time ... ",
-       s_last - s_first + 1, s_first);
-
-       command[0] = IAP_CMD_PREPARE;
-       command[1] = s_first;
-       command[2] = s_last;
-       iap_entry(command, result);
-       if (result[0] != IAP_RET_CMD_SUCCESS) {
-               printf("IAP prepare failed\n");
-               return ERR_PROTECTED;
-       }
-
-       command[0] = IAP_CMD_ERASE;
-       command[1] = s_first;
-       command[2] = s_last;
-       command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
-       iap_entry(command, result);
-       if (result[0] != IAP_RET_CMD_SUCCESS) {
-               printf("IAP erase failed\n");
-               return ERR_PROTECTED;
-       }
-
-       if (flag)
-               enable_interrupts();
-
-       return ERR_OK;
-}
-
-int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr,
-                       ulong cnt)
-{
-       int first_copy_size;
-       int last_copy_size;
-       int first_block;
-       int last_block;
-       int nbr_mid_blocks;
-       uchar memmap_value;
-       ulong i;
-       uchar* src_org;
-       uchar* dst_org;
-       int ret = ERR_OK;
-
-       src_org = src;
-       dst_org = (uchar*)addr;
-
-       first_block = addr / 512;
-       last_block = (addr + cnt) / 512;
-       nbr_mid_blocks = last_block - first_block - 1;
-
-       first_copy_size = 512 - (addr % 512);
-       last_copy_size = (addr + cnt) % 512;
-
-       debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
-               "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
-       (ulong)(first_block * 512),
-       (ulong)COPY_BUFFER_LOCATION,
-       (ulong)src,
-       (ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-       first_copy_size,
-       (ulong)COPY_BUFFER_LOCATION,
-       (ulong)(first_block * 512));
-
-       /* copy first block */
-       memcpy((void*)COPY_BUFFER_LOCATION,
-               (void*)(first_block * 512), 512);
-       memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-               src, first_copy_size);
-       lpc2292_copy_buffer_to_flash(info, first_block * 512);
-       src += first_copy_size;
-       addr += first_copy_size;
-
-       /* copy middle blocks */
-       for (i = 0; i < nbr_mid_blocks; i++) {
-               debug("copy middle block: %lX -> %lX 512 bytes, "
-               "%lX -> %lX 512 bytes\n",
-               (ulong)src,
-               (ulong)COPY_BUFFER_LOCATION,
-               (ulong)COPY_BUFFER_LOCATION,
-               (ulong)addr);
-
-               memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
-               lpc2292_copy_buffer_to_flash(info, addr);
-               src += 512;
-               addr += 512;
-       }
-
-
-       if (last_copy_size > 0) {
-               debug("copy last block: (1) %lX -> %lX 0x200 bytes, "
-               "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
-               (ulong)(last_block * 512),
-               (ulong)COPY_BUFFER_LOCATION,
-               (ulong)src,
-               (ulong)(COPY_BUFFER_LOCATION),
-               last_copy_size,
-               (ulong)COPY_BUFFER_LOCATION,
-               (ulong)addr);
-
-               /* copy last block */
-               memcpy((void*)COPY_BUFFER_LOCATION,
-                       (void*)(last_block * 512), 512);
-               memcpy((void*)COPY_BUFFER_LOCATION,
-                       src, last_copy_size);
-               lpc2292_copy_buffer_to_flash(info, addr);
-       }
-
-       /* verify write */
-       memmap_value = GET8(MEMMAP);
-
-       disable_interrupts();
-
-       PUT8(MEMMAP, 01);               /* we must make sure that initial 64
-                                                          bytes are taken from flash when we
-                                                          do the compare */
-
-       for (i = 0; i < cnt; i++) {
-               if (*dst_org != *src_org){
-                       printf("Write failed. Byte %lX differs\n", i);
-                       ret = ERR_PROG_ERROR;
-                       break;
-               }
-               dst_org++;
-               src_org++;
-       }
-
-       PUT8(MEMMAP, memmap_value);
-       enable_interrupts();
-
-       return ret;
-}
diff --git a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S
deleted file mode 100644 (file)
index c31d519..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-IAP_ADDRESS:   .word   0x7FFFFFF1
-
-.globl iap_entry
-iap_entry:
-       ldr     r2, IAP_ADDRESS
-       bx      r2
-       mov     pc, lr
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc.c b/arch/arm/cpu/arm720t/lpc2292/mmc.c
deleted file mode 100644 (file)
index beaffe9..0000000
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <mmc.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <part.h>
-#include <fat.h>
-#include "mmc_hw.h"
-#include <asm/arch/spi.h>
-
-#ifdef CONFIG_MMC
-
-#undef MMC_DEBUG
-
-static block_dev_desc_t mmc_dev;
-
-/* these are filled out by a call to mmc_hw_get_parameters */
-static int hw_size;            /* in kbytes */
-static int hw_nr_sects;
-static int hw_sect_size;       /* in bytes */
-
-block_dev_desc_t * mmc_get_dev(int dev)
-{
-       return (block_dev_desc_t *)(&mmc_dev);
-}
-
-unsigned long mmc_block_read(int dev,
-                            unsigned long start,
-                            lbaint_t blkcnt,
-                            void *buffer)
-{
-       unsigned long rc = 0;
-       unsigned char *p = (unsigned char *)buffer;
-       unsigned long i;
-       unsigned long addr = start;
-
-#ifdef MMC_DEBUG
-       printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
-                (unsigned long)blkcnt);
-#endif
-
-       for(i = 0; i < (unsigned long)blkcnt; i++) {
-#ifdef MMC_DEBUG
-               printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
-#endif
-               (void)mmc_read_sector(addr, p);
-               rc++;
-               addr++;
-               p += hw_sect_size;
-       }
-
-       return rc;
-}
-
-/*-----------------------------------------------------------------------------
- * Read hardware paramterers (sector size, size, number of sectors)
- */
-static int mmc_hw_get_parameters(void)
-{
-       unsigned char csddata[16];
-       unsigned int sizemult;
-       unsigned int size;
-
-       mmc_read_csd(csddata);
-       hw_sect_size = 1<<(csddata[5] & 0x0f);
-       size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
-       sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
-       hw_nr_sects = (size+1)*(1<<(sizemult+2));
-       hw_size = hw_nr_sects*hw_sect_size/1024;
-
-#ifdef MMC_DEBUG
-       printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
-                "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
-#endif
-
-       return 0;
-}
-
-int mmc_legacy_init(int verbose)
-{
-       int ret = -ENODEV;
-
-       if (verbose)
-               printf("mmc_legacy_init\n");
-
-       spi_init();
-       /* this meeds to be done twice */
-       mmc_hw_init();
-       udelay(1000);
-       mmc_hw_init();
-
-       mmc_hw_get_parameters();
-
-       mmc_dev.if_type = IF_TYPE_MMC;
-       mmc_dev.part_type = PART_TYPE_DOS;
-       mmc_dev.dev = 0;
-       mmc_dev.lun = 0;
-       mmc_dev.type = 0;
-       mmc_dev.blksz = hw_sect_size;
-       mmc_dev.lba = hw_nr_sects;
-       sprintf((char*)mmc_dev.vendor, "Unknown vendor");
-       sprintf((char*)mmc_dev.product, "Unknown product");
-       sprintf((char*)mmc_dev.revision, "N/A");
-       mmc_dev.removable = 0;  /* should be true??? */
-       mmc_dev.block_read = mmc_block_read;
-
-       fat_register_device(&mmc_dev, 1);
-
-       ret = 0;
-
-       return ret;
-}
-
-#endif /* CONFIG_MMC */
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
deleted file mode 100644 (file)
index bd6a5b1..0000000
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
-    This code was original written by Ulrich Radig and modified by
-    Embedded Artists AB (www.embeddedartists.com).
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
-#define MMC_Disable() PUT32(IO1SET, 1l << 22)
-#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
-
-static unsigned char Write_Command_MMC (unsigned char *CMD);
-static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
-                   unsigned short int Bytes);
-
-/* initialize the hardware */
-int mmc_hw_init(void)
-{
-       unsigned long a;
-       unsigned short int Timeout = 0;
-       unsigned char b;
-       unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
-
-       /* set-up GPIO and SPI */
-       (*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
-       (*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
-
-       MMC_Disable();
-
-       spi_lock();
-       spi_set_clock(248);
-       spi_set_cfg(0, 1, 0);
-       MMC_Enable();
-
-       /* waste some time */
-       for(a=0; a < 20000; a++)
-               asm("nop");
-
-       /* Put the MMC/SD-card into SPI-mode */
-       for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
-               spi_write(0xff);
-
-       /* Sends command CMD0 to MMC/SD-card */
-       while (Write_Command_MMC(CMD) != 1) {
-               if (Timeout++ > 200) {
-                       MMC_Disable();
-                       spi_unlock();
-                       return(1); /* Abort with command 1 (return 1) */
-               }
-       }
-       /* Sends Command CMD1 an MMC/SD-card */
-       Timeout = 0;
-       CMD[0] = 0x41;/* Command 1 */
-       CMD[5] = 0xFF;
-
-       while (Write_Command_MMC(CMD) != 0) {
-               if (Timeout++ > 200) {
-                       MMC_Disable();
-                       spi_unlock();
-                       return (2); /* Abort with command 2 (return 2) */
-               }
-       }
-
-       MMC_Disable();
-       spi_unlock();
-
-       return 0;
-}
-
-/* ############################################################################
-   Sends a command to the MMC/SD-card
-   ######################################################################### */
-static unsigned char Write_Command_MMC (unsigned char *CMD)
-{
-       unsigned char a, tmp = 0xff;
-       unsigned short int Timeout = 0;
-
-       MMC_Disable();
-       spi_write(0xFF);
-       MMC_Enable();
-
-       for (a = 0; a < 0x06; a++)
-               spi_write(*CMD++);
-
-       while (tmp == 0xff) {
-               tmp = spi_read();
-               if (Timeout++ > 5000)
-                 break;
-       }
-
-       return (tmp);
-}
-
-/* ############################################################################
-   Routine to read the CID register from the MMC/SD-card (16 bytes)
-   ######################################################################### */
-void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
-       int Bytes)
-{
-       unsigned short int a;
-
-       spi_lock();
-       mmc_spi_cfg();
-       MMC_Enable();
-
-       if (Write_Command_MMC(CMD) != 0) {
-               MMC_Disable();
-               spi_unlock();
-               return;
-       }
-
-       while (spi_read() != 0xfe) {};
-       for (a = 0; a < Bytes; a++)
-               *Buffer++ = spi_read();
-
-       /* Read the CRC-byte */
-       spi_read(); /* CRC - byte is discarded */
-       spi_read(); /* CRC - byte is discarded */
-       /* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
-       MMC_Disable();
-       spi_unlock();
-
-       return;
-}
-
-/* ############################################################################
-   Routine to read a block (512 bytes) from the MMC/SD-card
-   ######################################################################### */
-unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
-{
-       /* Command 16 to read aBlocks from the MMC/SD - caed */
-       unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
-
-       /* The address on the MMC/SD-card is in bytes,
-       addr is transformed from blocks to bytes and the result is
-       placed into the command */
-
-       addr = addr << 9; /* addr = addr * 512 */
-
-       CMD[1] = ((addr & 0xFF000000) >> 24);
-       CMD[2] = ((addr & 0x00FF0000) >> 16);
-       CMD[3] = ((addr & 0x0000FF00) >> 8 );
-
-       MMC_Read_Block(CMD, Buffer, 512);
-
-       return (0);
-}
-
-/* ############################################################################
-   Routine to write a block (512 byte) to the MMC/SD-card
-   ######################################################################### */
-unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
-{
-       unsigned char tmp, a;
-       unsigned short int b;
-       /* Command 24 to write a block to the MMC/SD - card */
-       unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
-
-       /* The address on the MMC/SD-card is in bytes,
-       addr is transformed from blocks to bytes and the result is
-       placed into the command */
-
-       addr = addr << 9; /* addr = addr * 512 */
-
-       CMD[1] = ((addr & 0xFF000000) >> 24);
-       CMD[2] = ((addr & 0x00FF0000) >> 16);
-       CMD[3] = ((addr & 0x0000FF00) >> 8 );
-
-       spi_lock();
-       mmc_spi_cfg();
-       MMC_Enable();
-
-       /* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
-       tmp = Write_Command_MMC(CMD);
-       if (tmp != 0) {
-               MMC_Disable();
-               spi_unlock();
-               return(tmp);
-       }
-
-       /* Do a short delay and send a clock-pulse to the MMC/SD-card */
-       for (a = 0; a < 100; a++)
-               spi_read();
-
-       /* Send a start byte to the MMC/SD-card */
-       spi_write(0xFE);
-
-       /* Write the block (512 bytes) to the MMC/SD-card */
-       for (b = 0; b < 512; b++)
-               spi_write(*Buffer++);
-
-       /* write the CRC-Byte */
-       spi_write(0xFF); /* write a dummy CRC */
-       spi_write(0xFF); /* CRC code is not used */
-
-       /* Wait for MMC/SD-card busy */
-       while (spi_read() != 0xff) {};
-
-       /* set MMC_Chip_Select to high (MMC/SD-card inactive) */
-       MMC_Disable();
-       spi_unlock();
-       return (0);
-}
-
-/* #########################################################################
-   Routine to read the CSD register from the MMC/SD-card (16 bytes)
-   ######################################################################### */
-unsigned char mmc_read_csd (unsigned char *Buffer)
-{
-       /* Command to read the CSD register */
-       unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
-
-       MMC_Read_Block(CMD, Buffer, 16);
-
-       return (0);
-}
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
deleted file mode 100644 (file)
index 3687dbf..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
-    This module implements a linux character device driver for the 24c256 chip.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef _MMC_HW_
-#define _MMC_HW_
-
-unsigned char mmc_read_csd(unsigned char *Buffer);
-unsigned char mmc_read_sector (unsigned long addr,
-                              unsigned char *Buffer);
-unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
-int mmc_hw_init(void);
-
-#endif /* _MMC_HW_ */
diff --git a/arch/arm/cpu/arm720t/lpc2292/spi.c b/arch/arm/cpu/arm720t/lpc2292/spi.c
deleted file mode 100644 (file)
index d296bda..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-    This module implements an interface to the SPI on the lpc22xx.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-unsigned long spi_flags;
-unsigned char spi_idle = 0x00;
-
-int spi_init(void)
-{
-       unsigned long pinsel0_value;
-
-       /* activate spi pins */
-       pinsel0_value = GET32(PINSEL0);
-       pinsel0_value &= ~(0xFFl << 8);
-       pinsel0_value |= (0x55l << 8);
-       PUT32(PINSEL0, pinsel0_value);
-
-       return 0;
-}
diff --git a/arch/arm/cpu/arm720t/s3c4510b/cache.c b/arch/arm/cpu/arm720t/s3c4510b/cache.c
deleted file mode 100644 (file)
index 104d287..0000000
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-void icache_enable (void)
-{
-       s32 i;
-
-       /* disable all cache bits */
-       CLR_REG( REG_SYSCFG, 0x3F);
-
-       /* 8KB cache, write enable */
-       SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
-
-       /* clear TAG RAM bits */
-       for ( i = 0; i < 256; i++)
-         PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
-
-       /* clear SET0 RAM */
-       for(i=0; i < 1024; i++)
-         PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
-
-       /* clear SET1 RAM */
-       for(i=0; i < 1024; i++)
-         PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
-
-       /* enable cache */
-       SET_REG( REG_SYSCFG, CACHE_ENABLE);
-
-}
-
-void icache_disable (void)
-{
-       /* disable all cache bits */
-       CLR_REG( REG_SYSCFG, 0x3F);
-}
-
-int icache_status (void)
-{
-       return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
-}
-
-void dcache_enable (void)
-{
-       /* we don't have seperate instruction/data caches */
-       icache_enable();
-}
-
-void dcache_disable (void)
-{
-       /* we don't have seperate instruction/data caches */
-       icache_disable();
-}
-
-int dcache_status (void)
-{
-       /* we don't have seperate instruction/data caches */
-       return icache_status();
-}
index 2f914e9b4e2fd6317861831af025693990c9495a..c2a7763fff00a2b4e974dacf7b31b144641c6e2c 100644 (file)
@@ -43,11 +43,7 @@ _start: b    reset
        ldr     pc, _software_interrupt
        ldr     pc, _prefetch_abort
        ldr     pc, _data_abort
-#ifdef CONFIG_LPC2292
-       .word   0xB4405F76 /* 2's complement of the checksum of the vectors */
-#else
        ldr     pc, _not_used
-#endif
        ldr     pc, _irq
        ldr     pc, _fiq
 
@@ -151,10 +147,6 @@ reset:
        bl      cpu_init_crit
 #endif
 
-#ifdef CONFIG_LPC2292
-       bl      lowlevel_init
-#endif
-
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
        ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
@@ -291,148 +283,9 @@ _dynsym_start_ofs:
  *************************************************************************
  */
 
-#if defined(CONFIG_LPC2292)
-PLLCFG_ADR:    .word   PLLCFG
-PLLFEED_ADR:   .word   PLLFEED
-PLLCON_ADR:    .word   PLLCON
-PLLSTAT_ADR:   .word   PLLSTAT
-VPBDIV_ADR:    .word   VPBDIV
-MEMMAP_ADR:    .word   MEMMAP
-
-#endif
-
 cpu_init_crit:
-#if defined(CONFIG_NETARM)
-       /*
-        * prior to software reset : need to set pin PORTC4 to be *HRESET
-        */
-       ldr     r0, =NETARM_GEN_MODULE_BASE
-       ldr     r1, =(NETARM_GEN_PORT_MODE(0x10) | \
-                       NETARM_GEN_PORT_DIR(0x10))
-       str     r1, [r0, #+NETARM_GEN_PORTC]
-       /*
-        * software reset : see HW Ref. Guide 8.2.4 : Software Service register
-        *                  for an explanation of this process
-        */
-       ldr     r0, =NETARM_GEN_MODULE_BASE
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETA
-       str     r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETB
-       str     r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETA
-       str     r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETB
-       str     r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-       /*
-        * setup PLL and System Config
-        */
-       ldr     r0, =NETARM_GEN_MODULE_BASE
-
-       ldr     r1, =(  NETARM_GEN_SYS_CFG_LENDIAN | \
-                       NETARM_GEN_SYS_CFG_BUSFULL | \
-                       NETARM_GEN_SYS_CFG_USER_EN | \
-                       NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
-                       NETARM_GEN_SYS_CFG_BUSARB_INT | \
-                       NETARM_GEN_SYS_CFG_BUSMON_EN )
-
-       str     r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
-
-#ifndef CONFIG_NETARM_PLL_BYPASS
-       ldr     r1, =(  NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
-                       NETARM_GEN_PLL_CTL_POLTST_DEF | \
-                       NETARM_GEN_PLL_CTL_INDIV(1) | \
-                       NETARM_GEN_PLL_CTL_ICP_DEF | \
-                       NETARM_GEN_PLL_CTL_OUTDIV(2) )
-       str     r1, [r0, #+NETARM_GEN_PLL_CONTROL]
-#endif
-
-       /*
-        * mask all IRQs by clearing all bits in the INTMRs
-        */
-       mov     r1, #0
-       ldr     r0, =NETARM_GEN_MODULE_BASE
-       str     r1, [r0, #+NETARM_GEN_INTR_ENABLE]
-
-#elif defined(CONFIG_S3C4510B)
 
-       /*
-        * Mask off all IRQ sources
-        */
-       ldr     r1, =REG_INTMASK
-       ldr     r0, =0x3FFFFF
-       str     r0, [r1]
-
-       /*
-        * Disable Cache
-        */
-       ldr r0, =REG_SYSCFG
-       ldr r1, =0x83ffffa0     /* cache-disabled  */
-       str r1, [r0]
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* No specific initialisation for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-       /* Set-up PLL */
-       mov     r3, #0xAA
-       mov     r4, #0x55
-       /* First disconnect and disable the PLL */
-       ldr     r0, PLLCON_ADR
-       mov     r1, #0x00
-       str     r1, [r0]
-       ldr     r0, PLLFEED_ADR /* start feed sequence */
-       str     r3, [r0]
-       str     r4, [r0]        /* feed sequence done */
-       /* Set new M and P values */
-       ldr     r0, PLLCFG_ADR
-       mov     r1, #0x23       /* M=4 and P=2 */
-       str     r1, [r0]
-       ldr     r0, PLLFEED_ADR /* start feed sequence */
-       str     r3, [r0]
-       str     r4, [r0]        /* feed sequence done */
-       /* Then enable the PLL */
-       ldr     r0, PLLCON_ADR
-       mov     r1, #0x01       /* PLL enable bit */
-       str     r1, [r0]
-       ldr     r0, PLLFEED_ADR /* start feed sequence */
-       str     r3, [r0]
-       str     r4, [r0]        /* feed sequence done */
-       /* Wait for the lock */
-       ldr     r0, PLLSTAT_ADR
-       mov     r1, #0x400      /* lock bit */
-lock_loop:
-       ldr     r2, [r0]
-       and     r2, r1, r2
-       cmp     r2, #0
-       beq     lock_loop
-       /* And finally connect the PLL */
-       ldr     r0, PLLCON_ADR
-       mov     r1, #0x03       /* PLL enable bit and connect bit */
-       str     r1, [r0]
-       ldr     r0, PLLFEED_ADR /* start feed sequence */
-       str     r3, [r0]
-       str     r4, [r0]        /* feed sequence done */
-       /* Set-up VPBDIV register */
-       ldr     r0, VPBDIV_ADR
-       mov     r1, #0x01       /* VPB clock is same as process clock */
-       str     r1, [r0]
-#elif defined(CONFIG_TEGRA)
-       /* No cpu_init_crit for tegra as yet */
-#else
-#error No cpu_init_crit() defined for current CPU type
-#endif
-
-#ifdef CONFIG_ARM7_REVD
-       /* set clock speed */
-       /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
-       /* !!! not doing DRAM refresh properly! */
-       ldr     r0, SYSCON3
-       ldr     r1, [r0]
-       bic     r1, r1, #CLKCTL
-       orr     r1, r1, #CLKCTL_36
-       str     r1, [r0]
-#endif
-
-#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA)
+#if !defined(CONFIG_TEGRA)
        mov     ip, lr
        /*
         * before relocating, we have to setup RAM timing
@@ -610,39 +463,3 @@ fiq:
 
 #endif
 #endif /* CONFIG_SPL_BUILD */
-
-#if defined(CONFIG_NETARM)
-       .align  5
-.globl reset_cpu
-reset_cpu:
-       ldr     r1, =NETARM_MEM_MODULE_BASE
-       ldr     r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
-       ldr     r1, =0xFFFFF000
-       and     r0, r1, r0
-       ldr     r1, =(relocate-CONFIG_SYS_TEXT_BASE)
-       add     r0, r1, r0
-       ldr     r4, =NETARM_GEN_MODULE_BASE
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETA
-       str     r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETB
-       str     r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETA
-       str     r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETB
-       str     r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-       mov     pc, r0
-#elif defined(CONFIG_S3C4510B)
-/* Nothing done here as reseting the CPU is board specific, depending
- * on external peripherals such as watchdog timers, etc. */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* No specific reset actions for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-       .align  5
-.globl reset_cpu
-reset_cpu:
-       mov     pc, r0
-#elif defined(CONFIG_TEGRA)
-       /* No specific reset actions for tegra as yet */
-#else
-#error No reset_cpu() defined for current CPU type
-#endif
index 0d37ce83c8418a70d4d541db4e0899a4b9a1a9f1..c280ab7d0f9c89bc60fec15077709087999da0fe 100644 (file)
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <nand.h>
-#include <mmc.h>
-#include <fat.h>
-#include <version.h>
-#include <i2c.h>
-#include <image.h>
-#include <malloc.h>
-#include <linux/compiler.h>
 #include "cpu.h"
+#include <spl.h>
 
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/board.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
-#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch/spl.h>
 
-DECLARE_GLOBAL_DATA_PTR;
 
-/* Define global data structure pointer to it*/
-static gd_t gdata __attribute__ ((section(".data")));
-static bd_t bdata __attribute__ ((section(".data")));
-
-inline void hang(void)
+void spl_board_init(void)
 {
-       puts("### ERROR ### Please RESET the board ###\n");
-       for (;;)
-               ;
-}
+       struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+
+       /* enable JTAG */
+       writel(0xC0, &pmt->pmt_cfg_ctl);
 
-void board_init_f(ulong dummy)
-{
        board_init_uart_f();
 
        /* Initialize periph GPIOs */
        gpio_early_init_uart();
 
-       /*
-        * We call relocate_code() with relocation target same as the
-        * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
-        * skipped. Instead, only .bss initialization will happen. That's
-        * all we need
-        */
-       debug(">>board_init_f()\n");
-       relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
+       clock_early_init();
+       preloader_console_init();
 }
 
-/* This requires UART clocks to be enabled */
-static void preloader_console_init(void)
+u32 spl_boot_device(void)
 {
-       const char *u_boot_rev = U_BOOT_VERSION;
-
-       gd = &gdata;
-       gd->bd = &bdata;
-       gd->flags |= GD_FLG_RELOC;
-       gd->baudrate = CONFIG_BAUDRATE;
-
-       serial_init();          /* serial communications setup */
-
-       gd->have_console = 1;
-
-       /* Avoid a second "U-Boot" coming from this string */
-       u_boot_rev = &u_boot_rev[7];
-
-       printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
-               U_BOOT_TIME);
+       return BOOT_DEVICE_RAM;
 }
 
-void board_init_r(gd_t *id, ulong dummy)
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
-       struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-
-       /* enable JTAG */
-       writel(0xC0, &pmt->pmt_cfg_ctl);
-
-       debug(">>spl:board_init_r()\n");
-
-       mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
-                       CONFIG_SYS_SPL_MALLOC_SIZE);
-
-#ifdef CONFIG_SPL_BOARD_INIT
-       spl_board_init();
-#endif
+       debug("image entry point: 0x%X\n", spl_image->entry_point);
 
-       clock_early_init();
-       serial_init();
-       preloader_console_init();
-
-       start_cpu((u32)CONFIG_SYS_TEXT_BASE);
+       start_cpu((u32)spl_image->entry_point);
        halt_avp();
-       /* not reached */
-}
-
-int board_usb_init(const void *blob)
-{
-       return 0;
 }
index dc6ba34082ecd33e58e8b989f83e82b84a3fe6f2..008ae891cafd8e47b8dc44ad9fc4b0918f37cdb1 100644 (file)
@@ -48,9 +48,11 @@ SECTIONS
        .got : { *(.got) }
 
        . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
        __bss_start = .;
index e9f1227dd6038aeeee8b7e8b9f76791b1b6284db..1bba571077740cd131ef46df4fe1663246e2c650 100644 (file)
@@ -72,10 +72,10 @@ lowlevel_init:
         * enable UART for early debug trace
         */
        ldr     r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
-       mov     r2, #0xd9
-       str     r2, [r1]                /* 115200 baud */
+       mov     r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
+       str     r2, [r1]
        ldr     r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
-       mov     r2, #0x03
+       mov     r2, #KS8695_UART_LINEC_WLEN8
        str     r2, [r1]                /* 8 data bits, no parity, 1 stop */
        ldr     r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
        mov     r2, #0x41
index 6d77219d0daeca8bb75fcd59a363a260a1b86faa..93485523b585077e48a9ca03a6d163f80ed5f77e 100644 (file)
@@ -118,6 +118,21 @@ void at91_serial2_hw_init(void)
        writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
+void at91_mci_hw_init(void)
+{
+       /* Initialize the MCI0 */
+       at91_set_a_periph(AT91_PIO_PORTA, 17, 1);       /* MCCK */
+       at91_set_a_periph(AT91_PIO_PORTA, 16, 1);       /* MCCDA */
+       at91_set_a_periph(AT91_PIO_PORTA, 15, 1);       /* MCDA0 */
+       at91_set_a_periph(AT91_PIO_PORTA, 18, 1);       /* MCDA1 */
+       at91_set_a_periph(AT91_PIO_PORTA, 19, 1);       /* MCDA2 */
+       at91_set_a_periph(AT91_PIO_PORTA, 20, 1);       /* MCDA3 */
+
+       /* Enable clock for MCI0 */
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+}
+
 #ifdef CONFIG_ATMEL_SPI
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
index f8ea38c03d4758f261e063b710273e6ab66ac9e4..6dc681a313988550f78399232d6a6a7bcdff57ba 100644 (file)
@@ -50,9 +50,10 @@ SECTIONS
        }
 
        . = ALIGN(4);
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       .u_boot_list : {
+               #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
index afd3381e1675bd33457215f523d928590fb179f3..f3bd5e736757e756a4829206164052513d42e717 100644 (file)
@@ -50,9 +50,10 @@ SECTIONS
        }
 
        . = ALIGN(4);
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       .u_boot_list : {
+               #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
index 2709860ca274884302c88a895faf00ed97cdb999..1c9223fa0783072f77a4aabdb4db225c0ae49856 100644 (file)
@@ -338,7 +338,7 @@ static u32 get_ipg_per_clk(void)
 /* Get the output clock rate of a standard PLL MUX for peripherals. */
 static u32 get_standard_pll_sel_clk(u32 clk_sel)
 {
-       u32 freq;
+       u32 freq = 0;
 
        switch (clk_sel & 0x3) {
        case 0:
index 529e35b4405aa5f611e5232ad8c6dec49bd4eb91..29ec95797baebacf4ea849da93291f624cf9abf5 100644 (file)
 
 .section ".text.init", "x"
 
+.macro init_arm_erratum
+       /* ARM erratum ID #468414 */
+       mrc 15, 0, r1, c1, c0, 1
+       orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+       mcr 15, 0, r1, c1, c0, 1
+.endm
+
 /*
  * L2CC Cache setup/invalidation/disable
  */
@@ -162,9 +169,9 @@ setup_pll_func:
 .endm
 
 .macro init_clock
+#if defined (CONFIG_MX51)
        ldr r0, =CCM_BASE_ADDR
 
-#if defined(CONFIG_MX51)
        /* Gate of clocks to the peripherals first */
        ldr r1, =0x3FFFFFFF
        str r1, [r0, #CLKCTL_CCGR0]
@@ -190,21 +197,6 @@ setup_pll_func:
 1:     ldr r1, [r0, #CLKCTL_CDHIPR]
        cmp r1, #0x0
        bne 1b
-#else
-       ldr r1, =0x3FFFFFFF
-       str r1, [r0, #CLKCTL_CCGR0]
-       str r4, [r0, #CLKCTL_CCGR1]
-       str r4, [r0, #CLKCTL_CCGR2]
-       str r4, [r0, #CLKCTL_CCGR3]
-       str r4, [r0, #CLKCTL_CCGR7]
-
-       ldr r1, =0x00030000
-       str r1, [r0, #CLKCTL_CCGR4]
-       ldr r1, =0x00FFF030
-       str r1, [r0, #CLKCTL_CCGR5]
-       ldr r1, =0x0F00030F
-       str r1, [r0, #CLKCTL_CCGR6]
-#endif
 
        /* Switch ARM to step clock */
        mov r1, #0x4
@@ -217,7 +209,6 @@ setup_pll_func:
        setup_pll PLL1_BASE_ADDR, 800
 #endif
 
-#if defined(CONFIG_MX51)
        setup_pll PLL3_BASE_ADDR, 665
 
        /* Switch peripheral to PLL 3 */
@@ -234,7 +225,7 @@ setup_pll_func:
        str r1, [r0, #CLKCTL_CBCDR]
        ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
        str r1, [r0, #CLKCTL_CBCMR]
-#endif
+
        setup_pll PLL3_BASE_ADDR, 216
 
        /* Set the platform clock dividers */
@@ -244,21 +235,17 @@ setup_pll_func:
 
        ldr r0, =CCM_BASE_ADDR
 
-#if defined(CONFIG_MX51)
        /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
        ldr r3, [r4, #ROM_SI_REV]
        cmp r3, #0x10
        movls r1, #0x1
        movhi r1, #0
-#else
-       mov r1, #0
-#endif
+
        str r1, [r0, #CLKCTL_CACRR]
 
        /* Switch ARM back to PLL 1 */
        str r4, [r0, #CLKCTL_CCSR]
 
-#if defined(CONFIG_MX51)
        /* setup the rest */
        /* Use lp_apm (24MHz) source for perclk */
        ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
@@ -266,7 +253,6 @@ setup_pll_func:
        /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
        ldr r1, =CONFIG_SYS_CLKTL_CBCDR
        str r1, [r0, #CLKCTL_CBCDR]
-#endif
 
        /* Restore the default values in the Gate registers */
        ldr r1, =0xFFFFFFFF
@@ -277,47 +263,127 @@ setup_pll_func:
        str r1, [r0, #CLKCTL_CCGR4]
        str r1, [r0, #CLKCTL_CCGR5]
        str r1, [r0, #CLKCTL_CCGR6]
-#if defined(CONFIG_MX53)
-       str r1, [r0, #CLKCTL_CCGR7]
-#endif
 
-#if defined(CONFIG_MX51)
        /* Use PLL 2 for UART's, get 66.5MHz from it */
        ldr r1, =0xA5A2A020
        str r1, [r0, #CLKCTL_CSCMR1]
        ldr r1, =0x00C30321
        str r1, [r0, #CLKCTL_CSCDR1]
-#elif defined(CONFIG_MX53)
+       /* make sure divider effective */
+1:     ldr r1, [r0, #CLKCTL_CDHIPR]
+       cmp r1, #0x0
+       bne 1b
+
+       str r4, [r0, #CLKCTL_CCDR]
+
+       /* for cko - for ARM div by 8 */
+       mov r1, #0x000A0000
+       add r1, r1, #0x00000F0
+       str r1, [r0, #CLKCTL_CCOSR]
+#else  /* CONFIG_MX53 */
+       ldr r0, =CCM_BASE_ADDR
+
+       /* Gate of clocks to the peripherals first */
+       ldr r1, =0x3FFFFFFF
+       str r1, [r0, #CLKCTL_CCGR0]
+       str r4, [r0, #CLKCTL_CCGR1]
+       str r4, [r0, #CLKCTL_CCGR2]
+       str r4, [r0, #CLKCTL_CCGR3]
+       str r4, [r0, #CLKCTL_CCGR7]
+       ldr r1, =0x00030000
+       str r1, [r0, #CLKCTL_CCGR4]
+       ldr r1, =0x00FFF030
+       str r1, [r0, #CLKCTL_CCGR5]
+       ldr r1, =0x0F00030F
+       str r1, [r0, #CLKCTL_CCGR6]
+
+       /* Switch ARM to step clock */
+       mov r1, #0x4
+       str r1, [r0, #CLKCTL_CCSR]
+
+       setup_pll PLL1_BASE_ADDR, 800
+
+        setup_pll PLL3_BASE_ADDR, 400
+
+        /* Switch peripheral to PLL3 */
+        ldr r0, =CCM_BASE_ADDR
+        ldr r1, =0x00015154
+        str r1, [r0, #CLKCTL_CBCMR]
+        ldr r1, =0x02888945
+        orr r1, r1, #(1 << 16)
+        str r1, [r0, #CLKCTL_CBCDR]
+        /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+        cmp r1, #0x0
+        bne 1b
+
+        setup_pll PLL2_BASE_ADDR, 400
+
        /* Switch peripheral to PLL2 */
        ldr r0, =CCM_BASE_ADDR
        ldr r1, =0x00808145
-       orr r1, r1, #2 << 10
-       orr r1, r1, #1 << 19
+       orr r1, r1, #(2 << 10)
+       orr r1, r1, #(0 << 16)
+       orr r1, r1, #(1 << 19)
        str r1, [r0, #CLKCTL_CBCDR]
 
        ldr r1, =0x00016154
        str r1, [r0, #CLKCTL_CBCMR]
-       /* Change uart clk parent to pll2*/
+
+       /*change uart clk parent to pll2*/
        ldr r1, [r0, #CLKCTL_CSCMR1]
        and r1, r1, #0xfcffffff
        orr r1, r1, #0x01000000
        str r1, [r0, #CLKCTL_CSCMR1]
+
+       /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+       cmp r1, #0x0
+       bne 1b
+
+        setup_pll PLL3_BASE_ADDR, 216
+
+       setup_pll PLL4_BASE_ADDR, 455
+
+       /* Set the platform clock dividers */
+       ldr r0, =ARM_BASE_ADDR
+       ldr r1, =0x00000124
+       str r1, [r0, #0x14]
+
+       ldr r0, =CCM_BASE_ADDR
+       mov r1, #0
+       str r1, [r0, #CLKCTL_CACRR]
+
+       /* Switch ARM back to PLL 1. */
+       mov r1, #0x0
+       str r1, [r0, #CLKCTL_CCSR]
+
+       /* make uart div=6 */
        ldr r1, [r0, #CLKCTL_CSCDR1]
        and r1, r1, #0xffffffc0
        orr r1, r1, #0x0a
        str r1, [r0, #CLKCTL_CSCDR1]
-#endif
-       /* make sure divider effective */
-1:     ldr r1, [r0, #CLKCTL_CDHIPR]
-       cmp r1, #0x0
-       bne 1b
 
-       str r4, [r0, #CLKCTL_CCDR]
+       /* Restore the default values in the Gate registers */
+       ldr r1, =0xFFFFFFFF
+       str r1, [r0, #CLKCTL_CCGR0]
+       str r1, [r0, #CLKCTL_CCGR1]
+       str r1, [r0, #CLKCTL_CCGR2]
+       str r1, [r0, #CLKCTL_CCGR3]
+       str r1, [r0, #CLKCTL_CCGR4]
+       str r1, [r0, #CLKCTL_CCGR5]
+       str r1, [r0, #CLKCTL_CCGR6]
+       str r1, [r0, #CLKCTL_CCGR7]
 
-       /* for cko - for ARM div by 8 */
-       mov r1, #0x000A0000
-       add r1, r1, #0x00000F0
-       str r1, [r0, #CLKCTL_CCOSR]
+        mov r1, #0x00000
+        str r1, [r0, #CLKCTL_CCDR]
+
+        /* for cko - for ARM div by 8 */
+        mov r1, #0x000A0000
+        add r1, r1, #0x00000F0
+        str r1, [r0, #CLKCTL_CCOSR]
+
+#endif /* CONFIG_MX53 */
 .endm
 
 .macro setup_wdog
@@ -340,6 +406,8 @@ ENTRY(lowlevel_init)
        str r1, [r0, #0x4]
 #endif
 
+       init_arm_erratum
+
        init_l2cc
 
        init_aips
@@ -370,3 +438,9 @@ W_DP_665:           .word DP_OP_665
 W_DP_216:              .word DP_OP_216
                        .word DP_MFD_216
                        .word DP_MFN_216
+W_DP_400:               .word DP_OP_400
+                       .word DP_MFD_400
+                       .word DP_MFN_400
+W_DP_455:               .word DP_OP_455
+                       .word DP_MFD_455
+                       .word DP_MFN_455
index 1d8efb213bf4f9198e4a43db16870d5b54f20afe..9979c3085360b19c5c5e585fc6f677ec84018857 100644 (file)
@@ -47,6 +47,11 @@ SECTIONS
 
        . = ALIGN(4);
        .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+       .u_boot_list : {
+               #include <u-boot.lst>
+       }
+
        . = ALIGN(4);
        __image_copy_end = .;
        _end = .;
index 7199de4af1e317fed2cf01764d57d536f6c2f562..81d954f2de7fce029d5e74b81bdfcc00ff9b82cb 100644 (file)
@@ -46,9 +46,11 @@ SECTIONS
        . = ALIGN(4);
 
        . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
index 97420d70661b6af167ffa4d5d576e0b91552fe01..90edf00a5e308f428400a2ecbe34fc9464821ae2 100644 (file)
@@ -257,7 +257,7 @@ static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
 int tegra_set_emc(const void *blob, unsigned rate)
 {
        struct emc_ctlr *emc;
-       const u32 *table;
+       const u32 *table = NULL;
        int err, i;
 
        err = decode_emc(blob, rate, &emc, &table);
index e49ca0c5522912ba8849182105cf141e04d0c6b3..e6b202bd14765a1a24e8bd87f88e2166df79383e 100644 (file)
@@ -34,8 +34,8 @@ SECTIONS
        .text :
        {
                __image_copy_start = .;
-               CPUDIR/start.o (.text)
-               *(.text)
+               CPUDIR/start.o (.text*)
+               *(.text*)
        }
 
        . = ALIGN(4);
@@ -43,15 +43,17 @@ SECTIONS
 
        . = ALIGN(4);
        .data : {
-               *(.data)
+               *(.data*)
        }
 
        . = ALIGN(4);
 
        . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
@@ -81,7 +83,7 @@ SECTIONS
 
        .bss __rel_dyn_start (OVERLAY) : {
                __bss_start = .;
-               *(.bss)
+               *(.bss*)
                 . = ALIGN(4);
                __bss_end__ = .;
        }
@@ -92,3 +94,7 @@ SECTIONS
        /DISCARD/ : { *(.interp*) }
        /DISCARD/ : { *(.gnu*) }
 }
+
+#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
+ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
+#endif
index 02fe72ed7faa2f418ad85bf7eabc2ea906c74b90..ddc14b099e6cdd4e46dbfe83bd0f1025bcebd0f9 100644 (file)
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/imx-common/boot_mode.h>
 #include <malloc.h>
+#include <command.h>
 
 static const struct boot_mode *modes[2];
 
@@ -103,9 +104,11 @@ void add_board_boot_modes(const struct boot_mode *p)
        int size;
        char *dest;
 
-       if (__u_boot_cmd_bmode.usage) {
-               free(__u_boot_cmd_bmode.usage);
-               __u_boot_cmd_bmode.usage = NULL;
+       cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
+
+       if (entry->usage) {
+               free(entry->usage);
+               entry->usage = NULL;
        }
 
        modes[0] = p;
@@ -114,6 +117,6 @@ void add_board_boot_modes(const struct boot_mode *p)
        dest = malloc(size);
        if (dest) {
                create_usage(dest);
-               __u_boot_cmd_bmode.usage = dest;
+               entry->usage = dest;
        }
 }
index da093fbe1489ec516dfd41ea136377f0529563df..08fad7851c98e8d64ddc05b06b356884b3f7a75f 100644 (file)
@@ -54,9 +54,10 @@ int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
        return 0;
 }
 
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
+int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+                                    unsigned count)
 {
-       iomux_v3_cfg_t *p = pad_list;
+       iomux_v3_cfg_t const *p = pad_list;
        int i;
        int ret;
 
index 0a357b1e0a42825270cdc36fa282719849a0b4d3..0a766108a610b89c1033c1da65957727ec5e0513 100644 (file)
@@ -24,9 +24,7 @@
  * MA 02111-1307 USA
  */
 
-#if defined(CONFIG_NETARM)
-#include <asm/arch-arm720t/netarm_registers.h>
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 /* include IntegratorCP/CM720T specific hardware file if there was one */
 #else
 #error No hardware file defined for this configuration
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h b/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h
deleted file mode 100644 (file)
index 328eaf0..0000000
+++ /dev/null
@@ -1,182 +0,0 @@
-/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *             David Smith
- */
-
-#ifndef __NETARM_DMA_MODULE_REGISTERS_H
-#define __NETARM_DMA_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define        NETARM_DMA_MODULE_BASE          (0xFF900000)
-
-#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c)))
-
-#define        NETARM_DMA1A_BFR_DESCRPTOR_PTR  (0x00)
-#define        NETARM_DMA1A_CONTROL            (0x10)
-#define        NETARM_DMA1A_STATUS             (0x14)
-#define        NETARM_DMA1B_BFR_DESCRPTOR_PTR  (0x20)
-#define        NETARM_DMA1B_CONTROL            (0x30)
-#define        NETARM_DMA1B_STATUS             (0x34)
-#define        NETARM_DMA1C_BFR_DESCRPTOR_PTR  (0x40)
-#define        NETARM_DMA1C_CONTROL            (0x50)
-#define        NETARM_DMA1C_STATUS             (0x54)
-#define        NETARM_DMA1D_BFR_DESCRPTOR_PTR  (0x60)
-#define        NETARM_DMA1D_CONTROL            (0x70)
-#define        NETARM_DMA1D_STATUS             (0x74)
-
-#define        NETARM_DMA2_BFR_DESCRPTOR_PTR   (0x80)
-#define        NETARM_DMA2_CONTROL             (0x90)
-#define        NETARM_DMA2_STATUS              (0x94)
-
-#define        NETARM_DMA3_BFR_DESCRPTOR_PTR   (0xA0)
-#define        NETARM_DMA3_CONTROL             (0xB0)
-#define        NETARM_DMA3_STATUS              (0xB4)
-
-#define        NETARM_DMA4_BFR_DESCRPTOR_PTR   (0xC0)
-#define        NETARM_DMA4_CONTROL             (0xD0)
-#define        NETARM_DMA4_STATUS              (0xD4)
-
-#define        NETARM_DMA5_BFR_DESCRPTOR_PTR   (0xE0)
-#define        NETARM_DMA5_CONTROL             (0xF0)
-#define        NETARM_DMA5_STATUS              (0xF4)
-
-#define        NETARM_DMA6_BFR_DESCRPTOR_PTR   (0x100)
-#define        NETARM_DMA6_CONTROL             (0x110)
-#define        NETARM_DMA6_STATUS              (0x114)
-
-#define        NETARM_DMA7_BFR_DESCRPTOR_PTR   (0x120)
-#define        NETARM_DMA7_CONTROL             (0x130)
-#define        NETARM_DMA7_STATUS              (0x134)
-
-#define        NETARM_DMA8_BFR_DESCRPTOR_PTR   (0x140)
-#define        NETARM_DMA8_CONTROL             (0x150)
-#define        NETARM_DMA8_STATUS              (0x154)
-
-#define        NETARM_DMA9_BFR_DESCRPTOR_PTR   (0x160)
-#define        NETARM_DMA9_CONTROL             (0x170)
-#define        NETARM_DMA9_STATUS              (0x174)
-
-#define        NETARM_DMA10_BFR_DESCRPTOR_PTR  (0x180)
-#define        NETARM_DMA10_CONTROL            (0x190)
-#define        NETARM_DMA10_STATUS             (0x194)
-
-/* select bitfield defintions */
-
-/* DMA Control Register ( 0xFF90_0XX0 ) */
-
-#define NETARM_DMA_CTL_ENABLE          (0x80000000)
-
-#define NETARM_DMA_CTL_ABORT           (0x40000000)
-
-#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000)
-#define NETARM_DMA_CTL_BUS_75_PERCENT  (0x10000000)
-#define NETARM_DMA_CTL_BUS_50_PERCENT  (0x20000000)
-#define NETARM_DMA_CTL_BUS_25_PERCENT  (0x30000000)
-
-#define NETARM_DMA_CTL_BUS_MASK                (0x30000000)
-
-#define NETARM_DMA_CTL_MODE_FB_TO_MEM  (0x00000000)
-#define NETARM_DMA_CTL_MODE_FB_FROM_MEM        (0x04000000)
-#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000)
-
-#define NETARM_DMA_CTL_BURST_NONE      (0x00000000)
-#define NETARM_DMA_CTL_BURST_8_BYTE    (0x01000000)
-#define NETARM_DMA_CTL_BURST_16_BYTE   (0x02000000)
-
-#define NETARM_DMA_CTL_BURST_MASK      (0x03000000)
-
-#define NETARM_DMA_CTL_SRC_INCREMENT   (0x00200000)
-
-#define NETARM_DMA_CTL_DST_INCREMENT   (0x00100000)
-
-/* these apply only to ext xfers on DMA 3 or 4 */
-
-#define NETARM_DMA_CTL_CH_3_4_REQ_EXT  (0x00800000)
-
-#define NETARM_DMA_CTL_CH_3_4_DATA_32  (0x00000000)
-#define NETARM_DMA_CTL_CH_3_4_DATA_16  (0x00010000)
-#define NETARM_DMA_CTL_CH_3_4_DATA_8   (0x00020000)
-
-#define NETARM_DMA_CTL_STATE(X)        ((X) & 0xFC00)
-#define NETARM_DMA_CTL_INDEX(X)        ((X) & 0x03FF)
-
-/* DMA Status Register ( 0xFF90_0XX4 ) */
-
-#define NETARM_DMA_STAT_NC_INTPEN      (0x80000000)
-#define NETARM_DMA_STAT_EC_INTPEN      (0x40000000)
-#define NETARM_DMA_STAT_NR_INTPEN      (0x20000000)
-#define NETARM_DMA_STAT_CA_INTPEN      (0x10000000)
-#define NETARM_DMA_STAT_INTPEN_MASK    (0xF0000000)
-
-#define NETARM_DMA_STAT_NC_INT_EN      (0x00800000)
-#define NETARM_DMA_STAT_EC_INT_EN      (0x00400000)
-#define NETARM_DMA_STAT_NR_INT_EN      (0x00200000)
-#define NETARM_DMA_STAT_CA_INT_EN      (0x00100000)
-#define NETARM_DMA_STAT_INT_EN_MASK    (0x00F00000)
-
-#define NETARM_DMA_STAT_WRAP           (0x00080000)
-#define NETARM_DMA_STAT_IDONE          (0x00040000)
-#define NETARM_DMA_STAT_LAST           (0x00020000)
-#define NETARM_DMA_STAT_FULL           (0x00010000)
-
-#define        NETARM_DMA_STAT_BUFLEN(X)       ((X) & 0x7FFF)
-
-/* DMA Buffer Descriptor Word 0 bitfields. */
-
-#define NETARM_DMA_BD0_WRAP            (0x80000000)
-#define NETARM_DMA_BD0_IDONE           (0x40000000)
-#define NETARM_DMA_BD0_LAST            (0x20000000)
-#define NETARM_DMA_BD0_BUFPTR_MASK     (0x1FFFFFFF)
-
-/* DMA Buffer Descriptor Word 1 bitfields. */
-
-#define NETARM_DMA_BD1_STATUS_MASK     (0xFFFF0000)
-#define NETARM_DMA_BD1_FULL            (0x00008000)
-#define NETARM_DMA_BD1_BUFLEN_MASK     (0x00007FFF)
-
-#ifndef        __ASSEMBLER__
-
-typedef        struct __NETARM_DMA_Buff_Desc_FlyBy
-{
-       unsigned int word0;
-       unsigned int word1;
-} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ;
-
-typedef        struct __NETARM_DMA_Buff_Desc_M_to_M
-{
-       unsigned int word0;
-       unsigned int word1;
-       unsigned int word2;
-       unsigned int word3;
-} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ;
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h
deleted file mode 100644 (file)
index 317b354..0000000
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_eni_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : David Smith
- */
-
-#ifndef __NETARM_ENI_MODULE_REGISTERS_H
-#define __NETARM_ENI_MODULE_REGISTERS_H
-
-/* ENI unit register offsets */
-
-/* #ifdef CONFIG_ARCH_NETARM */
-#define        NETARM_ENI_MODULE_BASE          (0xFFA00000)
-/* #endif / * CONFIG_ARCH_NETARM */
-
-#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c)))
-#define get_eni_ctl_reg_addr(minor) \
-       (get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor))
-
-#define        NETARM_ENI_GENERAL_CONTROL      (0x00)
-#define        NETARM_ENI_STATUS_CONTROL       (0x04)
-#define        NETARM_ENI_FIFO_MODE_DATA       (0x08)
-
-#define        NETARM_ENI_1284_PORT1_CONTROL   (0x10)
-#define        NETARM_ENI_1284_PORT2_CONTROL   (0x14)
-#define        NETARM_ENI_1284_PORT3_CONTROL   (0x18)
-#define        NETARM_ENI_1284_PORT4_CONTROL   (0x1c)
-
-#define        NETARM_ENI_1284_CHANNEL1_DATA   (0x20)
-#define        NETARM_ENI_1284_CHANNEL2_DATA   (0x24)
-#define        NETARM_ENI_1284_CHANNEL3_DATA   (0x28)
-#define        NETARM_ENI_1284_CHANNEL4_DATA   (0x2c)
-
-#define        NETARM_ENI_ENI_CONTROL          (0x30)
-#define        NETARM_ENI_ENI_PULSED_INTR      (0x34)
-#define        NETARM_ENI_ENI_SHARED_RAM_ADDR  (0x38)
-#define        NETARM_ENI_ENI_SHARED           (0x3c)
-
-/* select bitfield defintions */
-
-/* General Control Register (0xFFA0_0000) */
-
-#define NETARM_ENI_GCR_ENIMODE_IEEE1284        (0x00000001)
-#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004)
-#define NETARM_ENI_GCR_ENIMODE_SHRAM8  (0x00000005)
-#define NETARM_ENI_GCR_ENIMODE_FIFO16  (0x00000006)
-#define NETARM_ENI_GCR_ENIMODE_FIFO8   (0x00000007)
-
-#define NETARM_ENI_GCR_ENIMODE_MASK    (0x00000007)
-
-/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014,
-   0xFFA0_0018, 0xFFA0_001c) */
-
-#define NETARM_ENI_1284PC_PORT_ENABLE  (0x80000000)
-#define NETARM_ENI_1284PC_DMA_ENABLE   (0x40000000)
-#define NETARM_ENI_1284PC_OBE_INT_EN   (0x20000000)
-#define NETARM_ENI_1284PC_ACK_INT_EN   (0x10000000)
-#define NETARM_ENI_1284PC_ECP_MODE     (0x08000000)
-#define NETARM_ENI_1284PC_LOOPBACK_MODE        (0x04000000)
-
-#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */
-#define NETARM_ENI_1284PC_STROBE_MASK  (0x03000000)
-
-#define NETARM_ENI_1284PC_MAN_STROBE_EN        (0x00800000)
-#define NETARM_ENI_1284PC_FAST_MODE    (0x00400000)
-#define NETARM_ENI_1284PC_BIDIR_MODE   (0x00200000)
-
-#define NETARM_ENI_1284PC_MAN_STROBE   (0x00080000)
-#define NETARM_ENI_1284PC_AUTO_FEED    (0x00040000)
-#define NETARM_ENI_1284PC_INIT         (0x00020000)
-#define NETARM_ENI_1284PC_HSELECT      (0x00010000)
-#define NETARM_ENI_1284PC_FE_INT_EN    (0x00008000)
-#define NETARM_ENI_1284PC_EPP_MODE     (0x00004000)
-#define NETARM_ENI_1284PC_IBR_INT_EN   (0x00002000)
-#define NETARM_ENI_1284PC_IBR          (0x00001000)
-
-#define NETARM_ENI_1284PC_RXFDB_1BYTE  (0x00000400)
-#define NETARM_ENI_1284PC_RXFDB_2BYTE  (0x00000800)
-#define NETARM_ENI_1284PC_RXFDB_3BYTE  (0x00000c00)
-#define NETARM_ENI_1284PC_RXFDB_4BYTE  (0x00000000)
-
-#define NETARM_ENI_1284PC_RBCC         (0x00000200)
-#define NETARM_ENI_1284PC_RBCT         (0x00000100)
-#define NETARM_ENI_1284PC_ACK          (0x00000080)
-#define NETARM_ENI_1284PC_FIFO_E       (0x00000040)
-#define NETARM_ENI_1284PC_OBE          (0x00000020)
-#define NETARM_ENI_1284PC_ACK_INT      (0x00000010)
-#define NETARM_ENI_1284PC_BUSY         (0x00000008)
-#define NETARM_ENI_1284PC_PE           (0x00000004)
-#define NETARM_ENI_1284PC_PSELECT      (0x00000002)
-#define NETARM_ENI_1284PC_FAULT                (0x00000001)
-
-#endif /* __NETARM_ENI_MODULE_REGISTERS_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h
deleted file mode 100644 (file)
index 8f2f369..0000000
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_eth_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Jackie Smith Cashion
- *             David Smith
- */
-
-#ifndef __NETARM_ETH_MODULE_REGISTERS_H
-#define __NETARM_ETH_MODULE_REGISTERS_H
-
-/* ETH unit register offsets */
-
-#define        NETARM_ETH_MODULE_BASE          (0xFF800000)
-
-#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c)))
-
-#define NETARM_ETH_GEN_CTRL            (0x000) /* Ethernet Gen Control Reg */
-#define NETARM_ETH_GEN_STAT            (0x004) /* Ethernet Gen Status Reg */
-#define NETARM_ETH_FIFO_DAT1            (0x008) /* Fifo Data Reg 1 */
-#define NETARM_ETH_FIFO_DAT2            (0x00C) /* Fifo Data Reg 2 */
-#define NETARM_ETH_TX_STAT              (0x010) /* Transmit Status Reg */
-#define NETARM_ETH_RX_STAT              (0x014) /* Receive Status Reg */
-
-#define NETARM_ETH_MAC_CFG             (0x400) /* MAC Configuration Reg */
-#define NETARM_ETH_PCS_CFG             (0x408) /* PCS Configuration Reg */
-#define NETARM_ETH_STL_CFG             (0x410) /* STL Configuration Reg */
-#define NETARM_ETH_B2B_IPG_GAP_TMR     (0x440) /* Back-to-back IPG
-                                                  Gap Timer Reg */
-#define NETARM_ETH_NB2B_IPG_GAP_TMR    (0x444) /* Non Back-to-back
-                                                  IPG Gap Timer Reg */
-#define NETARM_ETH_MII_CMD             (0x540) /* MII (PHY) Command Reg */
-#define NETARM_ETH_MII_ADDR            (0x544) /* MII Address Reg */
-#define NETARM_ETH_MII_WRITE           (0x548) /* MII Write Data Reg */
-#define NETARM_ETH_MII_READ            (0x54C) /* MII Read Data Reg */
-#define NETARM_ETH_MII_IND             (0x550) /* MII Indicators Reg */
-#define NETARM_ETH_MIB_CRCEC           (0x580) /* (MIB) CRC Error Counter */
-#define NETARM_ETH_MIB_AEC             (0x584) /* Alignment Error Counter */
-#define NETARM_ETH_MIB_CEC             (0x588) /* Code Error Counter */
-#define NETARM_ETH_MIB_LFC             (0x58C) /* Long Frame Counter */
-#define NETARM_ETH_MIB_SFC             (0x590) /* Short Frame Counter */
-#define NETARM_ETH_MIB_LCC             (0x594) /* Late Collision Counter */
-#define NETARM_ETH_MIB_EDC             (0x598) /* Excessive Deferral
-                                                  Counter */
-#define NETARM_ETH_MIB_MCC             (0x59C) /* Maximum Collision Counter */
-#define NETARM_ETH_SAL_FILTER          (0x5C0) /* SAL Station Address
-                                                  Filter Reg */
-#define NETARM_ETH_SAL_STATION_ADDR_1  (0x5C4) /* SAL Station Address
-                                                  Reg */
-#define NETARM_ETH_SAL_STATION_ADDR_2  (0x5C8)
-#define NETARM_ETH_SAL_STATION_ADDR_3  (0x5CC)
-#define NETARM_ETH_SAL_HASH_TBL_1      (0x5D0) /* SAL Multicast Hash Table*/
-#define NETARM_ETH_SAL_HASH_TBL_2      (0x5D4)
-#define NETARM_ETH_SAL_HASH_TBL_3      (0x5D8)
-#define NETARM_ETH_SAL_HASH_TBL_4      (0x5DC)
-
-/* select bitfield defintions */
-
-/* Ethernet General Control Register (0xFF80_0000) */
-
-#define NETARM_ETH_GCR_ERX             (0x80000000) /* Enable Receive FIFO */
-#define NETARM_ETH_GCR_ERXDMA          (0x40000000) /* Enable Receive DMA */
-#define NETARM_ETH_GCR_ETX             (0x00800000) /* Enable Transmit FIFO */
-#define NETARM_ETH_GCR_ETXDMA          (0x00400000) /* Enable Transmit DMA */
-#define NETARM_ETH_GCR_ETXWM_50                (0x00100000) /* Transmit FIFO Water
-                                                       Mark.  Start transmit
-                                                       when FIFO is 50%
-                                                       full. */
-#define NETARM_ETH_GCR_PNA             (0x00000400) /* pSOS pNA Buffer
-                                                       Descriptor Format */
-
-/* Ethernet General Status Register (0xFF80_0004) */
-
-#define NETARM_ETH_GST_RXFDB            (0x30000000)
-#define NETARM_ETH_GST_RXREGR          (0x08000000) /* Receive Register
-                                                       Ready */
-#define NETARM_ETH_GST_RXFIFOH         (0x04000000)
-#define NETARM_ETH_GST_RXBR            (0x02000000)
-#define NETARM_ETH_GST_RXSKIP          (0x01000000)
-
-#define NETARM_ETH_GST_TXBC             (0x00020000)
-
-
-/* Ethernet Transmit Status Register (0xFF80_0010) */
-
-#define NETARM_ETH_TXSTAT_TXOK          (0x00008000)
-
-
-/* Ethernet Receive Status Register (0xFF80_0014) */
-
-#define NETARM_ETH_RXSTAT_SIZE          (0xFFFF0000)
-#define NETARM_ETH_RXSTAT_RXOK          (0x00002000)
-
-
-/* PCS Configuration Register (0xFF80_0408) */
-
-#define NETARM_ETH_PCSC_NOCFR          (0x1) /* Disable Ciphering */
-#define NETARM_ETH_PCSC_ENJAB          (0x2) /* Enable Jabber Protection */
-#define NETARM_ETH_PCSC_CLKS_25M       (0x0) /* 25 MHz Clock Speed Select */
-#define NETARM_ETH_PCSC_CLKS_33M       (0x4) /* 33 MHz Clock Speed Select */
-
-/* STL Configuration Register (0xFF80_0410) */
-
-#define NETARM_ETH_STLC_RXEN           (0x2) /* Enable Packet Receiver */
-#define NETARM_ETH_STLC_AUTOZ          (0x4) /* Auto Zero Statistics */
-
-/* MAC Configuration Register (0xFF80_0400) */
-
-#define NETARM_ETH_MACC_HUGEN          (0x1) /* Enable Unlimited Transmit
-                                                Frame Sizes */
-#define NETARM_ETH_MACC_PADEN          (0x4) /* Automatic Pad Fill Frames
-                                                to 64 Bytes */
-#define NETARM_ETH_MACC_CRCEN          (0x8) /* Append CRC to Transmit
-                                                Frames */
-
-/* MII (PHY) Command Register (0xFF80_0540) */
-
-#define NETARM_ETH_MIIC_RSTAT          (0x1) /* Single Scan for Read Data */
-
-/* MII Indicators Register (0xFF80_0550) */
-
-#define NETARM_ETH_MIII_BUSY           (0x1) /* MII I/F Busy with
-                                                Read/Write */
-
-/* SAL Station Address Filter Register (0xFF80_05C0) */
-
-#define NETARM_ETH_SALF_PRO            (0x8) /* Enable Promiscuous Mode */
-#define NETARM_ETH_SALF_PRM            (0x4) /* Accept All Multicast
-                                                Packets */
-#define NETARM_ETH_SALF_PRA            (0x2) /* Accept Mulitcast Packets
-                                                using Hash Table */
-#define NETARM_ETH_SALF_BROAD          (0x1) /* Accept All Broadcast
-                                                Packets */
-
-
-#endif /* __NETARM_GEN_MODULE_REGISTERS_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h b/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h
deleted file mode 100644 (file)
index 13656a3..0000000
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_gen_module.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NETARM_GEN_MODULE_REGISTERS_H
-#define __NETARM_GEN_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define NETARM_GEN_MODULE_BASE         (0xFFB00000)
-
-#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
-
-#define NETARM_GEN_SYSTEM_CONTROL      (0x00)
-#define NETARM_GEN_STATUS_CONTROL      (0x04)
-#define NETARM_GEN_PLL_CONTROL         (0x08)
-#define NETARM_GEN_SOFTWARE_SERVICE    (0x0c)
-
-#define NETARM_GEN_TIMER1_CONTROL      (0x10)
-#define NETARM_GEN_TIMER1_STATUS       (0x14)
-#define NETARM_GEN_TIMER2_CONTROL      (0x18)
-#define NETARM_GEN_TIMER2_STATUS       (0x1c)
-
-#define NETARM_GEN_PORTA               (0x20)
-#ifndef CONFIG_NETARM_NS7520
-#define NETARM_GEN_PORTB               (0x24)
-#endif
-#define NETARM_GEN_PORTC               (0x28)
-
-#define NETARM_GEN_INTR_ENABLE         (0x30)
-#define NETARM_GEN_INTR_ENABLE_SET     (0x34)
-#define NETARM_GEN_INTR_ENABLE_CLR     (0x38)
-#define NETARM_GEN_INTR_STATUS_EN      (0x34)
-#define NETARM_GEN_INTR_STATUS_RAW     (0x38)
-
-#define NETARM_GEN_CACHE_CONTROL1      (0x40)
-#define NETARM_GEN_CACHE_CONTROL2      (0x44)
-
-/* select bitfield definitions */
-
-/* System Control Register ( 0xFFB0_0000 ) */
-
-#define NETARM_GEN_SYS_CFG_LENDIAN     (0x80000000)
-#define NETARM_GEN_SYS_CFG_BENDIAN     (0x00000000)
-
-#define NETARM_GEN_SYS_CFG_BUSQRTR     (0x00000000)
-#define NETARM_GEN_SYS_CFG_BUSHALF     (0x20000000)
-#define NETARM_GEN_SYS_CFG_BUSFULL     (0x40000000)
-
-#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
-
-#define NETARM_GEN_SYS_CFG_WDOG_EN     (0x01000000)
-#define NETARM_GEN_SYS_CFG_WDOG_IRQ    (0x00000000)
-#define NETARM_GEN_SYS_CFG_WDOG_FIQ    (0x00400000)
-#define NETARM_GEN_SYS_CFG_WDOG_RST    (0x00800000)
-#define NETARM_GEN_SYS_CFG_WDOG_24     (0x00000000)
-#define NETARM_GEN_SYS_CFG_WDOG_26     (0x00100000)
-#define NETARM_GEN_SYS_CFG_WDOG_28     (0x00200000)
-#define NETARM_GEN_SYS_CFG_WDOG_29     (0x00300000)
-
-#define NETARM_GEN_SYS_CFG_BUSMON_EN   (0x00040000)
-#define NETARM_GEN_SYS_CFG_BUSMON_128  (0x00000000)
-#define NETARM_GEN_SYS_CFG_BUSMON_64   (0x00010000)
-#define NETARM_GEN_SYS_CFG_BUSMON_32   (0x00020000)
-#define NETARM_GEN_SYS_CFG_BUSMON_16   (0x00030000)
-
-#define NETARM_GEN_SYS_CFG_USER_EN     (0x00008000)
-#define NETARM_GEN_SYS_CFG_BUSER_EN    (0x00004000)
-
-#define NETARM_GEN_SYS_CFG_BUSARB_INT  (0x00002000)
-#define NETARM_GEN_SYS_CFG_BUSARB_EXT  (0x00000000)
-
-#define NETARM_GEN_SYS_CFG_DMATST      (0x00001000)
-
-#define NETARM_GEN_SYS_CFG_TEALAST     (0x00000800)
-
-#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400)
-
-#define NETARM_GEN_SYS_CFG_CACHE_EN    (0x00000200)
-
-#define NETARM_GEN_SYS_CFG_WRI_BUF_EN  (0x00000100)
-
-#define NETARM_GEN_SYS_CFG_CACHE_INIT  (0x00000080)
-
-/* PLL Control Register ( 0xFFB0_0008 ) */
-
-#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000)
-
-#define NETARM_GEN_PLL_CTL_PLLCNT(x)   (((x)<<24) & \
-                                        NETARM_GEN_PLL_CTL_PLLCNT_MASK)
-
-/* Defaults for POLTST and ICP Fields in PLL CTL */
-#define NETARM_GEN_PLL_CTL_OUTDIV(x)   (x)
-#define NETARM_GEN_PLL_CTL_INDIV(x)    ((x)<<6)
-#define NETARM_GEN_PLL_CTL_POLTST_DEF  (0x00000E00)
-#define NETARM_GEN_PLL_CTL_ICP_DEF     (0x0000003C)
-
-
-/* Software Service Register ( 0xFFB0_000C ) */
-
-#define NETARM_GEN_SW_SVC_RESETA       (0x123)
-#define NETARM_GEN_SW_SVC_RESETB       (0x321)
-
-/* PORT C Register ( 0xFFB0_0028 ) */
-
-#ifndef CONFIG_NETARM_NS7520
-#define NETARM_GEN_PORT_MODE(x)                (((x)<<24) + (0xFF00))
-#define NETARM_GEN_PORT_DIR(x)         (((x)<<16) + (0xFF00))
-#else
-#define NETARM_GEN_PORT_MODE(x)                ((x)<<24)
-#define NETARM_GEN_PORT_DIR(x)         ((x)<<16)
-#define NETARM_GEN_PORT_CSF(x)         ((x)<<8)
-#endif
-
-/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
-
-#define NETARM_GEN_TCTL_ENABLE         (0x80000000)
-#define NETARM_GEN_TCTL_INT_ENABLE     (0x40000000)
-
-#define NETARM_GEN_TCTL_USE_IRQ                (0x00000000)
-#define NETARM_GEN_TCTL_USE_FIQ                (0x20000000)
-
-#define NETARM_GEN_TCTL_USE_PRESCALE   (0x10000000)
-#define NETARM_GEN_TCTL_INIT_COUNT(x)  ((x) & 0x1FF)
-
-#define NETARM_GEN_TSTAT_INTPEN                (0x40000000)
-#if ~defined(CONFIG_NETARM_NS7520)
-#define NETARM_GEN_TSTAT_CTC_MASK      (0x000001FF)
-#else
-#define NETARM_GEN_TSTAT_CTC_MASK      (0x0FFFFFFF)
-#endif
-
-/* prescale to msecs conversion */
-
-#if !defined(CONFIG_NETARM_PLL_BYPASS)
-#define NETARM_GEN_TIMER_MSEC_P(x)     ( ( ( 20480 ) * ( 0x1FF - ( (x) &           \
-                                           NETARM_GEN_TSTAT_CTC_MASK ) +   \
-                                           1 ) ) / (NETARM_XTAL_FREQ/1000) )
-
-#define NETARM_GEN_TIMER_SET_HZ(x)     ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
-                                         NETARM_GEN_TSTAT_CTC_MASK ) | \
-                                         NETARM_GEN_TCTL_USE_PRESCALE )
-
-#else
-#define NETARM_GEN_TIMER_MSEC_P(x)     ( ( ( 4096 ) * ( 0x1FF - ( (x) &    \
-                                           NETARM_GEN_TSTAT_CTC_MASK ) +   \
-                                           1 ) ) / (NETARM_XTAL_FREQ/1000) )
-
-#define NETARM_GEN_TIMER_SET_HZ(x)     ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
-                                         NETARM_GEN_TSTAT_CTC_MASK ) | \
-                                         NETARM_GEN_TCTL_USE_PRESCALE )
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h b/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h
deleted file mode 100644 (file)
index c650c3b..0000000
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_mem_module.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NETARM_MEM_MODULE_REGISTERS_H
-#define __NETARM_MEM_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define        NETARM_MEM_MODULE_BASE          (0xFFC00000)
-
-#define        NETARM_MEM_MODULE_CONFIG        (0x00)
-#define        NETARM_MEM_CS0_BASE_ADDR        (0x10)
-#define        NETARM_MEM_CS0_OPTIONS          (0x14)
-#define        NETARM_MEM_CS1_BASE_ADDR        (0x20)
-#define        NETARM_MEM_CS1_OPTIONS          (0x24)
-#define        NETARM_MEM_CS2_BASE_ADDR        (0x30)
-#define        NETARM_MEM_CS2_OPTIONS          (0x34)
-#define        NETARM_MEM_CS3_BASE_ADDR        (0x40)
-#define        NETARM_MEM_CS3_OPTIONS          (0x44)
-#define        NETARM_MEM_CS4_BASE_ADDR        (0x50)
-#define        NETARM_MEM_CS4_OPTIONS          (0x54)
-
-/* select bitfield defintions */
-
-/* Module Configuration Register ( 0xFFC0_0000 ) */
-
-#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000)
-#define NETARM_MEM_CFG_REFRESH_EN      (0x00800000)
-
-#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS        (0x00000000)
-#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS        (0x00200000)
-#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS        (0x00400000)
-#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS        (0x00600000)
-
-#define NETARM_MEM_CFG_PORTC_AMUX      (0x00100000)
-
-#define NETARM_MEM_CFG_A27_ADDR                (0x00080000)
-#define NETARM_MEM_CFG_A27_CS0OE       (0x00000000)
-
-#define NETARM_MEM_CFG_A26_ADDR                (0x00040000)
-#define NETARM_MEM_CFG_A26_CS0WE       (0x00000000)
-
-#define NETARM_MEM_CFG_A25_ADDR                (0x00020000)
-#define NETARM_MEM_CFG_A25_BLAST       (0x00000000)
-
-#define NETARM_MEM_CFG_PORTC_AMUX2     (0x00010000)
-
-
-/* range on this period is about 1 to 275 usec (with 18.432MHz clock)   */
-/* the expression will round down, so make sure to reverse it to verify */
-/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal        */
-/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
-
-#define        NETARM_MEM_REFR_PERIOD_USEC(p)  (NETARM_MEM_CFG_REFR_COUNT_MASK & \
-                                        (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
-                                           ) - (1) ) << (24)))
-
-#if 0
-/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
-/* the expression will round down, so make sure to reverse it toverify */
-/* it is what you want. period = [( count + 1 ) * 4] / Fxtal          */
-
-#define        NETARM_MEM_REFR_PERIOD_USEC(p)  (NETARM_MEM_CFG_REFR_COUNT_MASK & \
-                                        (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
-                                           ) - (1) ) << (24)))
-#endif
-
-/* Base Address Registers (0xFFC0_00X0) */
-
-#define NETARM_MEM_BAR_BASE_MASK       (0xFFFFF000)
-
-/* macro to define base */
-
-#define NETARM_MEM_BAR_BASE(x)         ((x) & NETARM_MEM_BAR_BASE_MASK)
-
-#define NETARM_MEM_BAR_DRAM_FP         (0x00000000)
-#define NETARM_MEM_BAR_DRAM_EDO                (0x00000100)
-#define NETARM_MEM_BAR_DRAM_SYNC       (0x00000200)
-
-#define NETARM_MEM_BAR_DRAM_MUX_INT    (0x00000000)
-#define NETARM_MEM_BAR_DRAM_MUX_EXT    (0x00000080)
-
-#define NETARM_MEM_BAR_DRAM_MUX_BAL    (0x00000000)
-#define NETARM_MEM_BAR_DRAM_MUX_UNBAL  (0x00000020)
-
-#define NETARM_MEM_BAR_1BCLK_IDLE      (0x00000010)
-
-#define NETARM_MEM_BAR_DRAM_SEL                (0x00000008)
-
-#define NETARM_MEM_BAR_BURST_EN                (0x00000004)
-
-#define NETARM_MEM_BAR_WRT_PROT                (0x00000002)
-
-#define NETARM_MEM_BAR_VALID           (0x00000001)
-
-/* Option Registers (0xFFC0_00X4) */
-
-/* macro to define which bits of the base are significant */
-
-#define NETARM_MEM_OPT_BASE_USE(x)     ((x) & NETARM_MEM_BAR_BASE_MASK)
-
-#define NETARM_MEM_OPT_WAIT_MASK       (0x00000F00)
-
-#define        NETARM_MEM_OPT_WAIT_STATES(x)   (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
-
-#define NETARM_MEM_OPT_BCYC_1          (0x00000000)
-#define NETARM_MEM_OPT_BCYC_2          (0x00000040)
-#define NETARM_MEM_OPT_BCYC_3          (0x00000080)
-#define NETARM_MEM_OPT_BCYC_4          (0x000000C0)
-
-#define NETARM_MEM_OPT_BSIZE_2         (0x00000000)
-#define NETARM_MEM_OPT_BSIZE_4         (0x00000010)
-#define NETARM_MEM_OPT_BSIZE_8         (0x00000020)
-#define NETARM_MEM_OPT_BSIZE_16                (0x00000030)
-
-#define NETARM_MEM_OPT_32BIT           (0x00000000)
-#define NETARM_MEM_OPT_16BIT           (0x00000004)
-#define NETARM_MEM_OPT_8BIT            (0x00000008)
-#define NETARM_MEM_OPT_32BIT_EXT_ACK   (0x0000000C)
-
-#define NETARM_MEM_OPT_BUS_SIZE_MASK   (0x0000000C)
-
-#define NETARM_MEM_OPT_READ_ASYNC      (0x00000000)
-#define NETARM_MEM_OPT_READ_SYNC       (0x00000002)
-
-#define NETARM_MEM_OPT_WRITE_ASYNC     (0x00000000)
-#define NETARM_MEM_OPT_WRITE_SYNC      (0x00000001)
-
-#ifdef CONFIG_NETARM_NS7520
-/* The NS7520 has a second options register for each chip select */
-#define        NETARM_MEM_CS0_OPTIONS_B  (0x18)
-#define        NETARM_MEM_CS1_OPTIONS_B  (0x28)
-#define        NETARM_MEM_CS2_OPTIONS_B  (0x38)
-#define        NETARM_MEM_CS3_OPTIONS_B  (0x48)
-#define        NETARM_MEM_CS4_OPTIONS_B  (0x58)
-
-/* Option B Registers (0xFFC0_00x8) */
-#define NETARM_MEM_OPTB_SYNC_1_STAGE   (0x00000001)
-#define NETARM_MEM_OPTB_SYNC_2_STAGE   (0x00000002)
-#define NETARM_MEM_OPTB_BCYC_PLUS0     (0x00000000)
-#define NETARM_MEM_OPTB_BCYC_PLUS4     (0x00000004)
-#define NETARM_MEM_OPTB_BCYC_PLUS8     (0x00000008)
-#define NETARM_MEM_OPTB_BCYC_PLUS12    (0x0000000C)
-
-#define NETARM_MEM_OPTB_WAIT_PLUS0     (0x00000000)
-#define NETARM_MEM_OPTB_WAIT_PLUS16    (0x00000010)
-#define NETARM_MEM_OPTB_WAIT_PLUS32    (0x00000020)
-#define NETARM_MEM_OPTB_WAIT_PLUS48    (0x00000030)
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_registers.h b/arch/arm/include/asm/arch-arm720t/netarm_registers.h
deleted file mode 100644 (file)
index fa88128..0000000
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * linux/include/asm-arm/arch-netarm/netarm_registers.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NET_ARM_REGISTERS_H
-#define __NET_ARM_REGISTERS_H
-
-#include <config.h>
-
-/* fundamental constants : */
-/* the input crystal/clock frequency ( in Hz ) */
-#define        NETARM_XTAL_FREQ_25MHz          (18432000)
-#define        NETARM_XTAL_FREQ_33MHz          (23698000)
-#define        NETARM_XTAL_FREQ_48MHz          (48000000)
-#define        NETARM_XTAL_FREQ_55MHz          (55000000)
-#define NETARM_XTAL_FREQ_EMLIN1                (20000000)
-
-/* the frequency of SYS_CLK */
-#if defined(CONFIG_NETARM_EMLIN)
-
-/* EMLIN board:  33 MHz (exp.) */
-#define        NETARM_PLL_COUNT_VAL            6
-#define NETARM_XTAL_FREQ               NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET40_REV2)
-
-/* NET+40 Rev2 boards:  33 MHz (with NETARM_XTAL_FREQ_25MHz) */
-#define        NETARM_PLL_COUNT_VAL            6
-#define        NETARM_XTAL_FREQ                NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET40_REV4)
-
-/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with
-   NETARM_XTAL_FREQ_25MHz) 4 */
-#define        NETARM_PLL_COUNT_VAL            4
-#define        NETARM_XTAL_FREQ                NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET50)
-
-/* NET+50 boards:  40 MHz (with NETARM_XTAL_FREQ_25MHz) */
-#define NETARM_PLL_COUNT_VAL           8
-#define        NETARM_XTAL_FREQ                NETARM_XTAL_FREQ_25MHz
-
-#else  /* CONFIG_NETARM_NS7520 */
-
-#define        NETARM_PLL_COUNT_VAL            0
-
-#if defined(CONFIG_BOARD_UNC20)
-#define        NETARM_XTAL_FREQ                NETARM_XTAL_FREQ_48MHz
-#else
-#define        NETARM_XTAL_FREQ                NETARM_XTAL_FREQ_55MHz
-#endif
-
-#endif
-
-/* #include "arm_registers.h" */
-#include <asm/arch/netarm_gen_module.h>
-#include <asm/arch/netarm_mem_module.h>
-#include <asm/arch/netarm_ser_module.h>
-#include <asm/arch/netarm_eni_module.h>
-#include <asm/arch/netarm_dma_module.h>
-#include <asm/arch/netarm_eth_module.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h b/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h
deleted file mode 100644 (file)
index 6fbae11..0000000
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * linux/include/asm-arm/arch-netarm/netarm_ser_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *             Clark Williams
- */
-
-#ifndef __NETARM_SER_MODULE_REGISTERS_H
-#define __NETARM_SER_MODULE_REGISTERS_H
-
-#ifndef        __ASSEMBLER__
-
-/* (--sub)#include "types.h" */
-
-/* serial channel control structure */
-typedef struct {
-  u32  ctrl_a;
-  u32  ctrl_b;
-  u32  status_a;
-  u32  bitrate;
-  u32  fifo;
-  u32  rx_buf_timer;
-  u32  rx_char_timer;
-  u32  rx_match;
-  u32  rx_match_mask;
-  u32  ctrl_c;
-  u32  status_b;
-  u32  status_c;
-  u32  fifo_last;
-  u32  unused[3];
-} netarm_serial_channel_t;
-
-#endif
-
-/* SER unit register offsets */
-
-/* #ifdef CONFIG_ARCH_NETARM */
-#define        NETARM_SER_MODULE_BASE          (0xFFD00000)
-/* #else */
-/* extern serial_channel_t netarm_dummy_registers[]; */
-/* #define NETARM_SER_MODULE_BASE              (netarm_dummy_registers) */
-/* #ifndef NETARM_XTAL_FREQ */
-/* #define NETARM_XTAL_FREQ                18432000 */
-/* #endif */
-/* #endif */
-
-/* calculate the sysclk value from the pll setting */
-#define        NETARM_PLLED_SYSCLK_FREQ        (( NETARM_XTAL_FREQ / 5 ) * \
-                                        ( NETARM_PLL_COUNT_VAL + 3 ))
-
-#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c]))
-
-#define        NETARM_SER_CH1_CTRL_A           (0x00)
-#define        NETARM_SER_CH1_CTRL_B           (0x04)
-#define        NETARM_SER_CH1_STATUS_A         (0x08)
-#define        NETARM_SER_CH1_BITRATE          (0x0C)
-#define        NETARM_SER_CH1_FIFO             (0x10)
-#define        NETARM_SER_CH1_RX_BUF_TMR       (0x14)
-#define        NETARM_SER_CH1_RX_CHAR_TMR      (0x18)
-#define        NETARM_SER_CH1_RX_MATCH         (0x1c)
-#define        NETARM_SER_CH1_RX_MATCH_MASK    (0x20)
-#define        NETARM_SER_CH1_CTRL_C           (0x24)
-#define        NETARM_SER_CH1_STATUS_B         (0x28)
-#define        NETARM_SER_CH1_STATUS_C         (0x2c)
-#define        NETARM_SER_CH1_FIFO_LAST        (0x30)
-
-#define        NETARM_SER_CH2_CTRL_A           (0x40)
-#define        NETARM_SER_CH2_CTRL_B           (0x44)
-#define        NETARM_SER_CH2_STATUS_A         (0x48)
-#define        NETARM_SER_CH2_BITRATE          (0x4C)
-#define        NETARM_SER_CH2_FIFO             (0x50)
-#define        NETARM_SER_CH2_RX_BUF_TMR       (0x54)
-#define        NETARM_SER_CH2_RX_CHAR_TMR      (0x58)
-#define        NETARM_SER_CH2_RX_MATCH         (0x5c)
-#define        NETARM_SER_CH2_RX_MATCH_MASK    (0x60)
-#define        NETARM_SER_CH2_CTRL_C           (0x64)
-#define        NETARM_SER_CH2_STATUS_B         (0x68)
-#define        NETARM_SER_CH2_STATUS_C         (0x6c)
-#define        NETARM_SER_CH2_FIFO_LAST        (0x70)
-
-/* select bitfield defintions */
-
-/* Control Register A */
-
-#define        NETARM_SER_CTLA_ENABLE          (0x80000000)
-#define        NETARM_SER_CTLA_BRK             (0x40000000)
-
-#define        NETARM_SER_CTLA_STICKP          (0x20000000)
-
-#define        NETARM_SER_CTLA_P_EVEN          (0x18000000)
-#define        NETARM_SER_CTLA_P_ODD           (0x08000000)
-#define        NETARM_SER_CTLA_P_NONE          (0x00000000)
-
-/* if you read the errata, you will find that the STOP bits don't work right */
-#define        NETARM_SER_CTLA_2STOP           (0x00000000)
-#define        NETARM_SER_CTLA_3STOP           (0x04000000)
-
-#define        NETARM_SER_CTLA_5BITS           (0x00000000)
-#define        NETARM_SER_CTLA_6BITS           (0x01000000)
-#define        NETARM_SER_CTLA_7BITS           (0x02000000)
-#define        NETARM_SER_CTLA_8BITS           (0x03000000)
-
-#define        NETARM_SER_CTLA_CTSTX           (0x00800000)
-#define        NETARM_SER_CTLA_RTSRX           (0x00400000)
-
-#define        NETARM_SER_CTLA_LOOP_REM        (0x00200000)
-#define        NETARM_SER_CTLA_LOOP_LOC        (0x00100000)
-
-#define        NETARM_SER_CTLA_GPIO2           (0x00080000)
-#define        NETARM_SER_CTLA_GPIO1           (0x00040000)
-
-#define        NETARM_SER_CTLA_DTR_EN          (0x00020000)
-#define        NETARM_SER_CTLA_RTS_EN          (0x00010000)
-
-#define        NETARM_SER_CTLA_IE_RX_BRK       (0x00008000)
-#define        NETARM_SER_CTLA_IE_RX_FRMERR    (0x00004000)
-#define        NETARM_SER_CTLA_IE_RX_PARERR    (0x00002000)
-#define        NETARM_SER_CTLA_IE_RX_OVERRUN   (0x00001000)
-#define        NETARM_SER_CTLA_IE_RX_RDY       (0x00000800)
-#define        NETARM_SER_CTLA_IE_RX_HALF      (0x00000400)
-#define        NETARM_SER_CTLA_IE_RX_FULL      (0x00000200)
-#define        NETARM_SER_CTLA_IE_RX_DMAEN     (0x00000100)
-#define        NETARM_SER_CTLA_IE_RX_DCD       (0x00000080)
-#define        NETARM_SER_CTLA_IE_RX_RI        (0x00000040)
-#define        NETARM_SER_CTLA_IE_RX_DSR       (0x00000020)
-
-#define NETARM_SER_CTLA_IE_RX_ALL      (NETARM_SER_CTLA_IE_RX_BRK \
-                                       |NETARM_SER_CTLA_IE_RX_FRMERR \
-                                       |NETARM_SER_CTLA_IE_RX_PARERR \
-                                       |NETARM_SER_CTLA_IE_RX_OVERRUN \
-                                       |NETARM_SER_CTLA_IE_RX_RDY \
-                                       |NETARM_SER_CTLA_IE_RX_HALF \
-                                       |NETARM_SER_CTLA_IE_RX_FULL \
-                                       |NETARM_SER_CTLA_IE_RX_DMAEN \
-                                       |NETARM_SER_CTLA_IE_RX_DCD \
-                                       |NETARM_SER_CTLA_IE_RX_RI \
-                                       |NETARM_SER_CTLA_IE_RX_DSR)
-
-#define        NETARM_SER_CTLA_IE_TX_CTS       (0x00000010)
-#define        NETARM_SER_CTLA_IE_TX_EMPTY     (0x00000008)
-#define        NETARM_SER_CTLA_IE_TX_HALF      (0x00000004)
-#define        NETARM_SER_CTLA_IE_TX_FULL      (0x00000002)
-#define        NETARM_SER_CTLA_IE_TX_DMAEN     (0x00000001)
-
-#define NETARM_SER_CTLA_IE_TX_ALL      (NETARM_SER_CTLA_IE_TX_CTS \
-                                       |NETARM_SER_CTLA_IE_TX_EMPTY \
-                                       |NETARM_SER_CTLA_IE_TX_HALF \
-                                       |NETARM_SER_CTLA_IE_TX_FULL \
-                                       |NETARM_SER_CTLA_IE_TX_DMAEN)
-
-/* Control Register B */
-
-#define        NETARM_SER_CTLB_MATCH1_EN       (0x80000000)
-#define        NETARM_SER_CTLB_MATCH2_EN       (0x40000000)
-#define        NETARM_SER_CTLB_MATCH3_EN       (0x20000000)
-#define        NETARM_SER_CTLB_MATCH4_EN       (0x10000000)
-
-#define        NETARM_SER_CTLB_RBGT_EN         (0x08000000)
-#define        NETARM_SER_CTLB_RCGT_EN         (0x04000000)
-
-#define        NETARM_SER_CTLB_UART_MODE       (0x00000000)
-#define        NETARM_SER_CTLB_HDLC_MODE       (0x00100000)
-#define        NETARM_SER_CTLB_SPI_MAS_MODE    (0x00200000)
-#define        NETARM_SER_CTLB_SPI_SLV_MODE    (0x00300000)
-
-#define        NETARM_SER_CTLB_REV_BIT_ORDER   (0x00080000)
-
-#define        NETARM_SER_CTLB_MAM1            (0x00040000)
-#define        NETARM_SER_CTLB_MAM2            (0x00020000)
-
-/* Status Register A */
-
-#define        NETARM_SER_STATA_MATCH1         (0x80000000)
-#define        NETARM_SER_STATA_MATCH2         (0x40000000)
-#define        NETARM_SER_STATA_MATCH3         (0x20000000)
-#define        NETARM_SER_STATA_MATCH4         (0x10000000)
-
-#define        NETARM_SER_STATA_BGAP           (0x80000000)
-#define        NETARM_SER_STATA_CGAP           (0x40000000)
-
-#define        NETARM_SER_STATA_RX_1B          (0x00100000)
-#define        NETARM_SER_STATA_RX_2B          (0x00200000)
-#define        NETARM_SER_STATA_RX_3B          (0x00300000)
-#define        NETARM_SER_STATA_RX_4B          (0x00000000)
-
-/* downshifted values */
-
-#define        NETARM_SER_STATA_RXFDB_1BYTES   (0x001)
-#define        NETARM_SER_STATA_RXFDB_2BYTES   (0x002)
-#define        NETARM_SER_STATA_RXFDB_3BYTES   (0x003)
-#define        NETARM_SER_STATA_RXFDB_4BYTES   (0x000)
-
-#define        NETARM_SER_STATA_RXFDB_MASK     (0x00300000)
-#define        NETARM_SER_STATA_RXFDB(x)       (((x) & NETARM_SER_STATA_RXFDB_MASK) \
-                                        >> 20)
-
-#define        NETARM_SER_STATA_DCD            (0x00080000)
-#define        NETARM_SER_STATA_RI             (0x00040000)
-#define        NETARM_SER_STATA_DSR            (0x00020000)
-#define        NETARM_SER_STATA_CTS            (0x00010000)
-
-#define        NETARM_SER_STATA_RX_BRK         (0x00008000)
-#define        NETARM_SER_STATA_RX_FRMERR      (0x00004000)
-#define        NETARM_SER_STATA_RX_PARERR      (0x00002000)
-#define        NETARM_SER_STATA_RX_OVERRUN     (0x00001000)
-#define        NETARM_SER_STATA_RX_RDY         (0x00000800)
-#define        NETARM_SER_STATA_RX_HALF        (0x00000400)
-#define        NETARM_SER_STATA_RX_CLOSED      (0x00000200)
-#define        NETARM_SER_STATA_RX_FULL        (0x00000100)
-#define        NETARM_SER_STATA_RX_DCD         (0x00000080)
-#define        NETARM_SER_STATA_RX_RI          (0x00000040)
-#define        NETARM_SER_STATA_RX_DSR         (0x00000020)
-
-#define        NETARM_SER_STATA_TX_CTS         (0x00000010)
-#define        NETARM_SER_STATA_TX_RDY         (0x00000008)
-#define        NETARM_SER_STATA_TX_HALF        (0x00000004)
-#define        NETARM_SER_STATA_TX_FULL        (0x00000002)
-#define        NETARM_SER_STATA_TX_DMAEN       (0x00000001)
-
-/* you have to clear all receive signals to get the fifo to move forward */
-#define NETARM_SER_STATA_CLR_ALL       (NETARM_SER_STATA_RX_BRK | \
-                                        NETARM_SER_STATA_RX_FRMERR | \
-                                        NETARM_SER_STATA_RX_PARERR | \
-                                        NETARM_SER_STATA_RX_OVERRUN | \
-                                        NETARM_SER_STATA_RX_HALF | \
-                                        NETARM_SER_STATA_RX_CLOSED | \
-                                        NETARM_SER_STATA_RX_FULL | \
-                                        NETARM_SER_STATA_RX_DCD | \
-                                        NETARM_SER_STATA_RX_RI | \
-                                        NETARM_SER_STATA_RX_DSR | \
-                                        NETARM_SER_STATA_TX_CTS )
-
-/* Bit Rate Registers */
-
-#define        NETARM_SER_BR_EN                (0x80000000)
-#define        NETARM_SER_BR_TMODE             (0x40000000)
-
-#define        NETARM_SER_BR_RX_CLK_INT        (0x00000000)
-#define        NETARM_SER_BR_RX_CLK_EXT        (0x20000000)
-#define        NETARM_SER_BR_TX_CLK_INT        (0x00000000)
-#define        NETARM_SER_BR_TX_CLK_EXT        (0x10000000)
-
-#define        NETARM_SER_BR_RX_CLK_DRV        (0x08000000)
-#define        NETARM_SER_BR_TX_CLK_DRV        (0x04000000)
-
-#define        NETARM_SER_BR_CLK_EXT_5         (0x00000000)
-#define        NETARM_SER_BR_CLK_SYSTEM        (0x01000000)
-#define        NETARM_SER_BR_CLK_OUT1A         (0x02000000)
-#define        NETARM_SER_BR_CLK_OUT2A         (0x03000000)
-
-#define        NETARM_SER_BR_TX_CLK_INV        (0x00800000)
-#define        NETARM_SER_BR_RX_CLK_INV        (0x00400000)
-
-/* complete settings assuming system clock input is 18MHz */
-
-#define        NETARM_SER_BR_MASK              (0x000007FF)
-
-/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */
-/* from section 7.5.4 of HW Ref Guide */
-
-/* #ifdef CONFIG_NETARM_PLL_BYPASS */
-#define        NETARM_SER_BR_X16(x)    ( NETARM_SER_BR_EN |                    \
-                                 NETARM_SER_BR_RX_CLK_INT |            \
-                                 NETARM_SER_BR_TX_CLK_INT |            \
-                                 NETARM_SER_BR_CLK_EXT_5 |             \
-                                 ( ( ( ( NETARM_XTAL_FREQ /            \
-                                         ( x * 10 ) ) - 1 ) /  16 ) &  \
-                                   NETARM_SER_BR_MASK ) )
-/*
-#else
-#define        NETARM_SER_BR_X16(x)    ( NETARM_SER_BR_EN |                    \
-                                 NETARM_SER_BR_RX_CLK_INT |            \
-                                 NETARM_SER_BR_TX_CLK_INT |            \
-                                 NETARM_SER_BR_CLK_SYSTEM |            \
-                                 ( ( ( ( NETARM_PLLED_SYSCLK_FREQ /            \
-                                         ( x * 2 ) ) - 1 ) /   16 ) &  \
-                                   NETARM_SER_BR_MASK ) )
-#endif
-*/
-
-/* Receive Buffer Gap Timer */
-
-#define        NETARM_SER_RX_GAP_TIMER_EN      (0x80000000)
-#define        NETARM_SER_RX_GAP_MASK          (0x00003FFF)
-
-/* rx gap is a function of bit rate x */
-
-/* #ifdef CONFIG_NETARM_PLL_BYPASS */
-#define        NETARM_SER_RXGAP(x)     ( NETARM_SER_RX_GAP_TIMER_EN |          \
-                                 ( ( ( ( 10 * NETARM_XTAL_FREQ ) /     \
-                                       ( x * 5 * 512 ) ) - 1 ) &       \
-                                     NETARM_SER_RX_GAP_MASK ) )
-/*
-#else
-#define        NETARM_SER_RXGAP(x)     ( NETARM_SER_RX_GAP_TIMER_EN |                  \
-                                 ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /      \
-                                       ( x * 512 ) ) - 1 ) &                   \
-                                     NETARM_SER_RX_GAP_MASK ) )
-#endif
-*/
-
-#if 0
-#define        NETARM_SER_RXGAP(x)     ( NETARM_SER_RX_GAP_TIMER_EN |          \
-                                 ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /      \
-                                       ( x * 5 * 512 ) ) - 1 ) &       \
-                                     NETARM_SER_RX_GAP_MASK ) )
-#define        NETARM_SER_RXGAP(x)     ( NETARM_SER_RX_GAP_TIMER_EN |          \
-                                 ( ( ( ( 10 * NETARM_XTAL_FREQ ) /     \
-                                       ( x * 512 ) ) - 1 ) &   \
-                                     NETARM_SER_RX_GAP_MASK ) )
-#endif
-
-#define MIN_BAUD_RATE        600
-#define MAX_BAUD_RATE     115200
-
-/* the default BAUD rate for the BOOTLOADER, there is a separate */
-/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */
-#define DEFAULT_BAUD_RATE 9600
-#define NETARM_SER_FIFO_SIZE 32
-#define MIN_GAP 0
-
-#endif
diff --git a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h b/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h
deleted file mode 100644 (file)
index 5715f3e..0000000
+++ /dev/null
@@ -1,225 +0,0 @@
-#ifndef __LPC2292_REGISTERS_H
-#define __LPC2292_REGISTERS_H
-
-#include <config.h>
-
-/* Macros for reading/writing registers */
-#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
-#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
-#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
-#define GET8(reg) (*(volatile unsigned char*)(reg))
-#define GET16(reg) (*(volatile unsigned short*)(reg))
-#define GET32(reg) (*(volatile unsigned int*)(reg))
-
-/* External Memory Controller */
-
-#define BCFG0 0xFFE00000       /* 32-bits */
-#define BCFG1 0xFFE00004       /* 32-bits */
-#define BCFG2 0xFFE00008       /* 32-bits */
-#define BCFG3 0xFFE0000c       /* 32-bits */
-
-/* System Control Block */
-
-#define EXTINT   0xE01FC140
-#define EXTWAKE  0xE01FC144
-#define EXTMODE  0xE01FC148
-#define EXTPOLAR 0xE01FC14C
-#define MEMMAP   0xE01FC040
-#define PLLCON   0xE01FC080
-#define PLLCFG   0xE01FC084
-#define PLLSTAT  0xE01FC088
-#define PLLFEED  0xE01FC08C
-#define PCON     0xE01FC0C0
-#define PCONP    0xE01FC0C4
-#define VPBDIV   0xE01FC100
-
-/* Memory Acceleration Module */
-
-#define MAMCR  0xE01FC000
-#define MAMTIM 0xE01FC004
-
-/* Vectored Interrupt Controller */
-
-#define VICIRQStatus    0xFFFFF000
-#define VICFIQStatus    0xFFFFF004
-#define VICRawIntr      0xFFFFF008
-#define VICIntSelect    0xFFFFF00C
-#define VICIntEnable    0xFFFFF010
-#define VICIntEnClr     0xFFFFF014
-#define VICSoftInt      0xFFFFF018
-#define VICSoftIntClear 0xFFFFF01C
-#define VICProtection   0xFFFFF020
-#define VICVectAddr     0xFFFFF030
-#define VICDefVectAddr  0xFFFFF034
-#define VICVectAddr0    0xFFFFF100
-#define VICVectAddr1    0xFFFFF104
-#define VICVectAddr2    0xFFFFF108
-#define VICVectAddr3    0xFFFFF10C
-#define VICVectAddr4    0xFFFFF110
-#define VICVectAddr5    0xFFFFF114
-#define VICVectAddr6    0xFFFFF118
-#define VICVectAddr7    0xFFFFF11C
-#define VICVectAddr8    0xFFFFF120
-#define VICVectAddr9    0xFFFFF124
-#define VICVectAddr10   0xFFFFF128
-#define VICVectAddr11   0xFFFFF12C
-#define VICVectAddr12   0xFFFFF130
-#define VICVectAddr13   0xFFFFF134
-#define VICVectAddr14   0xFFFFF138
-#define VICVectAddr15   0xFFFFF13C
-#define VICVectCntl0    0xFFFFF200
-#define VICVectCntl1   0xFFFFF204
-#define VICVectCntl2   0xFFFFF208
-#define VICVectCntl3   0xFFFFF20C
-#define VICVectCntl4   0xFFFFF210
-#define VICVectCntl5   0xFFFFF214
-#define VICVectCntl6   0xFFFFF218
-#define VICVectCntl7   0xFFFFF21C
-#define VICVectCntl8   0xFFFFF220
-#define VICVectCntl9   0xFFFFF224
-#define VICVectCntl10  0xFFFFF228
-#define VICVectCntl11  0xFFFFF22C
-#define VICVectCntl12  0xFFFFF230
-#define VICVectCntl13  0xFFFFF234
-#define VICVectCntl14  0xFFFFF238
-#define VICVectCntl15  0xFFFFF23C
-
-/* Pin connect block */
-
-#define PINSEL0 0xE002C000     /* 32 bits */
-#define PINSEL1 0xE002C004     /* 32 bits */
-#define PINSEL2 0xE002C014     /* 32 bits */
-
-/* GPIO */
-
-#define IO0PIN 0xE0028000
-#define IO0SET 0xE0028004
-#define IO0DIR 0xE0028008
-#define IO0CLR 0xE002800C
-#define IO1PIN 0xE0028010
-#define IO1SET 0xE0028014
-#define IO1DIR 0xE0028018
-#define IO1CLR 0xE002801C
-#define IO2PIN 0xE0028020
-#define IO2SET 0xE0028024
-#define IO2DIR 0xE0028028
-#define IO2CLR 0xE002802C
-#define IO3PIN 0xE0028030
-#define IO3SET 0xE0028034
-#define IO3DIR 0xE0028038
-#define IO3CLR 0xE002803C
-
-/* Uarts */
-
-#define U0RBR 0xE000C000
-#define U0THR 0xE000C000
-#define U0IER 0xE000C004
-#define U0IIR 0xE000C008
-#define U0FCR 0xE000C008
-#define U0LCR 0xE000C00C
-#define U0LSR 0xE000C014
-#define U0SCR 0xE000C01C
-#define U0DLL 0xE000C000
-#define U0DLM 0xE000C004
-
-#define U1RBR 0xE0010000
-#define U1THR 0xE0010000
-#define U1IER 0xE0010004
-#define U1IIR 0xE0010008
-#define U1FCR 0xE0010008
-#define U1LCR 0xE001000C
-#define U1MCR 0xE0010010
-#define U1LSR 0xE0010014
-#define U1MSR 0xE0010018
-#define U1SCR 0xE001001C
-#define U1DLL 0xE0010000
-#define U1DLM 0xE0010004
-
-/* I2C */
-
-#define I2CONSET 0xE001C000
-#define I2STAT   0xE001C004
-#define I2DAT    0xE001C008
-#define I2ADR    0xE001C00C
-#define I2SCLH   0xE001C010
-#define I2SCLL   0xE001C014
-#define I2CONCLR 0xE001C018
-
-/* SPI */
-
-#define S0SPCR  0xE0020000
-#define S0SPSR  0xE0020004
-#define S0SPDR  0xE0020008
-#define S0SPCCR 0xE002000C
-#define S0SPINT 0xE002001C
-
-#define S1SPCR  0xE0030000
-#define S1SPSR  0xE0030004
-#define S1SPDR  0xE0030008
-#define S1SPCCR 0xE003000C
-#define S1SPINT 0xE003001C
-
-/* CAN controller */
-
-/* skip for now */
-
-/* Timers */
-
-#define T0IR  0xE0004000
-#define T0TCR 0xE0004004
-#define T0TC  0xE0004008
-#define T0PR  0xE000400C
-#define T0PC  0xE0004010
-#define T0MCR 0xE0004014
-#define T0MR0 0xE0004018
-#define T0MR1 0xE000401C
-#define T0MR2 0xE0004020
-#define T0MR3 0xE0004024
-#define T0CCR 0xE0004028
-#define T0CR0 0xE000402C
-#define T0CR1 0xE0004030
-#define T0CR2 0xE0004034
-#define T0CR3 0xE0004038
-#define T0EMR 0xE000403C
-
-#define T1IR  0xE0008000
-#define T1TCR 0xE0008004
-#define T1TC  0xE0008008
-#define T1PR  0xE000800C
-#define T1PC  0xE0008010
-#define T1MCR 0xE0008014
-#define T1MR0 0xE0008018
-#define T1MR1 0xE000801C
-#define T1MR2 0xE0008020
-#define T1MR3 0xE0008024
-#define T1CCR 0xE0008028
-#define T1CR0 0xE000802C
-#define T1CR1 0xE0008030
-#define T1CR2 0xE0008034
-#define T1CR3 0xE0008038
-#define T1EMR 0xE000803C
-
-/* PWM */
-
-/* skip for now */
-
-/* A/D converter */
-
-/* skip for now */
-
-/* Real Time Clock */
-
-/* skip for now */
-
-/* Watchdog */
-
-#define WDMOD  0xE0000000
-#define WDTC   0xE0000004
-#define WDFEED 0xE0000008
-#define WDTV   0xE000000C
-
-/* EmbeddedICE LOGIC */
-
-/* skip for now */
-
-#endif
diff --git a/arch/arm/include/asm/arch-lpc2292/spi.h b/arch/arm/include/asm/arch-lpc2292/spi.h
deleted file mode 100644 (file)
index 6ae66e8..0000000
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
-    This file defines the interface to the lpc22xx SPI module.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This file may be included in software not adhering to the GPL.
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef SPI_H
-#define SPI_H
-
-#include <config.h>
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-
-#define SPIF 0x80
-
-#define spi_lock() disable_interrupts();
-#define spi_unlock() enable_interrupts();
-
-extern unsigned long spi_flags;
-extern unsigned char spi_idle;
-
-int spi_init(void);
-
-static inline unsigned char spi_read(void)
-{
-       unsigned char b;
-
-       PUT8(S0SPDR, spi_idle);
-       while (!(GET8(S0SPSR) & SPIF));
-       b = GET8(S0SPDR);
-
-       return b;
-}
-
-static inline void spi_write(unsigned char b)
-{
-       PUT8(S0SPDR, b);
-       while (!(GET8(S0SPSR) & SPIF));
-       GET8(S0SPDR);           /* this will clear the SPIF bit */
-}
-
-static inline void spi_set_clock(unsigned char clk_value)
-{
-       PUT8(S0SPCCR, clk_value);
-}
-
-static inline void spi_set_cfg(unsigned char phase,
-                              unsigned char polarity,
-                              unsigned char lsbf)
-{
-       unsigned char v = 0x20; /* master bit set */
-
-       if (phase)
-               v |= 0x08;                      /* set phase bit */
-       if (polarity) {
-               v |= 0x10;                      /* set polarity bit */
-               spi_idle = 0xFF;
-       } else {
-               spi_idle = 0x00;
-       }
-       if (lsbf)
-               v |= 0x40;                      /* set lsbf bit */
-
-       PUT8(S0SPCR, v);
-}
-#endif /* SPI_H */
index e78029604b71d962babcef4575f8e63f38134a98..53aafe3075f4af9fbbea20f6a8a1e5444a95595a 100644 (file)
@@ -2,7 +2,7 @@
  * Copyright (C) 2009, DENX Software Engineering
  * Author: John Rigby <jcrigby@gmail.com
  *
- *   Based on arch-mx31/mx31-regs.h
+ *   Based on arch-mx31/imx-regs.h
  *     Copyright (C) 2009 Ilya Yanok,
  *             Emcraft Systems <yanok@emcraft.com>
  *   and arch-mx27/imx-regs.h
@@ -33,8 +33,7 @@
 #ifndef _IMX_REGS_H
 #define _IMX_REGS_H
 
-#ifndef __ASSEMBLY__
-
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
 #ifdef CONFIG_FEC_MXC
@@ -254,6 +253,7 @@ struct aips_regs {
 
 /* 128K Internal Static RAM */
 #define IMX_RAM_BASE           (0x78000000)
+#define IMX_RAM_SIZE           (128 * 1024)
 
 /* SDRAM BANKS */
 #define IMX_SDRAM_BANK0_BASE   (0x80000000)
index 2eff08d1d49a681aed726f7a15e0987f39a7d78f..00679ef6a91a47a3a1e761bd18fd9ac13643644a 100644 (file)
@@ -44,7 +44,9 @@ enum mxc_clock {
        MXC_IPG_CLK,
        MXC_IPG_PERCLK,
        MXC_UART_CLK,
-       MXC_ESDHC_CLK,
+       MXC_ESDHC1_CLK,
+       MXC_ESDHC2_CLK,
+       MXC_ESDHC3_CLK,
        MXC_USB_CLK,
        MXC_CSPI_CLK,
        MXC_FEC_CLK,
index 05aa951d10b2a9e025dc1adf6a269eea74d6bbaf..bc6dbea665558f8fb2d05f6420cd27ec47b77381 100644 (file)
  * MA 02111-1307 USA
  */
 
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+#include <asm/macro.h>
+
 /*
  * AIPS setup - Only setup MPROTx registers.
  * The PACR default values are good.
+ *
+ * Default argument values:
+ *  - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
+ *    user-mode.
+ *  - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
+ *    SDMA to access them.
  */
-.macro init_aips
-       /*
-        * Set all MPROTx to be non-bufferable, trusted for R/W,
-        * not forced to user-mode.
-        */
-       ldr r0, =AIPS1_BASE_ADDR
-       ldr r1, =AIPS_MPR_CONFIG
-       str r1, [r0, #0x00]
-       str r1, [r0, #0x04]
-       ldr r0, =AIPS2_BASE_ADDR
-       str r1, [r0, #0x00]
-       str r1, [r0, #0x04]
+.macro init_aips mpr=0x77777777, opacr=0x00000000
+       ldr     r0, =AIPS1_BASE_ADDR
+       ldr     r1, =\mpr
+       str     r1, [r0, #AIPS_MPR_0_7]
+       str     r1, [r0, #AIPS_MPR_8_15]
+       ldr     r2, =AIPS2_BASE_ADDR
+       str     r1, [r2, #AIPS_MPR_0_7]
+       str     r1, [r2, #AIPS_MPR_8_15]
 
-       /*
-        * Clear the on and off peripheral modules Supervisor Protect bit
-        * for SDMA to access them. Did not change the AIPS control registers
-        * (offset 0x20) access type
-        */
-       ldr r0, =AIPS1_BASE_ADDR
-       ldr r1, =AIPS_OPACR_CONFIG
-       str r1, [r0, #0x40]
-       str r1, [r0, #0x44]
-       str r1, [r0, #0x48]
-       str r1, [r0, #0x4C]
-       str r1, [r0, #0x50]
-       ldr r0, =AIPS2_BASE_ADDR
-       str r1, [r0, #0x40]
-       str r1, [r0, #0x44]
-       str r1, [r0, #0x48]
-       str r1, [r0, #0x4C]
-       str r1, [r0, #0x50]
+       /* Did not change the AIPS control registers access type. */
+       ldr     r1, =\opacr
+       str     r1, [r0, #AIPS_OPACR_0_7]
+       str     r1, [r0, #AIPS_OPACR_8_15]
+       str     r1, [r0, #AIPS_OPACR_16_23]
+       str     r1, [r0, #AIPS_OPACR_24_31]
+       str     r1, [r0, #AIPS_OPACR_32_39]
+       str     r1, [r2, #AIPS_OPACR_0_7]
+       str     r1, [r2, #AIPS_OPACR_8_15]
+       str     r1, [r2, #AIPS_OPACR_16_23]
+       str     r1, [r2, #AIPS_OPACR_24_31]
+       str     r1, [r2, #AIPS_OPACR_32_39]
 .endm
 
-/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-.macro init_max
-       ldr r0, =MAX_BASE_ADDR
-       /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-       ldr r1, =MAX_MPR_CONFIG
-       str r1, [r0, #0x000]        /* for S0 */
-       str r1, [r0, #0x100]        /* for S1 */
-       str r1, [r0, #0x200]        /* for S2 */
-       str r1, [r0, #0x300]        /* for S3 */
-       str r1, [r0, #0x400]        /* for S4 */
-       /* SGPCR - always park on last master */
-       ldr r1, =MAX_SGPCR_CONFIG
-       str r1, [r0, #0x010]        /* for S0 */
-       str r1, [r0, #0x110]        /* for S1 */
-       str r1, [r0, #0x210]        /* for S2 */
-       str r1, [r0, #0x310]        /* for S3 */
-       str r1, [r0, #0x410]        /* for S4 */
-       /* MGPCR - restore default values */
-       ldr r1, =MAX_MGPCR_CONFIG
-       str r1, [r0, #0x800]        /* for M0 */
-       str r1, [r0, #0x900]        /* for M1 */
-       str r1, [r0, #0xA00]        /* for M2 */
-       str r1, [r0, #0xB00]        /* for M3 */
-       str r1, [r0, #0xC00]        /* for M4 */
-       str r1, [r0, #0xD00]        /* for M5 */
+/*
+ * MAX (Multi-Layer AHB Crossbar Switch) setup
+ *
+ * Default argument values:
+ *  - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
+ *  - SGPCR: always park on last master
+ *  - MGPCR: restore default values
+ */
+.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
+       ldr     r0, =MAX_BASE_ADDR
+       ldr     r1, =\mpr
+       str     r1, [r0, #MAX_MPR0]     /* for S0 */
+       str     r1, [r0, #MAX_MPR1]     /* for S1 */
+       str     r1, [r0, #MAX_MPR2]     /* for S2 */
+       str     r1, [r0, #MAX_MPR3]     /* for S3 */
+       str     r1, [r0, #MAX_MPR4]     /* for S4 */
+       ldr     r1, =\sgpcr
+       str     r1, [r0, #MAX_SGPCR0]   /* for S0 */
+       str     r1, [r0, #MAX_SGPCR1]   /* for S1 */
+       str     r1, [r0, #MAX_SGPCR2]   /* for S2 */
+       str     r1, [r0, #MAX_SGPCR3]   /* for S3 */
+       str     r1, [r0, #MAX_SGPCR4]   /* for S4 */
+       ldr     r1, =\mgpcr
+       str     r1, [r0, #MAX_MGPCR0]   /* for M0 */
+       str     r1, [r0, #MAX_MGPCR1]   /* for M1 */
+       str     r1, [r0, #MAX_MGPCR2]   /* for M2 */
+       str     r1, [r0, #MAX_MGPCR3]   /* for M3 */
+       str     r1, [r0, #MAX_MGPCR4]   /* for M4 */
+       str     r1, [r0, #MAX_MGPCR5]   /* for M5 */
 .endm
 
-/* M3IF setup */
-.macro init_m3if
-       /* Configure M3IF registers */
-       ldr r1, =M3IF_BASE_ADDR
-       /*
-       * M3IF Control Register (M3IFCTL)
      * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
      * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
      * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
      * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
      * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
      * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
      * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
-       * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
-       *                                               ------------
-       *                                                 0x00000040
-       */
-       ldr r0, =M3IF_CONFIG
-       str r0, [r1]  /* M3IF control reg */
+/*
+ * M3IF setup
+ *
+ * Default argument values:
+ *  - CTL:
+ * MRRP[0] = L2CC0 not on priority list (0 << 0)       = 0x00000000
* MRRP[1] = L2CC1 not on priority list (0 << 1)       = 0x00000000
* MRRP[2] = MBX not on priority list (0 << 2)         = 0x00000000
* MRRP[3] = MAX1 not on priority list (0 << 3)                = 0x00000000
* MRRP[4] = SDMA not on priority list (0 << 4)                = 0x00000000
* MRRP[5] = MPEG4 not on priority list (0 << 5)       = 0x00000000
* MRRP[6] = IPU1 on priority list (1 << 6)            = 0x00000040
* MRRP[7] = IPU2 not on priority list (0 << 7)                = 0x00000000
+ *                                                     ------------
+ *                                                       0x00000040
+ */
+.macro init_m3if ctl=0x00000040
+       /* M3IF Control Register (M3IFCTL) */
+       write32 M3IF_BASE_ADDR, \ctl
 .endm
 
 .macro core_init
-       mrc 15, 0, r1, c1, c0, 0
+       mrc     p15, 0, r1, c1, c0, 0
 
-       mrc 15, 0, r0, c1, c0, 1
-       orr r0, r0, #7
-       mcr 15, 0, r0, c1, c0, 1
-       orr r1, r1, #(1<<11)
+       /* Set branch prediction enable */
+       mrc     p15, 0, r0, c1, c0, 1
+       orr     r0, r0, #7
+       mcr     p15, 0, r0, c1, c0, 1
+       orr     r1, r1, #1 << 11
 
        /* Set unaligned access enable */
-       orr r1, r1, #(1<<22)
+       orr     r1, r1, #1 << 22
 
        /* Set low int latency enable */
-       orr r1, r1, #(1<<21)
+       orr     r1, r1, #1 << 21
 
-       mcr 15, 0, r1, c1, c0, 0
+       mcr     p15, 0, r1, c1, c0, 0
 
-       mov r0, #0
+       mov     r0, #0
 
-       /* Set branch prediction enable */
-       mcr 15, 0, r0, c15, c2, 4
+       mcr     p15, 0, r0, c15, c2, 4
 
-       mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
-       mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
-       mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
+       mcr     p15, 0, r0, c7, c7, 0   /* Invalidate I cache and D cache */
+       mcr     p15, 0, r0, c8, c7, 0   /* Invalidate TLBs */
+       mcr     p15, 0, r0, c7, c10, 4  /* Drain the write buffer */
 
-       /*
-        * initializes very early AIPS
-        * Then it also initializes Multi-Layer AHB Crossbar Switch,
-        * M3IF
-        * Also setup the Peripheral Port Remap register inside the core
-        */
-       ldr r0, =0x40000015        /* start from AIPS 2GB region */
-       mcr p15, 0, r0, c15, c2, 4
+       /* Setup the Peripheral Port Memory Remap Register */
+       ldr     r0, =0x40000015         /* Start from AIPS 2-GB region */
+       mcr     p15, 0, r0, c15, c2, 4
 .endm
index 46017f4ad062a5289e007ab4507bef43db6a5216..1d060fd23ed0b13c8780a299c287d1450b22c604 100644 (file)
 #define DP_MFD_400     (3 - 1)
 #define DP_MFN_400     1
 
+#define DP_OP_455      ((9 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_455     (48 - 1)
+#define DP_MFN_455     23
+
 #define DP_OP_216      ((6 << 4) + ((3 - 1)  << 0))
 #define DP_MFD_216     (4 - 1)
 #define DP_MFN_216     3
index dc737ba12721999206ceaae34dd4cae36ee06c87..09ab010138b965950fb45679e84f5bad8ac36908 100644 (file)
@@ -200,6 +200,12 @@ struct src {
        u32     gpr10;
 };
 
+/* OCOTP Registers */
+struct ocotp_regs {
+       u32     reserved[0x198];
+       u32     gp1;    /* 0x660 */
+};
+
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET             29
 #define IOMUXC_GPR3_GPU_DBG_MASK               (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
index 3d66d64d209019c40d749efed5ab49ee982fa431..3ade8dc4337e0b6b310aaf9532bfa117f2a7576a 100644 (file)
@@ -530,20 +530,20 @@ enum {
        MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16       = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
        MX6Q_PAD_EIM_BCLK__GPIO_6_31            = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
        MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31       = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
-       MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
        MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
        MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
        MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16        = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
        MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0     = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
-       MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15      = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15      = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15      = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC     = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN15__GPIO_4_17           = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1   = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
-       MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2        = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2        = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2        = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD      = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30  = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
@@ -551,7 +551,7 @@ enum {
        MX6Q_PAD_DI0_PIN2__GPIO_4_18            = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2         = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9   = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3        = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3        = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3        = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS     = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
@@ -564,17 +564,17 @@ enum {
        MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD      = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN4__USDHC1_WP            = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
        MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD     = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
-       MX6Q_PAD_DI0_PIN4__GPIO_4_20            = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0),
+       MX6Q_PAD_DI0_PIN4__GPIO_4_20            = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4    = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11  = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0   = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0   = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0   = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK        = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN  = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT0__GPIO_4_21          = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5  = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1   = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1   = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1   = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI        = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
@@ -582,7 +582,7 @@ enum {
        MX6Q_PAD_DISP0_DAT1__GPIO_4_22          = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6       = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2   = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2   = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2   = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO        = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
@@ -590,7 +590,7 @@ enum {
        MX6Q_PAD_DISP0_DAT2__GPIO_4_23          = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7       = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3   = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3   = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3   = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0         = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
@@ -598,7 +598,7 @@ enum {
        MX6Q_PAD_DISP0_DAT3__GPIO_4_24          = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8    = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4   = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4   = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4   = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1         = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
@@ -606,7 +606,7 @@ enum {
        MX6Q_PAD_DISP0_DAT4__GPIO_4_25          = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9  = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5   = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5   = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5   = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2         = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS   = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
@@ -614,7 +614,7 @@ enum {
        MX6Q_PAD_DISP0_DAT5__GPIO_4_26          = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10      = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6   = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6   = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6   = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3         = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC    = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
@@ -622,7 +622,7 @@ enum {
        MX6Q_PAD_DISP0_DAT6__GPIO_4_27          = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11      = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7   = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7   = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7   = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY         = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
@@ -630,7 +630,7 @@ enum {
        MX6Q_PAD_DISP0_DAT7__GPIO_4_28          = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12      = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8   = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8   = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8   = IOMU