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raw | patch | inline | side by side (parent: e74244c)
author | Kim Phillips <kim.phillips@freescale.com> | |
Fri, 14 May 2010 18:18:54 +0000 (13:18 -0500) | ||
committer | Kim Phillips <kim.phillips@freescale.com> | |
Mon, 17 May 2010 19:44:25 +0000 (14:44 -0500) |
commit 167cdad1372917bc11c636c359aad02625291fa9 "SERIAL: Enable
port-mapped access" inadvertently broke 83xx nand boards by
converting NS16550_init to use io accessors, which expanded
the size of the generated code.
this patch fixes the problem by removing icache functions from
the nand builds, which somewhat follows commit
1a2e203b31d33fb720f2cf1033b241ad36ab405a "mpc83xx: turn on icache
in core initialization to improve u-boot boot time"
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
port-mapped access" inadvertently broke 83xx nand boards by
converting NS16550_init to use io accessors, which expanded
the size of the generated code.
this patch fixes the problem by removing icache functions from
the nand builds, which somewhat follows commit
1a2e203b31d33fb720f2cf1033b241ad36ab405a "mpc83xx: turn on icache
in core initialization to improve u-boot boot time"
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
arch/powerpc/cpu/mpc83xx/start.S | patch | blob | history |
index a7c80792ded4dc54f6e87a73421be44b11b88140..1b3d618f499095e1d686103de6ac9b00653ba5ba 100644 (file)
* Note: requires that all cache bits in
* HID0 are in the low half word.
*/
+#ifndef CONFIG_NAND_SPL
.globl icache_enable
icache_enable:
mfspr r3, HID0
mfspr r3, HID0
rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
blr
+#endif /* !CONFIG_NAND_SPL */
.globl dcache_enable
dcache_enable: