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raw | patch | inline | side by side (parent: cd5e64e)
raw | patch | inline | side by side (parent: cd5e64e)
author | Somnath Mukherjee <somnath@ti.com> | |
Wed, 14 Aug 2013 11:16:23 +0000 (16:46 +0530) | ||
committer | Somnath Mukherjee <somnath@ti.com> | |
Wed, 14 Aug 2013 11:31:43 +0000 (17:01 +0530) |
Signed-off-by: Somnath Mukherjee <somnath@ti.com>
board/ti/dra7xx/evm.c | patch | blob | history |
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 8214a7acb4a906784092b414df902c5ed3c69591..d3a09aaddddb9877da151a83a91da8d2bc2d45b1 100644 (file)
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
#define CTRL_CORE_MPU_IRQ_144_REG 0x4a002b58
#define CTRL_CORE_MPU_IRQ_145_REG 0x4a002b5a
#define CTRL_CORE_MPU_IRQ_124_REG 0x4a002b34
+#define CTRL_CORE_MPU_IRQ_50_REG 0x4a002aa0
+#define CTRL_CORE_MPU_IRQ_51_REG 0x4a002aa2
+#define CTRL_CORE_MPU_IRQ_52_REG 0x4a002aa4
+#define CTRL_CORE_MPU_IRQ_53_REG 0x4a002aa6
#define CTRL_CORE_DMA_SYSTEM_DREQ_79_REG 0x4a002c16
#define CTRL_CORE_DMA_SYSTEM_DREQ_78_REG 0x4a002c14
writew(146, CTRL_CORE_MPU_IRQ_144_REG); /* DSP2 MMU0 */
writew(147, CTRL_CORE_MPU_IRQ_145_REG); /* DSP2 MMU1 */
writew(343, CTRL_CORE_MPU_IRQ_124_REG); /* QSPI */
+ writew(334, CTRL_CORE_MPU_IRQ_50_REG); /* CPSW_RX_THRESH */
+ writew(335, CTRL_CORE_MPU_IRQ_51_REG); /* CPSW_RX */
+ writew(336, CTRL_CORE_MPU_IRQ_52_REG); /* CPSW_TX */
+ writew(337, CTRL_CORE_MPU_IRQ_53_REG); /* CPSW_MISC */
}
static void set_crossbar_sdma_dreq()