ARM: DRA7xx: Add CPSW support to DRA7xx EVM
authorMugunthan V N <mugunthanvnm@ti.com>
Mon, 8 Jul 2013 10:34:41 +0000 (16:04 +0530)
committerSomnath Mukherjee <somnath@ti.com>
Wed, 14 Aug 2013 16:02:11 +0000 (21:32 +0530)
Adding support for CPSW Ethernet support found in DRA7xx EVM

Change-Id: Id68e606967aeeecaaf991eb26ef94d2119dc7a83
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Resolved merge conflicts and added change id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/include/asm/arch-omap5/cpu.h
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/omap_common.h
board/ti/dra7xx/evm.c

index 091338397e8f878a5e355a8861ae8901e5b2781f..fb09ce7516524dc477da90b4940bad811d8322e0 100644 (file)
@@ -387,6 +387,10 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 
 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_status                         = 0x4A002134,
+       .control_core_mac_id_0_lo               = 0x4A002514,
+       .control_core_mac_id_0_hi               = 0x4A002518,
+       .control_core_mac_id_1_lo               = 0x4A00251C,
+       .control_core_mac_id_1_hi               = 0x4A002520,
        .control_core_mmr_lock1                 = 0x4A002540,
        .control_core_mmr_lock2                 = 0x4A002544,
        .control_core_mmr_lock3                 = 0x4A002548,
index 4753f4624ec499d1728859a71c7c8e43c26156a2..347f104e80e3af6815c19ba6ccc8eb159962c1cc 100644 (file)
@@ -116,6 +116,8 @@ struct watchdog {
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
+#define BIT(x)                         (1 << (x))
+
 #define WD_UNLOCK1             0xAAAA
 #define WD_UNLOCK2             0x5555
 
@@ -175,4 +177,8 @@ struct watchdog {
 #define PRM_RSTST              (PRM_DEVICE_BASE + 0x4)
 #define PRM_RSTST_WARM_RESET_MASK      0x7FEA
 
+/* DRA7XX CPSW Config space */
+#define CPSW_BASE                      0x48484000
+#define CPSW_MDIO_BASE                 0x48485000
+
 #endif /* _CPU_H */
index d2c493011d1680b4f9bc9d65675492fab698f3c9..3076a5ec89f550e17049a5bfb991d0baf58b8ab3 100644 (file)
@@ -180,6 +180,27 @@ struct s32ktimer {
 #define SRCODE_OVERRIDE_SEL_XS_SHIFT   0
 #define SRCODE_OVERRIDE_SEL_XS_MASK    (1 << 0)
 
+/* IO Delay module defines */
+#define CFG_IO_DELAY_BASE              0x4844A000
+#define CFG_IO_DELAY_LOCK              (CFG_IO_DELAY_BASE + 0x02C)
+
+/* CPSW IO Delay registers*/
+#define CFG_RGMII0_TXCTL               (CFG_IO_DELAY_BASE + 0x74C)
+#define CFG_RGMII0_TXD0                        (CFG_IO_DELAY_BASE + 0x758)
+#define CFG_RGMII0_TXD1                        (CFG_IO_DELAY_BASE + 0x764)
+#define CFG_RGMII0_TXD2                        (CFG_IO_DELAY_BASE + 0x770)
+#define CFG_RGMII0_TXD3                        (CFG_IO_DELAY_BASE + 0x77C)
+#define CFG_VIN2A_D13                  (CFG_IO_DELAY_BASE + 0xA7C)
+#define CFG_VIN2A_D17                  (CFG_IO_DELAY_BASE + 0xAAC)
+#define CFG_VIN2A_D16                  (CFG_IO_DELAY_BASE + 0xAA0)
+#define CFG_VIN2A_D15                  (CFG_IO_DELAY_BASE + 0xA94)
+#define CFG_VIN2A_D14                  (CFG_IO_DELAY_BASE + 0xA88)
+
+#define CFG_IO_DELAY_UNLOCK_KEY                0x0000AAAA
+#define CFG_IO_DELAY_LOCK_KEY          0x0000AAAB
+#define CFG_IO_DELAY_ACCESS_PATTERN    0x00029000
+#define CFG_IO_DELAY_LOCK_MASK         0x400
+
 #ifndef __ASSEMBLY__
 struct srcomp_params {
        s8 divide_factor;
@@ -196,5 +217,10 @@ struct ctrl_ioregs {
        u32 ctrl_emif_sdram_config_ext;
        u32 ctrl_ddr_ctrl_ext_0;
 };
+
+struct io_delay {
+       u32 addr;
+       u32 dly;
+};
 #endif /* __ASSEMBLY__ */
 #endif
index d9f9c33118bb927c33d3580713ab65493c7cafba..c9d6fa0a74e9ce467829da4d5af255c9a0922ea1 100644 (file)
@@ -357,6 +357,10 @@ struct prcm_regs {
 
 struct omap_sys_ctrl_regs {
        u32 control_status;
+       u32 control_core_mac_id_0_lo;
+       u32 control_core_mac_id_0_hi;
+       u32 control_core_mac_id_1_lo;
+       u32 control_core_mac_id_1_hi;
        u32 control_core_mmr_lock1;
        u32 control_core_mmr_lock2;
        u32 control_core_mmr_lock3;
index d3a09aaddddb9877da151a83a91da8d2bc2d45b1..bbd71d47fa508ec981ba896c695320de0671823b 100644 (file)
 #include <asm/ehci-omap.h>
 #endif
 
+#ifdef CONFIG_DRIVER_TI_CPSW
+#include <cpsw.h>
+#endif
+
 #define CTRL_CORE_MPU_IRQ_159_REG                      0x4a002b76
 #define CTRL_CORE_MPU_IRQ_155_REG                      0x4a002b6e
 #define CTRL_CORE_MPU_IRQ_154_REG                      0x4a002b6c
@@ -67,6 +71,43 @@ const struct omap_sysinfo sysinfo = {
        "Board: DRA7xx\n"
 };
 
+/*
+ * Adjust I/O delays on the Tx control and data lines of each MAC port. This
+ * is a workaround in order to work properly with the DP83865 PHYs on the EVM.
+ * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we
+ * essentially need to counteract the DRA7xx internal delay, and we do this
+ * by delaying the control and data lines. If not using this PHY, you probably
+ * don't need to do this stuff!
+ */
+static void dra7xx_adj_io_delay(const struct io_delay *io_dly)
+{
+       int i = 0;
+       u32 reg_val;
+       u32 delta;
+       u32 coarse;
+       u32 fine;
+
+       writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK);
+
+       while(io_dly[i].addr) {
+               writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK,
+                      io_dly[i].addr);
+               delta = io_dly[i].dly;
+               reg_val = readl(io_dly[i].addr) & 0x3ff;
+               coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F);
+               coarse = (coarse > 0x1F) ? (0x1F) : (coarse);
+               fine = (reg_val & 0x1F) + (delta & 0x1F);
+               fine = (fine > 0x1F) ? (0x1F) : (fine);
+               reg_val = CFG_IO_DELAY_ACCESS_PATTERN |
+                               CFG_IO_DELAY_LOCK_MASK |
+                               ((coarse << 5) | (fine));
+               writel(reg_val, io_dly[i].addr);
+               i++;
+       }
+
+       writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK);
+}
+
 /**
  * @brief board_init
  *
@@ -80,11 +121,6 @@ int board_init(void)
        return 0;
 }
 
-int board_eth_init(bd_t *bis)
-{
-       return 0;
-}
-
 /**
  * @brief misc_init_r - Configure EVM board specific configurations
  * such as power configurations, ethernet initialization as phase2 of
@@ -159,3 +195,107 @@ void set_crossbar_regs(void)
        set_crossbar_mpu_irq();
        set_crossbar_sdma_dreq();
 }
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+
+/* Delay value to add to calibrated value */
+#define RGMII0_TXCTL_DLY_VAL           ((0x3 << 5) + 0x8)
+#define RGMII0_TXD0_DLY_VAL            ((0x3 << 5) + 0x8)
+#define RGMII0_TXD1_DLY_VAL            ((0x3 << 5) + 0x2)
+#define RGMII0_TXD2_DLY_VAL            ((0x4 << 5) + 0x0)
+#define RGMII0_TXD3_DLY_VAL            ((0x4 << 5) + 0x0)
+#define VIN2A_D13_DLY_VAL              ((0x3 << 5) + 0x8)
+#define VIN2A_D17_DLY_VAL              ((0x3 << 5) + 0x8)
+#define VIN2A_D16_DLY_VAL              ((0x3 << 5) + 0x2)
+#define VIN2A_D15_DLY_VAL              ((0x4 << 5) + 0x0)
+#define VIN2A_D14_DLY_VAL              ((0x4 << 5) + 0x0)
+
+static void cpsw_control(int enabled)
+{
+       /* VTP can be added here */
+
+       return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+       {
+               .slave_reg_ofs  = 0x208,
+               .sliver_reg_ofs = 0xd80,
+               .phy_id         = 0,
+       },
+       {
+               .slave_reg_ofs  = 0x308,
+               .sliver_reg_ofs = 0xdc0,
+               .phy_id         = 1,
+       },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+       .mdio_base              = CPSW_MDIO_BASE,
+       .cpsw_base              = CPSW_BASE,
+       .mdio_div               = 0xff,
+       .channels               = 8,
+       .cpdma_reg_ofs          = 0x800,
+       .slaves                 = 1,
+       .slave_data             = cpsw_slaves,
+       .ale_reg_ofs            = 0xd00,
+       .ale_entries            = 1024,
+       .host_port_reg_ofs      = 0x108,
+       .hw_stats_reg_ofs       = 0x900,
+       .bd_ram_ofs             = 0x2000,
+       .mac_control            = (1 << 5),
+       .control                = cpsw_control,
+       .host_port_num          = 0,
+       .version                = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+       int ret;
+       uint8_t mac_addr[6];
+       uint32_t mac_hi, mac_lo;
+       uint32_t ctrl_val;
+       const struct io_delay io_dly[] = {
+               {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL},
+               {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL},
+               {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL},
+               {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL},
+               {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL},
+               {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL},
+               {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL},
+               {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL},
+               {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL},
+               {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL},
+               {0}
+       };
+
+       /* Adjust IO delay for RGMII tx path */
+       dra7xx_adj_io_delay(io_dly);
+
+       /* try reading mac address from efuse */
+       mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
+       mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
+       mac_addr[0] = mac_hi & 0xFF;
+       mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+       mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+       mac_addr[3] = mac_lo & 0xFF;
+       mac_addr[4] = (mac_lo & 0xFF00) >> 8;
+       mac_addr[5] = (mac_lo & 0xFF0000) >> 16;
+
+       if (!getenv("ethaddr")) {
+               printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+               if (is_valid_ether_addr(mac_addr))
+                       eth_setenv_enetaddr("ethaddr", mac_addr);
+       }
+       ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
+       ctrl_val |= 0x22;
+       writel(ctrl_val, (*ctrl)->control_core_control_io1);
+
+       ret = cpsw_register(&cpsw_data);
+       if (ret < 0)
+               printf("Error %d registering CPSW switch\n", ret);
+
+       return ret;
+}
+#endif