Merge remote-tracking branch 'u-boot-ti/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Fri, 26 Oct 2012 05:00:28 +0000 (07:00 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Fri, 26 Oct 2012 05:00:28 +0000 (07:00 +0200)
548 files changed:
.gitignore
MAINTAINERS
Makefile
README
arch/arm/cpu/arm920t/ep93xx/u-boot.lds
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
arch/arm/cpu/ixp/u-boot.lds
arch/arm/cpu/u-boot.lds
arch/arm/imx-common/cmd_bmode.c
arch/arm/include/asm/global_data.h
arch/arm/include/asm/u-boot.h
arch/arm/lib/board.c
arch/avr32/cpu/u-boot.lds
arch/avr32/include/asm/global_data.h
arch/avr32/include/asm/u-boot.h
arch/avr32/lib/board.c
arch/blackfin/cpu/u-boot.lds
arch/blackfin/include/asm/global_data.h
arch/blackfin/include/asm/u-boot.h
arch/blackfin/lib/board.c
arch/m68k/cpu/mcf5227x/cpu_init.c
arch/m68k/cpu/mcf5227x/start.S
arch/m68k/cpu/mcf523x/start.S
arch/m68k/cpu/mcf52x2/start.S
arch/m68k/cpu/mcf532x/start.S
arch/m68k/cpu/mcf5445x/config.mk
arch/m68k/cpu/mcf5445x/cpu.c
arch/m68k/cpu/mcf5445x/cpu_init.c
arch/m68k/cpu/mcf5445x/speed.c
arch/m68k/cpu/mcf5445x/start.S
arch/m68k/cpu/mcf547x_8x/start.S
arch/m68k/include/asm/cache.h
arch/m68k/include/asm/global_data.h
arch/m68k/include/asm/immap.h
arch/m68k/include/asm/immap_5441x.h [new file with mode: 0644]
arch/m68k/include/asm/m5441x.h [new file with mode: 0644]
arch/m68k/include/asm/u-boot.h
arch/m68k/lib/board.c
arch/microblaze/cpu/u-boot.lds
arch/microblaze/include/asm/global_data.h
arch/microblaze/include/asm/u-boot.h
arch/mips/cpu/mips32/au1x00/Makefile
arch/mips/cpu/mips32/au1x00/au1x00_ide.c [moved from board/bmw/m48t59y.h with 59% similarity]
arch/mips/cpu/mips32/au1x00/au1x00_serial.c
arch/mips/cpu/mips32/cache.S
arch/mips/cpu/mips32/cpu.c
arch/mips/cpu/mips32/incaip/asc_serial.c
arch/mips/cpu/mips64/Makefile [new file with mode: 0644]
arch/mips/cpu/mips64/cache.S [new file with mode: 0644]
arch/mips/cpu/mips64/config.mk [new file with mode: 0644]
arch/mips/cpu/mips64/cpu.c [new file with mode: 0644]
arch/mips/cpu/mips64/interrupts.c [new file with mode: 0644]
arch/mips/cpu/mips64/start.S [new file with mode: 0644]
arch/mips/cpu/mips64/time.c [new file with mode: 0644]
arch/mips/cpu/xburst/cpu.c
arch/mips/cpu/xburst/jz_serial.c
arch/mips/cpu/xburst/start.S
arch/mips/include/asm/addrspace.h
arch/mips/include/asm/asm.h
arch/mips/include/asm/cacheops.h
arch/mips/include/asm/global_data.h
arch/mips/include/asm/io.h
arch/mips/include/asm/posix_types.h
arch/mips/include/asm/u-boot.h
arch/mips/lib/board.c
arch/nds32/cpu/n1213/u-boot.lds
arch/nds32/include/asm/global_data.h
arch/nds32/include/asm/u-boot.h
arch/nds32/lib/board.c
arch/nios2/cpu/u-boot.lds
arch/nios2/include/asm/global_data.h
arch/nios2/include/asm/u-boot.h
arch/openrisc/include/asm/global_data.h
arch/openrisc/include/asm/u-boot.h
arch/powerpc/cpu/74xx_7xx/u-boot.lds
arch/powerpc/cpu/mpc512x/u-boot.lds
arch/powerpc/cpu/mpc5xx/serial.c
arch/powerpc/cpu/mpc5xx/u-boot.lds
arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
arch/powerpc/cpu/mpc5xxx/u-boot.lds
arch/powerpc/cpu/mpc8220/u-boot.lds
arch/powerpc/cpu/mpc8220/uart.c
arch/powerpc/cpu/mpc824x/cpu_init.c
arch/powerpc/cpu/mpc824x/start.S
arch/powerpc/cpu/mpc824x/u-boot.lds
arch/powerpc/cpu/mpc8260/serial_scc.c
arch/powerpc/cpu/mpc8260/serial_smc.c
arch/powerpc/cpu/mpc8260/u-boot.lds
arch/powerpc/cpu/mpc83xx/cpu.c
arch/powerpc/cpu/mpc83xx/cpu_init.c
arch/powerpc/cpu/mpc83xx/speed.c
arch/powerpc/cpu/mpc83xx/u-boot.lds
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/b4860_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/b4860_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
arch/powerpc/cpu/mpc85xx/liodn.c
arch/powerpc/cpu/mpc85xx/mp.c
arch/powerpc/cpu/mpc85xx/mp.h
arch/powerpc/cpu/mpc85xx/p5040_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/p5040_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/portals.c
arch/powerpc/cpu/mpc85xx/release.S
arch/powerpc/cpu/mpc85xx/serial_scc.c
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc85xx/t4240_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/t4240_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/tlb.c
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
arch/powerpc/cpu/mpc85xx/u-boot.lds
arch/powerpc/cpu/mpc86xx/fdt.c
arch/powerpc/cpu/mpc86xx/mp.c
arch/powerpc/cpu/mpc86xx/u-boot.lds
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
arch/powerpc/cpu/mpc8xxx/ddr/main.c
arch/powerpc/cpu/mpc8xxx/ddr/options.c
arch/powerpc/cpu/mpc8xxx/ddr/util.c
arch/powerpc/cpu/mpc8xxx/fdt.c
arch/powerpc/cpu/mpc8xxx/srio.c
arch/powerpc/cpu/ppc4xx/u-boot.lds
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_ddr_sdram.h
arch/powerpc/include/asm/fsl_fman.h
arch/powerpc/include/asm/fsl_liodn.h
arch/powerpc/include/asm/fsl_memac.h [new file with mode: 0644]
arch/powerpc/include/asm/fsl_portals.h
arch/powerpc/include/asm/fsl_serdes.h
arch/powerpc/include/asm/global_data.h
arch/powerpc/include/asm/immap_83xx.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/immap_qe.h
arch/powerpc/include/asm/mp.h
arch/powerpc/include/asm/mpc85xx_gpio.h
arch/powerpc/include/asm/processor.h
arch/powerpc/include/asm/u-boot.h
arch/powerpc/lib/Makefile
arch/powerpc/lib/board.c
arch/powerpc/lib/ide.c [new file with mode: 0644]
arch/powerpc/lib/ide.h [new file with mode: 0644]
arch/sandbox/cpu/u-boot.lds
arch/sandbox/include/asm/global_data.h
arch/sh/cpu/sh2/u-boot.lds
arch/sh/cpu/sh3/u-boot.lds
arch/sh/cpu/sh4/u-boot.lds
arch/sh/include/asm/global_data.h
arch/sh/include/asm/u-boot.h
arch/sparc/cpu/leon2/serial.c
arch/sparc/cpu/leon3/serial.c
arch/sparc/include/asm/global_data.h
arch/sparc/include/asm/u-boot.h
arch/sparc/lib/board.c
arch/x86/cpu/u-boot.lds
arch/x86/include/asm/global_data.h
board/BuS/eb_cpu5282/u-boot.lds
board/LEOX/elpt860/u-boot.lds
board/Marvell/common/serial.c
board/RPXClassic/u-boot.lds
board/RPXClassic/u-boot.lds.debug
board/RPXlite/u-boot.lds
board/RPXlite/u-boot.lds.debug
board/RPXlite_dw/u-boot.lds
board/RPXlite_dw/u-boot.lds.debug
board/RRvision/u-boot.lds
board/actux1/u-boot.lds
board/actux2/u-boot.lds
board/actux3/u-boot.lds
board/adder/u-boot.lds
board/ait/cam_enc_4xx/u-boot-spl.lds
board/altera/nios2-generic/u-boot.lds
board/amcc/acadia/u-boot-nand.lds
board/amcc/bamboo/u-boot-nand.lds
board/amcc/canyonlands/u-boot-nand.lds
board/amcc/kilauea/u-boot-nand.lds
board/amcc/sequoia/u-boot-nand.lds
board/amcc/sequoia/u-boot-ram.lds
board/astro/mcf5373l/u-boot.lds
board/bmw/README [deleted file]
board/bmw/bmw.c [deleted file]
board/bmw/bmw.h [deleted file]
board/bmw/early_init.S [deleted file]
board/bmw/flash.c [deleted file]
board/bmw/m48t59y.c [deleted file]
board/bmw/ns16550.c [deleted file]
board/bmw/ns16550.h [deleted file]
board/bmw/serial.c [deleted file]
board/c2mon/u-boot.lds
board/c2mon/u-boot.lds.debug
board/cobra5272/u-boot.lds
board/cogent/serial.c
board/cogent/u-boot.lds
board/cogent/u-boot.lds.debug
board/cpc45/Makefile
board/cpc45/cpc45.c
board/cpc45/ide.c [new file with mode: 0644]
board/cray/L1/u-boot.lds.debug
board/dave/PPChameleonEVB/u-boot.lds
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
board/davinci/da8xxevm/u-boot-spl-hawk.lds
board/dbau1x00/u-boot.lds
board/dvlhost/u-boot.lds
board/eltec/mhpc/u-boot.lds
board/eltec/mhpc/u-boot.lds.debug
board/emk/top860/u-boot.lds
board/ep88x/u-boot.lds
board/esd/cpci750/ide.c
board/esd/cpci750/serial.c
board/esd/dasa_sim/u-boot.lds
board/esd/pmc440/u-boot-nand.lds
board/esd/tasreg/u-boot.lds
board/esteem192e/u-boot.lds
board/etx094/u-boot.lds
board/evb64260/serial.c
board/evb64260/u-boot.lds
board/fads/u-boot.lds
board/flagadm/u-boot.lds
board/flagadm/u-boot.lds.debug
board/freescale/common/Makefile
board/freescale/common/qixis.c
board/freescale/common/qixis.h
board/freescale/common/vsc3316_3308.c [new file with mode: 0644]
board/freescale/common/vsc3316_3308.h [new file with mode: 0644]
board/freescale/m5208evbe/u-boot.lds
board/freescale/m52277evb/u-boot.lds
board/freescale/m5235evb/u-boot.lds
board/freescale/m5249evb/u-boot.lds
board/freescale/m5253demo/u-boot.lds
board/freescale/m5253evbe/u-boot.lds
board/freescale/m5271evb/u-boot.lds
board/freescale/m5272c3/u-boot.lds
board/freescale/m5275evb/u-boot.lds
board/freescale/m5282evb/u-boot.lds
board/freescale/m53017evb/u-boot.lds
board/freescale/m5329evb/u-boot.lds
board/freescale/m5373evb/u-boot.lds
board/freescale/m54418twr/Makefile [moved from board/bmw/Makefile with 75% similarity]
board/freescale/m54418twr/config.mk [moved from board/bmw/config.mk with 73% similarity]
board/freescale/m54418twr/m54418twr.c [new file with mode: 0644]
board/freescale/m54418twr/u-boot.lds [new file with mode: 0644]
board/freescale/m54451evb/u-boot.lds
board/freescale/m54455evb/u-boot.lds
board/freescale/m547xevb/u-boot.lds
board/freescale/m548xevb/u-boot.lds
board/freescale/mx31ads/u-boot.lds
board/freescale/t4qds/Makefile [moved from board/sbc8560/Makefile with 81% similarity]
board/freescale/t4qds/ddr.c [new file with mode: 0644]
board/freescale/t4qds/eth.c [new file with mode: 0644]
board/freescale/t4qds/law.c [new file with mode: 0644]
board/freescale/t4qds/pci.c [new file with mode: 0644]
board/freescale/t4qds/t4240qds_qixis.h [new file with mode: 0644]
board/freescale/t4qds/t4qds.c [new file with mode: 0644]
board/freescale/t4qds/t4qds.h [new file with mode: 0644]
board/freescale/t4qds/tlb.c [new file with mode: 0644]
board/gaisler/gr_cpci_ax2000/u-boot.lds
board/gaisler/gr_ep2s60/u-boot.lds
board/gaisler/gr_xc3s_1500/u-boot.lds
board/gaisler/grsim/u-boot.lds
board/gaisler/grsim_leon2/u-boot.lds
board/gen860t/u-boot-flashenv.lds
board/gen860t/u-boot.lds
board/genietv/u-boot.lds
board/genietv/u-boot.lds.debug
board/hermes/u-boot.lds
board/hermes/u-boot.lds.debug
board/hymod/u-boot.lds
board/hymod/u-boot.lds.debug
board/icu862/u-boot.lds
board/icu862/u-boot.lds.debug
board/idmr/u-boot.lds
board/incaip/u-boot.lds
board/ip860/u-boot.lds
board/ip860/u-boot.lds.debug
board/ivm/ivm.c
board/ivm/u-boot.lds
board/ivm/u-boot.lds.debug
board/keymile/km83xx/km83xx.c
board/kmc/kzm9g/kzm9g.c
board/korat/u-boot-F7FC.lds
board/kup/kup4k/u-boot.lds
board/kup/kup4k/u-boot.lds.debug
board/kup/kup4x/u-boot.lds
board/kup/kup4x/u-boot.lds.debug
board/lantec/u-boot.lds
board/lantec/u-boot.lds.debug
board/linkstation/ide.c
board/lubbock/lubbock.c
board/lwmon/u-boot.lds
board/lwmon/u-boot.lds.debug
board/manroland/uc100/u-boot.lds
board/matrix_vision/mvsmr/u-boot.lds
board/mbx8xx/u-boot.lds
board/mbx8xx/u-boot.lds.debug
board/micronas/vct/u-boot.lds
board/mousse/u-boot.lds
board/mousse/u-boot.lds.ram
board/mousse/u-boot.lds.rom
board/mpl/pip405/u-boot.lds.debug
board/mvblue/u-boot.lds
board/netphone/u-boot.lds
board/netphone/u-boot.lds.debug
board/netta/u-boot.lds
board/netta/u-boot.lds.debug
board/netta2/u-boot.lds
board/netta2/u-boot.lds.debug
board/netvia/u-boot.lds
board/netvia/u-boot.lds.debug
board/nx823/u-boot.lds
board/nx823/u-boot.lds.debug
board/openrisc/openrisc-generic/u-boot.lds
board/palmtc/palmtc.c
board/pb1x00/u-boot.lds
board/pcippc2/fpga_serial.c
board/pcippc2/fpga_serial.h
board/pcippc2/pcippc2.c
board/pcs440ep/pcs440ep.c
board/prodrive/p3mx/serial.c
board/pxa255_idp/pxa_idp.c
board/qemu-mips/config.mk [deleted file]
board/qemu-mips/u-boot.lds
board/qi/qi_lb60/u-boot.lds
board/quantum/u-boot.lds
board/r360mpi/u-boot.lds
board/rbc823/u-boot.lds
board/renesas/sh7757lcr/u-boot.lds
board/rsdproto/u-boot.lds
board/samsung/smdk5250/smdk5250-uboot-spl.lds
board/samsung/smdk6400/u-boot-nand.lds
board/sandburst/karef/u-boot.lds.debug
board/sandburst/metrobox/u-boot.lds.debug
board/sandpoint/u-boot.lds
board/sbc8560/README [deleted file]
board/sbc8560/ddr.c [deleted file]
board/sbc8560/law.c [deleted file]
board/sbc8560/sbc8560.c [deleted file]
board/sbc8560/tlb.c [deleted file]
board/siemens/IAD210/u-boot.lds
board/sixnet/u-boot.lds
board/snmc/qs850/u-boot.lds
board/snmc/qs860t/u-boot.lds
board/spc1920/u-boot.lds
board/spd8xx/u-boot.lds
board/spd8xx/u-boot.lds.debug
board/stx/stxxtc/u-boot.lds
board/stx/stxxtc/u-boot.lds.debug
board/svm_sc8xx/u-boot.lds
board/ti/omap2420h4/omap2420h4.c
board/tqc/tqm8xx/u-boot.lds
board/trizepsiv/conxs.c
board/v37/u-boot.lds
board/vpac270/u-boot-spl.lds
board/w7o/u-boot.lds.debug
board/westel/amx860/u-boot.lds
board/westel/amx860/u-boot.lds.debug
board/xes/xpedite1000/u-boot.lds.debug
boards.cfg
common/Makefile
common/bouncebuf.c [new file with mode: 0644]
common/cmd_bdinfo.c
common/cmd_cbfs.c [new file with mode: 0644]
common/cmd_fdt.c
common/cmd_help.c
common/cmd_i2c.c
common/cmd_ide.c
common/command.c
common/env_common.c
common/env_embedded.c
common/image.c
common/usb.c
common/usb_storage.c
config.mk
disk/part.c
disk/part_dos.c
disk/part_efi.c
disk/part_efi.h
doc/DocBook/Makefile
doc/DocBook/linker_lists.tmpl [new file with mode: 0644]
doc/DocBook/stdio.tmpl [new file with mode: 0644]
doc/README.VSC3316-3308 [new file with mode: 0644]
doc/README.commands
doc/README.fsl-ddr
doc/README.m54418twr [new file with mode: 0644]
doc/README.mpc85xx-spin-table [new file with mode: 0644]
doc/README.t4240qds [new file with mode: 0644]
drivers/i2c/sh_i2c.c
drivers/input/i8042.c
drivers/input/input.c
drivers/mmc/Makefile
drivers/mmc/dw_mmc.c [new file with mode: 0644]
drivers/mmc/mmc.c
drivers/mmc/mmc_spi.c
drivers/mmc/mxsmmc.c
drivers/mmc/pxa_mmc.c [deleted file]
drivers/mmc/s5p_sdhci.c
drivers/mmc/sdhci.c
drivers/net/fm/Makefile
drivers/net/fm/eth.c
drivers/net/fm/init.c
drivers/net/fm/memac.c [new file with mode: 0644]
drivers/net/fm/memac_phy.c [new file with mode: 0644]
drivers/net/fm/t4240.c [new file with mode: 0644]
drivers/net/mcfmii.c
drivers/pci/fsl_pci_init.c
drivers/qe/qe.c
drivers/serial/altera_jtag_uart.c
drivers/serial/altera_uart.c
drivers/serial/atmel_usart.c
drivers/serial/lpc32xx_hsuart.c
drivers/serial/mcfuart.c
drivers/serial/ns9750_serial.c
drivers/serial/opencores_yanu.c
drivers/serial/s3c4510b_uart.c
drivers/serial/s3c64xx.c
drivers/serial/serial.c
drivers/serial/serial_clps7111.c
drivers/serial/serial_imx.c
drivers/serial/serial_ixp.c
drivers/serial/serial_ks8695.c
drivers/serial/serial_lpc2292.c
drivers/serial/serial_mxc.c
drivers/serial/serial_netarm.c
drivers/serial/serial_pl01x.c
drivers/serial/serial_s3c44b0.c
drivers/serial/serial_sa1100.c
drivers/serial/serial_sh.c
drivers/spi/fsl_espi.c
drivers/usb/host/ehci-fsl.c
examples/standalone/mips64.lds [new file with mode: 0644]
examples/standalone/sparc.lds
fs/Makefile
fs/cbfs/Makefile [new file with mode: 0644]
fs/cbfs/cbfs.c [new file with mode: 0644]
fs/fat/fat.c
fs/fat/fat_write.c
helper.mk [new file with mode: 0644]
include/bouncebuf.h [new file with mode: 0644]
include/cbfs.h [new file with mode: 0644]
include/command.h
include/config_phylib_all_drivers.h
include/configs/BMW.h [deleted file]
include/configs/CPC45.h
include/configs/ICU862.h
include/configs/IVML24.h
include/configs/IVMS8.h
include/configs/KUP4K.h
include/configs/KUP4X.h
include/configs/M54418TWR.h [new file with mode: 0644]
include/configs/MBX.h
include/configs/MPC8308RDB.h
include/configs/NETTA.h
include/configs/NSCU.h
include/configs/P3041DS.h
include/configs/P4080DS.h
include/configs/P5020DS.h
include/configs/R360MPI.h
include/configs/RPXClassic.h
include/configs/RPXlite.h
include/configs/RPXlite_DW.h
include/configs/RRvision.h
include/configs/SBC8540.h [deleted file]
include/configs/SPD823TS.h
include/configs/T4240QDS.h [new file with mode: 0644]
include/configs/TK885D.h
include/configs/TQM823L.h
include/configs/TQM823M.h
include/configs/TQM850L.h
include/configs/TQM850M.h
include/configs/TQM855L.h
include/configs/TQM855M.h
include/configs/TQM860L.h
include/configs/TQM860M.h
include/configs/TQM862L.h
include/configs/TQM862M.h
include/configs/TQM866M.h
include/configs/TQM885D.h
include/configs/apx4devkit.h
include/configs/atc.h
include/configs/c2mon.h
include/configs/coreboot.h
include/configs/corenet_ds.h
include/configs/km/km8309-common.h [new file with mode: 0644]
include/configs/km/km8321-common.h
include/configs/km/km83xx-common.h
include/configs/kzm9g.h
include/configs/lubbock.h
include/configs/lwmon.h
include/configs/m28evk.h
include/configs/mpc8308_p1m.h
include/configs/mx28evk.h
include/configs/palmtc.h
include/configs/pxa255_idp.h
include/configs/qemu-mips.h
include/configs/qemu-mips64.h [new file with mode: 0644]
include/configs/quantum.h
include/configs/sbc8560.h [deleted file]
include/configs/suvd3.h
include/configs/svm_sc8xx.h
include/configs/t4qds.h [new file with mode: 0644]
include/configs/trizepsiv.h
include/configs/uc100.h
include/configs/virtlab2.h
include/dwmmc.h [new file with mode: 0644]
include/e500.h
include/env_default.h [new file with mode: 0644]
include/fm_eth.h
include/fsl_mdio.h
include/i8042.h
include/ide.h
include/image.h
include/input.h
include/libfdt.h
include/linker_lists.h [new file with mode: 0644]
include/mpc83xx.h
include/sdhci.h
include/serial.h
lib/libfdt/Makefile
lib/libfdt/fdt_empty_tree.c [new file with mode: 0644]
lib/libfdt/fdt_rw.c
nand_spl/board/freescale/mpc8536ds/Makefile
nand_spl/board/freescale/mpc8569mds/Makefile
nand_spl/board/freescale/mpc8572ds/Makefile
nand_spl/board/freescale/mx31pdk/Makefile
nand_spl/board/freescale/mx31pdk/u-boot.lds
nand_spl/board/freescale/p1010rdb/Makefile
nand_spl/board/freescale/p1023rds/Makefile
nand_spl/board/freescale/p1_p2_rdb/Makefile
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
nand_spl/board/karo/tx25/Makefile
nand_spl/board/karo/tx25/u-boot.lds
nand_spl/board/samsung/smdk6400/u-boot.lds
spl/.gitignore
spl/Makefile
tools/env/fw_env.c
tools/patman/gitutil.py
tools/patman/patchstream.py

index d91e91b1e652dcac5a91e5f653e7d08e763e1d1c..1ac43f2825666d93f2f611e86ab2f735777bf83f 100644 (file)
@@ -38,6 +38,7 @@
 /u-boot.sha1
 /u-boot.dis
 /u-boot.lds
+/u-boot.lst
 /u-boot.ubl
 /u-boot.ais
 /u-boot.dtb
index c0fff0e40cb2b360af8708be3eadeed93fbfc577..1b2da9421ae824bf5cdbf77113de45974fd228ea 100644 (file)
@@ -214,9 +214,7 @@ Siddarth Gore <gores@marvell.com>
 Paul Gortmaker <paul.gortmaker@windriver.com>
 
        sbc8349         MPC8349
-       sbc8540         MPC8540
        sbc8548         MPC8548
-       sbc8560         MPC8560
        sbc8641d        MPC8641D
 
 Frank Gottschling <fgottschling@eltec.de>
index 08eecbbbcdff22746e2febc856c8045f600ec6b6..328347d1775a4c78a4293bbebfe6165334462eac 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -260,7 +260,8 @@ LIBS-y += drivers/net/npe/libnpe.o
 endif
 LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
 LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/cramfs/libcramfs.o \
+LIBS-y += fs/cbfs/libcbfs.o \
+       fs/cramfs/libcramfs.o \
        fs/ext4/libext4fs.o \
        fs/fat/libfat.o \
        fs/fdos/libfdos.o \
@@ -533,9 +534,10 @@ GEN_UBOOT = \
                        $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
 else
 GEN_UBOOT = \
-               UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
-               sed  -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
-               cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__OBJS) \
+               UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+               sed  -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
+               cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+                       $$UNDEF_LST $(__OBJS) \
                        --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
                        -Map u-boot.map -o u-boot
 endif
@@ -568,8 +570,12 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot
 $(LDSCRIPT):   depend
                $(MAKE) -C $(dir $@) $(notdir $@)
 
-$(obj)u-boot.lds: $(LDSCRIPT)
-               $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates u-boot.lst,
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
+$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
+               $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
 
 nand_spl:      $(TIMESTAMP_FILE) $(VERSION_FILE) depend
                $(MAKE) -C nand_spl/board/$(BOARDDIR) all
@@ -808,6 +814,7 @@ clean:
               $(obj)board/matrix_vision/*/bootscript.img                 \
               $(obj)board/voiceblue/eeprom                               \
               $(obj)u-boot.lds                                           \
+              $(obj)include/u-boot.lst                                   \
               $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]          \
               $(obj)arch/blackfin/cpu/init.{lds,elf}
        @rm -f $(obj)include/bmp_logo.h
@@ -841,8 +848,10 @@ clobber:   tidy
        @rm -f $(obj)u-boot.dtb
        @rm -f $(obj)u-boot.sb
        @rm -f $(obj)u-boot.spr
-       @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
-       @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
+       @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
+       @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
+       @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
+       @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
        @rm -f $(obj)MLO
        @rm -f $(obj)tools/xway-swap-bytes
        @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
diff --git a/README b/README
index df4aed14e4ed35f6e0d6f7a448b15b0c8240a164..69da2b86ba14219d735fe401af34d46a54ab0433 100644 (file)
--- a/README
+++ b/README
@@ -363,6 +363,12 @@ The following options need to be configured:
                ICache only when Code runs from RAM.
 
 - 85xx CPU Options:
+               CONFIG_SYS_PPC64
+
+               Specifies that the core is a 64-bit PowerPC implementation (implements
+               the "64" category of the Power ISA). This is necessary for ePAPR
+               compliance, among other possible reasons.
+
                CONFIG_SYS_FSL_TBCLK_DIV
 
                Defines the core time base clock divider ratio compared to the
@@ -1084,7 +1090,7 @@ The following options need to be configured:
                CONFIG_CALXEDA_XGMAC
                Support for the Calxeda XGMAC device
 
-               CONFIG_DRIVER_LAN91C96
+               CONFIG_LAN91C96
                Support for SMSC's LAN91C96 chips.
 
                        CONFIG_LAN91C96_BASE
@@ -1094,7 +1100,7 @@ The following options need to be configured:
                        CONFIG_LAN91C96_USE_32_BIT
                        Define this to enable 32 bit addressing
 
-               CONFIG_DRIVER_SMC91111
+               CONFIG_SMC91111
                Support for SMSC's LAN91C111 chip
 
                        CONFIG_SMC91111_BASE
@@ -1316,6 +1322,13 @@ The following options need to be configured:
                This will also enable the command "fatwrite" enabling the
                user to write files to FAT.
 
+CBFS (Coreboot Filesystem) support
+               CONFIG_CMD_CBFS
+
+               Define this to enable support for reading from a Coreboot
+               filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
+               and cbfsload.
+
 - Keyboard Support:
                CONFIG_ISA_KEYBOARD
 
index dc6ba34082ecd33e58e8b989f83e82b84a3fe6f2..008ae891cafd8e47b8dc44ad9fc4b0918f37cdb1 100644 (file)
@@ -48,9 +48,11 @@ SECTIONS
        .got : { *(.got) }
 
        . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
        __bss_start = .;
index f8ea38c03d4758f261e063b710273e6ab66ac9e4..6dc681a313988550f78399232d6a6a7bcdff57ba 100644 (file)
@@ -50,9 +50,10 @@ SECTIONS
        }
 
        . = ALIGN(4);
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       .u_boot_list : {
+               #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
index afd3381e1675bd33457215f523d928590fb179f3..f3bd5e736757e756a4829206164052513d42e717 100644 (file)
@@ -50,9 +50,10 @@ SECTIONS
        }
 
        . = ALIGN(4);
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       .u_boot_list : {
+               #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
index 1d8efb213bf4f9198e4a43db16870d5b54f20afe..9979c3085360b19c5c5e585fc6f677ec84018857 100644 (file)
@@ -47,6 +47,11 @@ SECTIONS
 
        . = ALIGN(4);
        .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+       .u_boot_list : {
+               #include <u-boot.lst>
+       }
+
        . = ALIGN(4);
        __image_copy_end = .;
        _end = .;
index 7199de4af1e317fed2cf01764d57d536f6c2f562..81d954f2de7fce029d5e74b81bdfcc00ff9b82cb 100644 (file)
@@ -46,9 +46,11 @@ SECTIONS
        . = ALIGN(4);
 
        . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
index e49ca0c5522912ba8849182105cf141e04d0c6b3..227aaff1e60b822056736137e402faf6a3e707a9 100644 (file)
@@ -49,9 +49,11 @@ SECTIONS
        . = ALIGN(4);
 
        . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
index 02fe72ed7faa2f418ad85bf7eabc2ea906c74b90..ddc14b099e6cdd4e46dbfe83bd0f1025bcebd0f9 100644 (file)
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/imx-common/boot_mode.h>
 #include <malloc.h>
+#include <command.h>
 
 static const struct boot_mode *modes[2];
 
@@ -103,9 +104,11 @@ void add_board_boot_modes(const struct boot_mode *p)
        int size;
        char *dest;
 
-       if (__u_boot_cmd_bmode.usage) {
-               free(__u_boot_cmd_bmode.usage);
-               __u_boot_cmd_bmode.usage = NULL;
+       cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
+
+       if (entry->usage) {
+               free(entry->usage);
+               entry->usage = NULL;
        }
 
        modes[0] = p;
@@ -114,6 +117,6 @@ void add_board_boot_modes(const struct boot_mode *p)
        dest = malloc(size);
        if (dest) {
                create_usage(dest);
-               __u_boot_cmd_bmode.usage = dest;
+               entry->usage = dest;
        }
 }
index f8088fe21a1f9c889f2518efa3f7d10873667c4d..2b9af938068ed1e30e264bf65510104859ff5d2f 100644 (file)
@@ -34,7 +34,7 @@
 typedef        struct  global_data {
        bd_t            *bd;
        unsigned long   flags;
-       unsigned long   baudrate;
+       unsigned int    baudrate;
        unsigned long   have_console;   /* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
        unsigned long   precon_buf_idx; /* Pre-Console buffer index */
index eac3800729feded2aaf21c86fa83bd34a3c9404d..2ba98bca7da953e8493205bb806aa5c0a6af44fe 100644 (file)
@@ -37,7 +37,7 @@
 #define _U_BOOT_H_     1
 
 typedef struct bd_info {
-    int                        bi_baudrate;    /* serial console baudrate */
+       unsigned int    bi_baudrate;    /* serial console baudrate */
     ulong              bi_arch_number; /* unique id for this board */
     ulong              bi_boot_params; /* where this board expects params */
        unsigned long   bi_arm_freq; /* arm frequency */
index 99cb54b8d8c88e1ef4a7e81e8a8b72e747169a29..92cad9a6eb1a8c2f0b71ad7d6c19bb61780fc383 100644 (file)
 #include <miiphy.h>
 #endif
 
-#ifdef CONFIG_DRIVER_SMC91111
-#include "../drivers/net/smc91111.h"
-#endif
-#ifdef CONFIG_DRIVER_LAN91C96
-#include "../drivers/net/lan91c96.h"
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 ulong monitor_flash_len;
@@ -613,16 +606,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
        /* enable exceptions */
        enable_interrupts();
 
-       /* Perform network card initialisation if necessary */
-#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
-       /* XXX: this needs to be moved to board init */
-       if (getenv("ethaddr")) {
-               uchar enetaddr[6];
-               eth_getenv_enetaddr("ethaddr", enetaddr);
-               smc_set_mac_addr(enetaddr);
-       }
-#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
-
        /* Initialize from environment */
        load_addr = getenv_ulong("loadaddr", 16, load_addr);
 
index 0e532f234e4c3d0a0350dba456433d308fb66c9d..0b16d2a883d9bc3e9303889962ee73bf8aaee018 100644 (file)
@@ -47,11 +47,11 @@ SECTIONS
        }
 
        . = ALIGN(4);
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : {
-               KEEP(*(.u_boot_cmd))
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
        }
-       __u_boot_cmd_end = .;
 
        . = ALIGN(4);
        _got = .;
index 7878bb185a96d5375c01d56ff6b656e56e939e88..bf661e23be93d9384f03618aa34e1e3c1a279504 100644 (file)
@@ -33,7 +33,7 @@
 typedef        struct  global_data {
        bd_t            *bd;
        unsigned long   flags;
-       unsigned long   baudrate;
+       unsigned int    baudrate;
        unsigned long   stack_end;      /* highest stack address */
        unsigned long   have_console;   /* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
index 1d2959a2adabf03f17737474ba5b747240964e25..97bbbdef6df76b152d9769d918ba36b7ff663144 100644 (file)
@@ -23,7 +23,7 @@
 #define __ASM_U_BOOT_H__ 1
 
 typedef struct bd_info {
-       unsigned long           bi_baudrate;
+       unsigned int            bi_baudrate;
        unsigned char           bi_phy_id[4];
        unsigned long           bi_board_number;
        void                    *bi_boot_params;
index 9d3b76e15ae8504551eeb23a15f9ac84aa19e5f8..e3287c486b1b985d462e1085b20cb09b8db781b7 100644 (file)
@@ -272,8 +272,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
        /*
         * We have to relocate the command table manually
         */
-       fixup_cmdtable(&__u_boot_cmd_start,
-               (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+       fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+                       ll_entry_count(cmd_tbl_t, cmd));
 #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
        /* there are some other pointer constants we must deal with */
index 2b8d285e1f420a52be8d99c1e1dbbb3e0ff2a7e1..58db838fb02bbd950b2fed3ead12858e22477791 100644 (file)
@@ -112,11 +112,9 @@ SECTIONS
                CONSTRUCTORS
        } >ram_data
 
-       .u_boot_cmd :
-       {
-               ___u_boot_cmd_start = .;
-               *(.u_boot_cmd)
-               ___u_boot_cmd_end = .;
+
+       .u_boot_list : {
+               #include <u-boot.lst>
        } >ram_data
 
        .text_l1 :
index 290a9e766294e9e91846998457c0d0b2d025241f..d91e5a40d314f2dd96b8cf28739bf798e7a7a30b 100644 (file)
@@ -41,7 +41,7 @@ typedef struct global_data {
        bd_t *bd;
        unsigned long flags;
        unsigned long board_type;
-       unsigned long baudrate;
+       unsigned int baudrate;
        unsigned long have_console;     /* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
        unsigned long   precon_buf_idx; /* Pre-Console buffer index */
index df81183e81127eaf33cf14104ee2615d6fe12695..7abd6c2a329dc5bdb23c574f950c1dda59b12cc2 100644 (file)
@@ -29,7 +29,7 @@
 #define _U_BOOT_H_     1
 
 typedef struct bd_info {
-       int bi_baudrate;                /* serial console baudrate */
+       unsigned int bi_baudrate;       /* serial console baudrate */
        unsigned long bi_boot_params;   /* where this board expects params */
        unsigned long bi_memstart;      /* start of DRAM memory */
        phys_size_t bi_memsize;         /* size  of DRAM memory in bytes */
index e47b606e8768f7d2478847720cc977b51bc72ba9..9fbbea0d9b092cee0f6d4019418a701d5577be8d 100644 (file)
@@ -78,7 +78,7 @@ static void display_global_data(void)
        printf(" gd: %p\n", gd);
        printf(" |-flags: %lx\n", gd->flags);
        printf(" |-board_type: %lx\n", gd->board_type);
-       printf(" |-baudrate: %lu\n", gd->baudrate);
+       printf(" |-baudrate: %u\n", gd->baudrate);
        printf(" |-have_console: %lx\n", gd->have_console);
        printf(" |-ram_size: %lx\n", gd->ram_size);
        printf(" |-env_addr: %lx\n", gd->env_addr);
index e23b20df9166473e6627aa3ec208799670acf192..1928eb384e23170a70b33b341a638f8e2be4e733 100644 (file)
@@ -31,6 +31,7 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 #include <asm/rtc.h>
+#include <linux/compiler.h>
 
 /*
  * Breath some life into the CPU...
  */
 void cpu_init_f(void)
 {
-       scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-       fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-       pll_t *pll = (pll_t *)MMAP_PLL;
+       fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
 
 #if !defined(CONFIG_CF_SBF)
+       scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+       pll_t *pll = (pll_t *)MMAP_PLL;
+
        /* Workaround, must place before fbcs */
        out_be32(&pll->psr, 0x12);
 
index c5096a80c204dcb4aeeef864389140ca8ee46f87..a6837781277d94f62f53f304a68c1a7a8e3e6597 100644 (file)
@@ -485,7 +485,7 @@ clear_bss:
 /* exception code */
        .globl _fault
 _fault:
-       jmp _fault
+       bra _fault
        .globl  _exc_handler
 
 _exc_handler:
index e6a69ab470cb0c71661acb7a90ceb4cf4e69fa7f..05f17231b293c4b60da86e5ad905495622da7d84 100644 (file)
@@ -247,7 +247,7 @@ clear_bss:
 /* exception code */
        .globl _fault
 _fault:
-       jmp _fault
+       bra _fault
        .globl  _exc_handler
 
 _exc_handler:
index ee17792cb391ca3a485a8e27834b180fb81965d7..f5e55dd9657c9209ca72dd3346165a02ee38a12f 100644 (file)
@@ -307,7 +307,7 @@ clear_bss:
 /* exception code */
        .globl _fault
 _fault:
-       jmp _fault
+       bra _fault
 
        .globl  _exc_handler
 _exc_handler:
index fe98d76474af37aefb37c3a7bcab499e7db0faf4..583ed1d41ac1c50037878bc7805fb6edf1ce0671 100644 (file)
@@ -261,7 +261,7 @@ clear_bss:
 /* exception code */
        .globl _fault
 _fault:
-       jmp _fault
+       bra _fault
        .globl  _exc_handler
 
 _exc_handler:
index 61a731eeffc348d4a89736d9057c875e9d87fac6..0c48783e4cb0277e4b0a1c6eddaeba8b31db4cb3 100644 (file)
@@ -4,6 +4,8 @@
 # (C) Copyright 2000-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
+# Copyright 2011-2012 Freescale Semiconductor, Inc.
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg))
+
+ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x)))
+PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC
+else
 PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
+endif
 
 ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
 ifneq (,$(findstring GOT,$(shell $(LD) --help)))
index adfc708c35968b07b50e3060928d2ab02a300302..b612cdaea1ac28975184fbb090c79c40f69d7ab6 100644 (file)
@@ -39,6 +39,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        rcm_t *rcm = (rcm_t *) (MMAP_RCM);
        udelay(1000);
+       out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT);
+       udelay(10000);
        setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
        /* we don't return! */
@@ -74,6 +76,21 @@ int checkcpu(void)
        case 0x4f:
                id = 54450;
                break;
+       case 0x9F:
+               id = 54410;
+               break;
+       case 0xA0:
+               id = 54415;
+               break;
+       case 0xA1:
+               id = 54416;
+               break;
+       case 0xA2:
+               id = 54417;
+               break;
+       case 0xA3:
+               id = 54418;
+               break;
        }
 
        if (id) {
index 3f9209ff196ed8ff93887c84f33f9bfe3b84d05c..6e947d06f92af2c6689bd4758bbd029c17aa785f 100644 (file)
@@ -31,6 +31,7 @@
 #include <asm/processor.h>
 #include <asm/rtc.h>
 #include <asm/io.h>
+#include <linux/compiler.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
 #include <asm/fec.h>
 #endif
 
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
+void init_fbcs(void)
 {
-       scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-       fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
-       out_be32(&scm1->mpr, 0x77777777);
-       out_be32(&scm1->pacra, 0);
-       out_be32(&scm1->pacrb, 0);
-       out_be32(&scm1->pacrc, 0);
-       out_be32(&scm1->pacrd, 0);
-       out_be32(&scm1->pacre, 0);
-       out_be32(&scm1->pacrf, 0);
-       out_be32(&scm1->pacrg, 0);
+       fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
 
-       /* FlexBus */
-       out_8(&gpio->par_be,
-               GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
-               GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
-       out_8(&gpio->par_fbctl,
-               GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
-               GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
-
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
        out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
        out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
@@ -106,6 +81,145 @@ void cpu_init_f(void)
        out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
        out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
+}
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+#ifdef CONFIG_MCF5441x
+       scm_t *scm = (scm_t *) MMAP_SCM;
+       pm_t *pm = (pm_t *) MMAP_PM;
+
+       /* Disable Switch */
+       *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
+
+       /* Disable core watchdog */
+       out_be16(&scm->cwcr, 0);
+       out_8(&gpio->par_fbctl,
+               GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
+               GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
+               GPIO_PAR_FBCTL_TA_TA);
+       out_8(&gpio->par_be,
+               GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+               GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+
+       /* eDMA */
+       out_8(&pm->pmcr0, 17);
+
+       /* INTR0 - INTR2 */
+       out_8(&pm->pmcr0, 18);
+       out_8(&pm->pmcr0, 19);
+       out_8(&pm->pmcr0, 20);
+
+       /* I2C */
+       out_8(&pm->pmcr0, 22);
+       out_8(&pm->pmcr1, 4);
+       out_8(&pm->pmcr1, 7);
+
+       /* DTMR0 - DTMR3*/
+       out_8(&pm->pmcr0, 28);
+       out_8(&pm->pmcr0, 29);
+       out_8(&pm->pmcr0, 30);
+       out_8(&pm->pmcr0, 31);
+
+       /* PIT0 - PIT3 */
+       out_8(&pm->pmcr0, 32);
+       out_8(&pm->pmcr0, 33);
+       out_8(&pm->pmcr0, 34);
+       out_8(&pm->pmcr0, 35);
+
+       /* Edge Port */
+       out_8(&pm->pmcr0, 36);
+       out_8(&pm->pmcr0, 37);
+
+       /* USB OTG */
+       out_8(&pm->pmcr0, 44);
+       /* USB Host */
+       out_8(&pm->pmcr0, 45);
+
+       /* ESDHC */
+       out_8(&pm->pmcr0, 51);
+
+       /* ENET0 - ENET1 */
+       out_8(&pm->pmcr0, 53);
+       out_8(&pm->pmcr0, 54);
+
+       /* NAND */
+       out_8(&pm->pmcr0, 63);
+
+#ifdef CONFIG_SYS_I2C_0
+       out_8(&gpio->par_cani2c, 0xF0);
+       /* I2C0 pull up */
+       out_be16(&gpio->pcr_b, 0x003C);
+       /* I2C0 max speed */
+       out_8(&gpio->srcr_cani2c, 0x03);
+#endif
+#ifdef CONFIG_SYS_I2C_2
+       /* I2C2 */
+       out_8(&gpio->par_ssi0h, 0xA0);
+       /* I2C2, UART7 */
+       out_8(&gpio->par_ssi0h, 0xA8);
+       /* UART7 */
+       out_8(&gpio->par_ssi0l, 0x2);
+       /* UART8, UART9 */
+       out_8(&gpio->par_cani2c, 0xAA);
+       /* UART4, UART0 */
+       out_8(&gpio->par_uart0, 0xAF);
+       /* UART5, UART1 */
+       out_8(&gpio->par_uart1, 0xAF);
+       /* UART6, UART2 */
+       out_8(&gpio->par_uart2, 0xAF);
+       /* I2C2 pull up */
+       out_be16(&gpio->pcr_h, 0xF000);
+#endif
+#ifdef CONFIG_SYS_I2C_5
+       /* I2C5 */
+       out_8(&gpio->par_uart1, 0x0A);
+       /* I2C5 pull up */
+       out_be16(&gpio->pcr_e, 0x0003);
+       out_be16(&gpio->pcr_f, 0xC000);
+#endif
+
+       /* Lowest slew rate for UART0,1,2 */
+       out_8(&gpio->srcr_uart, 0x00);
+#endif         /* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
+       scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+       out_be32(&scm1->mpr, 0x77777777);
+       out_be32(&scm1->pacra, 0);
+       out_be32(&scm1->pacrb, 0);
+       out_be32(&scm1->pacrc, 0);
+       out_be32(&scm1->pacrd, 0);
+       out_be32(&scm1->pacre, 0);
+       out_be32(&scm1->pacrf, 0);
+       out_be32(&scm1->pacrg, 0);
+
+       /* FlexBus */
+       out_8(&gpio->par_be,
+               GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+               GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+       out_8(&gpio->par_fbctl,
+               GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+               GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+
+#ifdef CONFIG_FSL_I2C
+       out_be16(&gpio->par_feci2c,
+               GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
+#endif
+#endif         /* CONFIG_MCF5445x */
+
+       /* FlexBus Chipselect */
+       init_fbcs();
 
        /*
         * now the flash base address is no longer at 0 (Newer ColdFire family
@@ -115,11 +229,6 @@ void cpu_init_f(void)
        if (CONFIG_SYS_CS0_BASE != 0)
                setvbr(CONFIG_SYS_CS0_BASE);
 
-#ifdef CONFIG_FSL_I2C
-       out_be16(&gpio->par_feci2c,
-               GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
-#endif
-
        icache_enable();
 }
 
@@ -142,9 +251,95 @@ int cpu_init_r(void)
 void uart_port_conf(int port)
 {
        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5441x
+       pm_t *pm = (pm_t *) MMAP_PM;
+#endif
 
        /* Setup Ports: */
        switch (port) {
+#ifdef CONFIG_MCF5441x
+       case 0:
+               /* UART0 */
+               out_8(&pm->pmcr0, 24);
+               clrbits_8(&gpio->par_uart0,
+                       ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
+               setbits_8(&gpio->par_uart0,
+                       GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
+               break;
+       case 1:
+               /* UART1 */
+               out_8(&pm->pmcr0, 25);
+               clrbits_8(&gpio->par_uart1,
+                       ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
+               setbits_8(&gpio->par_uart1,
+                       GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
+               break;
+       case 2:
+               /* UART2 */
+               out_8(&pm->pmcr0, 26);
+               clrbits_8(&gpio->par_uart2,
+                       ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
+               setbits_8(&gpio->par_uart2,
+                       GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
+               break;
+       case 3:
+               /* UART3 */
+               out_8(&pm->pmcr0, 27);
+               clrbits_8(&gpio->par_dspi0,
+                       ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
+               setbits_8(&gpio->par_dspi0,
+                       GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
+               break;
+       case 4:
+               /* UART4 */
+               out_8(&pm->pmcr1, 24);
+               clrbits_8(&gpio->par_uart0,
+                       ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
+               setbits_8(&gpio->par_uart0,
+                       GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
+               break;
+       case 5:
+               /* UART5 */
+               out_8(&pm->pmcr1, 25);
+               clrbits_8(&gpio->par_uart1,
+                       ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
+               setbits_8(&gpio->par_uart1,
+                       GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
+               break;
+       case 6:
+               /* UART6 */
+               out_8(&pm->pmcr1, 26);
+               clrbits_8(&gpio->par_uart2,
+                       ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
+               setbits_8(&gpio->par_uart2,
+                       GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
+               break;
+       case 7:
+               /* UART7 */
+               out_8(&pm->pmcr1, 27);
+               clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
+               clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
+               setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
+               setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
+               break;
+       case 8:
+               /* UART8 */
+               out_8(&pm->pmcr0, 28);
+               clrbits_8(&gpio->par_cani2c,
+                       ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
+               setbits_8(&gpio->par_cani2c,
+                       GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
+               break;
+       case 9:
+               /* UART9 */
+               out_8(&pm->pmcr1, 29);
+               clrbits_8(&gpio->par_cani2c,
+                       ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
+               setbits_8(&gpio->par_cani2c,
+                       GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
+               break;
+#endif
+#ifdef CONFIG_MCF5445x
        case 0:
                clrbits_8(&gpio->par_uart,
                        GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
@@ -177,6 +372,7 @@ void uart_port_conf(int port)
                        GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
 #endif
                break;
+#endif /* CONFIG_MCF5445x */
        }
 }
 
@@ -186,6 +382,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
        struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
+#ifdef CONFIG_MCF5445x
        if (setclear) {
 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
                if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
@@ -223,6 +420,21 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 #endif
                }
        }
+#endif /* CONFIG_MCF5445x */
+
+#ifdef CONFIG_MCF5441x
+       if (setclear) {
+               out_8(&gpio->par_fec, 0x03);
+               out_8(&gpio->srcr_fec, 0x0F);
+               clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
+                       GPIO_PAR_SIMP0H_DAT_GPIO);
+               clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
+                       GPIO_PDDR_G4_OUTPUT);
+               clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
+
+       } else
+               clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
+#endif
        return 0;
 }
 #endif
@@ -232,10 +444,24 @@ void cfspi_port_conf(void)
 {
        gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
+#ifdef CONFIG_MCF5445x
        out_8(&gpio->par_dspi,
                GPIO_PAR_DSPI_SIN_SIN |
                GPIO_PAR_DSPI_SOUT_SOUT |
                GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+       pm_t *pm = (pm_t *) MMAP_PM;
+
+       out_8(&gpio->par_dspi0,
+               GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+               GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+       out_8(&gpio->srcr_dspiow, 3);
+
+       /* DSPI0 */
+       out_8(&pm->pmcr0, 23);
+#endif
 }
 
 int cfspi_claim_bus(uint bus, uint cs)
@@ -249,6 +475,7 @@ int cfspi_claim_bus(uint bus, uint cs)
        /* Clear FIFO and resume transfer */
        clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
+#ifdef CONFIG_MCF5445x
        switch (cs) {
        case 0:
                clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
@@ -271,6 +498,20 @@ int cfspi_claim_bus(uint bus, uint cs)
                setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
                break;
        }
+#endif
+
+#ifdef CONFIG_MCF5441x
+       switch (cs) {
+       case 0:
+               clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
+               setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
+               break;
+       case 1:
+               clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+               setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+               break;
+       }
+#endif
 
        return 0;
 }
@@ -283,6 +524,7 @@ void cfspi_release_bus(uint bus, uint cs)
        /* Clear FIFO */
        clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
+#ifdef CONFIG_MCF5445x
        switch (cs) {
        case 0:
                clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
@@ -300,5 +542,11 @@ void cfspi_release_bus(uint bus, uint cs)
                clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
                break;
        }
+#endif
+
+#ifdef CONFIG_MCF5441x
+       if (cs == 1)
+               clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+#endif
 }
 #endif
index 073b7efafb5b7769d7be4ca33d19791a8750deac..55d1c488a317f5e11e803fb2a2a2f7901062c93d 100644 (file)
@@ -57,8 +57,10 @@ void clock_enter_limp(int lpdiv)
        /* Round divider down to nearest power of two */
        for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
 
+#ifdef CONFIG_MCF5445x
        /* Apply the divider to the system clock */
        clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
+#endif
 
        /* Enable Limp Mode */
        setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
@@ -81,19 +83,76 @@ void clock_exit_limp(void)
                ;
 }
 
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
-int get_clocks(void)
+#ifdef CONFIG_MCF5441x
+void setup_5441x_clocks(void)
 {
+       ccm_t *ccm = (ccm_t *)MMAP_CCM;
+       pll_t *pll = (pll_t *)MMAP_PLL;
+       int temp, vco = 0, bootmod_ccr, pdr;
+
+       bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
+
+       switch (bootmod_ccr) {
+       case 0:
+               out_be32(&pll->pcr, 0x00000013);
+               out_be32(&pll->pdr, 0x00e70c61);
+               clock_exit_limp();
+               break;
+       case 2:
+               break;
+       case 3:
+               break;
+       }
+
+       /*Change frequency for Modelo SER1 USB host*/
+#ifdef CONFIG_LOW_MCFCLK
+       temp = in_be32(&pll->pcr);
+       temp &= ~0x3f;
+       temp |= 5;
+       out_be32(&pll->pcr, temp);
+
+       temp = in_be32(&pll->pdr);
+       temp &= ~0x001f0000;
+       temp |= 0x00040000;
+       out_be32(&pll->pdr, temp);
+       __asm__("tpf");
+#endif
 
+       setbits_be16(&ccm->misccr2, 0x02);
+
+       vco =  ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
+               CONFIG_SYS_INPUT_CLKSRC;
+       gd->vco_clk = vco;
+
+       gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;  /* Input clock */
+
+       pdr = in_be32(&pll->pdr);
+       temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
+       gd->cpu_clk = vco / temp;       /* cpu clock */
+       gd->flb_clk = vco / temp;       /* FlexBus clock */
+       gd->flb_clk >>= 1;
+       if (in_be16(ccm->misccr2) & 2)          /* fsys/4 */
+               gd->flb_clk >>= 1;
+
+       temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
+       gd->bus_clk = vco / temp;       /* bus clock */
+
+}
+#endif
+
+#ifdef CONFIG_MCF5445x
+void setup_5445x_clocks(void)
+{
        ccm_t *ccm = (ccm_t *)MMAP_CCM;
        pll_t *pll = (pll_t *)MMAP_PLL;
        int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
        int pllmult_pci[] = { 12, 6, 16, 8 };
-       int vco = 0, bPci, temp, fbtemp, pcrvalue;
+       int vco = 0, temp, fbtemp, pcrvalue;
        int *pPllmult = NULL;
        u16 fbpll_mask;
+#ifdef CONFIG_PCI
+       int bPci;
+#endif
 
 #ifdef CONFIG_M54455EVB
        u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
@@ -105,14 +164,16 @@ int get_clocks(void)
            ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
                pPllmult = &pllmult_pci[0];
                fbpll_mask = 3;         /* 11b */
+#ifdef CONFIG_PCI
                bPci = 1;
+#endif
        } else {
                pPllmult = &pllmult_nopci[0];
                fbpll_mask = 7;         /* 111b */
 #ifdef CONFIG_PCI
                gd->pci_clk = 0;
-#endif
                bPci = 0;
+#endif
        }
 
 #ifdef CONFIG_M54455EVB
@@ -212,6 +273,22 @@ int get_clocks(void)
 #endif
        }
 
+#ifdef CONFIG_FSL_I2C
+       gd->i2c1_clk = gd->bus_clk;
+#endif
+}
+#endif
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+#ifdef CONFIG_MCF5441x
+       setup_5441x_clocks();
+#endif
+#ifdef CONFIG_MCF5445x
+       setup_5445x_clocks();
+#endif
+
 #ifdef CONFIG_FSL_I2C
        gd->i2c1_clk = gd->bus_clk;
 #endif
index 99060141d883b40d27b05f5197fadb14f05bd5e1..5fc944d2f3edfd009e955df1bf968d92a46eb573 100644 (file)
@@ -2,6 +2,9 @@
  * Copyright (C) 2003  Josef Baumgartner <josef.baumgartner@telex.de>
  * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
  *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * MA 02111-1307 USA
  */
 
+#include <common.h>
 #include <asm-offsets.h>
 #include <config.h>
+#include <timestamp.h>
 #include "version.h"
 #include <asm/cache.h>
 
@@ -43,8 +48,9 @@
        addl    #60,%sp;                /* space for 15 regs */ \
        rte;
 
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
 #define ASM_DRAMINIT   (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT_N (asm_dram_init - TEXT_BASE)
 #define ASM_SBF_IMG_HDR        (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
 #endif
 
  *     These vectors are to catch any un-intended traps.
  */
 _vectors:
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
 
 INITSP:        .long   0               /* Initial SP   */
+#ifdef CONFIG_CF_SBF
 INITPC:        .long   ASM_DRAMINIT    /* Initial PC   */
+#endif
+#ifdef CONFIG_SYS_NAND_BOOT
+INITPC:        .long   ASM_DRAMINIT_N  /* Initial PC   */
+#endif
 
 #else
 
@@ -95,7 +106,7 @@ vector1D:    .long   _FAULT  /* Autovector Level 5   */
 vector1E:      .long   _FAULT  /* Autovector Level 6   */
 vector1F:      .long   _FAULT  /* Autovector Level 7   */
 
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
 
 /* TRAP #0 - #15 */
 vector20_2F:
@@ -138,16 +149,26 @@ vector192_255:
 .long  _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 #endif
 
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
        /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
 asm_sbf_img_hdr:
        .long   0x00000000      /* checksum, not yet implemented */
-       .long   0x00030000      /* image length */
+       .long   0x00040000      /* image length */
        .long   CONFIG_SYS_TEXT_BASE    /* image to be relocated at */
 
 asm_dram_init:
        move.w #0x2700,%sr              /* Mask off Interrupt */
 
+#ifdef CONFIG_SYS_NAND_BOOT
+       /* for assembly stack */
+       move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+       movec   %d0, %RAMBAR1
+
+       move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+       clr.l %sp@-
+#endif
+
+#ifdef CONFIG_CF_SBF
        move.l  #CONFIG_SYS_INIT_RAM_ADDR, %d0
        movec   %d0, %VBR
 
@@ -180,7 +201,90 @@ asm_dram_init:
        move.l  #(CONFIG_SYS_CS0_CTRL), (%a1)
        move.l  #0xFC008004, %a1
        move.l  #(CONFIG_SYS_CS0_MASK), (%a1)
+#endif                 /* CONFIG_CF_SBF */
+
+#ifdef CONFIG_MCF5441x
+       /* TC: enable all peripherals,
+       in the future only enable certain peripherals */
+       move.l  #0xFC04002D, %a1
 
+#if defined(CONFIG_CF_SBF)
+       move.b  #23, (%a1)      /* dspi */
+#endif
+       move.b  #46, (%a1)      /* DDR */
+
+       /* slew settings */
+       move.l  #0xEC094060, %a1
+       move.b  #0, (%a1)
+
+       /* use vco instead of cpu*2 clock for ddr clock */
+       move.l  #0xEC09001A, %a1
+       move.w  #0xE01D, (%a1)
+
+       /* DDR settings */
+       move.l  #0xFC0B8180, %a1
+       move.l  #0x00000000, (%a1)
+       move.l  #0x40000000, (%a1)
+
+       move.l  #0xFC0B81AC, %a1
+       move.l  #0x01030203, (%a1)
+
+       move.l  #0xFC0B8000, %a1
+       move.l  #0x01010101, (%a1)+     /* 0x00 */
+       move.l  #0x00000101, (%a1)+     /* 0x04 */
+       move.l  #0x01010100, (%a1)+     /* 0x08 */
+       move.l  #0x01010000, (%a1)+     /* 0x0C */
+       move.l  #0x00010101, (%a1)+     /* 0x10 */
+       move.l  #0xFC0B8018, %a1
+       move.l  #0x00010100, (%a1)+     /* 0x18 */
+       move.l  #0x00000001, (%a1)+     /* 0x1C */
+       move.l  #0x01000001, (%a1)+     /* 0x20 */
+       move.l  #0x00000100, (%a1)+     /* 0x24 */
+       move.l  #0x00010001, (%a1)+     /* 0x28 */
+       move.l  #0x00000200, (%a1)+     /* 0x2C */
+       move.l  #0x01000002, (%a1)+     /* 0x30 */
+       move.l  #0x00000000, (%a1)+     /* 0x34 */
+       move.l  #0x00000100, (%a1)+     /* 0x38 */
+       move.l  #0x02000100, (%a1)+     /* 0x3C */
+       move.l  #0x02000407, (%a1)+     /* 0x40 */
+       move.l  #0x02030007, (%a1)+     /* 0x44 */
+       move.l  #0x02000100, (%a1)+     /* 0x48 */
+       move.l  #0x0A030203, (%a1)+     /* 0x4C */
+       move.l  #0x00020708, (%a1)+     /* 0x50 */
+       move.l  #0x00050008, (%a1)+     /* 0x54 */
+       move.l  #0x04030002, (%a1)+     /* 0x58 */
+       move.l  #0x00000004, (%a1)+     /* 0x5C */
+       move.l  #0x020A0000, (%a1)+     /* 0x60 */
+       move.l  #0x0C00000E, (%a1)+     /* 0x64 */
+       move.l  #0x00002004, (%a1)+     /* 0x68 */
+       move.l  #0x00000000, (%a1)+     /* 0x6C */
+       move.l  #0x00100010, (%a1)+     /* 0x70 */
+       move.l  #0x00100010, (%a1)+     /* 0x74 */
+       move.l  #0x00000000, (%a1)+     /* 0x78 */
+       move.l  #0x07990000, (%a1)+     /* 0x7C */
+       move.l  #0xFC0B80A0, %a1
+       move.l  #0x00000000, (%a1)+     /* 0xA0 */
+       move.l  #0x00C80064, (%a1)+     /* 0xA4 */
+       move.l  #0x44520002, (%a1)+     /* 0xA8 */
+       move.l  #0x00C80023, (%a1)+     /* 0xAC */
+       move.l  #0xFC0B80B4, %a1
+       move.l  #0x0000C350, (%a1)      /* 0xB4 */
+       move.l  #0xFC0B80E0, %a1
+       move.l  #0x04000000, (%a1)+     /* 0xE0 */
+       move.l  #0x03000304, (%a1)+     /* 0xE4 */
+       move.l  #0x40040000, (%a1)+     /* 0xE8 */
+       move.l  #0xC0004004, (%a1)+     /* 0xEC */
+       move.l  #0x0642C000, (%a1)+     /* 0xF0 */
+       move.l  #0x00000642, (%a1)+     /* 0xF4 */
+       move.l  #0xFC0B8024, %a1
+       tpf
+       move.l  #0x01000100, (%a1)      /* 0x24 */
+
+       move.l  #0x2000, %d1
+       jsr     asm_delay
+#endif         /* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
        /* Dram Initialization a1, a2, and d0 */
        /* mscr sdram */
        move.l  #0xFC0A4074, %a1
@@ -203,7 +307,9 @@ dramsz_loop:
        add.l   #1, %d1
        cmp.l   #1, %d2
        bne     dramsz_loop
-
+#ifdef CONFIG_SYS_NAND_BOOT
+       beq     asm_nand_chk_status
+#endif
        /* SDRAM Chip 0 and 1 */
        move.l  #(CONFIG_SYS_SDRAM_BASE), (%a1)
        or.l    %d1, (%a1)
@@ -275,7 +381,9 @@ dramsz_loop:
 
        move.l  #2000, %d1
        jsr     asm_delay
+#endif         /* CONFIG_MCF5445x */
 
+#ifdef CONFIG_CF_SBF
        /*
         * DSPI Initialization
         * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
@@ -286,15 +394,28 @@ dramsz_loop:
         */
        /* Enable pins for DSPI mode - chip-selects are enabled later */
 asm_dspi_init:
+#ifdef CONFIG_MCF5441x
+       move.l  #0xEC09404E, %a1
+       move.l  #0xEC09404F, %a2
+       move.b  #0xFF, (%a1)
+       move.b  #0x80, (%a2)
+#endif
+
+#ifdef CONFIG_MCF5445x
        move.l  #0xFC0A4063, %a0
        move.b  #0x7F, (%a0)
-
+#endif
        /* Configure DSPI module */
        move.l  #0xFC05C000, %a0
        move.l  #0x80FF0C00, (%a0)      /* Master, clear TX/RX FIFO */
 
        move.l  #0xFC05C00C, %a0
+#ifdef CONFIG_MCF5441x
+       move.l  #0x3E000016, (%a0)
+#endif
+#ifdef CONFIG_MCF5445x
        move.l  #0x3E000011, (%a0)
+#endif
 
        move.l  #0xFC05C034, %a2        /* dtfr */
        move.l  #0xFC05C03B, %a3        /* drfr */
@@ -379,19 +500,148 @@ asm_dspi_rd_status:
 
        move.b  (%a3), %d1
        rts
+#endif                 /* CONFIG_CF_SBF */
+
+#ifdef CONFIG_SYS_NAND_BOOT
+       /* copy 4 boot pages to dram as soon as possible */
+       /* each page is 996 bytes (1056 total with 60 ECC bytes */
+       move.l  #0x00000000, %a1        /* src */
+       move.l  #TEXT_BASE, %a2         /* dst */
+       move.l  #0x3E0, %d0             /* sz in long */
+
+asm_boot_nand_copy:
+       move.l  (%a1)+, (%a2)+
+       subq.l  #1, %d0
+       bne     asm_boot_nand_copy
+
+       /* jump to memory and execute */
+       move.l  #(asm_nand_init), %a0
+       jmp     (%a0)
+
+asm_nand_init:
+       /* exit nand boot-mode */
+       move.l  #0xFC0FFF30, %a1
+       or.l    #0x00000040, %d1
+       move.l  %d1, (%a1)
+
+       /* initialize general use internal ram */
+       move.l #0, %d0
+       move.l #(CACR_STATUS), %a1      /* CACR */
+       move.l #(ICACHE_STATUS), %a2    /* icache */
+       move.l #(DCACHE_STATUS), %a3    /* dcache */
+       move.l %d0, (%a1)
+       move.l %d0, (%a2)
+       move.l %d0, (%a3)
+
+       /* invalidate and disable cache */
+       move.l  #0x01004100, %d0        /* Invalidate cache cmd */
+       movec   %d0, %CACR              /* Invalidate cache */
+       move.l  #0, %d0
+       movec   %d0, %ACR0
+       movec   %d0, %ACR1
+       movec   %d0, %ACR2
+       movec   %d0, %ACR3
+
+       /* Must disable global address */
+       move.l  #0xFC008000, %a1
+       move.l  #(CONFIG_SYS_CS0_BASE), (%a1)
+       move.l  #0xFC008008, %a1
+       move.l  #(CONFIG_SYS_CS0_CTRL), (%a1)
+       move.l  #0xFC008004, %a1
+       move.l  #(CONFIG_SYS_CS0_MASK), (%a1)
+
+       /* NAND port configuration */
+       move.l  #0xEC094048, %a1
+       move.b  #0xFD, (%a1)+
+       move.b  #0x5F, (%a1)+
+       move.b  #0x04, (%a1)+
+
+       /* reset nand */
+       move.l  #0xFC0FFF38, %a1        /* isr */
+       move.l  #0x000e0000, (%a1)
+       move.l  #0xFC0FFF08, %a2
+       move.l  #0x00000000, (%a2)+     /* car */
+       move.l  #0x11000000, (%a2)+     /* rar */
+       move.l  #0x00000000, (%a2)+     /* rpt */
+       move.l  #0x00000000, (%a2)+     /* rai */
+       move.l  #0xFC0FFF2c, %a2        /* cfg */
+       move.l  #0x00000000, (%a2)+     /* secsz */
+       move.l  #0x000e0681, (%a2)+
+       move.l  #0xFC0FFF04, %a2        /* cmd2 */
+       move.l  #0xFF404001, (%a2)
+       move.l  #0x000e0000, (%a1)
+
+       move.l  #0x2000, %d1
+       jsr     asm_delay
+
+       /* setup nand */
+       move.l  #0xFC0FFF00, %a1
+       move.l  #0x30700000, (%a1)+     /* cmd1 */
+       move.l  #0x007EF000, (%a1)+     /* cmd2 */
+
+       move.l  #0xFC0FFF2C, %a1
+       move.l  #0x00000841, (%a1)+     /* secsz */
+       move.l  #0x000e0681, (%a1)+     /* cfg */
+
+       move.l  #100, %d4               /* 100 pages ~200KB */
+       move.l  #4, %d2                 /* start at 4 */
+       move.l  #0xFC0FFF04, %a0        /* cmd2 */
+       move.l  #0xFC0FFF0C, %a1        /* rar */
+       move.l  #(TEXT_BASE + 0xF80), %a2       /* dst */
+
+asm_nand_read:
+       move.l  #0x11000000, %d0        /* rar */
+       or.l    %d2, %d0
+       move.l  %d0, (%a1)
+       add.l   #1, %d2
+
+       move.l  (%a0), %d0              /* cmd2 */
+       or.l    #1, %d0
+       move.l  %d0, (%a0)
+
+       move.l  #0x200, %d1
+       jsr     asm_delay
+
+asm_nand_chk_status:
+       move.l  #0xFC0FFF38, %a4        /* isr */
+       move.l  (%a4), %d0
+       and.l   #0x40000000, %d0
+       tst.l   %d0
+       beq     asm_nand_chk_status
+
+       move.l  #0xFC0FFF38, %a4        /* isr */
+       move.l  (%a4), %d0
+       or.l    #0x000E0000, %d0
+       move.l  %d0, (%a4)
+
+       move.l  #0x200, %d3
+       move.l  #0xFC0FC000, %a3        /* buf 1 */
+asm_nand_copy:
+       move.l  (%a3)+, (%a2)+
+       subq.l  #1, %d3
+       bgt     asm_nand_copy
+
+       subq.l  #1, %d4
+       bgt     asm_nand_read
+
+       /* jump to memory and execute */
+       move.l  #(TEXT_BASE + 0x400), %a0
+       jmp     (%a0)
+
+#endif                 /* CONFIG_SYS_NAND_BOOT */
 
 asm_delay:
        nop
        subq.l  #1, %d1
        bne     asm_delay
        rts
-#endif                 /* CONFIG_CF_SBF */
+#endif                 /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
 
        .text
        . = 0x400
        .globl  _start
 _start:
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
        nop
        nop
        move.w #0x2700,%sr              /* Mask off Interrupt */
@@ -418,12 +668,15 @@ _start:
        movec   %d0, %ACR1
        movec   %d0, %ACR2
        movec   %d0, %ACR3
+#else
+       move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+       movec   %d0, %RAMBAR1
+#endif
 
        /* set stackpointer to end of internal ram to get some stackspace for
           the first c-code */
        move.l  #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
        clr.l %sp@-
-#endif
 
        move.l #__got_start, %a5        /* put relocation table address to a5 */
 
index ec65cae3d88d4bace978e8cbf94b6eab3e20b9a7..d99747b7fa9089bf4cf935f08dab48d861390fcc 100644 (file)
@@ -164,8 +164,8 @@ _start:
 
        move.l #__got_start, %a5        /* put relocation table address to a5 */
 
-       bsr cpu_init_f                  /* run low-level CPU init code (from flash) */
-       bsr board_init_f                /* run low-level board init code (from flash) */
+       jbsr cpu_init_f                 /* run low-level CPU init code (from flash) */
+       jbsr board_init_f               /* run low-level board init code (from flash) */
 
        /* board_init_f() does not return */
 
index 5c9bb308356b397075eb2cf22470468e68cb42e8..f9e2d15f43f0bfa7ba5e2a26fbffb8365a7b4c2d 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * ColdFire cache
  *
- * Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
 
 #if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
 #define CONFIG_CF_V4
-#if defined(CONFIG_MCF5441x)
+#elif defined(CONFIG_MCF5441x)
 #define CONFIG_CF_V4E          /* Four Extra ACRn */
 #endif
-#endif
 
 /* ***** CACR ***** */
 /* V2 Core */
@@ -87,7 +86,7 @@
 #endif                         /* CONFIG_CF_V3 */
 
 /* V4 Core */
-#ifdef CONFIG_CF_V4
+#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
 
 #define CF_CACR_DEC            (1 << 31)
 #define CF_CACR_DW             (1 << 30)
 #define CF_CACR_IDSP           (1 << 7)
 #define CF_CACR_EUSP           (1 << 5)
 
-#ifdef CONFIG_MCF5445x
+#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
 #define CF_CACR_IVO            (1 << 20)
 #define CF_CACR_SPA            (1 << 14)
 #else
 #endif                         /* CONFIG_CF_V2 */
 
 /* V4 Core */
-#ifdef CONFIG_CF_V4
+#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
 #define CF_ACR_AMM             (1 << 10)
 #define CF_ACR_SP              (1 << 3)
 #endif                         /* CONFIG_CF_V4 */
index cd55b83c525ba269029614638a8b77ed6224a795..0cdb11cf99eeccce75df5d9482c3e4a066a4b3af 100644 (file)
@@ -34,7 +34,7 @@
 typedef        struct  global_data {
        bd_t            *bd;
        unsigned long   flags;
-       unsigned long   baudrate;
+       unsigned int    baudrate;
        unsigned long   cpu_clk;        /* CPU clock in Hz!             */
        unsigned long   bus_clk;
 #ifdef CONFIG_PCI
index e83ce08d5766c2b61fcc8ba5bafe27ab3112cb54..2aab463a90fc06ed12d6d1d4a30ce58ee9aa1eb7 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * ColdFire Internal Memory Map and Defines
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
 #define CONFIG_SYS_NUM_IRQS            (128)
 #endif                         /* CONFIG_M5329 && CONFIG_M5373 */
 
+#if defined(CONFIG_M54418)
+#include <asm/immap_5441x.h>
+#include <asm/m5441x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE         (MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE         (MMAP_FEC1)
+
+#if (CONFIG_SYS_UART_PORT < 4)
+#define CONFIG_SYS_UART_BASE           (MMAP_UART0 + \
+                                       (CONFIG_SYS_UART_PORT * 0x4000))
+#else
+#define CONFIG_SYS_UART_BASE           (MMAP_UART4 + \
+                                       ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
+#endif
+
+#define MMAP_DSPI                      MMAP_DSPI0
+#define CONFIG_SYS_MCFRTC_BASE         (MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE         (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE            (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG  (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO          (INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK                (INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND                (CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI         (6)
+#define CONFIG_SYS_TIMER_PRESCALER     (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE         (MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE            (MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE        (6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE           (MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS            (128)
+
+#endif                         /* CONFIG_M54418 */
+
 #if defined(CONFIG_M54451) || defined(CONFIG_M54455)
 #include <asm/immap_5445x.h>
 #include <asm/m5445x.h>
diff --git a/arch/m68k/include/asm/immap_5441x.h b/arch/m68k/include/asm/immap_5441x.h
new file mode 100644 (file)
index 0000000..300f4d2
--- /dev/null
@@ -0,0 +1,387 @@
+/*
+ * MCF5441x Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5441X__
+#define __IMMAP_5441X__
+
+/* Module Base Addresses */
+#define MMAP_XBS       0xFC004000
+#define MMAP_FBCS      0xFC008000
+#define MMAP_CAN0      0xFC020000
+#define MMAP_CAN1      0xFC024000
+#define MMAP_I2C1      0xFC038000
+#define MMAP_DSPI1     0xFC03C000
+#define MMAP_SCM       0xFC040000
+#define MMAP_PM                0xFC04002C
+#define MMAP_EDMA      0xFC044000
+#define MMAP_INTC0     0xFC048000
+#define MMAP_INTC1     0xFC04C000
+#define MMAP_INTC2     0xFC050000
+#define MMAP_IACK      0xFC054000
+#define MMAP_I2C0      0xFC058000
+#define MMAP_DSPI0     0xFC05C000
+#define MMAP_UART0     0xFC060000
+#define MMAP_UART1     0xFC064000
+#define MMAP_UART2     0xFC068000
+#define MMAP_UART3     0xFC06C000
+#define MMAP_DTMR0     0xFC070000
+#define MMAP_DTMR1     0xFC074000
+#define MMAP_DTMR2     0xFC078000
+#define MMAP_DTMR3     0xFC07C000
+#define MMAP_PIT0      0xFC080000
+#define MMAP_PIT1      0xFC084000
+#define MMAP_PIT2      0xFC088000
+#define MMAP_PIT3      0xFC08C000
+#define MMAP_EPORT0    0xFC090000
+#define MMAP_ADC       0xFC094000
+#define MMAP_DAC0      0xFC098000
+#define MMAP_DAC1      0xFC09C000
+#define MMAP_RRTC      0xFC0A8000
+#define MMAP_SIM       0xFC0AC000
+#define MMAP_USBOTG    0xFC0B0000
+#define MMAP_USBEHCI   0xFC0B4000
+#define MMAP_SDRAM     0xFC0B8000
+#define MMAP_SSI0      0xFC0BC000
+#define MMAP_PLL       0xFC0C0000
+#define MMAP_RNG       0xFC0C4000
+#define MMAP_SSI1      0xFC0C8000
+#define MMAP_ESDHC     0xFC0CC000
+#define MMAP_FEC0      0xFC0D4000
+#define MMAP_FEC1      0xFC0D8000
+#define MMAP_L2_SW0    0xFC0DC000
+#define MMAP_L2_SW1    0xFC0E0000
+
+#define MMAP_NFC_RAM   0xFC0FC000
+#define MMAP_NFC       0xFC0FF000
+
+#define MMAP_1WIRE     0xEC008000
+#define MMAP_I2C2      0xEC010000
+#define MMAP_I2C3      0xEC014000
+#define MMAP_I2C4      0xEC018000
+#define MMAP_I2C5      0xEC01C000
+#define MMAP_DSPI2     0xEC038000
+#define MMAP_DSPI3     0xEC03C000
+#define MMAP_UART4     0xEC060000
+#define MMAP_UART5     0xEC064000
+#define MMAP_UART6     0xEC068000
+#define MMAP_UART7     0xEC06C000
+#define MMAP_UART8     0xEC070000
+#define MMAP_UART9     0xEC074000
+#define MMAP_RCM       0xEC090000
+#define MMAP_CCM       0xEC090000
+#define MMAP_GPIO      0xEC094000
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+
+/* Serial Boot Facility (SBF) */
+typedef struct sbf {
+       u8 resv0[0x18];
+       u16 sbfsr;              /* Serial Boot Facility Status */
+       u8 resv1[0x6];
+       u16 sbfcr;              /* Serial Boot Facility Control */
+} sbf_t;
+
+/* Reset Controller Module (RCM) */
+typedef struct rcm {
+       u8 rcr;
+       u8 rsr;
+} rcm_t;
+
+/* Chip Configuration Module (CCM) */
+typedef struct ccm {
+       u8 ccm_resv0[0x4];      /* 0x00 */
+       u16 ccr;                /* 0x04 Chip Configuration */
+       u8 resv1[0x2];          /* 0x06 */
+       u16 rcon;               /* 0x08 Reset Configuration */
+       u16 cir;                /* 0x0A Chip Identification */
+       u8 resv2[0x2];          /* 0x0C */
+       u16 misccr;             /* 0x0E Miscellaneous Control */
+       u16 cdrh;               /* 0x10 Clock Divider */
+       u16 cdrl;               /* 0x12 Clock Divider */
+       u16 uocsr;              /* 0x14 USB On-the-Go Controller Status */
+       u16 uhcsr;              /* 0x16 */
+       u16 misccr3;            /* 0x18 */
+       u16 misccr2;            /* 0x1A */
+       u16 adctsr;             /* 0x1C */
+       u16 dactsr;             /* 0x1E */
+       u16 sbfsr;              /* 0x20 */
+       u16 sbfcr;              /* 0x22 */
+       u32 fnacr;              /* 0x24 */
+} ccm_t;
+
+/* General Purpose I/O Module (GPIO) */
+typedef struct gpio {
+       u8 podr_a;              /* 0x00 */
+       u8 podr_b;              /* 0x01 */
+       u8 podr_c;              /* 0x02 */
+       u8 podr_d;              /* 0x03 */
+       u8 podr_e;              /* 0x04 */
+       u8 podr_f;              /* 0x05 */
+       u8 podr_g;              /* 0x06 */
+       u8 podr_h;              /* 0x07 */
+       u8 podr_i;              /* 0x08 */
+       u8 podr_j;              /* 0x09 */
+       u8 podr_k;              /* 0x0A */
+       u8 rsvd0;               /* 0x0B */
+
+       u8 pddr_a;              /* 0x0C */
+       u8 pddr_b;              /* 0x0D */
+       u8 pddr_c;              /* 0x0E */
+       u8 pddr_d;              /* 0x0F */
+       u8 pddr_e;              /* 0x10 */
+       u8 pddr_f;              /* 0x11 */
+       u8 pddr_g;              /* 0x12 */
+       u8 pddr_h;              /* 0x13 */
+       u8 pddr_i;              /* 0x14 */
+       u8 pddr_j;              /* 0x15 */
+       u8 pddr_k;              /* 0x16 */
+       u8 rsvd1;               /* 0x17 */
+
+       u8 ppdsdr_a;            /* 0x18 */
+       u8 ppdsdr_b;            /* 0x19 */
+       u8 ppdsdr_c;            /* 0x1A */
+       u8 ppdsdr_d;            /* 0x1B */
+       u8 ppdsdr_e;            /* 0x1C */
+       u8 ppdsdr_f;            /* 0x1D */
+       u8 ppdsdr_g;            /* 0x1E */
+       u8 ppdsdr_h;            /* 0x1F */
+       u8 ppdsdr_i;            /* 0x20 */
+       u8 ppdsdr_j;            /* 0x21 */
+       u8 ppdsdr_k;            /* 0x22 */
+       u8 rsvd2;               /* 0x23 */
+
+       u8 pclrr_a;             /* 0x24 */
+       u8 pclrr_b;             /* 0x25 */
+       u8 pclrr_c;             /* 0x26 */
+       u8 pclrr_d;             /* 0x27 */
+       u8 pclrr_e;             /* 0x28 */
+       u8 pclrr_f;             /* 0x29 */
+       u8 pclrr_g;             /* 0x2A */
+       u8 pclrr_h;             /* 0x2B */
+       u8 pclrr_i;             /* 0x2C */
+       u8 pclrr_j;             /* 0x2D */
+       u8 pclrr_k;             /* 0x2E */
+       u8 rsvd3;               /* 0x2F */
+
+       u16 pcr_a;              /* 0x30 */
+       u16 pcr_b;              /* 0x32 */
+       u16 pcr_c;              /* 0x34 */
+       u16 pcr_d;              /* 0x36 */
+       u16 pcr_e;              /* 0x38 */
+       u16 pcr_f;              /* 0x3A */
+       u16 pcr_g;              /* 0x3C */
+       u16 pcr_h;              /* 0x3E */
+       u16 pcr_i;              /* 0x40 */
+       u16 pcr_j;              /* 0x42 */
+       u16 pcr_k;              /* 0x44 */
+       u16 rsvd4;              /* 0x46 */
+
+       u8 par_fbctl;           /* 0x48 */
+       u8 par_be;              /* 0x49 */
+       u8 par_cs;              /* 0x4A */
+       u8 par_cani2c;          /* 0x4B */
+       u8 par_irqh;            /* 0x4C */
+       u8 par_irql;            /* 0x4D */
+       u8 par_dspi0;           /* 0x4E */
+       u8 par_dspiow;          /* 0x4F */
+       u8 par_timer;           /* 0x50 */
+       u8 par_uart2;           /* 0x51 */
+       u8 par_uart1;           /* 0x52 */
+       u8 par_uart0;           /* 0x53 */
+       u8 par_sdhch;           /* 0x54 */
+       u8 par_sdhcl;           /* 0x55 */
+       u8 par_simp0h;          /* 0x56 */
+       u8 par_simp1h;          /* 0x57 */
+       u8 par_ssi0h;           /* 0x58 */
+       u8 par_ssi0l;           /* 0x59 */
+       u8 par_dbg1h;           /* 0x5A */
+       u8 par_dbg0h;           /* 0x5B */
+       u8 par_dbgl;            /* 0x5C */
+       u8 rsvd5;               /* 0x5D */
+       u8 par_fec;             /* 0x5E */
+       u8 rsvd6;               /* 0x5F */
+
+       u8 mscr_sdram;          /* 0x60 */
+       u8 rsvd7[3];            /* 0x61-0x63 */
+
+       u8 srcr_fb1;            /* 0x64 */
+       u8 srcr_fb2;            /* 0x65 */
+       u8 srcr_fb3;            /* 0x66 */
+       u8 srcr_fb4;            /* 0x67 */
+       u8 srcr_dspiow;         /* 0x68 */
+       u8 srcr_cani2c;         /* 0x69 */
+       u8 srcr_irq;            /* 0x6A */
+       u8 srcr_timer;          /* 0x6B */
+       u8 srcr_uart;           /* 0x6C */
+       u8 srcr_fec;            /* 0x6D */
+       u8 srcr_sdhc;           /* 0x6E */
+       u8 srcr_simp0;          /* 0x6F */
+       u8 srcr_ssi0;           /* 0x70 */
+       u8 rsvd8[3];            /* 0x71-0x73 */
+
+       u16 urts_pol;           /* 0x74 */
+       u16 ucts_pol;           /* 0x76 */
+       u16 utxd_wom;           /* 0x78 */
+       u32 urxd_wom;           /* 0x7c */
+
+       u32 hcr1;               /* 0x80 */
+       u32 hcr0;               /* 0x84 */
+} gpio_t;
+
+/* SDRAM Controller (SDRAMC) */
+typedef struct sdramc {
+       u32 cr00;               /* 0x00 */
+       u32 cr01;               /* 0x04 */
+       u32 cr02;               /* 0x08 */
+       u32 cr03;               /* 0x0C */
+       u32 cr04;               /* 0x10 */
+       u32 cr05;               /* 0x14 */
+       u32 cr06;               /* 0x18 */
+       u32 cr07;               /* 0x1C */
+
+       u32 cr08;               /* 0x20 */
+       u32 cr09;               /* 0x24 */
+       u32 cr10;               /* 0x28 */
+       u32 cr11;               /* 0x2C */
+       u32 cr12;               /* 0x30 */
+       u32 cr13;               /* 0x34 */
+       u32 cr14;               /* 0x38 */
+       u32 cr15;               /* 0x3C */
+
+       u32 cr16;               /* 0x40 */
+       u32 cr17;               /* 0x44 */
+       u32 cr18;               /* 0x48 */
+       u32 cr19;               /* 0x4C */
+       u32 cr20;               /* 0x50 */
+       u32 cr21;               /* 0x54 */
+       u32 cr22;               /* 0x58 */
+       u32 cr23;               /* 0x5C */
+
+       u32 cr24;               /* 0x60 */
+       u32 cr25;               /* 0x64 */
+       u32 cr26;               /* 0x68 */
+       u32 cr27;               /* 0x6C */
+       u32 cr28;               /* 0x70 */
+       u32 cr29;               /* 0x74 */
+       u32 cr30;               /* 0x78 */
+       u32 cr31;               /* 0x7C */
+
+       u32 cr32;               /* 0x80 */
+       u32 cr33;               /* 0x84 */
+       u32 cr34;               /* 0x88 */
+       u32 cr35;               /* 0x8C */
+       u32 cr36;               /* 0x90 */
+       u32 cr37;               /* 0x94 */
+       u32 cr38;               /* 0x98 */
+       u32 cr39;               /* 0x9C */
+
+       u32 cr40;               /* 0xA0 */
+       u32 cr41;               /* 0xA4 */
+       u32 cr42;               /* 0xA8 */
+       u32 cr43;               /* 0xAC */
+       u32 cr44;               /* 0xB0 */
+       u32 cr45;               /* 0xB4 */
+       u32 cr46;               /* 0xB8 */
+       u32 cr47;               /* 0xBC */
+       u32 cr48;               /* 0xC0 */
+       u32 cr49;               /* 0xC4 */
+       u32 cr50;               /* 0xC8 */
+       u32 cr51;               /* 0xCC */
+       u32 cr52;               /* 0xD0 */
+       u32 cr53;               /* 0xD4 */
+       u32 cr54;               /* 0xD8 */
+       u32 cr55;               /* 0xDC */
+       u32 cr56;               /* 0xE0 */
+       u32 cr57;               /* 0xE4 */
+       u32 cr58;               /* 0xE8 */
+       u32 cr59;               /* 0xEC */
+       u32 cr60;               /* 0xF0 */
+       u32 cr61;               /* 0xF4 */
+       u32 cr62;               /* 0xF8 */
+       u32 cr63;               /* 0xFC */
+
+       u32 rsvd3[32];          /* 0xF4-0x1A8 */
+
+       u32 rcrcr;              /* 0x180 */
+       u32 swrcr;              /* 0x184 */
+       u32 rcr;                /* 0x188 */
+       u32 msovr;              /* 0x18C */
+       u32 rcrdbg;             /* 0x190 */
+       u32 sl0adj;             /* 0x194 */
+       u32 sl1adj;             /* 0x198 */
+       u32 sl2adj;             /* 0x19C */
+       u32 sl3adj;             /* 0x1A0 */
+       u32 sl4adj;             /* 0x1A4 */
+       u32 flight_tm;          /* 0x1A8 */
+       u32 padcr;              /* 0x1AC */
+} sdramc_t;
+
+/* Phase Locked Loop (PLL) */
+typedef struct pll {
+       u32 pcr;                /* Control */
+       u32 pdr;                /* Divider */
+       u32 psr;                /* Status */
+} pll_t;
+
+typedef struct scm {
+       u8 rsvd1[19];           /* 0x00 - 0x12 */
+       u8 wcr;                 /* 0x13 */
+       u16 rsvd2;              /* 0x14 - 0x15 */
+       u16 cwcr;               /* 0x16 */
+       u8 rsvd3[3];            /* 0x18 - 0x1A */
+       u8 cwsr;                /* 0x1B */
+       u8 rsvd4[3];            /* 0x1C - 0x1E */
+       u8 scmisr;              /* 0x1F */
+       u32 rsvd5;              /* 0x20 - 0x23 */
+       u32 bcr;                /* 0x24 */
+       u8 rsvd6[72];           /* 0x28 - 0x6F */
+       u32 cfadr;              /* 0x70 */
+       u8 rsvd7;               /* 0x74 */
+       u8 cfier;               /* 0x75 */
+       u8 cfloc;               /* 0x76 */
+       u8 cfatr;               /* 0x77 */
+       u32 rsvd8;              /* 0x78 - 0x7B */
+       u32 cfdtr;              /* 0x7C */
+} scm_t;
+
+typedef struct pm {
+       u8 pmsr0;               /* */
+       u8 pmcr0;
+       u8 pmsr1;
+       u8 pmcr1;
+       u32 pmhr0;
+       u32 pmlr0;
+       u32 pmhr1;
+       u32 pmlr1;
+} pm_t;
+
+#endif                         /* __IMMAP_5441X__ */
diff --git a/arch/m68k/include/asm/m5441x.h b/arch/m68k/include/asm/m5441x.h
new file mode 100644 (file)
index 0000000..f5c82d4
--- /dev/null
@@ -0,0 +1,887 @@
+/*
+ * MCF5441X Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCF5441X__
+#define __MCF5441X__
+
+/* Interrupt Controller (INTC) */
+#define INT0_LO_RSVD0                  (0)
+#define INT0_LO_EPORT1                 (1)
+#define INT0_LO_EPORT2                 (2)
+#define INT0_LO_EPORT3                 (3)
+#define INT0_LO_EPORT4                 (4)
+#define INT0_LO_EPORT5                 (5)
+#define INT0_LO_EPORT6                 (6)
+#define INT0_LO_EPORT7                 (7)
+#define INT0_LO_EDMA_00                (8)
+#define INT0_LO_EDMA_01                (9)
+#define INT0_LO_EDMA_02                (10)
+#define INT0_LO_EDMA_03                (11)
+#define INT0_LO_EDMA_04                (12)
+#define INT0_LO_EDMA_05                (13)
+#define INT0_LO_EDMA_06                (14)
+#define INT0_LO_EDMA_07                (15)
+#define INT0_LO_EDMA_08                (16)
+#define INT0_LO_EDMA_09                (17)
+#define INT0_LO_EDMA_10                (18)
+#define INT0_LO_EDMA_11                (19)
+#define INT0_LO_EDMA_12                (20)
+#define INT0_LO_EDMA_13                (21)
+#define INT0_LO_EDMA_14                (22)
+#define INT0_LO_EDMA_15                (23)
+#define INT0_LO_EDMA_ERR               (24)
+#define INT0_LO_SCM                    (25)
+#define INT0_LO_UART0                  (26)
+#define INT0_LO_UART1                  (27)
+#define INT0_LO_UART2                  (28)
+#define INT0_LO_UART3                  (29)
+#define INT0_LO_I2C0                   (30)
+#define INT0_LO_DSPI0                  (31)
+#define INT0_HI_DTMR0                  (32)
+#define INT0_HI_DTMR1                  (33)
+#define INT0_HI_DTMR2                  (34)
+#define INT0_HI_DTMR3                  (35)
+#define INT0_HI_MACNET0_TXF            (36)
+#define INT0_HI_MACNET0_TXB            (37)
+#define INT0_HI_MACNET0_UN             (38)
+#define INT0_HI_MACNET0_RL             (39)
+#define INT0_HI_MACNET0_RXF            (40)
+#define INT0_HI_MACNET0_RXB            (41)
+#define INT0_HI_MACNET0_MII            (42)
+#define INT0_HI_MACNET0_LC             (43)
+/* not used 44 */
+#define INT0_HI_MACNET0_GRA            (45)
+#define INT0_HI_MACNET0_EBERR          (46)
+#define INT0_HI_MACNET0_BABT           (47)
+#define INT0_HI_MACNET0_BABR           (48)
+#define INT0_HI_MACNET1_TXF            (49)
+#define INT0_HI_MACNET1_TXB            (50)
+#define INT0_HI_MACNET1_UN             (51)
+#define INT0_HI_MACNET1_RL             (52)
+#define INT0_HI_MACNET1_RXF            (53)
+#define INT0_HI_MACNET1_RXB            (54)
+#define INT0_HI_MACNET1_MII            (55)
+#define INT0_HI_MACNET1_LC             (56)
+/* not used 57 */
+#define INT0_HI_MACNET1_GRA            (58)
+#define INT0_HI_MACNET1_EBERR          (59)
+#define INT0_HI_MACNET1_BABT           (60)
+#define INT0_HI_MACNET1_BABR           (61)
+#define INT0_HI_SCMIR                  (62)
+#define INT0_HI_OW                     (63)
+
+#define INT1_LO_CAN0_IFG               (0)
+#define INT1_LO_CAN0_BOFF              (1)
+/* not used 2 */
+#define INT1_LO_CAN0_TXRXWRN           (3)
+#define INT1_LO_CAN1_IFG               (4)
+#define INT1_LO_CAN1_BOFF              (5)
+/* not used 6 */
+#define INT1_LO_CAN1_TXRXWRN           (7)
+#define INT1_LO_EDMA_16                (8)
+#define INT1_LO_EDMA_17                (9)
+#define INT1_LO_EDMA_18                (10)
+#define INT1_LO_EDMA_19                (11)
+#define INT1_LO_EDMA_20                (12)
+#define INT1_LO_EDMA_21                (13)
+#define INT1_LO_EDMA_22                (14)
+#define INT1_LO_EDMA_23                (15)
+#define INT1_LO_EDMA_24                (16)
+#define INT1_LO_EDMA_25                (17)
+#define INT1_LO_EDMA_26                (18)
+#define INT1_LO_EDMA_27                (19)
+#define INT1_LO_EDMA_28                (20)
+#define INT1_LO_EDMA_29                (21)
+#define INT1_LO_EDMA_30                (22)
+#define INT1_LO_EDMA_31                (23)
+#define INT1_LO_EDMA_32                (24)
+#define INT1_LO_EDMA_33                (25)
+#define INT1_LO_EDMA_34                (26)
+#define INT1_LO_EDMA_35                (27)
+#define INT1_LO_EDMA_36                (28)
+#define INT1_LO_EDMA_37                (29)
+#define INT1_LO_EDMA_38                (30)
+#define INT1_LO_EDMA_39                (31)
+#define INT1_LO_EDMA_40                (32)
+#define INT1_HI_EDMA_41                (33)
+#define INT1_HI_EDMA_42                (34)
+#define INT1_HI_EDMA_43                (35)
+#define INT1_HI_EDMA_44                (36)
+#define INT1_HI_EDMA_45                (37)
+#define INT1_HI_EDMA_46                (38)
+#define INT1_HI_EDMA_47                (39)
+#define INT1_HI_EDMA_48                (40)
+#define INT1_HI_EDMA_49                (41)
+#define INT1_HI_EDMA_50                (42)
+#define INT1_HI_EDMA_51                (43)
+#define INT1_HI_EDMA_52                (44)
+#define INT1_HI_EDMA_53                (45)
+#define INT1_HI_EDMA_54                (46)
+#define INT1_HI_EDMA_55                (47)
+#define INT1_HI_UART4                  (48)
+#define INT1_HI_UART5                  (49)
+#define INT1_HI_UART6                  (50)
+#define INT1_HI_UART7                  (51)
+#define INT1_HI_UART8                  (52)
+#define INT1_HI_UART9                  (53)
+#define INT1_HI_DSPI1                  (54)
+#define INT1_HI_DSPI2                  (55)
+#define INT1_HI_DSPI3                  (56)
+#define INT1_HI_I2C1                   (57)
+#define INT1_HI_I2C2                   (58)
+#define INT1_HI_I2C3                   (59)
+#define INT1_HI_I2C4                   (60)
+#define INT1_HI_I2C5                   (61)
+
+#define INT2_LO_EDMA56_63              (0)
+#define INT2_LO_PWM_SM0SR_CF           (1)
+#define INT2_LO_PWM_SM1SR_CF           (2)
+#define INT2_LO_PWM_SM2SR_CF           (3)
+#define INT2_LO_PWM_SM3SR_CF           (4)
+#define INT2_LO_PWM_SM0SR_RF           (5)
+#define INT2_LO_PWM_SM1SR_RF           (6)
+#define INT2_LO_PWM_SM2SR_RF           (7)
+#define INT2_LO_PWM_SM3SR_RF           (8)
+#define INT2_LO_PWM_FSR                (9)
+#define INT2_LO_PWM_SMSR_REF           (10)
+#define INT2_LO_PLL_SR_LOCF            (11)
+#define INT2_LO_PLL_SR_LOLF            (12)
+#define INT2_LO_PIT0_PIF               (13)
+#define INT2_LO_PIT1_PIF               (14)
+#define INT2_LO_PIT2_PIF               (15)
+#define INT2_LO_PIT3_PIF               (16)
+#define INT2_LO_USBOTG_USBSTS          (17)
+#define INT2_LO_USBH_USBSTS            (18)
+/* not used 19-20 */
+#define INT2_LO_SSI0                   (21)
+#define INT2_LO_SSI1                   (22)
+#define INT2_LO_NFC                    (23)
+/* not used 24-25 */
+#define INT2_LO_RTC                    (26)
+#define INT2_LO_CCM_UOCSR              (27)
+#define INT2_LO_RNG_EI                 (28)
+#define INT2_LO_SIM1_DATA              (29)
+#define INT2_LO_SIM1                   (30)
+#define INT2_LO_SDHC                   (31)
+/* not used 32-37 */
+#define INT2_HI_L2SW_BERR              (38)
+#define INT2_HI_L2SW_RXB               (39)
+#define INT2_HI_L2SW_RXF               (40)
+#define INT2_HI_L2SW_TXB               (41)
+#define INT2_HI_L2SW_TXF               (42)
+#define INT2_HI_L2SW_QM                (43)
+#define INT2_HI_L2SW_OD0               (44)
+#define INT2_HI_L2SW_OD1               (45)
+#define INT2_HI_L2SW_OD2               (46)
+#define INT2_HI_L2SW_LRN               (47)
+#define INT2_HI_MACNET0_TS             (48)
+#define INT2_HI_MACNET0_WAKE           (49)
+#define INT2_HI_MACNET0_PLR            (50)
+/* not used 51-54 */
+#define INT2_HI_MACNET1_TS             (51)
+#define INT2_HI_MACNET1_WAKE           (52)
+#define INT2_HI_MACNET1_PLR            (53)
+
+/* Serial Boot Facility (SBF) */
+#define SBF_SBFCR_BLDIV(x)             (((x)&0x000F))
+#define SBF_SBFCR_FR                   (0x0010)
+
+/* Reset Controller Module (RCM) */
+#define RCM_RCR_SOFTRST                (0x80)
+#define RCM_RCR_FRCRSTOUT              (0x40)
+
+#define RCM_RSR_SOFT                   (0x20)
+#define RCM_RSR_LOC                    (0x10)
+#define RCM_RSR_POR                    (0x08)
+#define RCM_RSR_EXT                    (0x04)
+#define RCM_RSR_WDR_CORE               (0x02)
+#define RCM_RSR_LOL                    (0x01)
+
+/* Chip Configuration Module (CCM) */
+#define CCM_CCR_BOOTMOD                (0xC000)
+#define CCM_CCR_PLLMULT                (0x0FC0)
+#define CCM_CCR_BOOTPS                 (0x0030)
+#define CCM_CCR_BOOTPS_32              (0x0000)
+#define CCM_CCR_BOOTPS_16              (0x0020)
+#define CCM_CCR_BOOTPS_8               (0x0010)
+#define CCM_CCR_BOOTPS_                (0x0000)
+#define CCM_CCR_ALESEL                 (0x0008)
+#define CCM_CCR_OSCMOD                 (0x0004)
+#define CCM_CCR_PLLMOD                 (0x0002)
+#define CCM_CCR_BOOTMEM                (0x0001)
+
+#define CCM_CIR_PIN_MASK               (0xFFC0)
+#define CCM_CIR_PRN_MASK               (0x003F)
+#define CCM_CIR_PIN_MCF54410           (0x9F<<6)
+#define CCM_CIR_PIN_MCF54415           (0xA0<<6)
+#define CCM_CIR_PIN_MCF54416           (0xA1<<6)
+#define CCM_CIR_PIN_MCF54417           (0xA2<<6)
+#define CCM_CIR_PIN_MCF54418           (0xA3<<6)
+
+#define CCM_MISCCR_PWM_EXTCLK(x)       (((x)&(0x0003)<<14)
+#define CCM_MISCCR_PWM_EXTCLK_MASK     (0x3FFF)
+#define CCM_MISCCR_PWM_EXTCLK_TMR0     (0x0000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR1     (0x4000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR2     (0x8000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR3     (0xC000)
+#define CCM_MISCCR_LIMP                (0x1000)
+#define CCM_MISCCR_BME                 (0x0800)
+#define CCM_MISCCR_BMT(x)              (((x)&0x0007)<<8)
+#define CCM_MISCCR_BMT_65536           (0)
+#define CCM_MISCCR_BMT_32768           (1)
+#define CCM_MISCCR_BMT_16384           (2)
+#define CCM_MISCCR_BMT_8192            (3)
+#define CCM_MISCCR_BMT_4096            (4)
+#define CCM_MISCCR_BMT_2048            (5)
+#define CCM_MISCCR_BMT_1024            (6)
+#define CCM_MISCCR_BMT_512             (7)
+#define CCM_MISCCR_SDHCSRC             (0x0040)
+#define CCM_MISCCR_SSI1SRC             (0x0020)
+#define CCM_MISCCR_SSI0SRC             (0x0010)
+#define CCM_MISCCR_USBHOC              (0x0008)
+#define CCM_MISCCR_USBOOC              (0x0004)
+#define CCM_MISCCR_USBPUE              (0x0002)
+#define CCM_MISCCR_USBSRC              (0x0001)
+
+#define CCM_CDRH_SSI0DIV(x)            (((x)&0x00FF)<<8)
+#define CCM_CDRH_SSI0DIV_MASK          (0x00FF)
+#define CCM_CDRH_SSI1DIV(x)            (((x)&0x00FF))
+#define CCM_CDRH_SSI1DIV_MASK          (0xFF00)
+#define CCM_CDRL_LPDIV(x)              (((x)&0x000F)<<8)
+#define CCM_CDRL_LPDIV_MASK            (0xFF0F)
+#define CCM_CDR_LPDIV(x)               CCM_CDRL_LPDIV(x)
+
+#define CCM_UOCSR_DPPD                 (0x2000)
+#define CCM_UOCSR_DMPD                 (0x1000)
+#define CCM_UOCSR_DRV_VBUS             (0x0800)
+#define CCM_UOCSR_CRG_VBUS             (0x0400)
+#define CCM_UOCSR_DCR_VBUS             (0x0200)
+#define CCM_UOCSR_DPPU                 (0x0100)
+#define CCM_UOCSR_AVLD                 (0x0080)
+#define CCM_UOCSR_BVLD                 (0x0040)
+#define CCM_UOCSR_VVLD                 (0x0020)
+#define CCM_UOCSR_SEND                 (0x0010)
+#define CCM_UOCSR_PWRFLT               (0x0008)
+#define CCM_UOCSR_WKUP                 (0x0004)
+#define CCM_UOCSR_UOMIE                (0x0002)
+#define CCM_UOCSR_XPDE                 (0x0001)
+
+#define CCM_UHCSR_DRV_VBUS             (0x0010)
+#define CCM_UHCSR_PWRFLT               (0x0008)
+#define CCM_UHCSR_WKUP                 (0x0004)
+#define CCM_UHCSR_UOMIE                (0x0002)
+#define CCM_UHCSR_XPDE                 (0x0001)
+
+#define CCM_MISCCR3_TMR_ENET           (0x1000)
+#define CCM_MISCCR3_ENETCLK(x)         (((x)&7)<<8)
+#define CCM_MISCCR3_ENETCLK_MASK       (0xF8FF)
+#define CCM_MISCCR3_ENETCLK_MII        (0x0700)
+#define CCM_MISCCR3_ENETCLK_OSC        (0x0600)
+#define CCM_MISCCR3_ENETCLK_USB        (0x0500)
+#define CCM_MISCCR3_ENETCLK_TMR3       (0x0400)
+#define CCM_MISCCR3_ENETCLK_TMR2       (0x0300)
+#define CCM_MISCCR3_ENETCLK_TMR1       (0x0200)
+#define CCM_MISCCR3_ENETCLK_TMR0       (0x0100)
+#define CCM_MISCCR3_ENETCLK_INTBUS     (0x0000)
+
+#define CCM_MISCCR2_EXTCLKBYP          (0x8000)
+#define CCM_MISCCR2_DDR2CLK            (0x4000)
+#define CCM_MISCCR2_RGPIO_HALF         (0x2000)
+#define CCM_MISCCR2_SWTSCR             (0x1000)
+#define CCM_MISCCR2_PLLMODE(x)         (((x)&7)<<8)
+#define CCM_MISCCR2_PLLMODE_MASK       (0xF8FF)
+#define CCM_MISCCR2_DCCBYP             (0x0080)
+#define CCM_MISCCR2_DAC1SEL            (0x0040)
+#define CCM_MISCCR2_DAC0SEL            (0x0020)
+#define CCM_MISCCR2_ADCEN              (0x0010)
+#define CCM_MISCCR2_ADC7SEL            (0x0008)
+#define CCM_MISCCR2_ADC3SEL            (0x0004)
+#define CCM_MISCCR2_FBHALF             (0x0002)
+#define CCM_MISCCR2_ULPI               (0x0001)
+
+#define CCM_FNACR_PCR(x)               (((x)&0x0F)<<24)
+#define CCM_FNACR_PCR_MASK             (0xF0FFFFFF)
+#define CCM_FNACR_MCC(x)               ((x)&0xFFFF)
+#define CCM_FNACR_MCC_MASK             (0xFFFF0000)
+
+/* General Purpose I/O Module (GPIO) */
+#define GPIO_PAR_FBCTL_ALE(x)          (((x)&3)<<6)
+#define GPIO_PAR_FBCTL_ALE_MASK        (0x3F)
+#define GPIO_PAR_FBCTL_ALE_FB_ALE      (0xC0)
+#define GPIO_PAR_FBCTL_ALE_FB_TS       (0x80)
+#define GPIO_PAR_FBCTL_ALE_GPIO        (0x00)
+#define GPIO_PAR_FBCTL_OE(x)           (((x)&3)<<4)
+#define GPIO_PAR_FBCTL_OE_MASK         (0xCF)
+#define GPIO_PAR_FBCTL_OE_FB_OE        (0x30)
+#define GPIO_PAR_FBCTL_OE_FB_TBST      (0x20)
+#define GPIO_PAR_FBCTL_OE_NFC_RE       (0x20)
+#define GPIO_PAR_FBCTL_OE_GPIO         (0x00)
+#define GPIO_PAR_FBCTL_FBCLK           (0x08)
+#define GPIO_PAR_FBCTL_RW              (0x04)
+#define GPIO_PAR_FBCTL_TA(x)           ((x)&3)
+#define GPIO_PAR_FBCTL_TA_MASK         (0xFC)
+#define GPIO_PAR_FBCTL_TA_TA           (0x03)
+#define GPIO_PAR_FBCTL_TA_NFC_RB       (0x01)
+#define GPIO_PAR_FBCTL_TA_GPIO         (0x00)
+
+#define GPIO_PAR_BE_BS3(x)             (((x)&0x03)<<6)
+#define GPIO_PAR_BE_BE3_MASK           (0x3F)
+#define GPIO_PAR_BE_BE3_BE3            (0xC0)
+#define GPIO_PAR_BE_BE3_CS3            (0x80)
+#define GPIO_PAR_BE_BE3_FB_A1          (0x40)
+#define GPIO_PAR_BE_BE3_NFC_ALE        (0x40)
+#define GPIO_PAR_BE_BE3_GPIO           (0x00)
+#define GPIO_PAR_BE_BS2(x)             (((x)&0x03)<<4)
+#define GPIO_PAR_BE_BE2_MASK           (0xCF)
+#define GPIO_PAR_BE_BE2_BE2            (0x30)
+#define GPIO_PAR_BE_BE2_CS2            (0x20)
+#define GPIO_PAR_BE_BE2_FB_A0          (0x10)
+#define GPIO_PAR_BE_BE2_NFC_CLE        (0x10)
+#define GPIO_PAR_BE_BE2_GPIO           (0x00)
+#define GPIO_PAR_BE_BS1(x)             (((x)&0x03)<<2)
+#define GPIO_PAR_BE_BE1_MASK           (0xF3)
+#define GPIO_PAR_BE_BE1_BE1            (0x0C)
+#define GPIO_PAR_BE_BE1_FB_TSZ1        (0x08)
+#define GPIO_PAR_BE_BE1_GPIO           (0x00)
+#define GPIO_PAR_BE_BS0(x)             ((x)&0x03)
+#define GPIO_PAR_BE_BE0_MASK           (0xFC)
+#define GPIO_PAR_BE_BE0_BE0            (0x03)
+#define GPIO_PAR_BE_BE0_FB_TSZ0        (0x02)
+#define GPIO_PAR_BE_BE0_GPIO           (0x00)
+
+#define GPIO_PAR_CS_CS5(x)             (((x)&0x03)<<6)
+#define GPIO_PAR_CS_CS5_MASK           (0x3F)
+#define GPIO_PAR_CS_CS5_CS5            (0xC0)
+#define GPIO_PAR_CS_CS5_DACK1          (0x80)
+#define GPIO_PAR_CS_CS5_GPIO           (0x00)
+#define GPIO_PAR_CS_CS4(x)             (((x)&0x03)<<4)
+#define GPIO_PAR_CS_CS4_MASK           (0xCF)
+#define GPIO_PAR_CS_CS4_CS4            (0x30)
+#define GPIO_PAR_CS_CS4_DREQ1          (0x20)
+#define GPIO_PAR_CS_CS4_GPIO           (0x00)
+#define GPIO_PAR_CS_CS1(x)             (((x)&0x03)<<2)
+#define GPIO_PAR_CS_CS1_MASK           (0xF3)
+#define GPIO_PAR_CS_CS1_CS1            (0x0C)
+#define GPIO_PAR_CS_CS1_NFC_CE         (0x04)
+#define GPIO_PAR_CS_CS1_GPIO           (0x00)
+#define GPIO_PAR_CS_CS0_CS0            (0x01)
+
+#define GPIO_PAR_CANI2C_I2C0SCL(x)     (((x)&0x03)<<6)
+#define GPIO_PAR_CANI2C_I2C0SCL_MASK   (0x3F)
+#define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL        (0xC0)
+#define GPIO_PAR_CANI2C_I2C0SCL_U8TXD  (0x80)
+#define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40)
+#define GPIO_PAR_CANI2C_I2C0SCL_GPIO   (0x00)
+#define GPIO_PAR_CANI2C_I2C0SDA(x)     (((x)&0x03)<<4)
+#define GPIO_PAR_CANI2C_I2C0SDA_MASK   (0xCF)
+#define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA        (0x30)
+#define GPIO_PAR_CANI2C_I2C0SDA_U8RXD  (0x20)
+#define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10)
+#define GPIO_PAR_CANI2C_I2C0SDA_GPIO   (0x00)
+#define GPIO_PAR_CANI2C_CAN1TX(x)      (((x)&0x03)<<2)
+#define GPIO_PAR_CANI2C_CAN1TX_MASK    (0xF3)
+#define GPIO_PAR_CANI2C_CAN1TX_CAN1TX  (0x0C)
+#define GPIO_PAR_CANI2C_CAN1TX_U9TXD   (0x08)
+#define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04)
+#define GPIO_PAR_CANI2C_CAN1TX_GPIO    (0x00)
+#define GPIO_PAR_CANI2C_CAN1RX(x)      ((x)&0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_MASK    (0xFC)
+#define GPIO_PAR_CANI2C_CAN1RX_CAN1RX  (0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_U9RXD   (0x02)
+#define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01)
+#define GPIO_PAR_CANI2C_CAN1RX_GPIO    (0x00)
+
+#define GPIO_PAR_IRQH_IRQ7             (0x10)
+#define GPIO_PAR_IRQH_IRQ4(x)          (((x)&0x03)<<2)
+#define GPIO_PAR_IRQH_IRQ4_MASK        (0xF3)
+#define GPIO_PAR_IRQH_IRQ4_IRQ4        (0x0C)
+#define GPIO_PAR_IRQH_IRQ4_DREQ0       (0x08)
+#define GPIO_PAR_IRQH_IRQ4_GPIO        (0x00)
+#define GPIO_PAR_IRQH_IRQ1             (0x03)
+
+#define GPIO_PAR_IRQL_IRQ6(x)          (((x)&0x03)<<6)
+#define GPIO_PAR_IRQL_IRQ6_MASK        (0x3F)
+#define GPIO_PAR_IRQL_IRQ6_IRQ6        (0xC0)
+#define GPIO_PAR_IRQL_IRQ6_USBCLKIN    (0x40)
+#define GPIO_PAR_IRQL_IRQ6_GPIO        (0x00)
+#define GPIO_PAR_IRQL_IRQ3(x)          (((x)&0x03)<<4)
+#define GPIO_PAR_IRQL_IRQ3_MASK        (0xCF)
+#define GPIO_PAR_IRQL_IRQ3_IRQ3        (0x30)
+#define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3  (0x20)
+#define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN        (0x10)
+#define GPIO_PAR_IRQL_IRQ3_GPIO        (0x00)
+#define GPIO_PAR_IRQL_IRQ2(x)          (((x)&0x03)<<2)
+#define GPIO_PAR_IRQL_IRQ2_MASK        (0xF3)
+#define GPIO_PAR_IRQL_IRQ2_IRQ2        (0x0C)
+#define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2  (0x08)
+#define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC        (0x04)
+#define GPIO_PAR_IRQL_IRQ2_GPIO        (0x00)
+
+#define GPIO_PAR_DSPI0_SIN(x)          (((x)&0x03)<<6)
+#define GPIO_PAR_DSPI0_SIN_MASK        (0x3F)
+#define GPIO_PAR_DSPI0_SIN_DSPI0SIN    (0xC0)
+#define GPIO_PAR_DSPI0_SIN_SBF_DI      (0xC0)
+#define GPIO_PAR_DSPI0_SIN_U3RXD       (0x80)
+#define GPIO_PAR_DSPI0_SIN_SDHC_CMD    (0x40)
+#define GPIO_PAR_DSPI0_SIN_GPIO        (0x00)
+#define GPIO_PAR_DSPI0_SOUT(x)         (((x)&0x03)<<4)
+#define GPIO_PAR_DSPI0_SOUT_MASK       (0xCF)
+#define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT  (0x30)
+#define GPIO_PAR_DSPI0_SOUT_SBF_DO     (0x30)
+#define GPIO_PAR_DSPI0_SOUT_U3TXD      (0x20)
+#define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0  (0x10)
+#define GPIO_PAR_DSPI0_SOUT_GPIO       (0x00)
+#define GPIO_PAR_DSPI0_SCK(x)          (((x)&0x03)<<2)
+#define GPIO_PAR_DSPI0_SCK_MASK        (0xF3)
+#define GPIO_PAR_DSPI0_SCK_DSPI0SCK    (0x0C)
+#define GPIO_PAR_DSPI0_SCK_SBF_CK      (0x0C)
+#define GPIO_PAR_DSPI0_SCK_I2C3SCL     (0x08)
+#define GPIO_PAR_DSPI0_SCK_SDHC_CLK    (0x04)
+#define GPIO_PAR_DSPI0_SCK_GPIO        (0x00)
+#define GPIO_PAR_DSPI0_PCS0(x)         ((x)&0x03)
+#define GPIO_PAR_DSPI0_PCS0_MASK       (0xFC)
+#define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0  (0x03)
+#define GPIO_PAR_DSPI0_PCS0_SS         (0x03)
+#define GPIO_PAR_DSPI0_PCS0_I2C3SDA    (0x02)
+#define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3  (0x01)
+#define GPIO_PAR_DSPI0_PCS0_GPIO       (0x00)
+
+#define GPIO_PAR_DSPIOW_DSPI0PSC1      (0x80)
+#define GPIO_PAR_DSPIOW_SBF_CS         (0x80)
+#define GPIO_PAR_DSPIOW_OWDAT          (((x)&0x03)<<4)
+#define GPIO_PAR_DSPIOW_OWDAT_MASK     (0xCF)
+#define GPIO_PAR_DSPIOW_OWDAT_OWDAT    (0x30)
+#define GPIO_PAR_DSPIOW_OWDAT_DACK0    (0x20)
+#define GPIO_PAR_DSPIOW_OWDAT_GPIO     (0x00)
+
+#define GPIO_PAR_TIMER_T3IN(x)         (((x)&0x03)<<6)
+#define GPIO_PAR_TIMER_T3IN_MASK       (0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN       (0xC0)
+#define GPIO_PAR_TIMER_T3IN_EXTA3      (0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT      (0x80)
+#define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN        (0x40)
+#define GPIO_PAR_TIMER_T3IN_ULIPI_DIR  (0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO       (0x00)
+#define GPIO_PAR_TIMER_T2IN(x)         (((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_T2IN_MASK       (0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN       (0x30)
+#define GPIO_PAR_TIMER_T2IN_EXTA2      (0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT      (0x20)
+#define GPIO_PAR_TIMER_T2IN_SDHC_DAT2  (0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO       (0x00)
+#define GPIO_PAR_TIMER_T1IN(x)         (((x)&0x03)<<2)
+#define GPIO_PAR_TIMER_T1IN_MASK       (0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN       (0x0C)
+#define GPIO_PAR_TIMER_T1IN_EXTA1      (0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT      (0x08)
+#define GPIO_PAR_TIMER_T1IN_SDHC_DAT1  (0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO       (0x00)
+#define GPIO_PAR_TIMER_T0IN(x)         ((x)&0x03)
+#define GPIO_PAR_TIMER_T0IN_MASK       (0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN       (0x03)
+#define GPIO_PAR_TIMER_T0IN_EXTA0      (0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT      (0x02)
+#define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC        (0x01)
+#define GPIO_PAR_TIMER_T0IN_ULPI_NXT   (0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO       (0x00)
+
+#define GPIO_PAR_UART2_U2CTS(x)        (((x)&0x03)<<6)
+#define GPIO_PAR_UART2_U2CTS_MASK      (0x3F)
+#define GPIO_PAR_UART2_U2CTS_U2CTS     (0xC0)
+#define GPIO_PAR_UART2_U2CTS_U6TXD     (0x80)
+#define GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40)
+#define GPIO_PAR_UART2_U2CTS_GPIO      (0x00)
+#define GPIO_PAR_UART2_U2RTS(x)        (((x)&0x03)<<4)
+#define GPIO_PAR_UART2_U2RTS_MASK      (0xCF)
+#define GPIO_PAR_UART2_U2RTS_U2RTS     (0x30)
+#define GPIO_PAR_UART2_U2RTS_U6RXD     (0x20)
+#define GPIO_PAR_UART2_U2RTS_SSI1_FS   (0x10)
+#define GPIO_PAR_UART2_U2RTS_GPIO      (0x00)
+#define GPIO_PAR_UART2_U2RXD(x)        (((x)&0x03)<<2)
+#define GPIO_PAR_UART2_U2RXD_MASK      (0xF3)
+#define GPIO_PAR_UART2_U2RXD_U2RXD     (0x0C)
+#define GPIO_PAR_UART2_U2RXD_PWM_A3    (0x08)
+#define GPIO_PAR_UART2_U2RXD_SSI1_RXD  (0x04)
+#define GPIO_PAR_UART2_U2RXD_GPIO      (0x00)
+#define GPIO_PAR_UART2_U2TXD(x)        ((x)&0x03)
+#define GPIO_PAR_UART2_U2TXD_MASK      (0xFC)
+#define GPIO_PAR_UART2_U2TXD_U2TXD     (0x03)
+#define GPIO_PAR_UART2_U2TXD_PWM_B3    (0x02)
+#define GPIO_PAR_UART2_U2TXD_SSI1_TXD  (0x01)
+#define GPIO_PAR_UART2_U2TXD_GPIO      (0x00)
+
+#define GPIO_PAR_UART1_U1CTS(x)        (((x)&0x03)<<6)
+#define GPIO_PAR_UART1_U1CTS_MASK      (0x3F)
+#define GPIO_PAR_UART1_U1CTS_U1CTS     (0xC0)
+#define GPIO_PAR_UART1_U1CTS_U5TXD     (0x80)
+#define GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40)
+#define GPIO_PAR_UART1_U1CTS_GPIO      (0x00)
+#define GPIO_PAR_UART1_U1RTS(x)        (((x)&0x03)<<4)
+#define GPIO_PAR_UART1_U1RTS_MASK      (0xCF)
+#define GPIO_PAR_UART1_U1RTS_U1RTS     (0x30)
+#define GPIO_PAR_UART1_U1RTS_U5RXD     (0x20)
+#define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0        (0x10)
+#define GPIO_PAR_UART1_U1RTS_GPIO      (0x00)
+#define GPIO_PAR_UART1_U1RXD(x)        (((x)&0x03)<<2)
+#define GPIO_PAR_UART1_U1RXD_MASK      (0xF3)
+#define GPIO_PAR_UART1_U1RXD_U1RXD     (0x0C)
+#define GPIO_PAR_UART1_U1RXD_I2C5SDA   (0x08)
+#define GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04)
+#define GPIO_PAR_UART1_U1RXD_GPIO      (0x00)
+#define GPIO_PAR_UART1_U1TXD(x)        ((x)&0x03)
+#define GPIO_PAR_UART1_U1TXD_MASK      (0xFC)
+#define GPIO_PAR_UART1_U1TXD_U1TXD     (0x03)
+#define GPIO_PAR_UART1_U1TXD_I2C5SCL   (0x02)
+#define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT        (0x01)
+#define GPIO_PAR_UART1_U1TXD_GPIO      (0x00)
+
+#define GPIO_PAR_UART0_U0CTS(x)        (((x)&0x03)<<6)
+#define GPIO_PAR_UART0_U0CTS_MASK      (0x3F)
+#define GPIO_PAR_UART0_U0CTS_U0CTS     (0xC0)
+#define GPIO_PAR_UART0_U0CTS_U4TXD     (0x80)
+#define GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40)
+#define GPIO_PAR_UART0_U0CTS_GPIO      (0x00)
+#define GPIO_PAR_UART0_U0RTS(x)        (((x)&0x03)<<4)
+#define GPIO_PAR_UART0_U0RTS_MASK      (0xCF)
+#define GPIO_PAR_UART0_U0RTS_U0RTS     (0x30)
+#define GPIO_PAR_UART0_U0RTS_U4RXD     (0x20)
+#define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0        (0x10)
+#define GPIO_PAR_UART0_U0RTS_GPIO      (0x00)
+#define GPIO_PAR_UART0_U0RXD(x)        (((x)&0x03)<<2)
+#define GPIO_PAR_UART0_U0RXD_MASK      (0xF3)
+#define GPIO_PAR_UART0_U0RXD_U0RXD     (0x0C)
+#define GPIO_PAR_UART0_U0RXD_I2C4SDA   (0x08)
+#define GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04)
+#define GPIO_PAR_UART0_U0RXD_GPIO      (0x00)
+#define GPIO_PAR_UART0_U0TXD(x)        ((x)&0x03)
+#define GPIO_PAR_UART0_U0TXD_MASK      (0xFC)
+#define GPIO_PAR_UART0_U0TXD_U0TXD     (0x03)
+#define GPIO_PAR_UART0_U0TXD_I2C4SCL   (0x02)
+#define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT        (0x01)
+#define GPIO_PAR_UART0_U0TXD_GPIO      (0x00)
+
+#define GPIO_PAR_SDHCH_DAT3(x)         (((x)&0x03)<<6)
+#define GPIO_PAR_SDHCH_DAT3_MASK       (0x3F)
+#define GPIO_PAR_SDHCH_DAT3_DAT3       (0xC0)
+#define GPIO_PAR_SDHCH_DAT3_PWM_A1     (0x80)
+#define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40)
+#define GPIO_PAR_SDHCH_DAT3_GPIO       (0x00)
+#define GPIO_PAR_SDHCH_DAT2(x)         (((x)&0x03)<<4)
+#define GPIO_PAR_SDHCH_DAT2_MASK       (0xCF)
+#define GPIO_PAR_SDHCH_DAT2_DAT2       (0x30)
+#define GPIO_PAR_SDHCH_DAT2_PWM_B1     (0x20)
+#define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10)
+#define GPIO_PAR_SDHCH_DAT2_GPIO       (0x00)
+#define GPIO_PAR_SDHCH_DAT1(x)         (((x)&0x03)<<2)
+#define GPIO_PAR_SDHCH_DAT1_MASK       (0xF3)
+#define GPIO_PAR_SDHCH_DAT1_DAT1       (0x0C)
+#define GPIO_PAR_SDHCH_DAT1_PWM_A2     (0x08)
+#define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04)
+#define GPIO_PAR_SDHCH_DAT1_GPIO       (0x00)
+#define GPIO_PAR_SDHCH_DAT0(x)         ((x)&0x03)
+#define GPIO_PAR_SDHCH_DAT0_MASK       (0xFC)
+#define GPIO_PAR_SDHCH_DAT0_DAT0       (0x03)
+#define GPIO_PAR_SDHCH_DAT0_PWM_B2     (0x02)
+#define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01)
+#define GPIO_PAR_SDHCH_DAT0_GPIO       (0x00)
+
+#define GPIO_PAR_SDHCL_CMD(x)          (((x)&0x03)<<2)
+#define GPIO_PAR_SDHCL_CMD_MASK        (0xF3)
+#define GPIO_PAR_SDHCL_CMD_CMD         (0x0C)
+#define GPIO_PAR_SDHCL_CMD_PWM_A0      (0x08)
+#define GPIO_PAR_SDHCL_CMD_DSPI1_SIN   (0x04)
+#define GPIO_PAR_SDHCL_CMD_GPIO        (0x00)
+#define GPIO_PAR_SDHCL_CLK(x)          ((x)&0x03)
+#define GPIO_PAR_SDHCL_CLK_MASK        (0xFC)
+#define GPIO_PAR_SDHCL_CLK_CLK         (0x03)
+#define GPIO_PAR_SDHCL_CLK_PWM_B0      (0x02)
+#define GPIO_PAR_SDHCL_CLK_DSPI1_SCK   (0x01)
+#define GPIO_PAR_SDHCL_CLK_GPIO        (0x00)
+
+#define GPIO_PAR_SIMP0H_DAT(x)         (((x)&0x03)<<6)
+#define GPIO_PAR_SIMP0H_DAT_MASK       (0x3F)
+#define GPIO_PAR_SIMP0H_DAT_DAT        (0xC0)
+#define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80)
+#define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7  (0x40)
+#define GPIO_PAR_SIMP0H_DAT_GPIO       (0x00)
+#define GPIO_PAR_SIMP0H_VEN(x)         (((x)&0x03)<<4)
+#define GPIO_PAR_SIMP0H_VEN_MASK       (0xCF)
+#define GPIO_PAR_SIMP0H_VEN_VEN        (0x30)
+#define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20)
+#define GPIO_PAR_SIMP0H_VEN_GPIO       (0x00)
+#define GPIO_PAR_SIMP0H_RST(x)         (((x)&0x03)<<2)
+#define GPIO_PAR_SIMP0H_RST_MASK       (0xF3)
+#define GPIO_PAR_SIMP0H_RST_RST        (0x0C)
+#define GPIO_PAR_SIMP0H_RST_PWM_FORCE  (0x08)
+#define GPIO_PAR_SIMP0H_RST_SDHC_DAT6  (0x04)
+#define GPIO_PAR_SIMP0H_RST_GPIO       (0x00)
+#define GPIO_PAR_SIMP0H_PD(x)          ((x)&0x03)
+#define GPIO_PAR_SIMP0H_PD_MASK        (0xFC)
+#define GPIO_PAR_SIMP0H_PD_PD          (0x03)
+#define GPIO_PAR_SIMP0H_PD_PWM_SYNC    (0x02)
+#define GPIO_PAR_SIMP0H_PD_SDHC_DAT5   (0x01)
+#define GPIO_PAR_SIMP0H_PD_GPIO        (0x00)
+
+#define GPIO_PAR_SIMP0L_CLK(x)         ((x)&0x03)
+#define GPIO_PAR_SIMP0L_CLK_MASK       (0xFC)
+#define GPIO_PAR_SIMP0L_CLK_CLK        (0x03)
+#define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02)
+#define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4  (0x01)
+#define GPIO_PAR_SIMP0L_CLK_GPIO       (0x00)
+
+#define GPIO_PAR_SSI0H_RXD(x)          (((x)&0x03)<<6)
+#define GPIO_PAR_SSI0H_RXD_MASK        (0x3F)
+#define GPIO_PAR_SSI0H_RXD_RXD         (0xC0)
+#define GPIO_PAR_SSI0H_RXD_I2C2SDA     (0x80)
+#define GPIO_PAR_SSI0H_RXD_SIM1_VEN    (0x40)
+#define GPIO_PAR_SSI0H_RXD_GPIO        (0x00)
+#define GPIO_PAR_SSI0H_TXD(x)          (((x)&0x03)<<4)
+#define GPIO_PAR_SSI0H_TXD_MASK        (0xCF)
+#define GPIO_PAR_SSI0H_TXD_TXD         (0x30)
+#define GPIO_PAR_SSI0H_TXD_I2C2SCL     (0x20)
+#define GPIO_PAR_SSI0H_TXD_SIM1_DAT    (0x10)
+#define GPIO_PAR_SSI0H_TXD_GPIO        (0x00)
+#define GPIO_PAR_SSI0H_FS(x)           (((x)&0x03)<<2)
+#define GPIO_PAR_SSI0H_FS_MASK         (0xF3)
+#define GPIO_PAR_SSI0H_FS_FS           (0x0C)
+#define GPIO_PAR_SSI0H_FS_U7TXD        (0x08)
+#define GPIO_PAR_SSI0H_FS_SIM1_RST     (0x04)
+#define GPIO_PAR_SSI0H_FS_GPIO         (0x00)
+#define GPIO_PAR_SSI0H_MCLK(x)         ((x)&0x03)
+#define GPIO_PAR_SSI0H_MCLK_MASK       (0xFC)
+#define GPIO_PAR_SSI0H_MCLK_MCLK       (0x03)
+#define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN  (0x02)
+#define GPIO_PAR_SSI0H_MCLK_SIM1_CLK   (0x01)
+#define GPIO_PAR_SSI0H_MCLK_GPIO       (0x00)
+
+#define GPIO_PAR_SSI0L_BCLK(x)         ((x)&0x03)
+#define GPIO_PAR_SSI0L_BCLK_MASK       (0xFC)
+#define GPIO_PAR_SSI0L_BCLK_BCLK       (0x03)
+#define GPIO_PAR_SSI0L_BCLK_U7RXD      (0x02)
+#define GPIO_PAR_SSI0L_BCLK_SIM1_PD    (0x01)
+#define GPIO_PAR_SSI0L_BCLK_GPIO       (0x00)
+
+#define GPIO_PAR_DEBUGH1_DAT3          (0x40)
+#define GPIO_PAR_DEBUGH1_DAT2          (0x10)
+#define GPIO_PAR_DEBUGH1_DAT1          (0x04)
+#define GPIO_PAR_DEBUGH1_DAT0          (0x01)
+
+#define GPIO_PAR_DEBUGH0_PST3          (0x40)
+#define GPIO_PAR_DEBUGH0_PST2          (0x10)
+#define GPIO_PAR_DEBUGH0_PST1          (0x04)
+#define GPIO_PAR_DEBUGH0_PST0          (0x01)
+
+#define GPIO_PODR_G4_VAL               (0x01 << 4)
+#define GPIO_PODR_G4_MASK              (0xff & ~GPIO_PODR_G4_VAL)
+#define GPIO_PDDR_G4_OUTPUT            (0x01 << 4)
+#define GPIO_PDDR_G4_MASK              (0xff & ~GPIO_PDDR_G4_OUTPUT)
+
+#define GPIO_PAR_DEBUGL_ALLPST         (0x01)
+
+#define GPIO_PAR_FEC_FEC(x)            ((x)&0x0F)
+#define GPIO_PAR_FEC_FEC_MASK          (0xF0)
+#define GPIO_PAR_FEC_FEC_GPIO          (0x0D)
+#define GPIO_PAR_FEC_FEC_RMII1         (0x0C)
+#define GPIO_PAR_FEC_FEC_RMII1FUL      (0x0B)
+#define GPIO_PAR_FEC_FEC_RMII_ULPI     (0x0A)
+#define GPIO_PAR_FEC_FEC_RMII0         (0x09)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08)
+#define GPIO_PAR_FEC_FEC_RMII0FUL      (0x07)
+#define GPIO_PAR_FEC_FEC_RMII0_1FUL    (0x06)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1    (0x05)  /* 0:Full 1: */
+/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
+#define GPIO_PAR_FEC_FEC_RMII0_1       (0x04)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03)
+#define GPIO_PAR_FEC_FEC_MII           (0x01)  /* MDC & MDIO - GPIO */
+#define GPIO_PAR_FEC_FEC_MIIFUL        (0x00)
+
+
+/* TC: Need to edit here.... */
+
+/* Mode Select Control */
+#define GPIO_MSCR_SDRAM_MSC(x)         ((x)&0x03)
+#define GPIO_MSCR_SDRAM_MSC_MASK       (0xFC)
+
+/* Slew Rate Control */
+
+#define GPIO_SRCR_FB3_FB3(x)           ((x)&0x03)
+#define GPIO_SRCR_FB3_FB3_MASK         (0xFC)
+
+#define GPIO_SRCR_FB2_FB2(x)           ((x)&0x03)
+#define GPIO_SRCR_FB2_FB2_MASK         (0xFC)
+
+#define GPIO_SRCR_FB1_FB1(x)           ((x)&0x03)
+#define GPIO_SRCR_FB1_FB1_MASK         (0xFC)
+
+#define GPIO_SRCR_FB4_FB5(x)           (((x)&0x03)<<2)
+#define GPIO_SRCR_FB4_FB5_MASK         (0xF3)
+#define GPIO_SRCR_FB4_FB4(x)           ((x)&0x03)
+#define GPIO_SRCR_FB4_FB4_MASK         (0xFC)
+
+#define GPIO_SRCR_DSPIOW_OWDAT(x)      (((x)&0x03)<<4)
+#define GPIO_SRCR_DSPIOW_OWDAT_MASK    (0xCF)
+#define GPIO_SRCR_DSPIOW_DSPI0(x)      ((x)&0x03)
+#define GPIO_SRCR_DSPIOW_DSPI0_MASK    (0xFC)
+
+#define GPIO_SRCR_CANI2C_CAN1(x)       (((x)&0x03)<<2)
+#define GPIO_SRCR_CANI2C_CAN1_MASK     (0xF3)
+#define GPIO_SRCR_CANI2C_I2C0(x)       ((x)&0x03)
+#define GPIO_SRCR_CANI2C_I2C0_MASK     (0xFC)
+
+#define GPIO_SRCR_IRQ0_IRQ0(x)         ((x)&0x03)
+#define GPIO_SRCR_IRQ0_IRQ0_MASK       (0xFC)
+
+#define GPIO_SRCR_TIMER_TMR3(x)        (((x)&0x03)<<6)
+#define GPIO_SRCR_TIMER_TMR3_MASK      (0x3F)
+#define GPIO_SRCR_TIMER_TMR2(x)        (((x)&0x03)<<4)
+#define GPIO_SRCR_TIMER_TMR2_MASK      (0xCF)
+#define GPIO_SRCR_TIMER_TMR1(x)        (((x)&0x03)<<2)
+#define GPIO_SRCR_TIMER_TMR1_MASK      (0xF3)
+#define GPIO_SRCR_TIMER_TMR0(x)        ((x)&0x03)
+#define GPIO_SRCR_TIMER_TMR0_MASK      (0xFC)
+
+#define GPIO_SRCR_UART_U2(x)           (((x)&0x03)<<4)
+#define GPIO_SRCR_UART_U2_MASK         (0xCF)
+#define GPIO_SRCR_UART_U1(x)           (((x)&0x03)<<2)
+#define GPIO_SRCR_UART_U1_MASK         (0xF3)
+#define GPIO_SRCR_UART_U0(x)           ((x)&0x03)
+#define GPIO_SRCR_UART_U0_MASK         (0xFC)
+
+#define GPIO_SRCR_FEC_RMII0(x)         (((x)&0x03)<<2)
+#define GPIO_SRCR_FEC_RMII0_MASK       (0xF3)
+#define GPIO_SRCR_FEC_RMII1(x)         ((x)&0x03)
+#define GPIO_SRCR_FEC_RMII1_MASK       (0xFC)
+
+#define GPIO_SRCR_SDHC_SDHC(x)         ((x)&0x03)
+#define GPIO_SRCR_SDHC_SDHC_MASK       (0xFC)
+
+#define GPIO_SRCR_SIM0_SIMP0(x)        ((x)&0x03)
+#define GPIO_SRCR_SIM0_SIMP0_MASK      (0xFC)
+
+#define GPIO_SRCR_SSI0_SSI0(x)         ((x)&0x03)
+#define GPIO_SRCR_SSI0_SSI0_MASK       (0xFC)
+
+#define GPIO_PCR_URTS_U2               (0x0004)
+#define GPIO_PCR_URTS_U1               (0x0002)
+#define GPIO_PCR_URTS_U0               (0x0001)
+
+#define GPIO_PCR_UCTS_U2               (0x0004)
+#define GPIO_PCR_UCTS_U1               (0x0002)
+#define GPIO_PCR_UCTS_U0               (0x0001)
+
+#define GPIO_UTXD_WOM_U9               (0x0200)
+#define GPIO_UTXD_WOM_U8               (0x0100)
+#define GPIO_UTXD_WOM_U7               (0x0080)
+#define GPIO_UTXD_WOM_U6               (0x0040)
+#define GPIO_UTXD_WOM_U5               (0x0020)
+#define GPIO_UTXD_WOM_U4               (0x0010)
+#define GPIO_UTXD_WOM_U3               (0x0008)
+#define GPIO_UTXD_WOM_U2               (0x0004)
+#define GPIO_UTXD_WOM_U1               (0x0002)
+#define GPIO_UTXD_WOM_U0               (0x0001)
+
+#define GPIO_URXD_WOM_U9(x)            (((x)&3)<<18)
+#define GPIO_URXD_WOM_U9_MASK          (0xFFF3FFFF)
+#define GPIO_URXD_WOM_U8(x)            (((x)&3)<<16)
+#define GPIO_URXD_WOM_U8_MASK          (0xFFFCFFFF)
+#define GPIO_URXD_WOM_U7(x)            (((x)&3)<<14)
+#define GPIO_URXD_WOM_U7_MASK          (0xFFFF3FFF)
+#define GPIO_URXD_WOM_U6(x)            (((x)&3)<<12)
+#define GPIO_URXD_WOM_U6_MASK          (0xFFFFCFFF)
+#define GPIO_URXD_WOM_U5(x)            (((x)&3)<<10)
+#define GPIO_URXD_WOM_U5_MASK          (0xFFFFF3FF)
+#define GPIO_URXD_WOM_U4(x)            (((x)&3)<<8)
+#define GPIO_URXD_WOM_U4_MASK          (0xFFFFFCFF)
+#define GPIO_URXD_WOM_U3(x)            (((x)&3)<<6)
+#define GPIO_URXD_WOM_U3_MASK          (0xFFFFFF3F)
+#define GPIO_URXD_WOM_U2(x)            (((x)&3)<<4)
+#define GPIO_URXD_WOM_U2_MASK          (0xFFFFFFCF)
+#define GPIO_URXD_WOM_U1(x)            (((x)&3)<<2)
+#define GPIO_URXD_WOM_U1_MASK          (0xFFFFFFF3)
+#define GPIO_URXD_WOM_U0(x)            ((x)&3)
+#define GPIO_URXD_WOM_U0_MASK          (0xFFFFFFFC)
+
+#define GPIO_HCR1_PG4_0(x)             (((x)&0x1F)<<27)
+#define GPIO_HCR1_PG4_0_MASK           (0x07FFFFFF)
+#define GPIO_HCR1_PF7_3(x)             (((x)&0x1F)<<22)
+#define GPIO_HCR1_PF7_3_MASK           (0xF83FFFFF)
+#define GPIO_HCR1_PE6_0(x)             (((x)&0x7F)<<15)
+#define GPIO_HCR1_PE6_0_MASK           (0xFFC07FFF)
+#define GPIO_HCR1_PD7_3(x)             (((x)&0x1F)<<10)
+#define GPIO_HCR1_PD7_3_MASK           (0xFFFF83FF)
+#define GPIO_HCR1_PC7_1(x)             (((x)&0x7F)<<3)
+#define GPIO_HCR1_PC7_1_MASK           (0xFFFFFC07)
+#define GPIO_HCR1_PB2_0(x)             ((x)&7)
+#define GPIO_HCR1_PB2_0_MASK           (0xFFFFFFF8)
+
+#define GPIO_HCR0_PK3                  (0x00000400)
+#define GPIO_HCR0_PK0                  (0x00000200)
+#define GPIO_HCR0_PD2_0(x)             (((x)&7)<<6)
+#define GPIO_HCR0_PD2_0_MASK           (0xFFFFFE3F)
+#define GPIO_HCR0_PE7                  (0x00000020)
+#define GPIO_HCR0_PH7_3(x)             ((x)&0x1F)
+#define GPIO_HCR0_PH7_3_MASK(x)        (0xFFFFFFE0)
+
+/* SDRAM Controller (SDRAMC) */
+
+/* Phase Locked Loop (PLL) */
+#define PLL_CR_LOCIRQ                  (0x00040000)
+#define PLL_CR_LOCRE                   (0x00020000)
+#define PLL_CR_LOCEN                   (0x00010000)
+#define PLL_CR_LOLIRQ                  (0x00004000)
+#define PLL_CR_LOLRE                   (0x00002000)
+#define PLL_CR_LOLEN                   (0x00001000)
+#define PLL_CR_REFDIV(x)               (((x)&7)<<8)
+#define PLL_CR_REFDIV_MASK             (0xFFFFF8FF)
+#define PLL_CR_FBKDIV(x)               ((x)&0x3F)
+#define PLL_CR_FBKDIV_MASK             (0xFFFFFFC0)
+#define PLL_CR_FBKDIV_BITS             (0x3F)
+
+#define PLL_DR_OUTDIV5(x)              (((x)&0x1F)<<21)
+#define PLL_DR_OUTDIV5_MASK            (0xFC1FFFFF)
+#define PLL_DR_OUTDIV5_BITS            (0x03E00000)
+#define PLL_DR_OUTDIV4(x)              (((x)&0x1F)<<16)
+#define PLL_DR_OUTDIV4_MASK            (0xFFE0FFFF)
+#define PLL_DR_OUTDIV4_BITS            (0x001F0000)
+#define PLL_DR_OUTDIV3(x)              (((x)&0x1F)<<10)
+#define PLL_DR_OUTDIV3_MASK            (0xFFFF83FF)
+#define PLL_DR_OUTDIV3_BITS            (0x00007C00)
+#define PLL_DR_OUTDIV2(x)              (((x)&0x1F)<<5)
+#define PLL_DR_OUTDIV2_MASK            (0xFFFFFC1F)
+#define PLL_DR_OUTDIV2_BITS            (0x000003E0)
+#define PLL_DR_OUTDIV1(x)              ((x)&0x1F)
+#define PLL_DR_OUTDIV1_MASK            (0xFFFFFFE0)
+#define PLL_DR_OUTDIV1_BITS            (0x0000001F)
+
+#define PLL_SR_LOCF                    (0x00000200)
+#define PLL_SR_LOC                     (0x00000100)
+#define PLL_SR_LOLF                    (0x00000040)
+#define PLL_SR_LOCKS                   (0x00000020)
+#define PLL_SR_LOCK                    (0x00000010)
+#define PLL_PSR_LOCK                   PLL_SR_LOCK     /* compatible with 5x */
+#define PLL_SR_MODE(x)                 ((x)&7)
+#define PLL_SR_MODE_MASK               (0xFFFFFFF8)
+
+#endif                         /* __MCF5441X__ */
index 973c9ee09854f7dc8a5344e7a6f355ec3ab9d515..8c7c554a460b7ad282ba4b644f132d1fa2398191 100644 (file)
@@ -58,7 +58,7 @@ typedef struct bd_info {
        unsigned long bi_vcofreq;       /* vco Freq in MHz */
        unsigned long bi_flbfreq;       /* Flexbus Freq in MHz */
 #endif
-       unsigned long bi_baudrate;      /* Console Baudrate */
+       unsigned int bi_baudrate;       /* Console Baudrate */
 } bd_t;
 
 #endif                         /* __ASSEMBLY__ */
index 67c9a1382e30160f7278c9ec89df005fd10eff56..02d73fda6111045052d5be20e1efe19e833bbc14 100644 (file)
@@ -29,6 +29,7 @@
 #include <command.h>
 #include <malloc.h>
 #include <stdio_dev.h>
+#include <linux/compiler.h>
 
 #include <asm/immap.h>
 
@@ -387,7 +388,7 @@ board_init_f (ulong bootflag)
  */
 void board_init_r (gd_t *id, ulong dest_addr)
 {
-       char *s;
+       char *s __maybe_unused;
        bd_t *bd;
 
 #ifndef CONFIG_ENV_IS_NOWHERE
@@ -415,8 +416,8 @@ void board_init_r (gd_t *id, ulong dest_addr)
        /*
         * We have to relocate the command table manually
         */
-       fixup_cmdtable(&__u_boot_cmd_start,
-               (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+       fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+                       ll_entry_count(cmd_tbl_t, cmd));
 #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
        /* there are some other pointer constants we must deal with */
index d033a2835b362f48381390da2ce4649aeb38086d..4297b9344313af12b181ae084a109e88dc8afe8c 100644 (file)
@@ -50,12 +50,9 @@ SECTIONS
                __data_end = .;
        }
 
-       .u_boot_cmd ALIGN(0x4):
-       {
-               . = .;
-               __u_boot_cmd_start = .;
-               *(.u_boot_cmd)
-               __u_boot_cmd_end = .;
+       . = ALIGN(4);
+       .u_boot_list : {
+               #include <u-boot.lst>
        }
 
        .bss ALIGN(0x4):
index de3b8dbe92775a896b6e0ad164929c28090a06c4..2111c7cba27fb7a1e3e65e82c1e8cd7091f774aa 100644 (file)
@@ -35,7 +35,7 @@
 typedef        struct  global_data {
        bd_t            *bd;
        unsigned long   flags;
-       unsigned long   baudrate;
+       unsigned int    baudrate;
        unsigned long   have_console;   /* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
        unsigned long   precon_buf_idx; /* Pre-Console buffer index */
index a0b1dbf9e67802af81ee6e1469277ae6b01a8975..8d00658564c5ee34f676c3161a3ac448f5631848 100644 (file)
@@ -40,7 +40,7 @@ typedef struct bd_info {
        unsigned long   bi_flashoffset; /* reserved area for startup monitor */
        unsigned long   bi_sramstart;   /* start of SRAM memory */
        unsigned long   bi_sramsize;    /* size  of SRAM memory */
-       unsigned long   bi_baudrate;    /* Console Baudrate */
+       unsigned int    bi_baudrate;    /* Console Baudrate */
 } bd_t;
 
 /* For image.h:image_check_target_arch() */
index dc58475f68137972b5a099d4c2a96a0c28421240..b9f895df5b36d178cb315537e3a2569770bbbfd7 100644 (file)
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(SOC).o
 
-COBJS  = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+COBJS  = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
 
 SRCS   := $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
similarity index 59%
rename from board/bmw/m48t59y.h
rename to arch/mips/cpu/mips32/au1x00/au1x00_ide.c
index 717300d957bf1ce87875f129b5295ce13421e25a..932cdfb9bb6271f7e0ba5231f768de01f6674438 100644 (file)
@@ -1,13 +1,7 @@
 /*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * (C) Copyright 2000
+ * (C) Copyright 2000-2011
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
- *
- * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
- *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
+ *
  */
 
-#ifndef __M48_T59_Y_H
-#define __M48_T59_Y_H
-
-/*
- * M48 T59Y -Timekeeping Battery backed SRAM.
- */
-
-int m48_tod_init(void);
-
-int m48_tod_set(int year,
-               int month,
-               int day,
-               int hour,
-               int minute,
-               int second);
-
-int m48_tod_get(int *year,
-               int *month,
-               int *day,
-               int *hour,
-               int *minute,
-               int *second);
-
-int m48_tod_get_second(void);
-
-void m48_watchdog_arm(int usec);
+#include <common.h>
+#include <ide.h>
 
-#endif /*!__M48_T59_Y_H */
+/* AU1X00 swaps data in big-endian mode, enforce little-endian function */
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+       ide_input_data(dev, sect_buf, words);
+}
index 0beac98fdeb7bc1ce9b1e60ffccf42567b9e4dfc..3e85b90cded451b709da8dc795b164e8e8a34ab1 100644 (file)
@@ -103,12 +103,6 @@ static void au1x00_serial_putc(const char c)
        *uart_tx = (u32)c;
 }
 
-static void au1x00_serial_puts(const char *s)
-{
-       while (*s)
-               serial_putc(*s++);
-}
-
 static int au1x00_serial_getc(void)
 {
        volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
@@ -137,7 +131,7 @@ static struct serial_device au1x00_serial_drv = {
        .stop   = NULL,
        .setbrg = au1x00_serial_setbrg,
        .putc   = au1x00_serial_putc,
-       .puts   = au1x00_serial_puts,
+       .puts   = default_serial_puts,
        .getc   = au1x00_serial_getc,
        .tstc   = au1x00_serial_tstc,
 };
index e683e8be8cb9e8b42c1f53ac300fafea7672bdff..64dfad026324fc573d0b4a17965792826acec3e6 100644 (file)
@@ -85,17 +85,17 @@ LEAF(mips_init_icache)
        /* clear tag to invalidate */
        PTR_LI          t0, INDEX_BASE
        PTR_ADDU        t1, t0, a1
-1:     cache_op        Index_Store_Tag_I t0
+1:     cache_op        INDEX_STORE_TAG_I t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
        /* fill once, so data field parity is correct */
        PTR_LI          t0, INDEX_BASE
-2:     cache_op        Fill t0
+2:     cache_op        FILL t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 2b
        /* invalidate again - prudent but not strictly neccessary */
        PTR_LI          t0, INDEX_BASE
-1:     cache_op        Index_Store_Tag_I t0
+1:     cache_op        INDEX_STORE_TAG_I t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
 9:     jr              ra
@@ -110,7 +110,7 @@ LEAF(mips_init_dcache)
        /* clear all tags */
        PTR_LI          t0, INDEX_BASE
        PTR_ADDU        t1, t0, a1
-1:     cache_op        Index_Store_Tag_D t0
+1:     cache_op        INDEX_STORE_TAG_D t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
        /* load from each line (in cached space) */
@@ -120,7 +120,7 @@ LEAF(mips_init_dcache)
        bne             t0, t1, 2b
        /* clear all tags */
        PTR_LI          t0, INDEX_BASE
-1:     cache_op        Index_Store_Tag_D t0
+1:     cache_op        INDEX_STORE_TAG_D t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
 9:     jr              ra
index 7b49e1b612b70b876e6b78c27d4a52a7dc176b2b..50bb248bd0102ab12f04952572ecc32edc6d76b4 100644 (file)
@@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size)
                return;
 
        while (1) {
-               cache_op(Hit_Writeback_Inv_D, addr);
-               cache_op(Hit_Invalidate_I, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
+               cache_op(HIT_INVALIDATE_I, addr);
                if (addr == aend)
                        break;
                addr += lsize;
@@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        while (1) {
-               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
                if (addr == aend)
                        break;
                addr += lsize;
@@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        while (1) {
-               cache_op(Hit_Invalidate_D, addr);
+               cache_op(HIT_INVALIDATE_D, addr);
                if (addr == aend)
                        break;
                addr += lsize;
index 08949f4fb05d39ca77812c0a37b6ea86e5091f55..6f0e4f2520143a2909ff73585f2d1576b9a276da 100644 (file)
@@ -236,14 +236,6 @@ static void asc_serial_putc(const char c)
     }
 }
 
-static void asc_serial_puts(const char *s)
-{
-    while (*s)
-    {
-       serial_putc (*s++);
-    }
-}
-
 static int asc_serial_getc(void)
 {
     ulong symbol_mask;
@@ -292,7 +284,7 @@ static struct serial_device asc_serial_drv = {
        .stop   = NULL,
        .setbrg = asc_serial_setbrg,
        .putc   = asc_serial_putc,
-       .puts   = asc_serial_puts,
+       .puts   = default_serial_puts,
        .getc   = asc_serial_getc,
        .tstc   = asc_serial_tstc,
 };
diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile
new file mode 100644 (file)
index 0000000..be38664
--- /dev/null
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(CPU).o
+
+START  = start.o
+COBJS-y        = cpu.o interrupts.o time.o cache.o
+
+SRCS   := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START  := $(addprefix $(obj),$(START))
+
+all:   $(obj).depend $(START) $(LIB)
+
+$(LIB):        $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S
new file mode 100644 (file)
index 0000000..036f035
--- /dev/null
@@ -0,0 +1,229 @@
+/*
+ *  Cache-handling routined for MIPS CPUs
+ *
+ *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#define RA             t9
+
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE    0x10000
+
+#define INDEX_BASE     CKSEG0
+
+       .macro  cache_op op addr
+       .set    push
+       .set    noreorder
+       .set    mips3
+       cache   \op, 0(\addr)
+       .set    pop
+       .endm
+
+       .macro  f_fill64 dst, offset, val
+       LONG_S  \val, (\offset +  0 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  1 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  2 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  3 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  4 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  5 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  6 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  7 * LONGSIZE)(\dst)
+#if LONGSIZE == 4
+       LONG_S  \val, (\offset +  8 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset +  9 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 10 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 11 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 12 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 13 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 14 * LONGSIZE)(\dst)
+       LONG_S  \val, (\offset + 15 * LONGSIZE)(\dst)
+#endif
+       .endm
+
+/*
+ * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
+ */
+LEAF(mips_init_icache)
+       blez            a1, 9f
+       mtc0            zero, CP0_TAGLO
+       /* clear tag to invalidate */
+       PTR_LI          t0, INDEX_BASE
+       PTR_ADDU        t1, t0, a1
+1:     cache_op        INDEX_STORE_TAG_I t0
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 1b
+       /* fill once, so data field parity is correct */
+       PTR_LI          t0, INDEX_BASE
+2:     cache_op        FILL t0
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 2b
+       /* invalidate again - prudent but not strictly neccessary */
+       PTR_LI          t0, INDEX_BASE
+1:     cache_op        INDEX_STORE_TAG_I t0
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 1b
+9:     jr              ra
+       END(mips_init_icache)
+
+/*
+ * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
+ */
+LEAF(mips_init_dcache)
+       blez            a1, 9f
+       mtc0            zero, CP0_TAGLO
+       /* clear all tags */
+       PTR_LI          t0, INDEX_BASE
+       PTR_ADDU        t1, t0, a1
+1:     cache_op        INDEX_STORE_TAG_D t0
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 1b
+       /* load from each line (in cached space) */
+       PTR_LI          t0, INDEX_BASE
+2:     LONG_L          zero, 0(t0)
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 2b
+       /* clear all tags */
+       PTR_LI          t0, INDEX_BASE
+1:     cache_op        INDEX_STORE_TAG_D t0
+       PTR_ADDU        t0, a2
+       bne             t0, t1, 1b
+9:     jr              ra
+       END(mips_init_dcache)
+
+/*
+ * mips_cache_reset - low level initialisation of the primary caches
+ *
+ * This routine initialises the primary caches to ensure that they have good
+ * parity.  It must be called by the ROM before any cached locations are used
+ * to prevent the possibility of data with bad parity being written to memory.
+ *
+ * To initialise the instruction cache it is essential that a source of data
+ * with good parity is available. This routine will initialise an area of
+ * memory starting at location zero to be used as a source of parity.
+ *
+ * RETURNS: N/A
+ *
+ */
+NESTED(mips_cache_reset, 0, ra)
+       move    RA, ra
+       li      t2, CONFIG_SYS_ICACHE_SIZE
+       li      t3, CONFIG_SYS_DCACHE_SIZE
+       li      t8, CONFIG_SYS_CACHELINE_SIZE
+
+       li      v0, MIPS_MAX_CACHE_SIZE
+
+       /*
+        * Now clear that much memory starting from zero.
+        */
+       PTR_LI          a0, CKSEG1
+       PTR_ADDU        a1, a0, v0
+2:     PTR_ADDIU       a0, 64
+       f_fill64        a0, -64, zero
+       bne             a0, a1, 2b
+
+       /*
+        * The caches are probably in an indeterminate state,
+        * so we force good parity into them by doing an
+        * invalidate, load/fill, invalidate for each line.
+        */
+
+       /*
+        * Assume bottom of RAM will generate good parity for the cache.
+        */
+
+       /*
+        * Initialize the I-cache first,
+        */
+       move    a1, t2
+       move    a2, t8
+       PTR_LA  v1, mips_init_icache
+       jalr    v1
+
+       /*
+        * then initialize D-cache.
+        */
+       move    a1, t3
+       move    a2, t8
+       PTR_LA  v1, mips_init_dcache
+       jalr    v1
+
+       jr      RA
+       END(mips_cache_reset)
+
+/*
+ * dcache_status - get cache status
+ *
+ * RETURNS: 0 - cache disabled; 1 - cache enabled
+ *
+ */
+LEAF(dcache_status)
+       mfc0    t0, CP0_CONFIG
+       li      t1, CONF_CM_UNCACHED
+       andi    t0, t0, CONF_CM_CMASK
+       move    v0, zero
+       beq     t0, t1, 2f
+       li      v0, 1
+2:     jr      ra
+       END(dcache_status)
+
+/*
+ * dcache_disable - disable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_disable)
+       mfc0    t0, CP0_CONFIG
+       li      t1, -8
+       and     t0, t0, t1
+       ori     t0, t0, CONF_CM_UNCACHED
+       mtc0    t0, CP0_CONFIG
+       jr      ra
+       END(dcache_disable)
+
+/*
+ * dcache_enable - enable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_enable)
+       mfc0    t0, CP0_CONFIG
+       ori     t0, CONF_CM_CMASK
+       xori    t0, CONF_CM_CMASK
+       ori     t0, CONF_CM_CACHABLE_NONCOHERENT
+       mtc0    t0, CP0_CONFIG
+       jr      ra
+       END(dcache_enable)
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk
new file mode 100644 (file)
index 0000000..ebc1ceb
--- /dev/null
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Default optimization level for MIPS64
+#
+# Note: Toolchains with binutils prior to v2.16
+# are no longer supported by U-Boot MIPS tree!
+#
+MIPSFLAGS = -march=mips64
+
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS  += -m elf64btsmip
+else
+PLATFORM_LDFLAGS  += -m elf64ltsmip
+endif
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
new file mode 100644 (file)
index 0000000..2a38d0c
--- /dev/null
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+
+#define cache_op(op, addr)                                             \
+       __asm__ __volatile__(                                           \
+       "       .set    push\n"                                         \
+       "       .set    noreorder\n"                                    \
+       "       .set    mips64\n"                                       \
+       "       cache   %0, %1\n"                                       \
+       "       .set    pop\n"                                          \
+       :                                                               \
+       : "i" (op), "R" (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+       fprintf(stderr, "*** reset failed ***\n");
+
+       while (1)
+               /* NOP */;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+       _machine_restart();
+
+       return 0;
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+       /* aend will be miscalculated when size is zero, so we return here */
+       if (size == 0)
+               return;
+
+       while (1) {
+               cache_op(HIT_WRITEBACK_INV_D, addr);
+               cache_op(HIT_INVALIDATE_I, addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+       while (1) {
+               cache_op(HIT_WRITEBACK_INV_D, addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+       unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+       unsigned long addr = start_addr & ~(lsize - 1);
+       unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+       while (1) {
+               cache_op(HIT_INVALIDATE_D, addr);
+               if (addr == aend)
+                       break;
+               addr += lsize;
+       }
+}
+
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
+       write_c0_entrylo0(low0);
+       write_c0_pagemask(pagemask);
+       write_c0_entrylo1(low1);
+       write_c0_entryhi(hi);
+       write_c0_index(index);
+       tlb_write_indexed();
+}
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c
new file mode 100644 (file)
index 0000000..e4e9aae
--- /dev/null
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+void enable_interrupts(void)
+{
+}
+
+int disable_interrupts(void)
+{
+       return 0;
+}
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
new file mode 100644 (file)
index 0000000..4112de7
--- /dev/null
@@ -0,0 +1,256 @@
+/*
+ *  Startup Code for MIPS64 CPU-core
+ *
+ *  Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any dlater version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
+       /*
+        * For the moment disable interrupts, mark the kernel mode and
+        * set ST0_KX so that the CPU does not spit fire when using
+        * 64-bit addresses.
+        */
+       .macro  setup_c0_status set clr
+       .set    push
+       mfc0    t0, CP0_STATUS
+       or      t0, ST0_CU0 | \set | 0x1f | \clr
+       xor     t0, 0x1f | \clr
+       mtc0    t0, CP0_STATUS
+       .set    noreorder
+       sll     zero, 3                         # ehb
+       .set    pop
+       .endm
+
+       .set noreorder
+
+       .globl _start
+       .text
+_start:
+       .org 0x000
+       b       reset
+        nop
+       .org 0x080
+       b       romReserved
+        nop
+       .org 0x100
+       b       romReserved
+        nop
+       .org 0x180
+       b       romReserved
+        nop
+       .org 0x200
+       b       romReserved
+        nop
+       .org 0x280
+       b       romReserved
+        nop
+       .org 0x300
+       b       romReserved
+        nop
+       .org 0x380
+       b       romReserved
+        nop
+       .org 0x480
+       b       romReserved
+        nop
+
+       /*
+        * We hope there are no more reserved vectors!
+        * 128 * 8 == 1024 == 0x400
+        * so this is address R_VEC+0x400 == 0xbfc00400
+        */
+       .org 0x500
+       .align 4
+reset:
+
+       /* Clear watch registers */
+       dmtc0   zero, CP0_WATCHLO
+       dmtc0   zero, CP0_WATCHHI
+
+       /* WP(Watch Pending), SW0/1 should be cleared */
+       mtc0    zero, CP0_CAUSE
+
+       setup_c0_status ST0_KX 0
+
+       /* Init Timer */
+       mtc0    zero, CP0_COUNT
+       mtc0    zero, CP0_COMPARE
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+       /* CONFIG0 register */
+       dli     t0, CONF_CM_UNCACHED
+       mtc0    t0, CP0_CONFIG
+#endif
+
+       /* Initialize $gp */
+       bal     1f
+        nop
+       .dword  _gp
+1:
+       ld      gp, 0(ra)
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+       /* Initialize any external memory */
+       dla     t9, lowlevel_init
+       jalr    t9
+        nop
+
+       /* Initialize caches... */
+       dla     t9, mips_cache_reset
+       jalr    t9
+        nop
+
+       /* ... and enable them */
+       dli     t0, CONFIG_SYS_MIPS_CACHE_MODE
+       mtc0    t0, CP0_CONFIG
+#endif
+
+       /* Set up temporary stack */
+       dli     t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+       dla     sp, 0(t0)
+
+       dla     t9, board_init_f
+       jr      t9
+        nop
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+       .globl  relocate_code
+       .ent    relocate_code
+relocate_code:
+       move    sp, a0                  # set new stack pointer
+
+       dli     t0, CONFIG_SYS_MONITOR_BASE
+       dla     t3, in_ram
+       ld      t2, -24(t3)             # t2 <-- uboot_end_data
+       move    t1, a2
+       move    s2, a2                  # s2 <-- destination address
+
+       /*
+        * Fix $gp:
+        *
+        * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
+        */
+       move    t8, gp
+       dsub    gp, CONFIG_SYS_MONITOR_BASE
+       dadd    gp, a2                  # gp now adjusted
+       dsub    s1, gp, t8              # s1 <-- relocation offset
+
+       /*
+        * t0 = source address
+        * t1 = target address
+        * t2 = source end address
+        */
+
+       /*
+        * Save destination address and size for dlater usage in flush_cache()
+        */
+       move    s0, a1                  # save gd in s0
+       move    a0, t1                  # a0 <-- destination addr
+       dsub    a1, t2, t0              # a1 <-- size
+
+1:
+       lw      t3, 0(t0)
+       sw      t3, 0(t1)
+       daddu   t0, 4
+       ble     t0, t2, 1b
+        daddu  t1, 4
+
+       /* If caches were enabled, we would have to flush them here. */
+
+       /* a0 & a1 are already set up for flush_cache(start, size) */
+       dla     t9, flush_cache
+       jalr    t9
+        nop
+
+       /* Jump to where we've relocated ourselves */
+       daddi   t0, s2, in_ram - _start
+       jr      t0
+        nop
+
+       .dword  _gp
+       .dword  _GLOBAL_OFFSET_TABLE_
+       .dword  uboot_end_data
+       .dword  uboot_end
+       .dword  num_got_entries
+
+in_ram:
+       /*
+        * Now we want to update GOT.
+        *
+        * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+        * generated by GNU ld. Skip these reserved entries from relocation.
+        */
+       ld      t3, -8(t0)              # t3 <-- num_got_entries
+       ld      t8, -32(t0)             # t8 <-- _GLOBAL_OFFSET_TABLE_
+       ld      t9, -40(t0)             # t9 <-- _gp
+       dsub    t8, t9                  # compute offset
+       dadd    t8, t8, gp              # t8 now holds relocated _G_O_T_
+       daddi   t8, t8, 16              # skipping first two entries
+       dli     t2, 2
+1:
+       ld      t1, 0(t8)
+       beqz    t1, 2f
+        dadd   t1, s1
+       sd      t1, 0(t8)
+2:
+       daddi   t2, 1
+       blt     t2, t3, 1b
+        daddi  t8, 8
+
+       /* Clear BSS */
+       ld      t1, -24(t0)             # t1 <-- uboot_end_data
+       ld      t2, -16(t0)             # t2 <-- uboot_end
+       dadd    t1, s1                  # adjust pointers
+       dadd    t2, s1
+
+       dsub    t1, 8
+1:
+       daddi   t1, 8
+       bltl    t1, t2, 1b
+        sd     zero, 0(t1)
+
+       move    a0, s0                  # a0 <-- gd
+       dla     t9, board_init_r
+       jr      t9
+        move   a1, s2
+
+       .end    relocate_code
+
+       /* Exception handlers */
+romReserved:
+       b       romReserved
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
new file mode 100644 (file)
index 0000000..5154280
--- /dev/null
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY        \
+       (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+       /* Set up the timer for the first expiration. */
+       timestamp = 0;
+       write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+       return 0;
+}
+
+ulong get_timer(ulong base)
+{
+       unsigned int count;
+       unsigned int expirelo = read_c0_compare();
+
+       /* Check to see if we have missed any timestamps. */
+       count = read_c0_count();
+       while ((count - expirelo) < 0x7fffffff) {
+               expirelo += CYCLES_PER_JIFFY;
+               timestamp++;
+       }
+       write_c0_compare(expirelo);
+
+       return timestamp - base;
+}
+
+void __udelay(unsigned long usec)
+{
+       unsigned int tmo;
+
+       tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
+       while ((tmo - read_c0_count()) < 0x7fffffff)
+               /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+       return CONFIG_SYS_HZ;
+}
index ddcbfaa47c93f858d7a68f6fb9812ed35cb57636..cc190dfe56e13f45f2b92000ffb6e042ef2095e3 100644 (file)
@@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size)
        unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
        for (; addr <= aend; addr += lsize) {
-               cache_op(Hit_Writeback_Inv_D, addr);
-               cache_op(Hit_Invalidate_I, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
+               cache_op(HIT_INVALIDATE_I, addr);
        }
 }
 
@@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        for (; addr <= aend; addr += lsize)
-               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
 }
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        for (; addr <= aend; addr += lsize)
-               cache_op(Hit_Invalidate_D, addr);
+               cache_op(HIT_INVALIDATE_D, addr);
 }
 
 void flush_icache_all(void)
@@ -118,7 +118,7 @@ void flush_icache_all(void)
 
        for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
             addr += CONFIG_SYS_CACHELINE_SIZE) {
-               cache_op(Index_Store_Tag_I, addr);
+               cache_op(INDEX_STORE_TAG_I, addr);
        }
 
        /* invalidate btb */
@@ -139,7 +139,7 @@ void flush_dcache_all(void)
 
        for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
             addr += CONFIG_SYS_CACHELINE_SIZE) {
-               cache_op(Index_Writeback_Inv_D, addr);
+               cache_op(INDEX_WRITEBACK_INV_D, addr);
        }
 
        __asm__ __volatile__("sync");
index 319900775752e9ac5b652197dda5001aaeed0c51..a14765735020255d48b05a17953bcc7b8c29165b 100644 (file)
@@ -109,19 +109,13 @@ static int jz_serial_getc(void)
        return readb(&uart->rbr_thr_dllr);
 }
 
-static void jz_serial_puts(const char *s)
-{
-       while (*s)
-               serial_putc(*s++);
-}
-
 static struct serial_device jz_serial_drv = {
        .name   = "jz_serial",
        .start  = jz_serial_init,
        .stop   = NULL,
        .setbrg = jz_serial_setbrg,
        .putc   = jz_serial_putc,
-       .puts   = jz_serial_puts,
+       .puts   = default_serial_puts,
        .getc   = jz_serial_getc,
        .tstc   = jz_serial_tstc,
 };
index d846104d10151ed8a4b40c4a2a2f60254b29fba0..3a8280cb0ab850deaf36731e4c705f449a832866 100644 (file)
@@ -96,7 +96,7 @@ relocate_code:
        li      t0, KSEG0
        addi    t1, t0, CONFIG_SYS_DCACHE_SIZE
 2:
-       cache   Index_Writeback_Inv_D, 0(t0)
+       cache   INDEX_WRITEBACK_INV_D, 0(t0)
        bne     t0, t1, 2b
         addi   t0, CONFIG_SYS_CACHELINE_SIZE
 
@@ -106,7 +106,7 @@ relocate_code:
        li      t0, KSEG0
        addi    t1, t0, CONFIG_SYS_ICACHE_SIZE
 3:
-       cache   Index_Invalidate_I, 0(t0)
+       cache   INDEX_INVALIDATE_I, 0(t0)
        bne     t0, t1, 3b
         addi   t0, CONFIG_SYS_CACHELINE_SIZE
 
index 3a1e6d615fa95863c1a967823c544e76cc510e04..b768bb5081c45a94afd5b8a049f887fabdd65e64 100644 (file)
    cannot access physical memory directly from core */
 #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
 #else  /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
 #endif /* CONFIG_SOC_AU1X00 */
 #endif /* __ASSEMBLY__ */
 
index 608cfcfbb3eaad36da1e19f539bb3efa5084cfef..933ccb1b7864abb9993bcaa187f25f15c9878dbf 100644 (file)
@@ -401,7 +401,7 @@ symbol              =       value
 #ifdef CONFIG_SGI_IP28
 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
 #include <asm/cacheops.h>
-#define R10KCBARRIER(addr)  cache   Cache_Barrier, addr;
+#define R10KCBARRIER(addr)  cache   CACHE_BARRIER, addr;
 #else
 #define R10KCBARRIER(addr)
 #endif
index 70bcad7694dfc48410551c3a7c571fadfef764db..6464250d8486ec6261c1c6066dd7bb104dd61ee9 100644 (file)
 /*
  * Cache Operations available on all MIPS processors with R4000-style caches
  */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Load_Tag_I       0x04
-#define Index_Load_Tag_D       0x05
-#define Index_Store_Tag_I      0x08
-#define Index_Store_Tag_D      0x09
+#define INDEX_INVALIDATE_I      0x00
+#define INDEX_WRITEBACK_INV_D   0x01
+#define INDEX_LOAD_TAG_I       0x04
+#define INDEX_LOAD_TAG_D       0x05
+#define INDEX_STORE_TAG_I      0x08
+#define INDEX_STORE_TAG_D      0x09
 #if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I       0x00
+#define HIT_INVALIDATE_I       0x00
 #else
-#define Hit_Invalidate_I       0x10
+#define HIT_INVALIDATE_I       0x10
 #endif
-#define Hit_Invalidate_D       0x11
-#define Hit_Writeback_Inv_D    0x15
+#define HIT_INVALIDATE_D       0x11
+#define HIT_WRITEBACK_INV_D    0x15
 
 /*
  * R4000-specific cacheops
  */
-#define Create_Dirty_Excl_D    0x0d
-#define Fill                   0x14
-#define Hit_Writeback_I                0x18
-#define Hit_Writeback_D                0x19
+#define CREATE_DIRTY_EXCL_D    0x0d
+#define FILL                   0x14
+#define HIT_WRITEBACK_I                0x18
+#define HIT_WRITEBACK_D                0x19
 
 /*
  * R4000SC and R4400SC-specific cacheops
  */
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_SI      0x06
-#define Index_Load_Tag_SD      0x07
-#define Index_Store_Tag_SI     0x0A
-#define Index_Store_Tag_SD     0x0B
-#define Create_Dirty_Excl_SD   0x0f
-#define Hit_Invalidate_SI      0x12
-#define Hit_Invalidate_SD      0x13
-#define Hit_Writeback_Inv_SD   0x17
-#define Hit_Writeback_SD       0x1b
-#define Hit_Set_Virtual_SI     0x1e
-#define Hit_Set_Virtual_SD     0x1f
+#define INDEX_INVALIDATE_SI     0x02
+#define INDEX_WRITEBACK_INV_SD  0x03
+#define INDEX_LOAD_TAG_SI      0x06
+#define INDEX_LOAD_TAG_SD      0x07
+#define INDEX_STORE_TAG_SI     0x0A
+#define INDEX_STORE_TAG_SD     0x0B
+#define CREATE_DIRTY_EXCL_SD   0x0f
+#define HIT_INVALIDATE_SI      0x12
+#define HIT_INVALIDATE_SD      0x13
+#define HIT_WRITEBACK_INV_SD   0x17
+#define HIT_WRITEBACK_SD       0x1b
+#define HIT_SET_VIRTUAL_SI     0x1e
+#define HIT_SET_VIRTUAL_SD     0x1f
 
 /*
  * R5000-specific cacheops
  */
-#define R5K_Page_Invalidate_S  0x17
+#define R5K_PAGE_INVALIDATE_S  0x17
 
 /*
  * RM7000-specific cacheops
  */
-#define Page_Invalidate_T      0x16
+#define PAGE_INVALIDATE_T      0x16
 
 /*
  * R10000-specific cacheops
  * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
  * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
  */
-#define Index_Writeback_Inv_S  0x03
-#define Index_Load_Tag_S       0x07
-#define Index_Store_Tag_S      0x0B
-#define Hit_Invalidate_S       0x13
-#define Cache_Barrier          0x14
-#define Hit_Writeback_Inv_S    0x17
-#define Index_Load_Data_I      0x18
-#define Index_Load_Data_D      0x19
-#define Index_Load_Data_S      0x1b
-#define Index_Store_Data_I     0x1c
-#define Index_Store_Data_D     0x1d
-#define Index_Store_Data_S     0x1f
+#define INDEX_WRITEBACK_INV_S  0x03
+#define INDEX_LOAD_TAG_S       0x07
+#define INDEX_STORE_TAG_S      0x0B
+#define HIT_INVALIDATE_S       0x13
+#define CACHE_BARRIER          0x14
+#define HIT_WRITEBACK_INV_S    0x17
+#define INDEX_LOAD_DATA_I      0x18
+#define INDEX_LOAD_DATA_D      0x19
+#define INDEX_LOAD_DATA_S      0x1b
+#define INDEX_STORE_DATA_I     0x1c
+#define INDEX_STORE_DATA_D     0x1d
+#define INDEX_STORE_DATA_S     0x1f
 
 #endif /* __ASM_CACHEOPS_H */
index 6e2cdc72cf53dd53fdbfa244ebcc1e10d60062e4..a735a8a2c76d0cc3986dc705fd8f2e709d214008 100644 (file)
@@ -48,7 +48,7 @@ typedef       struct  global_data {
        unsigned long   tbl;
        unsigned long   lastinc;
 #endif
-       unsigned long   baudrate;
+       unsigned int    baudrate;
        unsigned long   have_console;   /* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
        unsigned long   precon_buf_idx; /* Pre-Console buffer index */
index 025012ae60cdec23c9dff86e7182fc0e94591e96..80eab75e153afdfff91beeea87152291edf54426 100644 (file)
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
  */
 extern inline phys_addr_t virt_to_phys(volatile void * address)
 {
+#ifndef CONFIG_64BIT
        return CPHYSADDR(address);
+#else
+       return XPHYSADDR(address);
+#endif
 }
 
 extern inline void * phys_to_virt(unsigned long address)
 {
+#ifndef CONFIG_64BIT
        return (void *)KSEG0ADDR(address);
+#else
+       return (void *)CKSEG0ADDR(address);
+#endif
 }
 
 /*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
  */
 extern inline unsigned long virt_to_bus(volatile void * address)
 {
+#ifndef CONFIG_64BIT
        return CPHYSADDR(address);
+#else
+       return XPHYSADDR(address);
+#endif
 }
 
 extern inline void * bus_to_virt(unsigned long address)
 {
+#ifndef CONFIG_64BIT
        return (void *)KSEG0ADDR(address);
+#else
+       return (void *)CKSEG0ADDR(address);
+#endif
 }
 
 /*
index 879aae210b2b833d489d14e9c63619784b740cf0..4deac5207aaeb2e07028852ac83e7428c0259c27 100644 (file)
@@ -24,9 +24,15 @@ typedef int          __kernel_pid_t;
 typedef int            __kernel_ipc_pid_t;
 typedef int            __kernel_uid_t;
 typedef int            __kernel_gid_t;
+#if _MIPS_SZLONG != 64
 typedef unsigned int   __kernel_size_t;
 typedef int            __kernel_ssize_t;
 typedef int            __kernel_ptrdiff_t;
+#else
+typedef unsigned long  __kernel_size_t;
+typedef long           __kernel_ssize_t;
+typedef long           __kernel_ptrdiff_t;
+#endif
 typedef long           __kernel_time_t;
 typedef long           __kernel_suseconds_t;
 typedef long           __kernel_clock_t;
index 590649aa3edf8c57b254c0a72f8986914791010f..5fa4a6a73044fb68912ff697e1d388586b72a337 100644 (file)
@@ -32,7 +32,7 @@
 #define _U_BOOT_H_     1
 
 typedef struct bd_info {
-       int             bi_baudrate;    /* serial console baudrate */
+       unsigned int    bi_baudrate;    /* serial console baudrate */
        unsigned long   bi_arch_number; /* unique id for this board */
        unsigned long   bi_boot_params; /* where this board expects params */
        unsigned long   bi_memstart;    /* start of DRAM memory */
index b14b33efcd0bf20317f01a27b58194662aaeba14..7ddd77832cc5f165111d5b553d212002fa6d1047 100644 (file)
@@ -266,8 +266,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
        /*
         * We have to relocate the command table manually
         */
-       fixup_cmdtable(&__u_boot_cmd_start,
-               (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+       fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+                       ll_entry_count(cmd_tbl_t, cmd));
 #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
        /* there are some other pointer constants we must deal with */
index 190342062aa8ea3026e34bf4035557d46df0039c..cef19c51ee5fa2d43837106d8f0908b25ed2f69a 100644 (file)
@@ -52,9 +52,11 @@ SECTIONS
        }
 
        . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
index 94bd4c27225d8c8888cf85086edec30c785179cf..b1feb2c0d0fc05558c9cb69a7ad00e3637a5d564 100644 (file)
@@ -44,7 +44,7 @@
 typedef        struct global_data {
        bd_t            *bd;
        unsigned long   flags;
-       unsigned long   baudrate;
+       unsigned int    baudrate;
        unsigned long   have_console;   /* serial_init() was called */
 
        unsigned long   reloc_off;      /* Relocation Offset */
index b533fea7c5b4a448de08b1e07acb17872ced9613..7b8d8e48fb9acd6aeb65333eb5536b27bea51a45 100644 (file)
@@ -39,7 +39,7 @@
 #include <environment.h>
 
 typedef struct bd_info {
-       int             bi_baudrate;    /* serial console baudrate */
+       unsigned int    bi_baudrate;    /* serial console baudrate */
        unsigned long   bi_arch_number; /* unique id for this board */
        unsigned long   bi_boot_params; /* where this board expects params */
        unsigned long   bi_memstart;    /* start of DRAM memory */
index 89900fea4359c960523321d2be6c863cf3b27258..91395cabf35dde2bbbc70c58a910270c1e407bf3 100644 (file)
@@ -320,8 +320,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
        /*
         * We have to relocate the command table manually
         */
-       fixup_cmdtable(&__u_boot_cmd_start,
-               (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+       fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+                       ll_entry_count(cmd_tbl_t, cmd));
 #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
        serial_initialize();
@@ -396,7 +396,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
        /* Initialize from environment */
        load_addr = getenv_ulong("loadaddr", 16, load_addr);
 
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
        board_late_init();
 #endif
 
index 4856bd368d249338a535c9fecd518f3aac792975..d0eb80de0e9804d3c84de41c0bc9b496db6ab3aa 100644 (file)
@@ -45,13 +45,11 @@ SECTIONS
         * the initialization code relocates the command table as
         * well -- admittedly, this is just pure laziness ;-)
         */
-       __u_boot_cmd_start = .;
-       .u_boot_cmd :
-       {
-         *(.u_boot_cmd)
-       }
+
        . = ALIGN(4);
-       __u_boot_cmd_end = .;
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        /* INIT DATA sections - "Small" data (see the gcc -G option)
         * is always gp-relative. Here we make all init data sections
index 3b0d9e629417017d7976949a7a4ee73797f9033b..413b485b61bc72af1a85c2091774a6e158313dd4 100644 (file)
@@ -26,7 +26,7 @@
 typedef        struct  global_data {
        bd_t            *bd;
        unsigned long   flags;
-       unsigned long   baudrate;
+       unsigned int    baudrate;
        unsigned long   cpu_clk;        /* CPU clock in Hz!             */
        unsigned long   have_console;   /* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
diff --git