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raw | patch | inline | side by side (from parent 1: 3fcdd4a)
raw | patch | inline | side by side (from parent 1: 3fcdd4a)
| author | Lokesh Vutla <lokeshvutla@ti.com> | |
| Mon, 4 Feb 2013 04:22:03 +0000 (04:22 +0000) | ||
| committer | Tom Rini <trini@ti.com> | |
| Mon, 11 Mar 2013 15:06:10 +0000 (11:06 -0400) |
Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.
These change reduces code addition for future Socs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.
These change reduces code addition for future Socs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index bb37cf314a3e561f272ac900a5ae6e2c9b310987..0683b9f74de25d3ac5110653e8652422f6c2c056 100644 (file)
static void do_lpddr2_init(u32 base, u32 cs)
{
u32 mr_addr;
+ const struct lpddr2_mr_regs *mr_regs;
+ get_lpddr2_mr_regs(&mr_regs);
/* Wait till device auto initialization is complete */
while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
;
- set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+ set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
/*
* tZQINIT = 1 us
* Enough loops assuming a maximum of 2GHz
sdelay(2000);
- if (omap_revision() >= OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
- else
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
-
- set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+ set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
+ set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
/*
* Enable refresh along with writing MR2
* Encoding of RL in MR2 is (RL - 2)
*/
mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
- set_mr(base, cs, mr_addr, RL_FINAL - 2);
+ set_mr(base, cs, mr_addr, mr_regs->mr2);
- if (omap_revision() >= OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR3, 0x1);
+ if (mr_regs->mr3 > 0)
+ set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
}
static void lpddr2_init(u32 base, const struct emif_regs *regs)
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- u32 i = 0;
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
- ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
- /*
- * external phy 6-24 registers do not change with
- * ddr frequency
- */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- }
+ do_ext_phy_settings(base, regs);
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 omap_rev = omap_revision();
- if (omap_rev == OMAP5430_ES1_0)
- return;
-
/* reset phy on ES2.0 */
if (omap_rev == OMAP4430_ES2_0)
emif_reset_phy(base);
index b9128faa5675c78cf2b26294e3e5d0c417adb0f9..01da790e3bb27580f02c5158ca72047950102592 100644 (file)
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
-/* Dummy registers for OMAP44xx */
-const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
__attribute__((weak, alias("emif_get_device_timings_sdp")));
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+
+const struct lpddr2_mr_regs mr_regs = {
+ .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
+ .mr2 = 0x4,
+ .mr3 = -1,
+ .mr10 = MR10_ZQ_ZQINIT,
+ .mr16 = MR16_REF_FULL_ARRAY
+};
+
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
+{
+ *regs = &mr_regs;
+}
index 6ebdf5fbfd04d904d17acd2606cb7c03e5e0f931..687800facc2d91eac41ac6199326fe3afb14beab 100644 (file)
.dmm_lisa_map_3 = 0xFF020100
};
+static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
+{
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ *regs = &emif_regs_532_mhz_2cs;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = &emif_regs_ddr3_532_mhz_1cs;
+ break;
+ default:
+ *regs = &emif_regs_ddr3_532_mhz_1cs;
+ }
+}
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+ __attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+ **dmm_lisa_regs)
+{
+ *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+ __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+#else
+
+static const struct lpddr2_device_details dev_4G_S4_details = {
+ .type = LPDDR2_TYPE_S4,
+ .density = LPDDR2_DENSITY_4Gb,
+ .io_width = LPDDR2_IO_WIDTH_32,
+ .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
+};
+
+static void emif_get_device_details_sdp(u32 emif_nr,
+ struct lpddr2_device_details *cs0_device_details,
+ struct lpddr2_device_details *cs1_device_details)
+{
+ /* EMIF1 & EMIF2 have identical configuration */
+ *cs0_device_details = dev_4G_S4_details;
+ *cs1_device_details = dev_4G_S4_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+ struct lpddr2_device_details *cs0_device_details,
+ struct lpddr2_device_details *cs1_device_details)
+ __attribute__((weak, alias("emif_get_device_details_sdp")));
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
0x00000077
};
-const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
0x04010040,
0x00000057
};
-static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
-{
- if (omap_revision() == OMAP5432_ES1_0)
- *regs = &emif_regs_ddr3_532_mhz_1cs;
- else
- *regs = &emif_regs_532_mhz_2cs;
-}
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
- __attribute__((weak, alias("emif_get_reg_dump_sdp")));
+const struct lpddr2_mr_regs mr_regs = {
+ .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
+ .mr2 = 0x6,
+ .mr3 = 0x1,
+ .mr10 = MR10_ZQ_ZQINIT,
+ .mr16 = MR16_REF_FULL_ARRAY
+};
-static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
- **dmm_lisa_regs)
+static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
{
- *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ *regs = ext_phy_ctrl_const_base;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = ddr3_ext_phy_ctrl_const_base_es1;
+ break;
+ default:
+ *regs = ddr3_ext_phy_ctrl_const_base_es1;
+ }
}
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
- __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
-
-#else
-
-static const struct lpddr2_device_details dev_4G_S4_details = {
- .type = LPDDR2_TYPE_S4,
- .density = LPDDR2_DENSITY_4Gb,
- .io_width = LPDDR2_IO_WIDTH_32,
- .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
-};
-
-static void emif_get_device_details_sdp(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
{
- /* EMIF1 & EMIF2 have identical configuration */
- *cs0_device_details = dev_4G_S4_details;
- *cs1_device_details = dev_4G_S4_details;
+ *regs = &mr_regs;
}
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
- __attribute__((weak, alias("emif_get_device_details_sdp")));
-
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
-
void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
+ const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
* external phy 6-24 registers do not change with
* ddr frequency
*/
+ emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
+ writel(ext_phy_ctrl_const_regs[i],
+ emif_ext_phy_ctrl_base++);
/* Update shadow registers */
- writel(ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
+ writel(ext_phy_ctrl_const_regs[i],
+ emif_ext_phy_ctrl_base++);
}
}
index 0824a80d06b8a8b061d4990615ee4311e5255154..fd530bb26a089cafd14f2cdfb02df6461e72c533 100644 (file)
u32 dmm_lisa_map_3;
};
-extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-
#define CS0 0
#define CS1 1
/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
u32 emif_rd_wr_exec_thresh;
};
+struct lpddr2_mr_regs {
+ s8 mr1;
+ s8 mr2;
+ s8 mr3;
+ s8 mr10;
+ s8 mr16;
+};
+
/* assert macros */
#if defined(DEBUG)
#define emif_assert(c) ({ if (!(c)) for (;;); })
#endif
void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern u32 *const T_num;