summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 7fd5b9b)
raw | patch | inline | side by side (parent: 7fd5b9b)
author | SRICHARAN R <r.sricharan@ti.com> | |
Thu, 24 May 2012 00:30:25 +0000 (00:30 +0000) | ||
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | |
Sat, 7 Jul 2012 12:07:24 +0000 (14:07 +0200) |
To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.
Correcting the above settings here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.
Correcting the above settings here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
arch/arm/include/asm/arch-omap4/omap.h | patch | blob | history |
index 47c5883025ce818b8865e92d9c577edb8a85d3fa..03bd9231450a8047d38ba73caf9d0441ef5fb9b3 100644 (file)
#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
#define LPDDR2IO_GR10_WD_MASK (3 << 17)
-#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
+#define CONTROL_LPDDR2IO_3_VAL 0xA0888C0F
/* CONTROL_EFUSE_2 */
#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000