OMAP5: Configure the io settings for omap5432 uevm board
authorLokesh Vutla <lokeshvutla@ti.com>
Tue, 22 May 2012 00:03:23 +0000 (00:03 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 7 Jul 2012 12:07:23 +0000 (14:07 +0200)
This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/include/asm/arch-omap5/omap.h

index e2f76a1bbde962396b8780b34adae35570eeb141..df0b76050db28cfadf9ba5923152177411852f5a 100644 (file)
@@ -52,6 +52,81 @@ static struct gpio_bank gpio_bank_54xx[6] = {
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
 
 #ifdef CONFIG_SPL_BUILD
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
 
 #ifdef CONFIG_SPL_BUILD
+/* LPDDR2 specific IO settings */
+static void io_settings_lpddr2(void)
+{
+       struct omap_sys_ctrl_regs *ioregs_base =
+                     (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+                               &(ioregs_base->control_ddrch1_0));
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+                               &(ioregs_base->control_ddrch1_1));
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+                               &(ioregs_base->control_ddrch2_0));
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+                               &(ioregs_base->control_ddrch2_1));
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+                               &(ioregs_base->control_lpddr2ch1_0));
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+                               &(ioregs_base->control_lpddr2ch1_1));
+       writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+                               &(ioregs_base->control_ddrio_0));
+       writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+                               &(ioregs_base->control_ddrio_1));
+       writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+                               &(ioregs_base->control_ddrio_2));
+}
+
+/* DDR3 specific IO settings */
+static void io_settings_ddr3(void)
+{
+       u32 io_settings = 0;
+       struct omap_sys_ctrl_regs *ioregs_base =
+                     (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+       writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddr3ch1_0));
+       writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddrch1_0));
+       writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddrch1_1));
+
+       writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddr3ch2_0));
+       writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddrch2_0));
+       writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddrch2_1));
+
+       writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+                               &(ioregs_base->control_ddrio_0));
+       writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+                               &(ioregs_base->control_ddrio_1));
+       writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+                               &(ioregs_base->control_ddrio_2));
+
+       /* omap5432 does not use lpddr2 */
+       writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
+       writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
+
+       writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+                       &(ioregs_base->control_emif1_sdram_config_ext));
+       writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+                       &(ioregs_base->control_emif2_sdram_config_ext));
+
+       /* Disable DLL select */
+       io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
+                                                       & 0xFFEFFFFF);
+       writel(io_settings,
+               &(ioregs_base->control_port_emif1_sdram_config));
+
+       io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
+                                                       & 0xFFEFFFFF);
+       writel(io_settings,
+               &(ioregs_base->control_port_emif2_sdram_config));
+}
+
 /*
  * Some tuning of IOs for optimal power and performance
  */
 /*
  * Some tuning of IOs for optimal power and performance
  */
@@ -115,25 +190,10 @@ void do_io_settings(void)
                       (sc_fast << 17) | (sc_fast << 14);
        writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
 
                       (sc_fast << 17) | (sc_fast << 14);
        writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
 
-       /* LPDDR2 io settings */
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-                                       &(ioregs_base->control_ddrch1_0));
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-                                       &(ioregs_base->control_ddrch1_1));
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-                                       &(ioregs_base->control_ddrch2_0));
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-                                       &(ioregs_base->control_ddrch2_1));
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
-                                       &(ioregs_base->control_lpddr2ch1_0));
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
-                                       &(ioregs_base->control_lpddr2ch1_1));
-       writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
-                                       &(ioregs_base->control_ddrio_0));
-       writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
-                                       &(ioregs_base->control_ddrio_1));
-       writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
-                                       &(ioregs_base->control_ddrio_2));
+       if (omap_revision() <= OMAP5430_ES1_0)
+               io_settings_lpddr2();
+       else
+               io_settings_ddr3();
 
        /* Efuse settings */
        writel(EFUSE_1, &(ioregs_base->control_efuse_1));
 
        /* Efuse settings */
        writel(EFUSE_1, &(ioregs_base->control_efuse_1));
index 94b6f3a89bda3ae15c99d4ccaaceb3280a9c1e35..7f05cb5b4a782314a74bf73fd10403f01c647a44 100644 (file)
@@ -179,7 +179,14 @@ struct omap_sys_ctrl_regs {
        u32 control_srcomp_east_side; /*0x4A002E7C*/
        u32 control_srcomp_west_side; /*0x4A002E80*/
        u32 control_srcomp_code_latch; /*0x4A002E84*/
        u32 control_srcomp_east_side; /*0x4A002E7C*/
        u32 control_srcomp_west_side; /*0x4A002E80*/
        u32 control_srcomp_code_latch; /*0x4A002E84*/
-       u32 pad4[3680198];
+       u32 pad4[3679394];
+       u32 control_port_emif1_sdram_config;            /*0x4AE0C110*/
+       u32 control_port_emif1_lpddr2_nvm_config;       /*0x4AE0C114*/
+       u32 control_port_emif2_sdram_config;            /*0x4AE0C118*/
+       u32 pad5[10];
+       u32 control_emif1_sdram_config_ext;             /* 0x4AE0C144 */
+       u32 control_emif2_sdram_config_ext;             /* 0x4AE0C148 */
+       u32 pad6[789];
        u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
        u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
        u32 control_padconf_mode; /* 0x4AE0CDA8 */
        u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
        u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
        u32 control_padconf_mode; /* 0x4AE0CDA8 */
@@ -234,6 +241,12 @@ struct omap_sys_ctrl_regs {
 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
 
 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
 
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL    0x7C7C7C6C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL       0x64646464
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE                         0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE                         0xBC6318DC
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE                         0x0
+
 #define EFUSE_1 0x45145100
 #define EFUSE_2 0x45145100
 #define EFUSE_3 0x45145100
 #define EFUSE_1 0x45145100
 #define EFUSE_2 0x45145100
 #define EFUSE_3 0x45145100