Merge remote-tracking branch 'u-boot-imx/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 27 Oct 2012 09:43:17 +0000 (11:43 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 27 Oct 2012 09:43:17 +0000 (11:43 +0200)
663 files changed:
.gitignore
CREDITS
MAINTAINERS
Makefile
README
arch/arm/cpu/arm1176/tnetv107x/Makefile
arch/arm/cpu/arm720t/cpu.c
arch/arm/cpu/arm720t/interrupts.c
arch/arm/cpu/arm720t/lpc2292/flash.c [deleted file]
arch/arm/cpu/arm720t/lpc2292/iap_entry.S [deleted file]
arch/arm/cpu/arm720t/lpc2292/mmc.c [deleted file]
arch/arm/cpu/arm720t/lpc2292/mmc_hw.c [deleted file]
arch/arm/cpu/arm720t/lpc2292/mmc_hw.h [deleted file]
arch/arm/cpu/arm720t/lpc2292/spi.c [deleted file]
arch/arm/cpu/arm720t/s3c4510b/cache.c [deleted file]
arch/arm/cpu/arm720t/start.S
arch/arm/cpu/arm920t/ep93xx/u-boot.lds
arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
arch/arm/cpu/arm920t/s3c24x0/Makefile
arch/arm/cpu/arm920t/s3c24x0/usb.c [deleted file]
arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
arch/arm/cpu/armv7/am33xx/Makefile
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock.c
arch/arm/cpu/armv7/am33xx/config.mk
arch/arm/cpu/armv7/am33xx/emif4.c
arch/arm/cpu/armv7/am33xx/mux.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
arch/arm/cpu/ixp/u-boot.lds
arch/arm/cpu/lh7a40x/speed.c [deleted file]
arch/arm/cpu/lh7a40x/start.S [deleted file]
arch/arm/cpu/lh7a40x/timer.c [deleted file]
arch/arm/cpu/u-boot.lds
arch/arm/imx-common/cmd_bmode.c
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/ddr_defs.h
arch/arm/include/asm/arch-am33xx/hardware.h
arch/arm/include/asm/arch-am33xx/mux.h [new file with mode: 0644]
arch/arm/include/asm/arch-am33xx/spl.h
arch/arm/include/asm/arch-am33xx/sys_proto.h
arch/arm/include/asm/arch-arm720t/hardware.h
arch/arm/include/asm/arch-arm720t/netarm_dma_module.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_eni_module.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_eth_module.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_gen_module.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_mem_module.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_registers.h [deleted file]
arch/arm/include/asm/arch-arm720t/netarm_ser_module.h [deleted file]
arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h [deleted file]
arch/arm/include/asm/arch-lpc2292/spi.h [deleted file]
arch/arm/include/asm/arch-omap3/dss.h
arch/arm/include/asm/arch-s3c4510b/hardware.h [deleted file]
arch/arm/include/asm/global_data.h
arch/arm/include/asm/u-boot.h
arch/arm/lib/board.c
arch/avr32/cpu/u-boot.lds
arch/avr32/include/asm/global_data.h
arch/avr32/include/asm/u-boot.h
arch/avr32/lib/board.c
arch/blackfin/cpu/u-boot.lds
arch/blackfin/include/asm/global_data.h
arch/blackfin/include/asm/u-boot.h
arch/blackfin/lib/board.c
arch/m68k/cpu/mcf5227x/cpu_init.c
arch/m68k/cpu/mcf5227x/start.S
arch/m68k/cpu/mcf523x/start.S
arch/m68k/cpu/mcf52x2/start.S
arch/m68k/cpu/mcf532x/start.S
arch/m68k/cpu/mcf5445x/config.mk
arch/m68k/cpu/mcf5445x/cpu.c
arch/m68k/cpu/mcf5445x/cpu_init.c
arch/m68k/cpu/mcf5445x/speed.c
arch/m68k/cpu/mcf5445x/start.S
arch/m68k/cpu/mcf547x_8x/start.S
arch/m68k/include/asm/cache.h
arch/m68k/include/asm/global_data.h
arch/m68k/include/asm/immap.h
arch/m68k/include/asm/immap_5441x.h [new file with mode: 0644]
arch/m68k/include/asm/m5441x.h [new file with mode: 0644]
arch/m68k/include/asm/u-boot.h
arch/m68k/lib/board.c
arch/microblaze/cpu/u-boot.lds
arch/microblaze/include/asm/global_data.h
arch/microblaze/include/asm/u-boot.h
arch/mips/cpu/mips32/au1x00/Makefile
arch/mips/cpu/mips32/au1x00/au1x00_ide.c [moved from board/bmw/m48t59y.h with 59% similarity]
arch/mips/cpu/mips32/au1x00/au1x00_serial.c
arch/mips/cpu/mips32/cache.S
arch/mips/cpu/mips32/cpu.c
arch/mips/cpu/mips32/incaip/asc_serial.c
arch/mips/cpu/mips64/Makefile [moved from arch/arm/cpu/lh7a40x/Makefile with 83% similarity]
arch/mips/cpu/mips64/cache.S [new file with mode: 0644]
arch/mips/cpu/mips64/config.mk [moved from arch/arm/cpu/lh7a40x/config.mk with 60% similarity]
arch/mips/cpu/mips64/cpu.c [new file with mode: 0644]
arch/mips/cpu/mips64/interrupts.c [moved from drivers/net/netarm_eth.h with 52% similarity]
arch/mips/cpu/mips64/start.S [new file with mode: 0644]
arch/mips/cpu/mips64/time.c [new file with mode: 0644]
arch/mips/cpu/xburst/cpu.c
arch/mips/cpu/xburst/jz_serial.c
arch/mips/cpu/xburst/start.S
arch/mips/include/asm/addrspace.h
arch/mips/include/asm/asm.h
arch/mips/include/asm/cacheops.h
arch/mips/include/asm/global_data.h
arch/mips/include/asm/io.h
arch/mips/include/asm/posix_types.h
arch/mips/include/asm/u-boot.h
arch/mips/lib/board.c
arch/nds32/cpu/n1213/u-boot.lds
arch/nds32/include/asm/global_data.h
arch/nds32/include/asm/u-boot.h
arch/nds32/lib/board.c
arch/nios2/cpu/u-boot.lds
arch/nios2/include/asm/global_data.h
arch/nios2/include/asm/u-boot.h
arch/openrisc/include/asm/global_data.h
arch/openrisc/include/asm/u-boot.h
arch/powerpc/cpu/74xx_7xx/u-boot.lds
arch/powerpc/cpu/mpc512x/u-boot.lds
arch/powerpc/cpu/mpc5xx/serial.c
arch/powerpc/cpu/mpc5xx/u-boot.lds
arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
arch/powerpc/cpu/mpc5xxx/u-boot.lds
arch/powerpc/cpu/mpc8220/u-boot.lds
arch/powerpc/cpu/mpc8220/uart.c
arch/powerpc/cpu/mpc824x/cpu_init.c
arch/powerpc/cpu/mpc824x/start.S
arch/powerpc/cpu/mpc824x/u-boot.lds
arch/powerpc/cpu/mpc8260/serial_scc.c
arch/powerpc/cpu/mpc8260/serial_smc.c
arch/powerpc/cpu/mpc8260/u-boot.lds
arch/powerpc/cpu/mpc83xx/cpu.c
arch/powerpc/cpu/mpc83xx/cpu_init.c
arch/powerpc/cpu/mpc83xx/speed.c
arch/powerpc/cpu/mpc83xx/u-boot.lds
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/b4860_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/b4860_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
arch/powerpc/cpu/mpc85xx/liodn.c
arch/powerpc/cpu/mpc85xx/mp.c
arch/powerpc/cpu/mpc85xx/mp.h
arch/powerpc/cpu/mpc85xx/p5040_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/p5040_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/portals.c
arch/powerpc/cpu/mpc85xx/release.S
arch/powerpc/cpu/mpc85xx/serial_scc.c
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc85xx/t4240_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/t4240_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/tlb.c
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
arch/powerpc/cpu/mpc85xx/u-boot.lds
arch/powerpc/cpu/mpc86xx/fdt.c
arch/powerpc/cpu/mpc86xx/mp.c
arch/powerpc/cpu/mpc86xx/u-boot.lds
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
arch/powerpc/cpu/mpc8xxx/ddr/main.c
arch/powerpc/cpu/mpc8xxx/ddr/options.c
arch/powerpc/cpu/mpc8xxx/ddr/util.c
arch/powerpc/cpu/mpc8xxx/fdt.c
arch/powerpc/cpu/mpc8xxx/srio.c
arch/powerpc/cpu/ppc4xx/u-boot.lds
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_ddr_sdram.h
arch/powerpc/include/asm/fsl_fman.h
arch/powerpc/include/asm/fsl_liodn.h
arch/powerpc/include/asm/fsl_memac.h [new file with mode: 0644]
arch/powerpc/include/asm/fsl_portals.h
arch/powerpc/include/asm/fsl_serdes.h
arch/powerpc/include/asm/global_data.h
arch/powerpc/include/asm/immap_83xx.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/immap_qe.h
arch/powerpc/include/asm/mp.h
arch/powerpc/include/asm/mpc85xx_gpio.h
arch/powerpc/include/asm/processor.h
arch/powerpc/include/asm/u-boot.h
arch/powerpc/lib/Makefile
arch/powerpc/lib/board.c
arch/powerpc/lib/ide.c [new file with mode: 0644]
arch/powerpc/lib/ide.h [moved from arch/arm/include/asm/arch-lpc2292/hardware.h with 71% similarity]
arch/sandbox/cpu/u-boot.lds
arch/sandbox/include/asm/global_data.h
arch/sh/cpu/sh2/u-boot.lds
arch/sh/cpu/sh3/u-boot.lds
arch/sh/cpu/sh4/u-boot.lds
arch/sh/include/asm/global_data.h
arch/sh/include/asm/u-boot.h
arch/sparc/cpu/leon2/serial.c
arch/sparc/cpu/leon3/serial.c
arch/sparc/include/asm/global_data.h
arch/sparc/include/asm/u-boot.h
arch/sparc/lib/board.c
arch/x86/cpu/u-boot.lds
arch/x86/include/asm/global_data.h
board/BuS/eb_cpu5282/u-boot.lds
board/LEOX/elpt860/u-boot.lds
board/Marvell/common/serial.c
board/RPXClassic/u-boot.lds
board/RPXClassic/u-boot.lds.debug
board/RPXlite/u-boot.lds
board/RPXlite/u-boot.lds.debug
board/RPXlite_dw/u-boot.lds
board/RPXlite_dw/u-boot.lds.debug
board/RRvision/u-boot.lds
board/actux1/u-boot.lds
board/actux2/u-boot.lds
board/actux3/u-boot.lds
board/adder/u-boot.lds
board/ait/cam_enc_4xx/u-boot-spl.lds
board/altera/nios2-generic/u-boot.lds
board/amcc/acadia/u-boot-nand.lds
board/amcc/bamboo/u-boot-nand.lds
board/amcc/canyonlands/u-boot-nand.lds
board/amcc/kilauea/u-boot-nand.lds
board/amcc/sequoia/u-boot-nand.lds
board/amcc/sequoia/u-boot-ram.lds
board/astro/mcf5373l/u-boot.lds
board/atmel/at91sam9x5ek/at91sam9x5ek.c
board/bmw/Makefile [deleted file]
board/bmw/README [deleted file]
board/bmw/bmw.c [deleted file]
board/bmw/bmw.h [deleted file]
board/bmw/early_init.S [deleted file]
board/bmw/flash.c [deleted file]
board/bmw/m48t59y.c [deleted file]
board/bmw/ns16550.c [deleted file]
board/bmw/ns16550.h [deleted file]
board/bmw/serial.c [deleted file]
board/c2mon/u-boot.lds
board/c2mon/u-boot.lds.debug
board/cobra5272/u-boot.lds
board/cogent/serial.c
board/cogent/u-boot.lds
board/cogent/u-boot.lds.debug
board/cpc45/Makefile
board/cpc45/cpc45.c
board/cpc45/ide.c [new file with mode: 0644]
board/cray/L1/u-boot.lds.debug
board/dave/PPChameleonEVB/u-boot.lds
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
board/davinci/da8xxevm/u-boot-spl-hawk.lds
board/dbau1x00/u-boot.lds
board/dvlhost/u-boot.lds
board/eltec/mhpc/u-boot.lds
board/eltec/mhpc/u-boot.lds.debug
board/emk/top860/u-boot.lds
board/ep88x/u-boot.lds
board/esd/cpci750/ide.c
board/esd/cpci750/serial.c
board/esd/dasa_sim/u-boot.lds
board/esd/pmc440/u-boot-nand.lds
board/esd/tasreg/u-boot.lds
board/esteem192e/u-boot.lds
board/etx094/u-boot.lds
board/evb64260/serial.c
board/evb64260/u-boot.lds
board/fads/u-boot.lds
board/flagadm/u-boot.lds
board/flagadm/u-boot.lds.debug
board/freescale/common/Makefile
board/freescale/common/qixis.c
board/freescale/common/qixis.h
board/freescale/common/vsc3316_3308.c [new file with mode: 0644]
board/freescale/common/vsc3316_3308.h [new file with mode: 0644]
board/freescale/m5208evbe/u-boot.lds
board/freescale/m52277evb/u-boot.lds
board/freescale/m5235evb/u-boot.lds
board/freescale/m5249evb/u-boot.lds
board/freescale/m5253demo/u-boot.lds
board/freescale/m5253evbe/u-boot.lds
board/freescale/m5271evb/u-boot.lds
board/freescale/m5272c3/u-boot.lds
board/freescale/m5275evb/u-boot.lds
board/freescale/m5282evb/u-boot.lds
board/freescale/m53017evb/u-boot.lds
board/freescale/m5329evb/u-boot.lds
board/freescale/m5373evb/u-boot.lds
board/freescale/m54418twr/Makefile [moved from board/sx1/Makefile with 85% similarity]
board/freescale/m54418twr/config.mk [moved from board/bmw/config.mk with 73% similarity]
board/freescale/m54418twr/m54418twr.c [new file with mode: 0644]
board/freescale/m54418twr/u-boot.lds [new file with mode: 0644]
board/freescale/m54451evb/u-boot.lds
board/freescale/m54455evb/u-boot.lds
board/freescale/m547xevb/u-boot.lds
board/freescale/m548xevb/u-boot.lds
board/freescale/mx31ads/u-boot.lds
board/freescale/t4qds/Makefile [moved from board/sbc8560/Makefile with 81% similarity]
board/freescale/t4qds/ddr.c [new file with mode: 0644]
board/freescale/t4qds/eth.c [new file with mode: 0644]
board/freescale/t4qds/law.c [new file with mode: 0644]
board/freescale/t4qds/pci.c [moved from arch/arm/cpu/lh7a40x/cpu.c with 54% similarity]
board/freescale/t4qds/t4240qds_qixis.h [new file with mode: 0644]
board/freescale/t4qds/t4qds.c [new file with mode: 0644]
board/freescale/t4qds/t4qds.h [new file with mode: 0644]
board/freescale/t4qds/tlb.c [new file with mode: 0644]
board/gaisler/gr_cpci_ax2000/u-boot.lds
board/gaisler/gr_ep2s60/u-boot.lds
board/gaisler/gr_xc3s_1500/u-boot.lds
board/gaisler/grsim/u-boot.lds
board/gaisler/grsim_leon2/u-boot.lds
board/gen860t/u-boot-flashenv.lds
board/gen860t/u-boot.lds
board/genietv/u-boot.lds
board/genietv/u-boot.lds.debug
board/h2200/Makefile [moved from arch/arm/cpu/arm720t/lpc2292/Makefile with 68% similarity]
board/h2200/h2200-header.S [new file with mode: 0644]
board/h2200/h2200.c [new file with mode: 0644]
board/hermes/u-boot.lds
board/hermes/u-boot.lds.debug
board/htkw/mcx/mcx.c
board/htkw/mcx/mcx.h
board/hymod/u-boot.lds
board/hymod/u-boot.lds.debug
board/icu862/u-boot.lds
board/icu862/u-boot.lds.debug
board/idmr/u-boot.lds
board/incaip/u-boot.lds
board/ip860/u-boot.lds
board/ip860/u-boot.lds.debug
board/ivm/ivm.c
board/ivm/u-boot.lds
board/ivm/u-boot.lds.debug
board/keymile/km83xx/km83xx.c
board/kmc/kzm9g/kzm9g.c
board/korat/u-boot-F7FC.lds
board/kup/kup4k/u-boot.lds
board/kup/kup4k/u-boot.lds.debug
board/kup/kup4x/u-boot.lds
board/kup/kup4x/u-boot.lds.debug
board/lantec/u-boot.lds
board/lantec/u-boot.lds.debug
board/linkstation/ide.c
board/lubbock/lubbock.c
board/lwmon/u-boot.lds
board/lwmon/u-boot.lds.debug
board/manroland/uc100/u-boot.lds
board/matrix_vision/mvsmr/u-boot.lds
board/mbx8xx/u-boot.lds
board/mbx8xx/u-boot.lds.debug
board/micronas/vct/u-boot.lds
board/mousse/u-boot.lds
board/mousse/u-boot.lds.ram
board/mousse/u-boot.lds.rom
board/mpl/pip405/u-boot.lds.debug
board/mvblue/u-boot.lds
board/netphone/u-boot.lds
board/netphone/u-boot.lds.debug
board/netta/u-boot.lds
board/netta/u-boot.lds.debug
board/netta2/u-boot.lds
board/netta2/u-boot.lds.debug
board/netvia/u-boot.lds
board/netvia/u-boot.lds.debug
board/nx823/u-boot.lds
board/nx823/u-boot.lds.debug
board/openrisc/openrisc-generic/u-boot.lds
board/palmtc/palmtc.c
board/pb1x00/u-boot.lds
board/pcippc2/fpga_serial.c
board/pcippc2/fpga_serial.h
board/pcippc2/pcippc2.c
board/pcs440ep/pcs440ep.c
board/prodrive/p3mx/serial.c
board/pxa255_idp/pxa_idp.c
board/qemu-mips/config.mk [deleted file]
board/qemu-mips/u-boot.lds
board/qi/qi_lb60/u-boot.lds
board/quantum/u-boot.lds
board/r360mpi/u-boot.lds
board/rbc823/u-boot.lds
board/renesas/sh7757lcr/u-boot.lds
board/rsdproto/u-boot.lds
board/samsung/origen/lowlevel_init.S
board/samsung/origen/origen_setup.h
board/samsung/smdk5250/smdk5250-uboot-spl.lds
board/samsung/smdk6400/u-boot-nand.lds
board/sandburst/karef/u-boot.lds.debug
board/sandburst/metrobox/u-boot.lds.debug
board/sandpoint/u-boot.lds
board/sbc8560/README [deleted file]
board/sbc8560/ddr.c [deleted file]
board/sbc8560/law.c [deleted file]
board/sbc8560/sbc8560.c [deleted file]
board/sbc8560/tlb.c [deleted file]
board/siemens/IAD210/u-boot.lds
board/sixnet/u-boot.lds
board/snmc/qs850/u-boot.lds
board/snmc/qs860t/u-boot.lds
board/spc1920/u-boot.lds
board/spd8xx/u-boot.lds
board/spd8xx/u-boot.lds.debug
board/stx/stxxtc/u-boot.lds
board/stx/stxxtc/u-boot.lds.debug
board/svm_sc8xx/u-boot.lds
board/sx1/config.mk [deleted file]
board/sx1/lowlevel_init.S [deleted file]
board/sx1/sx1.c [deleted file]
board/teejet/mt_ventoux/mt_ventoux.c
board/ti/am335x/Makefile
board/ti/am335x/board.c [new file with mode: 0644]
board/ti/am335x/board.h [new file with mode: 0644]
board/ti/am335x/mux.c
board/ti/omap2420h4/omap2420h4.c
board/tqc/tqm8xx/u-boot.lds
board/trizepsiv/conxs.c
board/v37/u-boot.lds
board/vpac270/u-boot-spl.lds
board/w7o/u-boot.lds.debug
board/westel/amx860/u-boot.lds
board/westel/amx860/u-boot.lds.debug
board/xes/xpedite1000/u-boot.lds.debug
boards.cfg
common/Makefile
common/bouncebuf.c [new file with mode: 0644]
common/cmd_bdinfo.c
common/cmd_cbfs.c [new file with mode: 0644]
common/cmd_fdt.c
common/cmd_help.c
common/cmd_i2c.c
common/cmd_ide.c
common/command.c
common/env_common.c
common/env_embedded.c
common/image.c
common/usb.c
common/usb_storage.c
config.mk
disk/part.c
disk/part_dos.c
disk/part_efi.c
disk/part_efi.h
doc/DocBook/Makefile
doc/DocBook/linker_lists.tmpl [new file with mode: 0644]
doc/DocBook/stdio.tmpl [new file with mode: 0644]
doc/README.VSC3316-3308 [new file with mode: 0644]
doc/README.commands
doc/README.fsl-ddr
doc/README.m54418twr [new file with mode: 0644]
doc/README.mpc85xx-spin-table [new file with mode: 0644]
doc/README.scrapyard
doc/README.t4240qds [new file with mode: 0644]
doc/driver-model/UDM-serial.txt
drivers/i2c/sh_i2c.c
drivers/i2c/soft_i2c.c
drivers/input/i8042.c
drivers/input/input.c
drivers/mmc/Makefile
drivers/mmc/dw_mmc.c [new file with mode: 0644]
drivers/mmc/gen_atmel_mci.c
drivers/mmc/mmc.c
drivers/mmc/mmc_spi.c
drivers/mmc/mxsmmc.c
drivers/mmc/pxa_mmc.c [deleted file]
drivers/mmc/s5p_sdhci.c
drivers/mmc/sdhci.c
drivers/net/Makefile
drivers/net/fm/Makefile
drivers/net/fm/eth.c
drivers/net/fm/init.c
drivers/net/fm/memac.c [new file with mode: 0644]
drivers/net/fm/memac_phy.c [new file with mode: 0644]
drivers/net/fm/t4240.c [new file with mode: 0644]
drivers/net/mcfmii.c
drivers/net/netarm_eth.c [deleted file]
drivers/pci/fsl_pci_init.c
drivers/qe/qe.c
drivers/serial/Makefile
drivers/serial/altera_jtag_uart.c
drivers/serial/altera_uart.c
drivers/serial/atmel_usart.c
drivers/serial/lpc32xx_hsuart.c
drivers/serial/mcfuart.c
drivers/serial/ns9750_serial.c
drivers/serial/opencores_yanu.c
drivers/serial/s3c4510b_uart.c [deleted file]
drivers/serial/s3c4510b_uart.h [deleted file]
drivers/serial/s3c64xx.c
drivers/serial/serial.c
drivers/serial/serial_clps7111.c [deleted file]
drivers/serial/serial_imx.c
drivers/serial/serial_ixp.c
drivers/serial/serial_ks8695.c
drivers/serial/serial_lh7a40x.c [deleted file]
drivers/serial/serial_lpc2292.c [deleted file]
drivers/serial/serial_mxc.c
drivers/serial/serial_netarm.c [deleted file]
drivers/serial/serial_pl01x.c
drivers/serial/serial_s3c44b0.c
drivers/serial/serial_sa1100.c
drivers/serial/serial_sh.c
drivers/spi/fsl_espi.c
drivers/spi/omap3_spi.c
drivers/usb/gadget/gadget_chips.h
drivers/usb/host/Makefile
drivers/usb/host/ehci-fsl.c
drivers/usb/host/ohci-s3c24xx.c [moved from arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c with 97% similarity]
drivers/usb/host/ohci-s3c24xx.h [moved from arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h with 100% similarity]
drivers/usb/musb/musb_udc.c
drivers/watchdog/Makefile
drivers/watchdog/tnetv107x_wdt.c [moved from arch/arm/cpu/arm1176/tnetv107x/wdt.c with 100% similarity]
examples/standalone/mips64.lds [new file with mode: 0644]
examples/standalone/sparc.lds
fs/Makefile
fs/cbfs/Makefile [moved from arch/arm/cpu/arm720t/s3c4510b/Makefile with 76% similarity]
fs/cbfs/cbfs.c [new file with mode: 0644]
fs/fat/fat.c
fs/fat/fat_write.c
helper.mk [new file with mode: 0644]
include/atmel_mci.h
include/bouncebuf.h [new file with mode: 0644]
include/cbfs.h [new file with mode: 0644]
include/clps7111.h [deleted file]
include/command.h
include/config_phylib_all_drivers.h
include/configs/BMW.h [deleted file]
include/configs/CPC45.h
include/configs/ICU862.h
include/configs/IVML24.h
include/configs/IVMS8.h
include/configs/KUP4K.h
include/configs/KUP4X.h
include/configs/M54418TWR.h [new file with mode: 0644]
include/configs/MBX.h
include/configs/MPC8308RDB.h
include/configs/NETTA.h
include/configs/NSCU.h
include/configs/P3041DS.h
include/configs/P4080DS.h
include/configs/P5020DS.h
include/configs/R360MPI.h
include/configs/RPXClassic.h
include/configs/RPXlite.h
include/configs/RPXlite_DW.h
include/configs/RRvision.h
include/configs/SBC8540.h [deleted file]
include/configs/SPD823TS.h
include/configs/SX1.h [deleted file]
include/configs/T4240QDS.h [new file with mode: 0644]
include/configs/TK885D.h
include/configs/TQM823L.h
include/configs/TQM823M.h
include/configs/TQM850L.h
include/configs/TQM850M.h
include/configs/TQM855L.h
include/configs/TQM855M.h
include/configs/TQM860L.h
include/configs/TQM860M.h
include/configs/TQM862L.h
include/configs/TQM862M.h
include/configs/TQM866M.h
include/configs/TQM885D.h
include/configs/VCMA9.h
include/configs/am335x_evm.h
include/configs/am3517_crane.h
include/configs/am3517_evm.h
include/configs/apx4devkit.h
include/configs/at91sam9x5ek.h
include/configs/atc.h
include/configs/c2mon.h
include/configs/ca9x4_ct_vxp.h
include/configs/cm_t35.h
include/configs/coreboot.h
include/configs/corenet_ds.h
include/configs/devkit8000.h
include/configs/h2200.h [new file with mode: 0644]
include/configs/igep00x0.h
include/configs/km/km8309-common.h [new file with mode: 0644]
include/configs/km/km8321-common.h
include/configs/km/km83xx-common.h
include/configs/kzm9g.h
include/configs/lubbock.h
include/configs/lwmon.h
include/configs/m28evk.h
include/configs/mcx.h
include/configs/mpc8308_p1m.h
include/configs/mx28evk.h
include/configs/mx51evk.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx53smd.h
include/configs/mx6qarm2.h
include/configs/mx6qsabrelite.h
include/configs/omap3_beagle.h
include/configs/omap3_evm.h
include/configs/omap3_logic.h
include/configs/omap3_overo.h
include/configs/omap3_zoom1.h
include/configs/omap4_common.h
include/configs/omap5_evm.h
include/configs/palmtc.h
include/configs/pxa255_idp.h
include/configs/qemu-mips.h
include/configs/qemu-mips64.h [new file with mode: 0644]
include/configs/quantum.h
include/configs/sbc8560.h [deleted file]
include/configs/smdk2410.h
include/configs/suvd3.h
include/configs/svm_sc8xx.h
include/configs/t4qds.h [new file with mode: 0644]
include/configs/tnetv107x_evm.h
include/configs/tricorder.h
include/configs/trizepsiv.h
include/configs/uc100.h
include/configs/versatile.h
include/configs/virtlab2.h
include/dwmmc.h [new file with mode: 0644]
include/e500.h
include/env_default.h [new file with mode: 0644]
include/flash.h
include/fm_eth.h
include/fsl_mdio.h
include/i8042.h
include/ide.h
include/image.h
include/input.h
include/lh7a400.h [deleted file]
include/lh7a404.h [deleted file]
include/lh7a40x.h [deleted file]
include/libfdt.h
include/linker_lists.h [new file with mode: 0644]
include/lpd7a400_cpld.h [deleted file]
include/mpc83xx.h
include/sdhci.h
include/serial.h
lib/libfdt/Makefile
lib/libfdt/fdt_empty_tree.c [new file with mode: 0644]
lib/libfdt/fdt_rw.c
nand_spl/board/freescale/mpc8536ds/Makefile
nand_spl/board/freescale/mpc8569mds/Makefile
nand_spl/board/freescale/mpc8572ds/Makefile
nand_spl/board/freescale/mx31pdk/Makefile
nand_spl/board/freescale/mx31pdk/u-boot.lds
nand_spl/board/freescale/p1010rdb/Makefile
nand_spl/board/freescale/p1023rds/Makefile
nand_spl/board/freescale/p1_p2_rdb/Makefile
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
nand_spl/board/karo/tx25/Makefile
nand_spl/board/karo/tx25/u-boot.lds
nand_spl/board/samsung/smdk6400/u-boot.lds
spl/.gitignore
spl/Makefile
tools/env/fw_env.c
tools/omapimage.c
tools/patman/gitutil.py
tools/patman/patchstream.py

index d91e91b1e652dcac5a91e5f653e7d08e763e1d1c..1ac43f2825666d93f2f611e86ab2f735777bf83f 100644 (file)
@@ -38,6 +38,7 @@
 /u-boot.sha1
 /u-boot.dis
 /u-boot.lds
+/u-boot.lst
 /u-boot.ubl
 /u-boot.ais
 /u-boot.dtb
diff --git a/CREDITS b/CREDITS
index fa9a14ebdd0f84eecbcf8423a93b3e375f907a1e..7c1458f51df42be7923dbd4ca9104e2f503ff409 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -79,11 +79,6 @@ N: Oliver Brown
 E: obrown@adventnetworks.com
 D: Port to the gw8260 board
 
-N: Curt Brune
-E: curt@cucy.com
-D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
-W: http://www.cucy.com
-
 N: Jonathan De Bruyne
 E: jonathan.debruyne@siemens.atea.be
 D: Port to Siemens IAD210 board
index 971235bbca3558a75822dae8ec53b378865ad9e8..1b2da9421ae824bf5cdbf77113de45974fd228ea 100644 (file)
@@ -214,9 +214,7 @@ Siddarth Gore <gores@marvell.com>
 Paul Gortmaker <paul.gortmaker@windriver.com>
 
        sbc8349         MPC8349
-       sbc8540         MPC8540
        sbc8548         MPC8548
-       sbc8560         MPC8560
        sbc8641d        MPC8641D
 
 Frank Gottschling <fgottschling@eltec.de>
@@ -585,6 +583,10 @@ Stefano Babic <sbabic@denx.de>
        twister         omap3
        vision2         i.MX51
 
+Lukasz Dalek <luk0104@gmail.com>
+
+       h2200           xscale/pxa
+
 Jason Liu <r64343@freescale.com>
 
        mx53evk         i.MX53
index 08eecbbbcdff22746e2febc856c8045f600ec6b6..d385467e8e2b96fb164278be3b8feb89e457990b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -260,7 +260,8 @@ LIBS-y += drivers/net/npe/libnpe.o
 endif
 LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
 LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/cramfs/libcramfs.o \
+LIBS-y += fs/cbfs/libcbfs.o \
+       fs/cramfs/libcramfs.o \
        fs/ext4/libext4fs.o \
        fs/fat/libfat.o \
        fs/fdos/libfdos.o \
@@ -533,9 +534,10 @@ GEN_UBOOT = \
                        $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
 else
 GEN_UBOOT = \
-               UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
-               sed  -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
-               cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__OBJS) \
+               UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+               sed  -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
+               cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+                       $$UNDEF_LST $(__OBJS) \
                        --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
                        -Map u-boot.map -o u-boot
 endif
@@ -568,8 +570,12 @@ $(SUBDIR_EXAMPLES): $(obj)u-boot
 $(LDSCRIPT):   depend
                $(MAKE) -C $(dir $@) $(notdir $@)
 
-$(obj)u-boot.lds: $(LDSCRIPT)
-               $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates u-boot.lst,
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
+$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
+               $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
 
 nand_spl:      $(TIMESTAMP_FILE) $(VERSION_FILE) depend
                $(MAKE) -C nand_spl/board/$(BOARDDIR) all
@@ -748,20 +754,6 @@ $(obj).boards.depend:      boards.cfg
 lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
 ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
 
-#========================================================================
-# ARM
-#========================================================================
-
-SX1_stdout_serial_config \
-SX1_config:            unconfig
-       @mkdir -p $(obj)include
-       @if [ "$(findstring _stdout_serial_, $@)" ] ; then \
-               echo "#undef CONFIG_STDOUT_USBTTY" >> $(obj)include/config.h ; \
-       else \
-               echo "#define CONFIG_STDOUT_USBTTY" >> $(obj)include/config.h ; \
-       fi;
-       @$(MKCONFIG) -n $@ SX1 arm arm925t sx1
-
 #########################################################################
 ## ARM1176 Systems
 #########################################################################
@@ -808,6 +800,7 @@ clean:
               $(obj)board/matrix_vision/*/bootscript.img                 \
               $(obj)board/voiceblue/eeprom                               \
               $(obj)u-boot.lds                                           \
+              $(obj)include/u-boot.lst                                   \
               $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]          \
               $(obj)arch/blackfin/cpu/init.{lds,elf}
        @rm -f $(obj)include/bmp_logo.h
@@ -841,8 +834,10 @@ clobber:   tidy
        @rm -f $(obj)u-boot.dtb
        @rm -f $(obj)u-boot.sb
        @rm -f $(obj)u-boot.spr
-       @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
-       @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
+       @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
+       @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
+       @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
+       @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
        @rm -f $(obj)MLO
        @rm -f $(obj)tools/xway-swap-bytes
        @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
diff --git a/README b/README
index df4aed14e4ed35f6e0d6f7a448b15b0c8240a164..69da2b86ba14219d735fe401af34d46a54ab0433 100644 (file)
--- a/README
+++ b/README
@@ -363,6 +363,12 @@ The following options need to be configured:
                ICache only when Code runs from RAM.
 
 - 85xx CPU Options:
+               CONFIG_SYS_PPC64
+
+               Specifies that the core is a 64-bit PowerPC implementation (implements
+               the "64" category of the Power ISA). This is necessary for ePAPR
+               compliance, among other possible reasons.
+
                CONFIG_SYS_FSL_TBCLK_DIV
 
                Defines the core time base clock divider ratio compared to the
@@ -1084,7 +1090,7 @@ The following options need to be configured:
                CONFIG_CALXEDA_XGMAC
                Support for the Calxeda XGMAC device
 
-               CONFIG_DRIVER_LAN91C96
+               CONFIG_LAN91C96
                Support for SMSC's LAN91C96 chips.
 
                        CONFIG_LAN91C96_BASE
@@ -1094,7 +1100,7 @@ The following options need to be configured:
                        CONFIG_LAN91C96_USE_32_BIT
                        Define this to enable 32 bit addressing
 
-               CONFIG_DRIVER_SMC91111
+               CONFIG_SMC91111
                Support for SMSC's LAN91C111 chip
 
                        CONFIG_SMC91111_BASE
@@ -1316,6 +1322,13 @@ The following options need to be configured:
                This will also enable the command "fatwrite" enabling the
                user to write files to FAT.
 
+CBFS (Coreboot Filesystem) support
+               CONFIG_CMD_CBFS
+
+               Define this to enable support for reading from a Coreboot
+               filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
+               and cbfsload.
+
 - Keyboard Support:
                CONFIG_ISA_KEYBOARD
 
index c63dc925efb725eea21858c7b13217e0da201081..c1d4d678c0cb6d6fa0eea55d5579e8f467a80b69 100644 (file)
@@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(SOC).o
 
-COBJS  += aemif.o clock.o init.o mux.o timer.o wdt.o
+COBJS  += aemif.o clock.o init.o mux.o timer.o
 SOBJS  += lowlevel_init.o
 
 SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
index ce7b3c9c24e1ac45e3f84ba46fc4b447aa726dd5..820614e0ea6da3c63d43c4421fa99af37921949f 100644 (file)
  */
 
 /*
- * CPU specific code
+ * cleanup_before_linux() - Prepare the CPU to jump to Linux
+ *
+ * This function is called just before we call Linux, it
+ * prepares the processor for linux
  */
-
-#include <common.h>
-#include <command.h>
-#include <clps7111.h>
-#include <asm/hardware.h>
-#include <asm/system.h>
-
-int cleanup_before_linux (void)
+int cleanup_before_linux(void)
 {
-       /*
-        * this function is called just before we call linux
-        * it prepares the processor for linux
-        *
-        * we turn off caches etc ...
-        * and we set the CPU-speed to 73 MHz - see start.S for details
-        */
-
-#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
-       disable_interrupts ();
-       /* Nothing more needed */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* No cleanup before linux for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_TEGRA)
-       /* No cleanup before linux for tegra as yet */
-#else
-#error No cleanup_before_linux() defined for this CPU type
-#endif
        return 0;
 }
index c2f898f2cc9bcec6f1da84796551749cd8bb133d..8e763b778845b1c1491f68ebd2e161239ed96072 100644 (file)
  * MA 02111-1307 USA
  */
 
-#include <common.h>
-#include <clps7111.h>
-#include <asm/proc-armv/ptrace.h>
-#include <asm/hardware.h>
-
-#ifndef CONFIG_NETARM
-/* we always count down the max. */
-#define TIMER_LOAD_VAL 0xffff
-/* macro to read the 16 bit timer */
-#define READ_TIMER (IO_TC1D & 0xffff)
-
-#ifdef CONFIG_LPC2292
-#undef READ_TIMER
-#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
-#endif
-
-#else
-#define IRQEN  (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
-#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
-#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
-#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
-#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
-#endif
-
-#ifdef CONFIG_S3C4510B
-/* require interrupts for the S3C4510B */
-# ifndef CONFIG_USE_IRQ
-#  error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
-# else
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-# endif
-#endif /* CONFIG_S3C4510B */
-
 #ifdef CONFIG_USE_IRQ
 void do_irq (struct pt_regs *pt_regs)
 {
-#if defined(CONFIG_S3C4510B)
-       unsigned int pending;
-
-       while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
-               IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
-
-               /* clear pending interrupt */
-               PUT_REG( REG_INTPEND, (1<<(pending>>2)));
-       }
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* No do_irq() for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-
-    void (*pfnct)(void);
-
-    pfnct = (void (*)(void))VICVectAddr;
-
-    (*pfnct)();
-#else
-#error do_irq() not defined for this CPU type
-#endif
-}
-#endif
-
-#ifdef CONFIG_S3C4510B
-static void default_isr( void *data) {
-       printf ("default_isr():  called for IRQ %d\n", (int)data);
-}
-
-static void timer_isr( void *data) {
-       unsigned int *pTime = (unsigned int *)data;
-
-       (*pTime)++;
-       if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
-               /* toggle LED 0 */
-               PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
-       }
-
 }
 #endif
 
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* Use IntegratorAP routines in board/integratorap.c */
-#else
-
+#if defined(CONFIG_TEGRA)
 static ulong timestamp;
 static ulong lastdec;
 
-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
-int arch_interrupt_init (void)
-{
-       int i;
-
-       /* install default interrupt handlers */
-       for ( i = 0; i < N_IRQS; i++) {
-               IRQ_HANDLER[i].m_data = (void *)i;
-               IRQ_HANDLER[i].m_func = default_isr;
-       }
-
-       /* configure interrupts for IRQ mode */
-       PUT_REG( REG_INTMODE, 0x0);
-       /* clear any pending interrupts */
-       PUT_REG( REG_INTPEND, 0x1FFFFF);
-
-       lastdec = 0;
-
-       /* install interrupt handler for timer */
-       IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
-       IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
-
-       return 0;
-}
-#endif
-
 int timer_init (void)
 {
-#if defined(CONFIG_NETARM)
-       /* disable all interrupts */
-       IRQEN = 0;
-
-       /* operate timer 2 in non-prescale mode */
-       TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
-                   NETARM_GEN_TCTL_ENABLE |
-                   NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
-
-       /* set timer 2 counter */
-       lastdec = TIMER_LOAD_VAL;
-#elif defined(CONFIG_S3C4510B)
-       /* configure free running timer 0 */
-       PUT_REG( REG_TMOD, 0x0);
-       /* Stop timer 0 */
-       CLR_REG( REG_TMOD, TM0_RUN);
-
-       /* Configure for interval mode */
-       CLR_REG( REG_TMOD, TM1_TOGGLE);
-
-       /*
-        * Load Timer data register with count down value.
-        * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
-        */
-       PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
-
-       /*
-        * Enable global interrupt
-        * Enable timer0 interrupt
-        */
-       CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
-
-       /* Start timer */
-       SET_REG( REG_TMOD, TM0_RUN);
-#elif defined(CONFIG_LPC2292)
-       PUT32(T0IR, 0);         /* disable all timer0 interrupts */
-       PUT32(T0TCR, 0);        /* disable timer0 */
-       PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
-       PUT32(T0MCR, 0);
-       PUT32(T0TC, 0);
-       PUT32(T0TCR, 1);        /* enable timer0 */
-
-#elif defined(CONFIG_TEGRA)
        /* No timer routines for tegra as yet */
        lastdec = 0;
-#else
-#error No timer_init() defined for this CPU type
-#endif
        timestamp = 0;
 
-       return (0);
-}
-
-#endif /* ! IntegratorAP */
-
-/*
- * timer without interrupts
- */
-
-
-#if defined(CONFIG_NETARM) || defined(CONFIG_LPC2292)
-
-ulong get_timer (ulong base)
-{
-       return get_timer_masked () - base;
-}
-
-void __udelay (unsigned long usec)
-{
-       ulong tmo;
-
-       tmo = usec / 1000;
-       tmo *= CONFIG_SYS_HZ;
-       tmo /= 1000;
-
-       tmo += get_timer (0);
-
-       while (get_timer_masked () < tmo)
-#ifdef CONFIG_LPC2292
-               /* GJ - not sure whether this is really needed or a misunderstanding */
-               __asm__ __volatile__(" nop");
-#else
-               /*NOP*/;
-#endif
-}
-
-ulong get_timer_masked (void)
-{
-       ulong now = READ_TIMER;
-
-       if (lastdec >= now) {
-               /* normal mode */
-               timestamp += lastdec - now;
-       } else {
-               /* we have an overflow ... */
-               timestamp += lastdec + TIMER_LOAD_VAL - now;
-       }
-       lastdec = now;
-
-       return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-       ulong tmo;
-       ulong endtime;
-       signed long diff;
-
-       if (usec >= 1000) {
-               tmo = usec / 1000;
-               tmo *= CONFIG_SYS_HZ;
-               tmo /= 1000;
-       } else {
-               tmo = usec * CONFIG_SYS_HZ;
-               tmo /= (1000*1000);
-       }
-
-       endtime = get_timer_masked () + tmo;
-
-       do {
-               ulong now = get_timer_masked ();
-               diff = endtime - now;
-       } while (diff >= 0);
-}
-
-#elif defined(CONFIG_S3C4510B)
-
-ulong get_timer (ulong base)
-{
-       return timestamp - base;
-}
-
-void __udelay (unsigned long usec)
-{
-       u32 ticks;
-
-       ticks = (usec * CONFIG_SYS_HZ) / 1000000;
-
-       ticks += get_timer (0);
-
-       while (get_timer (0) < ticks)
-               /*NOP*/;
-
+       return 0;
 }
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* No timer routines for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_TEGRA)
-       /* No timer routines for tegra as yet */
-#else
-#error Timer routines not defined for this CPU type
 #endif
diff --git a/arch/arm/cpu/arm720t/lpc2292/flash.c b/arch/arm/cpu/arm720t/lpc2292/flash.c
deleted file mode 100644 (file)
index 3d2dc32..0000000
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
- *
- * Modified to remove all but the IAP-command related code by
- * Gary Jennejohn <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-/* IAP commands use 32 bytes at the top of CPU internal sram, we
-   use 512 bytes below that */
-#define COPY_BUFFER_LOCATION 0x40003de0
-
-#define IAP_LOCATION 0x7ffffff1
-#define IAP_CMD_PREPARE 50
-#define IAP_CMD_COPY 51
-#define IAP_CMD_ERASE 52
-#define IAP_CMD_CHECK 53
-#define IAP_CMD_ID 54
-#define IAP_CMD_VERSION 55
-#define IAP_CMD_COMPARE 56
-
-#define IAP_RET_CMD_SUCCESS 0
-
-static unsigned long command[5];
-static unsigned long result[2];
-
-extern void iap_entry(unsigned long * command, unsigned long * result);
-
-/*-----------------------------------------------------------------------
- *
- */
-static int get_flash_sector(flash_info_t * info, ulong flash_addr)
-{
-       int i;
-
-       for(i = 1; i < (info->sector_count); i++) {
-               if (flash_addr < (info->start[i]))
-                       break;
-       }
-
-       return (i-1);
-}
-
-/*-----------------------------------------------------------------------
- * This function assumes that flash_addr is aligned on 512 bytes boundary
- * in flash. This function also assumes that prepare have been called
- * for the sector in question.
- */
-int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
-{
-       int first_sector;
-       int last_sector;
-
-       first_sector = get_flash_sector(info, flash_addr);
-       last_sector = get_flash_sector(info, flash_addr + 512 - 1);
-
-       /* prepare sectors for write */
-       command[0] = IAP_CMD_PREPARE;
-       command[1] = first_sector;
-       command[2] = last_sector;
-       iap_entry(command, result);
-       if (result[0] != IAP_RET_CMD_SUCCESS) {
-               printf("IAP prepare failed\n");
-               return ERR_PROG_ERROR;
-       }
-
-       command[0] = IAP_CMD_COPY;
-       command[1] = flash_addr;
-       command[2] = COPY_BUFFER_LOCATION;
-       command[3] = 512;
-       command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
-       iap_entry(command, result);
-       if (result[0] != IAP_RET_CMD_SUCCESS) {
-               printf("IAP copy failed\n");
-               return 1;
-       }
-
-       return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-       int flag;
-       int prot;
-       int sect;
-
-       prot = 0;
-       for (sect = s_first; sect <= s_last; ++sect) {
-               if (info->protect[sect]) {
-                       prot++;
-               }
-       }
-       if (prot)
-               return ERR_PROTECTED;
-
-
-       flag = disable_interrupts();
-
-       printf ("Erasing %d sectors starting at sector %2d.\n"
-       "This make take some time ... ",
-       s_last - s_first + 1, s_first);
-
-       command[0] = IAP_CMD_PREPARE;
-       command[1] = s_first;
-       command[2] = s_last;
-       iap_entry(command, result);
-       if (result[0] != IAP_RET_CMD_SUCCESS) {
-               printf("IAP prepare failed\n");
-               return ERR_PROTECTED;
-       }
-
-       command[0] = IAP_CMD_ERASE;
-       command[1] = s_first;
-       command[2] = s_last;
-       command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
-       iap_entry(command, result);
-       if (result[0] != IAP_RET_CMD_SUCCESS) {
-               printf("IAP erase failed\n");
-               return ERR_PROTECTED;
-       }
-
-       if (flag)
-               enable_interrupts();
-
-       return ERR_OK;
-}
-
-int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr,
-                       ulong cnt)
-{
-       int first_copy_size;
-       int last_copy_size;
-       int first_block;
-       int last_block;
-       int nbr_mid_blocks;
-       uchar memmap_value;
-       ulong i;
-       uchar* src_org;
-       uchar* dst_org;
-       int ret = ERR_OK;
-
-       src_org = src;
-       dst_org = (uchar*)addr;
-
-       first_block = addr / 512;
-       last_block = (addr + cnt) / 512;
-       nbr_mid_blocks = last_block - first_block - 1;
-
-       first_copy_size = 512 - (addr % 512);
-       last_copy_size = (addr + cnt) % 512;
-
-       debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
-               "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
-       (ulong)(first_block * 512),
-       (ulong)COPY_BUFFER_LOCATION,
-       (ulong)src,
-       (ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-       first_copy_size,
-       (ulong)COPY_BUFFER_LOCATION,
-       (ulong)(first_block * 512));
-
-       /* copy first block */
-       memcpy((void*)COPY_BUFFER_LOCATION,
-               (void*)(first_block * 512), 512);
-       memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-               src, first_copy_size);
-       lpc2292_copy_buffer_to_flash(info, first_block * 512);
-       src += first_copy_size;
-       addr += first_copy_size;
-
-       /* copy middle blocks */
-       for (i = 0; i < nbr_mid_blocks; i++) {
-               debug("copy middle block: %lX -> %lX 512 bytes, "
-               "%lX -> %lX 512 bytes\n",
-               (ulong)src,
-               (ulong)COPY_BUFFER_LOCATION,
-               (ulong)COPY_BUFFER_LOCATION,
-               (ulong)addr);
-
-               memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
-               lpc2292_copy_buffer_to_flash(info, addr);
-               src += 512;
-               addr += 512;
-       }
-
-
-       if (last_copy_size > 0) {
-               debug("copy last block: (1) %lX -> %lX 0x200 bytes, "
-               "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
-               (ulong)(last_block * 512),
-               (ulong)COPY_BUFFER_LOCATION,
-               (ulong)src,
-               (ulong)(COPY_BUFFER_LOCATION),
-               last_copy_size,
-               (ulong)COPY_BUFFER_LOCATION,
-               (ulong)addr);
-
-               /* copy last block */
-               memcpy((void*)COPY_BUFFER_LOCATION,
-                       (void*)(last_block * 512), 512);
-               memcpy((void*)COPY_BUFFER_LOCATION,
-                       src, last_copy_size);
-               lpc2292_copy_buffer_to_flash(info, addr);
-       }
-
-       /* verify write */
-       memmap_value = GET8(MEMMAP);
-
-       disable_interrupts();
-
-       PUT8(MEMMAP, 01);               /* we must make sure that initial 64
-                                                          bytes are taken from flash when we
-                                                          do the compare */
-
-       for (i = 0; i < cnt; i++) {
-               if (*dst_org != *src_org){
-                       printf("Write failed. Byte %lX differs\n", i);
-                       ret = ERR_PROG_ERROR;
-                       break;
-               }
-               dst_org++;
-               src_org++;
-       }
-
-       PUT8(MEMMAP, memmap_value);
-       enable_interrupts();
-
-       return ret;
-}
diff --git a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S
deleted file mode 100644 (file)
index c31d519..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-IAP_ADDRESS:   .word   0x7FFFFFF1
-
-.globl iap_entry
-iap_entry:
-       ldr     r2, IAP_ADDRESS
-       bx      r2
-       mov     pc, lr
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc.c b/arch/arm/cpu/arm720t/lpc2292/mmc.c
deleted file mode 100644 (file)
index beaffe9..0000000
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <mmc.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <part.h>
-#include <fat.h>
-#include "mmc_hw.h"
-#include <asm/arch/spi.h>
-
-#ifdef CONFIG_MMC
-
-#undef MMC_DEBUG
-
-static block_dev_desc_t mmc_dev;
-
-/* these are filled out by a call to mmc_hw_get_parameters */
-static int hw_size;            /* in kbytes */
-static int hw_nr_sects;
-static int hw_sect_size;       /* in bytes */
-
-block_dev_desc_t * mmc_get_dev(int dev)
-{
-       return (block_dev_desc_t *)(&mmc_dev);
-}
-
-unsigned long mmc_block_read(int dev,
-                            unsigned long start,
-                            lbaint_t blkcnt,
-                            void *buffer)
-{
-       unsigned long rc = 0;
-       unsigned char *p = (unsigned char *)buffer;
-       unsigned long i;
-       unsigned long addr = start;
-
-#ifdef MMC_DEBUG
-       printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
-                (unsigned long)blkcnt);
-#endif
-
-       for(i = 0; i < (unsigned long)blkcnt; i++) {
-#ifdef MMC_DEBUG
-               printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
-#endif
-               (void)mmc_read_sector(addr, p);
-               rc++;
-               addr++;
-               p += hw_sect_size;
-       }
-
-       return rc;
-}
-
-/*-----------------------------------------------------------------------------
- * Read hardware paramterers (sector size, size, number of sectors)
- */
-static int mmc_hw_get_parameters(void)
-{
-       unsigned char csddata[16];
-       unsigned int sizemult;
-       unsigned int size;
-
-       mmc_read_csd(csddata);
-       hw_sect_size = 1<<(csddata[5] & 0x0f);
-       size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
-       sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
-       hw_nr_sects = (size+1)*(1<<(sizemult+2));
-       hw_size = hw_nr_sects*hw_sect_size/1024;
-
-#ifdef MMC_DEBUG
-       printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
-                "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
-#endif
-
-       return 0;
-}
-
-int mmc_legacy_init(int verbose)
-{
-       int ret = -ENODEV;
-
-       if (verbose)
-               printf("mmc_legacy_init\n");
-
-       spi_init();
-       /* this meeds to be done twice */
-       mmc_hw_init();
-       udelay(1000);
-       mmc_hw_init();
-
-       mmc_hw_get_parameters();
-
-       mmc_dev.if_type = IF_TYPE_MMC;
-       mmc_dev.part_type = PART_TYPE_DOS;
-       mmc_dev.dev = 0;
-       mmc_dev.lun = 0;
-       mmc_dev.type = 0;
-       mmc_dev.blksz = hw_sect_size;
-       mmc_dev.lba = hw_nr_sects;
-       sprintf((char*)mmc_dev.vendor, "Unknown vendor");
-       sprintf((char*)mmc_dev.product, "Unknown product");
-       sprintf((char*)mmc_dev.revision, "N/A");
-       mmc_dev.removable = 0;  /* should be true??? */
-       mmc_dev.block_read = mmc_block_read;
-
-       fat_register_device(&mmc_dev, 1);
-
-       ret = 0;
-
-       return ret;
-}
-
-#endif /* CONFIG_MMC */
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
deleted file mode 100644 (file)
index bd6a5b1..0000000
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
-    This code was original written by Ulrich Radig and modified by
-    Embedded Artists AB (www.embeddedartists.com).
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
-#define MMC_Disable() PUT32(IO1SET, 1l << 22)
-#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
-
-static unsigned char Write_Command_MMC (unsigned char *CMD);
-static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
-                   unsigned short int Bytes);
-
-/* initialize the hardware */
-int mmc_hw_init(void)
-{
-       unsigned long a;
-       unsigned short int Timeout = 0;
-       unsigned char b;
-       unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
-
-       /* set-up GPIO and SPI */
-       (*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
-       (*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
-
-       MMC_Disable();
-
-       spi_lock();
-       spi_set_clock(248);
-       spi_set_cfg(0, 1, 0);
-       MMC_Enable();
-
-       /* waste some time */
-       for(a=0; a < 20000; a++)
-               asm("nop");
-
-       /* Put the MMC/SD-card into SPI-mode */
-       for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
-               spi_write(0xff);
-
-       /* Sends command CMD0 to MMC/SD-card */
-       while (Write_Command_MMC(CMD) != 1) {
-               if (Timeout++ > 200) {
-                       MMC_Disable();
-                       spi_unlock();
-                       return(1); /* Abort with command 1 (return 1) */
-               }
-       }
-       /* Sends Command CMD1 an MMC/SD-card */
-       Timeout = 0;
-       CMD[0] = 0x41;/* Command 1 */
-       CMD[5] = 0xFF;
-
-       while (Write_Command_MMC(CMD) != 0) {
-               if (Timeout++ > 200) {
-                       MMC_Disable();
-                       spi_unlock();
-                       return (2); /* Abort with command 2 (return 2) */
-               }
-       }
-
-       MMC_Disable();
-       spi_unlock();
-
-       return 0;
-}
-
-/* ############################################################################
-   Sends a command to the MMC/SD-card
-   ######################################################################### */
-static unsigned char Write_Command_MMC (unsigned char *CMD)
-{
-       unsigned char a, tmp = 0xff;
-       unsigned short int Timeout = 0;
-
-       MMC_Disable();
-       spi_write(0xFF);
-       MMC_Enable();
-
-       for (a = 0; a < 0x06; a++)
-               spi_write(*CMD++);
-
-       while (tmp == 0xff) {
-               tmp = spi_read();
-               if (Timeout++ > 5000)
-                 break;
-       }
-
-       return (tmp);
-}
-
-/* ############################################################################
-   Routine to read the CID register from the MMC/SD-card (16 bytes)
-   ######################################################################### */
-void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
-       int Bytes)
-{
-       unsigned short int a;
-
-       spi_lock();
-       mmc_spi_cfg();
-       MMC_Enable();
-
-       if (Write_Command_MMC(CMD) != 0) {
-               MMC_Disable();
-               spi_unlock();
-               return;
-       }
-
-       while (spi_read() != 0xfe) {};
-       for (a = 0; a < Bytes; a++)
-               *Buffer++ = spi_read();
-
-       /* Read the CRC-byte */
-       spi_read(); /* CRC - byte is discarded */
-       spi_read(); /* CRC - byte is discarded */
-       /* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
-       MMC_Disable();
-       spi_unlock();
-
-       return;
-}
-
-/* ############################################################################
-   Routine to read a block (512 bytes) from the MMC/SD-card
-   ######################################################################### */
-unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
-{
-       /* Command 16 to read aBlocks from the MMC/SD - caed */
-       unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
-
-       /* The address on the MMC/SD-card is in bytes,
-       addr is transformed from blocks to bytes and the result is
-       placed into the command */
-
-       addr = addr << 9; /* addr = addr * 512 */
-
-       CMD[1] = ((addr & 0xFF000000) >> 24);
-       CMD[2] = ((addr & 0x00FF0000) >> 16);
-       CMD[3] = ((addr & 0x0000FF00) >> 8 );
-
-       MMC_Read_Block(CMD, Buffer, 512);
-
-       return (0);
-}
-
-/* ############################################################################
-   Routine to write a block (512 byte) to the MMC/SD-card
-   ######################################################################### */
-unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
-{
-       unsigned char tmp, a;
-       unsigned short int b;
-       /* Command 24 to write a block to the MMC/SD - card */
-       unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
-
-       /* The address on the MMC/SD-card is in bytes,
-       addr is transformed from blocks to bytes and the result is
-       placed into the command */
-
-       addr = addr << 9; /* addr = addr * 512 */
-
-       CMD[1] = ((addr & 0xFF000000) >> 24);
-       CMD[2] = ((addr & 0x00FF0000) >> 16);
-       CMD[3] = ((addr & 0x0000FF00) >> 8 );
-
-       spi_lock();
-       mmc_spi_cfg();
-       MMC_Enable();
-
-       /* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
-       tmp = Write_Command_MMC(CMD);
-       if (tmp != 0) {
-               MMC_Disable();
-               spi_unlock();
-               return(tmp);
-       }
-
-       /* Do a short delay and send a clock-pulse to the MMC/SD-card */
-       for (a = 0; a < 100; a++)
-               spi_read();
-
-       /* Send a start byte to the MMC/SD-card */
-       spi_write(0xFE);
-
-       /* Write the block (512 bytes) to the MMC/SD-card */
-       for (b = 0; b < 512; b++)
-               spi_write(*Buffer++);
-
-       /* write the CRC-Byte */
-       spi_write(0xFF); /* write a dummy CRC */
-       spi_write(0xFF); /* CRC code is not used */
-
-       /* Wait for MMC/SD-card busy */
-       while (spi_read() != 0xff) {};
-
-       /* set MMC_Chip_Select to high (MMC/SD-card inactive) */
-       MMC_Disable();
-       spi_unlock();
-       return (0);
-}
-
-/* #########################################################################
-   Routine to read the CSD register from the MMC/SD-card (16 bytes)
-   ######################################################################### */
-unsigned char mmc_read_csd (unsigned char *Buffer)
-{
-       /* Command to read the CSD register */
-       unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
-
-       MMC_Read_Block(CMD, Buffer, 16);
-
-       return (0);
-}
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
deleted file mode 100644 (file)
index 3687dbf..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
-    This module implements a linux character device driver for the 24c256 chip.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef _MMC_HW_
-#define _MMC_HW_
-
-unsigned char mmc_read_csd(unsigned char *Buffer);
-unsigned char mmc_read_sector (unsigned long addr,
-                              unsigned char *Buffer);
-unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
-int mmc_hw_init(void);
-
-#endif /* _MMC_HW_ */
diff --git a/arch/arm/cpu/arm720t/lpc2292/spi.c b/arch/arm/cpu/arm720t/lpc2292/spi.c
deleted file mode 100644 (file)
index d296bda..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-    This module implements an interface to the SPI on the lpc22xx.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-unsigned long spi_flags;
-unsigned char spi_idle = 0x00;
-
-int spi_init(void)
-{
-       unsigned long pinsel0_value;
-
-       /* activate spi pins */
-       pinsel0_value = GET32(PINSEL0);
-       pinsel0_value &= ~(0xFFl << 8);
-       pinsel0_value |= (0x55l << 8);
-       PUT32(PINSEL0, pinsel0_value);
-
-       return 0;
-}
diff --git a/arch/arm/cpu/arm720t/s3c4510b/cache.c b/arch/arm/cpu/arm720t/s3c4510b/cache.c
deleted file mode 100644 (file)
index 104d287..0000000
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-void icache_enable (void)
-{
-       s32 i;
-
-       /* disable all cache bits */
-       CLR_REG( REG_SYSCFG, 0x3F);
-
-       /* 8KB cache, write enable */
-       SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
-
-       /* clear TAG RAM bits */
-       for ( i = 0; i < 256; i++)
-         PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
-
-       /* clear SET0 RAM */
-       for(i=0; i < 1024; i++)
-         PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
-
-       /* clear SET1 RAM */
-       for(i=0; i < 1024; i++)
-         PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
-
-       /* enable cache */
-       SET_REG( REG_SYSCFG, CACHE_ENABLE);
-
-}
-
-void icache_disable (void)
-{
-       /* disable all cache bits */
-       CLR_REG( REG_SYSCFG, 0x3F);
-}
-
-int icache_status (void)
-{
-       return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
-}
-
-void dcache_enable (void)
-{
-       /* we don't have seperate instruction/data caches */
-       icache_enable();
-}
-
-void dcache_disable (void)
-{
-       /* we don't have seperate instruction/data caches */
-       icache_disable();
-}
-
-int dcache_status (void)
-{
-       /* we don't have seperate instruction/data caches */
-       return icache_status();
-}
index 2f914e9b4e2fd6317861831af025693990c9495a..c2a7763fff00a2b4e974dacf7b31b144641c6e2c 100644 (file)
@@ -43,11 +43,7 @@ _start: b    reset
        ldr     pc, _software_interrupt
        ldr     pc, _prefetch_abort
        ldr     pc, _data_abort
-#ifdef CONFIG_LPC2292
-       .word   0xB4405F76 /* 2's complement of the checksum of the vectors */
-#else
        ldr     pc, _not_used
-#endif
        ldr     pc, _irq
        ldr     pc, _fiq
 
@@ -151,10 +147,6 @@ reset:
        bl      cpu_init_crit
 #endif
 
-#ifdef CONFIG_LPC2292
-       bl      lowlevel_init
-#endif
-
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
        ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
@@ -291,148 +283,9 @@ _dynsym_start_ofs:
  *************************************************************************
  */
 
-#if defined(CONFIG_LPC2292)
-PLLCFG_ADR:    .word   PLLCFG
-PLLFEED_ADR:   .word   PLLFEED
-PLLCON_ADR:    .word   PLLCON
-PLLSTAT_ADR:   .word   PLLSTAT
-VPBDIV_ADR:    .word   VPBDIV
-MEMMAP_ADR:    .word   MEMMAP
-
-#endif
-
 cpu_init_crit:
-#if defined(CONFIG_NETARM)
-       /*
-        * prior to software reset : need to set pin PORTC4 to be *HRESET
-        */
-       ldr     r0, =NETARM_GEN_MODULE_BASE
-       ldr     r1, =(NETARM_GEN_PORT_MODE(0x10) | \
-                       NETARM_GEN_PORT_DIR(0x10))
-       str     r1, [r0, #+NETARM_GEN_PORTC]
-       /*
-        * software reset : see HW Ref. Guide 8.2.4 : Software Service register
-        *                  for an explanation of this process
-        */
-       ldr     r0, =NETARM_GEN_MODULE_BASE
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETA
-       str     r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETB
-       str     r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETA
-       str     r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETB
-       str     r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-       /*
-        * setup PLL and System Config
-        */
-       ldr     r0, =NETARM_GEN_MODULE_BASE
-
-       ldr     r1, =(  NETARM_GEN_SYS_CFG_LENDIAN | \
-                       NETARM_GEN_SYS_CFG_BUSFULL | \
-                       NETARM_GEN_SYS_CFG_USER_EN | \
-                       NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
-                       NETARM_GEN_SYS_CFG_BUSARB_INT | \
-                       NETARM_GEN_SYS_CFG_BUSMON_EN )
-
-       str     r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
-
-#ifndef CONFIG_NETARM_PLL_BYPASS
-       ldr     r1, =(  NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
-                       NETARM_GEN_PLL_CTL_POLTST_DEF | \
-                       NETARM_GEN_PLL_CTL_INDIV(1) | \
-                       NETARM_GEN_PLL_CTL_ICP_DEF | \
-                       NETARM_GEN_PLL_CTL_OUTDIV(2) )
-       str     r1, [r0, #+NETARM_GEN_PLL_CONTROL]
-#endif
-
-       /*
-        * mask all IRQs by clearing all bits in the INTMRs
-        */
-       mov     r1, #0
-       ldr     r0, =NETARM_GEN_MODULE_BASE
-       str     r1, [r0, #+NETARM_GEN_INTR_ENABLE]
-
-#elif defined(CONFIG_S3C4510B)
 
-       /*
-        * Mask off all IRQ sources
-        */
-       ldr     r1, =REG_INTMASK
-       ldr     r0, =0x3FFFFF
-       str     r0, [r1]
-
-       /*
-        * Disable Cache
-        */
-       ldr r0, =REG_SYSCFG
-       ldr r1, =0x83ffffa0     /* cache-disabled  */
-       str r1, [r0]
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* No specific initialisation for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-       /* Set-up PLL */
-       mov     r3, #0xAA
-       mov     r4, #0x55
-       /* First disconnect and disable the PLL */
-       ldr     r0, PLLCON_ADR
-       mov     r1, #0x00
-       str     r1, [r0]
-       ldr     r0, PLLFEED_ADR /* start feed sequence */
-       str     r3, [r0]
-       str     r4, [r0]        /* feed sequence done */
-       /* Set new M and P values */
-       ldr     r0, PLLCFG_ADR
-       mov     r1, #0x23       /* M=4 and P=2 */
-       str     r1, [r0]
-       ldr     r0, PLLFEED_ADR /* start feed sequence */
-       str     r3, [r0]
-       str     r4, [r0]        /* feed sequence done */
-       /* Then enable the PLL */
-       ldr     r0, PLLCON_ADR
-       mov     r1, #0x01       /* PLL enable bit */
-       str     r1, [r0]
-       ldr     r0, PLLFEED_ADR /* start feed sequence */
-       str     r3, [r0]
-       str     r4, [r0]        /* feed sequence done */
-       /* Wait for the lock */
-       ldr     r0, PLLSTAT_ADR
-       mov     r1, #0x400      /* lock bit */
-lock_loop:
-       ldr     r2, [r0]
-       and     r2, r1, r2
-       cmp     r2, #0
-       beq     lock_loop
-       /* And finally connect the PLL */
-       ldr     r0, PLLCON_ADR
-       mov     r1, #0x03       /* PLL enable bit and connect bit */
-       str     r1, [r0]
-       ldr     r0, PLLFEED_ADR /* start feed sequence */
-       str     r3, [r0]
-       str     r4, [r0]        /* feed sequence done */
-       /* Set-up VPBDIV register */
-       ldr     r0, VPBDIV_ADR
-       mov     r1, #0x01       /* VPB clock is same as process clock */
-       str     r1, [r0]
-#elif defined(CONFIG_TEGRA)
-       /* No cpu_init_crit for tegra as yet */
-#else
-#error No cpu_init_crit() defined for current CPU type
-#endif
-
-#ifdef CONFIG_ARM7_REVD
-       /* set clock speed */
-       /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
-       /* !!! not doing DRAM refresh properly! */
-       ldr     r0, SYSCON3
-       ldr     r1, [r0]
-       bic     r1, r1, #CLKCTL
-       orr     r1, r1, #CLKCTL_36
-       str     r1, [r0]
-#endif
-
-#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA)
+#if !defined(CONFIG_TEGRA)
        mov     ip, lr
        /*
         * before relocating, we have to setup RAM timing
@@ -610,39 +463,3 @@ fiq:
 
 #endif
 #endif /* CONFIG_SPL_BUILD */
-
-#if defined(CONFIG_NETARM)
-       .align  5
-.globl reset_cpu
-reset_cpu:
-       ldr     r1, =NETARM_MEM_MODULE_BASE
-       ldr     r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
-       ldr     r1, =0xFFFFF000
-       and     r0, r1, r0
-       ldr     r1, =(relocate-CONFIG_SYS_TEXT_BASE)
-       add     r0, r1, r0
-       ldr     r4, =NETARM_GEN_MODULE_BASE
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETA
-       str     r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETB
-       str     r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETA
-       str     r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-       ldr     r1, =NETARM_GEN_SW_SVC_RESETB
-       str     r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-       mov     pc, r0
-#elif defined(CONFIG_S3C4510B)
-/* Nothing done here as reseting the CPU is board specific, depending
- * on external peripherals such as watchdog timers, etc. */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-       /* No specific reset actions for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-       .align  5
-.globl reset_cpu
-reset_cpu:
-       mov     pc, r0
-#elif defined(CONFIG_TEGRA)
-       /* No specific reset actions for tegra as yet */
-#else
-#error No reset_cpu() defined for current CPU type
-#endif
index dc6ba34082ecd33e58e8b989f83e82b84a3fe6f2..008ae891cafd8e47b8dc44ad9fc4b0918f37cdb1 100644 (file)
@@ -48,9 +48,11 @@ SECTIONS
        .got : { *(.got) }
 
        . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
        __bss_start = .;
index e9f1227dd6038aeeee8b7e8b9f76791b1b6284db..1bba571077740cd131ef46df4fe1663246e2c650 100644 (file)
@@ -72,10 +72,10 @@ lowlevel_init:
         * enable UART for early debug trace
         */
        ldr     r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
-       mov     r2, #0xd9
-       str     r2, [r1]                /* 115200 baud */
+       mov     r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
+       str     r2, [r1]
        ldr     r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
-       mov     r2, #0x03
+       mov     r2, #KS8695_UART_LINEC_WLEN8
        str     r2, [r1]                /* 8 data bits, no parity, 1 stop */
        ldr     r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
        mov     r2, #0x41
index 0029700e443f626e6fbb837baf93be98a8d35481..808ab8f0f29a8ad272e3aa8a568d8406cfdadc5f 100644 (file)
@@ -29,9 +29,6 @@ COBJS-$(CONFIG_USE_IRQ) += interrupts.o
 COBJS-$(CONFIG_DISPLAY_CPUINFO)        += cpu_info.o
 COBJS-y        += speed.o
 COBJS-y        += timer.o
-COBJS-y        += usb.o
-COBJS-y        += usb_ohci.o
-
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c
deleted file mode 100644 (file)
index 226a3f6..0000000
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering <mk@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && \
-    defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
-    defined(CONFIG_S3C24X0)
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/io.h>
-
-int usb_cpu_init(void)
-{
-       struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-       struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-
-       /*
-        * Set the 48 MHz UPLL clocking. Values are taken from
-        * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
-        */
-       writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
-       /* 1 = use pads related USB for USB host */
-       writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
-
-       /*
-        * Enable USB host clock.
-        */
-       writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
-
-       return 0;
-}
-
-int usb_cpu_stop(void)
-{
-       struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-       /* may not want to do this */
-       writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
-       return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-       struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-       writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
-       return 0;
-}
-
-#endif /* defined(CONFIG_USB_OHCI_NEW) && \
-          defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
-          defined(CONFIG_S3C24X0) */
index 6d77219d0daeca8bb75fcd59a363a260a1b86faa..93485523b585077e48a9ca03a6d163f80ed5f77e 100644 (file)
@@ -118,6 +118,21 @@ void at91_serial2_hw_init(void)
        writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
+void at91_mci_hw_init(void)
+{
+       /* Initialize the MCI0 */
+       at91_set_a_periph(AT91_PIO_PORTA, 17, 1);       /* MCCK */
+       at91_set_a_periph(AT91_PIO_PORTA, 16, 1);       /* MCCDA */
+       at91_set_a_periph(AT91_PIO_PORTA, 15, 1);       /* MCDA0 */
+       at91_set_a_periph(AT91_PIO_PORTA, 18, 1);       /* MCDA1 */
+       at91_set_a_periph(AT91_PIO_PORTA, 19, 1);       /* MCDA2 */
+       at91_set_a_periph(AT91_PIO_PORTA, 20, 1);       /* MCDA3 */
+
+       /* Enable clock for MCI0 */
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+}
+
 #ifdef CONFIG_ATMEL_SPI
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
index f8ea38c03d4758f261e063b710273e6ab66ac9e4..6dc681a313988550f78399232d6a6a7bcdff57ba 100644 (file)
@@ -50,9 +50,10 @@ SECTIONS
        }
 
        . = ALIGN(4);
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       .u_boot_list : {
+               #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
index afd3381e1675bd33457215f523d928590fb179f3..f3bd5e736757e756a4829206164052513d42e717 100644 (file)
@@ -50,9 +50,10 @@ SECTIONS
        }
 
        . = ALIGN(4);
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       .u_boot_list : {
+               #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
index 7768912603b2cdb7cb151b4c25f0381fcd53aa44..74875b32558c2957415ee177320fcb1daa9dad77 100644 (file)
@@ -21,6 +21,7 @@ COBJS += sys_info.o
 COBJS  += ddr.o
 COBJS  += emif4.o
 COBJS  += board.o
+COBJS  += mux.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
index 978b184fb221913a58b76f765727000a4232b12a..e4c123cd21d614f3b2bee6a3aabf6a9e5288be56 100644 (file)
@@ -36,9 +36,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-
 static const struct gpio_bank gpio_bank_am33xx[4] = {
        { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
        { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -48,153 +45,11 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 
-/* MII mode defines */
-#define MII_MODE_ENABLE                0x0
-#define RGMII_MODE_ENABLE      0xA
-
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN                7
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-static struct am335x_baseboard_id __attribute__((section (".data"))) header;
-
-static inline int board_is_bone(void)
-{
-       return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_sk(void)
-{
-       return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
-}
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(void)
-{
-       /* Check if baseboard eeprom is available */
-       if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-               puts("Could not probe the EEPROM; something fundamentally "
-                       "wrong on the I2C bus.\n");
-               return -ENODEV;
-       }
-
-       /* read the eeprom using i2c */
-       if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
-                                                       sizeof(header))) {
-               puts("Could not read the EEPROM; something fundamentally"
-                       " wrong on the I2C bus.\n");
-               return -EIO;
-       }
-
-       if (header.magic != 0xEE3355AA) {
-               /*
-                * read the eeprom using i2c again,
-                * but use only a 1 byte address
-                */
-               if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
-                                       (uchar *)&header, sizeof(header))) {
-                       puts("Could not read the EEPROM; something "
-                               "fundamentally wrong on the I2C bus.\n");
-                       return -EIO;
-               }
-
-               if (header.magic != 0xEE3355AA) {
-                       printf("Incorrect magic number (0x%x) in EEPROM\n",
-                                       header.magic);
-                       return -EINVAL;
-               }
-       }
-
-       return 0;
-}
-
-/* UART Defines */
-#ifdef CONFIG_SPL_BUILD
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
-#endif
-
-/*
- * Determine what type of DDR we have.
- */
-static short inline board_memory_type(void)
-{
-       /* The following boards are known to use DDR3. */
-       if (board_is_evm_sk())
-               return EMIF_REG_SDRAM_TYPE_DDR3;
-
-       return EMIF_REG_SDRAM_TYPE_DDR2;
-}
-
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
-{
-       /* WDT1 is already running when the bootloader gets control
-        * Disable it to avoid "random" resets
-        */
-       writel(0xAAAA, &wdtimer->wdtwspr);
-       while (readl(&wdtimer->wdtwwps) != 0x0)
-               ;
-       writel(0x5555, &wdtimer->wdtwspr);
-       while (readl(&wdtimer->wdtwwps) != 0x0)
-               ;
-
-#ifdef CONFIG_SPL_BUILD
-       /* Setup the PLLs and the clocks for the peripherals */
-       pll_init();
-
-       /* UART softreset */
-       u32 regVal;
-
-       enable_uart0_pin_mux();
-
-       regVal = readl(&uart_base->uartsyscfg);
-       regVal |= UART_RESET;
-       writel(regVal, &uart_base->uartsyscfg);
-       while ((readl(&uart_base->uartsyssts) &
-               UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-               ;
-
-       /* Disable smart idle */
-       regVal = readl(&uart_base->uartsyscfg);
-       regVal |= UART_SMART_IDLE_EN;
-       writel(regVal, &uart_base->uartsyscfg);
-
-       gd = &gdata;
-
-       preloader_console_init();
-
-       /* Initalize the board header */
-       enable_i2c0_pin_mux();
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-       if (read_eeprom() < 0)
-               puts("Could not get board ID.\n");
-
-       enable_board_pin_mux(&header);
-       if (board_is_evm_sk()) {
-               /*
-                * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
-                * This is safe enough to do on older revs.
-                */
-               gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
-               gpio_direction_output(GPIO_DDR_VTT_EN, 1);
-       }
-
-       config_ddr(board_memory_type());
-#endif
-}
-
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
+int cpu_mmc_init(bd_t *bis)
 {
        int ret;
-       
+
        ret = omap_mmc_init(0, 0, 0);
        if (ret)
                return ret;
@@ -208,93 +63,3 @@ void setup_clocks_for_console(void)
        /* Not yet implemented */
        return;
 }
-
-/*
- * Basic board specific setup.  Pinmux has been handled already.
- */
-int board_init(void)
-{
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-       if (read_eeprom() < 0)
-               puts("Could not get board ID.\n");
-
-       gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
-
-       return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
-       /* VTP can be added here */
-
-       return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-       {
-               .slave_reg_ofs  = 0x208,
-               .sliver_reg_ofs = 0xd80,
-               .phy_id         = 0,
-       },
-       {
-               .slave_reg_ofs  = 0x308,
-               .sliver_reg_ofs = 0xdc0,
-               .phy_id         = 1,
-       },
-};
-
-static struct cpsw_platform_data cpsw_data = {
-       .mdio_base              = AM335X_CPSW_MDIO_BASE,
-       .cpsw_base              = AM335X_CPSW_BASE,
-       .mdio_div               = 0xff,
-       .channels               = 8,
-       .cpdma_reg_ofs          = 0x800,
-       .slaves                 = 1,
-       .slave_data             = cpsw_slaves,
-       .ale_reg_ofs            = 0xd00,
-       .ale_entries            = 1024,
-       .host_port_reg_ofs      = 0x108,
-       .hw_stats_reg_ofs       = 0x900,
-       .mac_control            = (1 << 5),
-       .control                = cpsw_control,
-       .host_port_num          = 0,
-       .version                = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
-       uint8_t mac_addr[6];
-       uint32_t mac_hi, mac_lo;
-
-       if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
-               debug("<ethaddr> not set. Reading from E-fuse\n");
-               /* try reading mac address from efuse */
-               mac_lo = readl(&cdev->macid0l);
-               mac_hi = readl(&cdev->macid0h);
-               mac_addr[0] = mac_hi & 0xFF;
-               mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-               mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-               mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-               mac_addr[4] = mac_lo & 0xFF;
-               mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-               if (is_valid_ether_addr(mac_addr))
-                       eth_setenv_enetaddr("ethaddr", mac_addr);
-               else
-                       return -1;
-       }
-
-       if (board_is_bone()) {
-               writel(MII_MODE_ENABLE, &cdev->miisel);
-               cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
-                               PHY_INTERFACE_MODE_MII;
-       } else {
-               writel(RGMII_MODE_ENABLE, &cdev->miisel);
-               cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
-                               PHY_INTERFACE_MODE_RGMII;
-       }
-
-       return cpsw_register(&cpsw_data);
-}
-#endif
index 2b19506a341c01a39a5347aba4a76f865829689e..f870859414440628536554d6fba47918a087f428 100644 (file)
@@ -44,6 +44,7 @@
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
 
 static void enable_interface_clocks(void)
 {
@@ -153,6 +154,11 @@ static void enable_per_clocks(void)
        writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
        while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
                ;
+
+       /* RTC */
+       writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
+       while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
+               ;
 }
 
 static void mpu_pll_config(void)
index 5750bbdcb69a54d7e2ccfc523c6e7fe7e14d1c00..babf0eb5cc8d4895a9b8df0cb86400e792184898 100644 (file)
@@ -13,6 +13,7 @@
 #
 ifdef CONFIG_SPL_BUILD
 ALL-y  += $(OBJTREE)/MLO
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap
 else
 ALL-y  += $(obj)u-boot.img
 endif
index b2d7c0d95621495f3ad3c6c8beb3281217681f3d..01e3a5204ea96f7a91d2ab9da6d64ee31a311d94 100644 (file)
@@ -47,78 +47,6 @@ void dram_init_banksize(void)
 static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 
-static const struct ddr_data ddr2_data = {
-       .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
-                               |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
-       .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
-                               |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
-       .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
-                               |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
-       .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
-                               |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
-       .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
-                               |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
-       .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
-                               |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
-       .datauserank0delay = DDR2_PHY_RANK0_DELAY,
-       .datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
-       .cmd0csratio = DDR2_RATIO,
-       .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
-       .cmd0iclkout = DDR2_INVERT_CLKOUT,
-
-       .cmd1csratio = DDR2_RATIO,
-       .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
-       .cmd1iclkout = DDR2_INVERT_CLKOUT,
-
-       .cmd2csratio = DDR2_RATIO,
-       .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
-       .cmd2iclkout = DDR2_INVERT_CLKOUT,
-};
-
-static const struct emif_regs ddr2_emif_reg_data = {
-       .sdram_config = DDR2_EMIF_SDCFG,
-       .ref_ctrl = DDR2_EMIF_SDREF,
-       .sdram_tim1 = DDR2_EMIF_TIM1,
-       .sdram_tim2 = DDR2_EMIF_TIM2,
-       .sdram_tim3 = DDR2_EMIF_TIM3,
-       .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
-};
-
-static const struct ddr_data ddr3_data = {
-       .datardsratio0 = DDR3_RD_DQS,
-       .datawdsratio0 = DDR3_WR_DQS,
-       .datafwsratio0 = DDR3_PHY_FIFO_WE,
-       .datawrsratio0 = DDR3_PHY_WR_DATA,
-       .datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-       .cmd0csratio = DDR3_RATIO,
-       .cmd0dldiff = DDR3_DLL_LOCK_DIFF,
-       .cmd0iclkout = DDR3_INVERT_CLKOUT,
-
-       .cmd1csratio = DDR3_RATIO,
-       .cmd1dldiff = DDR3_DLL_LOCK_DIFF,
-       .cmd1iclkout = DDR3_INVERT_CLKOUT,
-
-       .cmd2csratio = DDR3_RATIO,
-       .cmd2dldiff = DDR3_DLL_LOCK_DIFF,
-       .cmd2iclkout = DDR3_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-       .sdram_config = DDR3_EMIF_SDCFG,
-       .ref_ctrl = DDR3_EMIF_SDREF,
-       .sdram_tim1 = DDR3_EMIF_TIM1,
-       .sdram_tim2 = DDR3_EMIF_TIM2,
-       .sdram_tim3 = DDR3_EMIF_TIM3,
-       .zq_config = DDR3_ZQ_CFG,
-       .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
-};
-
 static void config_vtp(void)
 {
        writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -134,46 +62,26 @@ static void config_vtp(void)
                ;
 }
 
-void config_ddr(short ddr_type)
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+               const struct ddr_data *data, const struct cmd_control *ctrl,
+               const struct emif_regs *regs)
 {
-       int ddr_pll, ioctrl_val;
-       const struct emif_regs *emif_regs;
-       const struct ddr_data *ddr_data;
-       const struct cmd_control *cmd_ctrl_data;
-
-       if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
-               ddr_pll = 266;
-               cmd_ctrl_data = &ddr2_cmd_ctrl_data;
-               ddr_data = &ddr2_data;
-               ioctrl_val = DDR2_IOCTRL_VALUE;
-               emif_regs = &ddr2_emif_reg_data;
-       } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
-               ddr_pll = 303;
-               cmd_ctrl_data = &ddr3_cmd_ctrl_data;
-               ddr_data = &ddr3_data;
-               ioctrl_val = DDR3_IOCTRL_VALUE;
-               emif_regs = &ddr3_emif_reg_data;
-       } else {
-               puts("Unknown memory type");
-               hang();
-       }
-
        enable_emif_clocks();
-       ddr_pll_config(ddr_pll);
+       ddr_pll_config(pll);
        config_vtp();
-       config_cmd_ctrl(cmd_ctrl_data);
+       config_cmd_ctrl(ctrl);
 
-       config_ddr_data(0, ddr_data);
-       config_ddr_data(1, ddr_data);
+       config_ddr_data(0, data);
+       config_ddr_data(1, data);
 
-       config_io_ctrl(ioctrl_val);
+       config_io_ctrl(ioctrl);
 
        /* Set CKE to be controlled by EMIF/DDR PHY */
        writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 
        /* Program EMIF instance */
-       config_ddr_phy(emif_regs);
-       set_sdram_timings(emif_regs);
-       config_sdram(emif_regs);
+       config_ddr_phy(regs);
+       set_sdram_timings(regs);
+       config_sdram(regs);
 }
 #endif
diff --git a/arch/arm/cpu/armv7/am33xx/mux.c b/arch/arm/cpu/armv7/am33xx/mux.c
new file mode 100644 (file)
index 0000000..2ded472
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+{
+       int i;
+
+       if (!mod_pin_mux)
+               return;
+
+       for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+               MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+}
index 1d8efb213bf4f9198e4a43db16870d5b54f20afe..9979c3085360b19c5c5e585fc6f677ec84018857 100644 (file)
@@ -47,6 +47,11 @@ SECTIONS
 
        . = ALIGN(4);
        .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+       .u_boot_list : {
+               #include <u-boot.lst>
+       }
+
        . = ALIGN(4);
        __image_copy_end = .;
        _end = .;
index 7199de4af1e317fed2cf01764d57d536f6c2f562..81d954f2de7fce029d5e74b81bdfcc00ff9b82cb 100644 (file)
@@ -46,9 +46,11 @@ SECTIONS
        . = ALIGN(4);
 
        . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
diff --git a/arch/arm/cpu/lh7a40x/speed.c b/arch/arm/cpu/lh7a40x/speed.c
deleted file mode 100644 (file)
index 333ebb5..0000000
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-ulong get_PLLCLK (void)
-{
-       return CONFIG_SYS_CLK_FREQ;
-}
-
-/* return FCLK frequency */
-ulong get_FCLK (void)
-{
-       lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-       ulong maindiv1, maindiv2, prediv, ps;
-
-       /*
-        * from userguide 6.1.1.2
-        *
-        * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
-        *                   ((PREDIV+2) * (2^PS))
-        */
-       maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
-       maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
-       prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
-       ps = (csc->clkset & CLKSET_PS) >> 16;
-
-       return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
-               ((prediv + 2) * (1 << ps)));
-}
-
-
-/* return HCLK frequency */
-ulong get_HCLK (void)
-{
-       lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-
-       return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1));
-}
-
-/* return PCLK frequency */
-ulong get_PCLK (void)
-{
-       lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-
-       return (get_HCLK () /
-               (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1)));
-}
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
deleted file mode 100644 (file)
index 33b9269..0000000
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- *  armboot - Startup Code for ARM920 CPU-core
- *
- *  Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:        b       reset
-       ldr     pc, _undefined_instruction
-       ldr     pc, _software_interrupt
-       ldr     pc, _prefetch_abort
-       ldr     pc, _data_abort
-       ldr     pc, _not_used
-       ldr     pc, _irq
-       ldr     pc, _fiq
-
-_undefined_instruction:        .word undefined_instruction
-_software_interrupt:   .word software_interrupt
-_prefetch_abort:       .word prefetch_abort
-_data_abort:           .word data_abort
-_not_used:             .word not_used
-_irq:                  .word irq
-_fiq:                  .word fiq
-
-       .balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-       .word   CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-       .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-       .word __bss_end__ - _start
-
-.globl _end_ofs
-_end_ofs:
-       .word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-       .word   0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-       .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-       .word   0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-       /*
-        * set the cpu to SVC32 mode
-        */
-       mrs     r0,cpsr
-       bic     r0,r0,#0x1f
-       orr     r0,r0,#0xd3
-       msr     cpsr,r0
-
-#define pWDTCTL                0x80001400  /* Watchdog Timer control register */
-#define pINTENC                0x8000050C  /* Interrupt-Controller enable clear register */
-#define pCLKSET                0x80000420  /* clock divisor register */
-
-       /* disable watchdog, set watchdog control register to
-        * all zeros (default reset)
-        */
-       ldr     r0, =pWDTCTL
-       mov     r1, #0x0
-       str     r1, [r0]
-
-       /*
-        * mask all IRQs by setting all bits in the INTENC register (default)
-        */
-       mov     r1, #0xffffffff
-       ldr     r0, =pINTENC
-       str     r1, [r0]
-
-       /* FCLK:HCLK:PCLK = 1:2:2 */
-       /* default FCLK is 200 MHz, using 14.7456 MHz fin */
-       ldr     r0, =pCLKSET
-       ldr r1, =0x0004ee39
-@      ldr r1, =0x0005ee39     @ 1: 2: 4
-       str     r1, [r0]
-
-       /*
-        * we do sys-critical inits only at reboot,
-        * not when booting from ram!
-        */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-       bl      cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-       ldr     sp, =(CONFIG_SYS_INIT_SP_ADDR)
-       bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
-       ldr     r0,=0x00000000
-       bl      board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-       .globl  relocate_code
-relocate_code:
-       mov     r4, r0  /* save addr_sp */
-       mov     r5, r1  /* save addr of gd */
-       mov     r6, r2  /* save addr of destination */
-
-       /* Set up the stack                                                 */
-stack_setup:
-       mov     sp, r4
-
-       adr     r0, _start
-       cmp     r0, r6
-       moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
-       beq     clear_bss               /* skip relocation */
-       mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _bss_start_ofs
-       add     r2, r0, r3              /* r2 <- source end address         */
-
-copy_loop:
-       ldmia   r0!, {r9-r10}           /* copy from source address [r0]    */
-       stmia   r1!, {r9-r10}           /* copy to   target address [r1]    */
-       cmp     r0, r2                  /* until source end address [r2]    */
-       blo     copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-       /*
-        * fix .rel.dyn relocations
-        */
-       ldr     r0, _TEXT_BASE          /* r0 <- Text base */
-       sub     r9, r6, r0              /* r9 <- relocation offset */
-       ldr     r10, _dynsym_start_ofs  /* r10 <- sym table ofs */
-       add     r10, r10, r0            /* r10 <- sym table in FLASH */
-       ldr     r2, _rel_dyn_start_ofs  /* r2 <- rel dyn start ofs */
-       add     r2, r2, r0              /* r2 <- rel dyn start in FLASH */
-       ldr     r3, _rel_dyn_end_ofs    /* r3 <- rel dyn end ofs */
-       add     r3, r3, r0              /* r3 <- rel dyn end in FLASH */
-fixloop:
-       ldr     r0, [r2]                /* r0 <- location to fix up, IN FLASH! */
-       add     r0, r0, r9              /* r0 <- location to fix up in RAM */
-       ldr     r1, [r2, #4]
-       and     r7, r1, #0xff
-       cmp     r7, #23                 /* relative fixup? */
-       beq     fixrel
-       cmp     r7, #2                  /* absolute fixup? */
-       beq     fixabs
-       /* ignore unknown type of fixup */
-       b       fixnext
-fixabs:
-       /* absolute fix: set location to (offset) symbol value */
-       mov     r1, r1, LSR #4          /* r1 <- symbol index in .dynsym */
-       add     r1, r10, r1             /* r1 <- address of symbol in table */
-       ldr     r1, [r1, #4]            /* r1 <- symbol value */
-       add     r1, r1, r9              /* r1 <- relocated sym addr */
-       b       fixnext
-fixrel:
-       /* relative fix: increase location by offset */
-       ldr     r1, [r0]
-       add     r1, r1, r9
-fixnext:
-       str     r1, [r0]
-       add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
-       cmp     r2, r3
-       blo     fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-       ldr     r0, _bss_start_ofs
-       ldr     r1, _bss_end_ofs
-       mov     r4, r6                  /* reloc addr */
-       add     r0, r0, r4
-       add     r1, r1, r4
-       mov     r2, #0x00000000         /* clear                            */
-
-clbss_l:cmp    r0, r1                  /* clear loop... */
-       bhs     clbss_e                 /* if reached end of bss, exit */
-       str     r2, [r0]
-       add     r0, r0, #4
-       b       clbss_l
-clbss_e:
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-       ldr     r0, _board_init_r_ofs
-       adr     r1, _start
-       add     lr, r0, r1
-       add     lr, lr, r9
-       /* setup parameters for board_init_r */
-       mov     r0, r5          /* gd_t */
-       mov     r1, r6          /* dest_addr */
-       /* jump to it ... */
-       mov     pc, lr
-
-_board_init_r_ofs:
-       .word board_init_r - _start
-
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-cpu_init_crit:
-       /*
-        * flush v4 I/D caches
-        */
-       mov     r0, #0
-       mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
-       mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
-
-       /*
-        * disable MMU stuff and caches
-        */
-       mrc     p15, 0, r0, c1, c0, 0
-       bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
-       bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
-       orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
-       orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
-       orr     r0, r0, #0x40000000     @ set bit 30 (nF) notFastBus
-       mcr     p15, 0, r0, c1, c0, 0
-
-
-       /*
-        * before relocating, we have to setup RAM timing
-        * because memory timing is board-dependend, you will
-        * find a lowlevel_init.S in your board directory.
-        */
-       mov     ip, lr
-       bl      lowlevel_init
-       mov     lr, ip
-
-       mov     pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE   72
-
-#define S_OLD_R0       68
-#define S_PSR          64
-#define S_PC           60
-#define S_LR           56
-#define S_SP           52
-
-#define S_IP           48
-#define S_FP           44
-#define S_R10          40
-#define S_R9           36
-#define S_R8           32
-#define S_R7           28
-#define S_R6           24
-#define S_R5           20
-#define S_R4           16
-#define S_R3           12
-#define S_R2           8
-#define S_R1           4
-#define S_R0           0
-
-#define MODE_SVC 0x13
-#define I_BIT   0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-       .macro  bad_save_user_regs
-       sub     sp, sp, #S_FRAME_SIZE
-       stmia   sp, {r0 - r12}                  @ Calling r0-r12
-       ldr     r2, IRQ_STACK_START_IN
-       ldmia   r2, {r2 - r3}                   @ get pc, cpsr
-       add     r0, sp, #S_FRAME_SIZE           @ restore sp_SVC
-
-       add     r5, sp, #S_SP
-       mov     r1, lr
-       stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
-       mov     r0, sp
-       .endm
-
-       .macro  irq_save_user_regs
-       sub     sp, sp, #S_FRAME_SIZE
-       stmia   sp, {r0 - r12}                  @ Calling r0-r12
-       add     r8, sp, #S_PC
-       stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-       str     lr, [r8, #0]                    @ Save calling PC
-       mrs     r6, spsr
-       str     r6, [r8, #4]                    @ Save CPSR
-       str     r0, [r8, #8]                    @ Save OLD_R0
-       mov     r0, sp
-       .endm
-
-       .macro  irq_restore_user_regs
-       ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
-       mov     r0, r0
-       ldr     lr, [sp, #S_PC]                 @ Get PC
-       add     sp, sp, #S_FRAME_SIZE
-       subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
-       .endm
-
-       .macro get_bad_stack
-       ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
-
-       str     lr, [r13]                       @ save caller lr / spsr
-       mrs     lr, spsr
-       str     lr, [r13, #4]
-
-       mov     r13, #MODE_SVC                  @ prepare SVC-Mode
-       @ msr   spsr_c, r13
-       msr     spsr, r13
-       mov     lr, pc
-       movs    pc, lr
-       .endm
-
-       .macro get_irq_stack                    @ setup IRQ stack
-       ldr     sp, IRQ_STACK_START
-       .endm
-
-       .macro get_fiq_stack                    @ setup FIQ stack
-       ldr     sp, FIQ_STACK_START
-       .endm
-
-/*
- * exception handlers
- */
-       .align  5
-undefined_instruction:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_undefined_instruction
-
-       .align  5
-software_interrupt:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_software_interrupt
-
-       .align  5
-prefetch_abort:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_prefetch_abort
-
-       .align  5
-data_abort:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_data_abort
-
-       .align  5
-not_used:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-       .align  5
-irq:
-       get_irq_stack
-       irq_save_user_regs
-       bl      do_irq
-       irq_restore_user_regs
-
-       .align  5
-fiq:
-       get_fiq_stack
-       /* someone ought to write a more effiction fiq_save_user_regs */
-       irq_save_user_regs
-       bl      do_fiq
-       irq_restore_user_regs
-
-#else
-
-       .align  5
-irq:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_irq
-
-       .align  5
-fiq:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_fiq
-
-#endif
-
-       .align  5
-.globl reset_cpu
-reset_cpu:
-       bl      disable_interrupts
-
-       /* Disable watchdog */
-       ldr     r1, =pWDTCTL
-       mov     r3, #0
-       str     r3, [r1]
-
-       /* reset counter */
-       ldr     r3, =0x00001984
-       str     r3, [r1, #4]
-
-       /* Enable the watchdog */
-       mov     r3, #1
-       str     r3, [r1]
-
-_loop_forever:
-       b       _loop_forever
diff --git a/arch/arm/cpu/lh7a40x/timer.c b/arch/arm/cpu/lh7a40x/timer.c
deleted file mode 100644 (file)
index 58b35b1..0000000
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-static ulong timer_load_val = 0;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
-       lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
-       lh7a40x_timer_t* timer = &timers->timer1;
-
-       return (timer->value & 0x0000ffff);
-}
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
-       lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
-       lh7a40x_timer_t* timer = &timers->timer1;
-
-       /* a periodic timer using the 508kHz source */
-       timer->control = (TIMER_PER | TIMER_CLK508K);
-
-       if (timer_load_val == 0) {
-               /*
-                * 10ms period with 508.469kHz clock = 5084
-                */
-               timer_load_val = CONFIG_SYS_HZ/100;
-       }
-
-       /* load value for 10 ms timeout */
-       lastdec = timer->load = timer_load_val;
-
-       /* auto load, start timer */
-       timer->control = timer->control | TIMER_EN;
-       timestamp = 0;
-
-       return (0);
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-       return (get_timer_masked() - base);
-}
-
-void __udelay (unsigned long usec)
-{
-       ulong tmo,tmp;
-
-       /* normalize */
-       if (usec >= 1000) {
-               tmo = usec / 1000;
-               tmo *= CONFIG_SYS_HZ;
-               tmo /= 1000;
-       }
-       else {
-               if (usec > 1) {
-                       tmo = usec * CONFIG_SYS_HZ;
-                       tmo /= (1000*1000);
-               }
-               else
-                       tmo = 1;
-       }
-
-       /* check for rollover during this delay */
-       tmp = get_timer (0);
-       if ((tmp + tmo) < tmp )
-               reset_timer_masked();  /* timer would roll over */
-       else
-               tmo += tmp;
-
-       while (get_timer_masked () < tmo);
-}
-
-void reset_timer_masked (void)
-{
-       /* reset time */
-       lastdec = READ_TIMER();
-       timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
-       ulong now = READ_TIMER();
-
-       if (lastdec >= now) {
-               /* normal mode */
-               timestamp += (lastdec - now);
-       } else {
-               /* we have an overflow ... */
-               timestamp += ((lastdec + timer_load_val) - now);
-       }
-       lastdec = now;
-
-       return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-       ulong tmo;
-       ulong endtime;
-       signed long diff;
-
-       /* normalize */
-       if (usec >= 1000) {
-               tmo = usec / 1000;
-               tmo *= CONFIG_SYS_HZ;
-               tmo /= 1000;
-       } else {
-               if (usec > 1) {
-                       tmo = usec * CONFIG_SYS_HZ;
-                       tmo /= (1000*1000);
-               } else {
-                       tmo = 1;
-               }
-       }
-
-       endtime = get_timer_masked () + tmo;
-
-       do {
-               ulong now = get_timer_masked ();
-               diff = endtime - now;
-       } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-       return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-       ulong tbclk;
-
-       tbclk = timer_load_val * 100;
-
-       return tbclk;
-}
index e49ca0c5522912ba8849182105cf141e04d0c6b3..1996b975360ef5da7f2b95527ce60cbf1334f594 100644 (file)
@@ -34,8 +34,8 @@ SECTIONS
        .text :
        {
                __image_copy_start = .;
-               CPUDIR/start.o (.text)
-               *(.text)
+               CPUDIR/start.o (.text*)
+               *(.text*)
        }
 
        . = ALIGN(4);
@@ -43,15 +43,17 @@ SECTIONS
 
        . = ALIGN(4);
        .data : {
-               *(.data)
+               *(.data*)
        }
 
        . = ALIGN(4);
 
        . = .;
-       __u_boot_cmd_start = .;
-       .u_boot_cmd : { *(.u_boot_cmd) }
-       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+       #include <u-boot.lst>
+       }
 
        . = ALIGN(4);
 
@@ -81,7 +83,7 @@ SECTIONS
 
        .bss __rel_dyn_start (OVERLAY) : {
                __bss_start = .;
-               *(.bss)
+               *(.bss*)
                 . = ALIGN(4);
                __bss_end__ = .;
        }
index 02fe72ed7faa2f418ad85bf7eabc2ea906c74b90..ddc14b099e6cdd4e46dbfe83bd0f1025bcebd0f9 100644 (file)
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/imx-common/boot_mode.h>
 #include <malloc.h>
+#include <command.h>
 
 static const struct boot_mode *modes[2];
 
@@ -103,9 +104,11 @@ void add_board_boot_modes(const struct boot_mode *p)
        int size;
        char *dest;
 
-       if (__u_boot_cmd_bmode.usage) {
-               free(__u_boot_cmd_bmode.usage);
-               __u_boot_cmd_bmode.usage = NULL;
+       cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
+
+       if (entry->usage) {
+               free(entry->usage);
+               entry->usage = NULL;
        }
 
        modes[0] = p;
@@ -114,6 +117,6 @@ void add_board_boot_modes(const struct boot_mode *p)
        dest = malloc(size);
        if (dest) {
                create_usage(dest);
-               __u_boot_cmd_bmode.usage = dest;
+               entry->usage = dest;
        }
 }
index 6cfbef76a79236130add2df5de3aa5f8a662e4e2..819fd2f026900bf82491035b4e513fc9b84f8e46 100644 (file)
@@ -169,6 +169,12 @@ struct cm_dpll {
        unsigned int clktimer2clk;      /* offset 0x08 */
 };
 
+/* Control Module RTC registers */
+struct cm_rtc {
+       unsigned int rtcclkctrl;        /* offset 0x0 */
+       unsigned int clkstctrl;         /* offset 0x4 */
+};
+
 /* Watchdog timer registers */
 struct wd_timer {
        unsigned int resv1[4];
@@ -218,6 +224,15 @@ struct gptimer {
        unsigned int tcar2;             /* offset 0x58 */
 };
 
+/* RTC Registers */
+struct rtc_regs {
+       unsigned int res[21];
+       unsigned int osc;               /* offset 0x54 */
+       unsigned int res2[5];
+       unsigned int kick0r;            /* offset 0x6c */
+       unsigned int kick1r;            /* offset 0x70 */
+};
+
 /* UART Registers */
 struct uart_sys {
        unsigned int resv1[21];
index 6b22c45f77525380883835ec5a151424e6ad9db3..8e69fb67b14bf53b85b263a551862c3cf434507a 100644 (file)
 #define PHY_DLL_LOCK_DIFF      0x0
 #define DDR_CKE_CTRL_NORMAL    0x1
 
-#define DDR2_EMIF_READ_LATENCY 0x100005        /* Enable Dynamic Power Down */
-#define DDR2_EMIF_TIM1         0x0666B3C9
-#define DDR2_EMIF_TIM2         0x243631CA
-#define DDR2_EMIF_TIM3         0x0000033F
-#define DDR2_EMIF_SDCFG                0x41805332
-#define DDR2_EMIF_SDREF                0x0000081a
-#define DDR2_DLL_LOCK_DIFF     0x0
-#define DDR2_RATIO             0x80
-#define DDR2_INVERT_CLKOUT     0x00
-#define DDR2_RD_DQS            0x12
-#define DDR2_WR_DQS            0x00
-#define DDR2_PHY_WRLVL         0x00
-#define DDR2_PHY_GATELVL       0x00
-#define DDR2_PHY_WR_DATA       0x40
-#define DDR2_PHY_FIFO_WE       0x80
-#define DDR2_PHY_RANK0_DELAY   0x1
-#define DDR2_IOCTRL_VALUE      0x18B
+/* Micron MT47H128M16RT-25E */
+#define MT47H128M16RT25E_EMIF_READ_LATENCY     0x100005
+#define MT47H128M16RT25E_EMIF_TIM1             0x0666B3C9
+#define MT47H128M16RT25E_EMIF_TIM2             0x243631CA
+#define MT47H128M16RT25E_EMIF_TIM3             0x0000033F
+#define MT47H128M16RT25E_EMIF_SDCFG            0x41805332
+#define MT47H128M16RT25E_EMIF_SDREF            0x0000081a
+#define MT47H128M16RT25E_DLL_LOCK_DIFF         0x0
+#define MT47H128M16RT25E_RATIO                 0x80
+#define MT47H128M16RT25E_INVERT_CLKOUT         0x00
+#define MT47H128M16RT25E_RD_DQS                        0x12
+#define MT47H128M16RT25E_WR_DQS                        0x00
+#define MT47H128M16RT25E_PHY_WRLVL             0x00
+#define MT47H128M16RT25E_PHY_GATELVL           0x00
+#define MT47H128M16RT25E_PHY_WR_DATA           0x40
+#define MT47H128M16RT25E_PHY_FIFO_WE           0x80
+#define MT47H128M16RT25E_PHY_RANK0_DELAY               0x1
+#define MT47H128M16RT25E_IOCTRL_VALUE          0x18B
 
 /* Micron MT41J128M16JT-125 */
-#define DDR3_EMIF_READ_LATENCY 0x06
-#define DDR3_EMIF_TIM1         0x0888A39B
-#define DDR3_EMIF_TIM2         0x26337FDA
-#define DDR3_EMIF_TIM3         0x501F830F
-#define DDR3_EMIF_SDCFG                0x61C04AB2
-#define DDR3_EMIF_SDREF                0x0000093B
-#define DDR3_ZQ_CFG            0x50074BE4
-#define DDR3_DLL_LOCK_DIFF     0x1
-#define DDR3_RATIO             0x40
-#define DDR3_INVERT_CLKOUT     0x1
-#define DDR3_RD_DQS            0x3B
-#define DDR3_WR_DQS            0x85
-#define DDR3_PHY_WR_DATA       0xC1
-#define DDR3_PHY_FIFO_WE       0x100
-#define DDR3_IOCTRL_VALUE      0x18B
+#define MT41J128MJT125_EMIF_READ_LATENCY       0x06
+#define MT41J128MJT125_EMIF_TIM1               0x0888A39B
+#define MT41J128MJT125_EMIF_TIM2               0x26337FDA
+#define MT41J128MJT125_EMIF_TIM3               0x501F830F
+#define MT41J128MJT125_EMIF_SDCFG              0x61C04AB2
+#define MT41J128MJT125_EMIF_SDREF              0x0000093B
+#define MT41J128MJT125_ZQ_CFG                  0x50074BE4
+#define MT41J128MJT125_DLL_LOCK_DIFF           0x1
+#define MT41J128MJT125_RATIO                   0x40
+#define MT41J128MJT125_INVERT_CLKOUT           0x1
+#define MT41J128MJT125_RD_DQS                  0x3B
+#define MT41J128MJT125_WR_DQS                  0x85
+#define MT41J128MJT125_PHY_WR_DATA             0xC1
+#define MT41J128MJT125_PHY_FIFO_WE             0x100
+#define MT41J128MJT125_IOCTRL_VALUE            0x18B
 
 /**
  * Configure SDRAM
@@ -189,6 +190,8 @@ struct ddr_ctrl {
        unsigned int ddrckectrl;
 };
 
-void config_ddr(short ddr_type);
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+               const struct ddr_data *data, const struct cmd_control *ctrl,
+               const struct emif_regs *regs);
 
 #endif  /* _DDR_DEFS_H */
index 62332f2ded54dcb70e362025b4c22253a86df00f..5bd4bc8722016e04c86fe0e4b33daeafaa1d9454 100644 (file)
@@ -61,6 +61,7 @@
 #define CM_WKUP                                0x44E00400
 #define CM_DPLL                                0x44E00500
 #define CM_DEVICE                      0x44E00700
+#define CM_RTC                         0x44E00800
 #define CM_CEFUSE                      0x44E00A00
 #define PRM_DEVICE                     0x44E00F00
 
@@ -83,4 +84,7 @@
 #define AM335X_CPSW_BASE               0x4A100000
 #define AM335X_CPSW_MDIO_BASE          0x4A101000
 
+/* RTC base address */
+#define AM335X_RTC_BASE                        0x44E3E000
+
 #endif /* __AM33XX_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
new file mode 100644 (file)
index 0000000..aed6b00
--- /dev/null
@@ -0,0 +1,261 @@
+/*
+ * mux.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_H_
+#define _MUX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset) \
+       __raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL       (0x1 << 6)
+#define RXACTIVE       (0x1 << 5)
+#define PULLUP_EN      (0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN       (0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS      (0x1 << 3) /* Pull up disabled */
+#define MODE(val)      val     /* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+       int gpmc_ad0;
+       int gpmc_ad1;
+       int gpmc_ad2;
+       int gpmc_ad3;
+       int gpmc_ad4;
+       int gpmc_ad5;
+       int gpmc_ad6;
+       int gpmc_ad7;
+       int gpmc_ad8;
+       int gpmc_ad9;
+       int gpmc_ad10;
+       int gpmc_ad11;
+       int gpmc_ad12;
+       int gpmc_ad13;
+       int gpmc_ad14;
+       int gpmc_ad15;
+       int gpmc_a0;
+       int gpmc_a1;
+       int gpmc_a2;
+       int gpmc_a3;
+       int gpmc_a4;
+       int gpmc_a5;
+       int gpmc_a6;
+       int gpmc_a7;
+       int gpmc_a8;
+       int gpmc_a9;
+       int gpmc_a10;
+       int gpmc_a11;
+       int gpmc_wait0;
+       int gpmc_wpn;
+       int gpmc_be1n;
+       int gpmc_csn0;
+       int gpmc_csn1;
+       int gpmc_csn2;
+       int gpmc_csn3;
+       int gpmc_clk;
+       int gpmc_advn_ale;
+       int gpmc_oen_ren;
+       int gpmc_wen;
+       int gpmc_be0n_cle;
+       int lcd_data0;
+       int lcd_data1;
+       int lcd_data2;
+       int lcd_data3;
+       int lcd_data4;
+       int lcd_data5;
+       int lcd_data6;
+       int lcd_data7;
+       int lcd_data8;
+       int lcd_data9;
+       int lcd_data10;
+       int lcd_data11;
+       int lcd_data12;
+       int lcd_data13;
+       int lcd_data14;
+       int lcd_data15;
+       int lcd_vsync;
+       int lcd_hsync;
+       int lcd_pclk;
+       int lcd_ac_bias_en;
+       int mmc0_dat3;
+       int mmc0_dat2;
+       int mmc0_dat1;
+       int mmc0_dat0;
+       int mmc0_clk;
+       int mmc0_cmd;
+       int mii1_col;
+       int mii1_crs;
+       int mii1_rxerr;
+       int mii1_txen;
+       int mii1_rxdv;
+       int mii1_txd3;
+       int mii1_txd2;
+       int mii1_txd1;
+       int mii1_txd0;
+       int mii1_txclk;
+       int mii1_rxclk;
+       int mii1_rxd3;
+       int mii1_rxd2;
+       int mii1_rxd1;
+       int mii1_rxd0;
+       int rmii1_refclk;
+       int mdio_data;
+       int mdio_clk;
+       int spi0_sclk;
+       int spi0_d0;
+       int spi0_d1;
+       int spi0_cs0;
+       int spi0_cs1;
+       int ecap0_in_pwm0_out;
+       int uart0_ctsn;
+       int uart0_rtsn;
+       int uart0_rxd;
+       int uart0_txd;
+       int uart1_ctsn;
+       int uart1_rtsn;
+       int uart1_rxd;
+       int uart1_txd;
+       int i2c0_sda;
+       int i2c0_scl;
+       int mcasp0_aclkx;
+       int mcasp0_fsx;
+       int mcasp0_axr0;
+       int mcasp0_ahclkr;
+       int mcasp0_aclkr;
+       int mcasp0_fsr;
+       int mcasp0_axr1;
+       int mcasp0_ahclkx;
+       int xdma_event_intr0;
+       int xdma_event_intr1;
+       int nresetin_out;
+       int porz;
+       int nnmi;
+       int osc0_in;
+       int osc0_out;
+       int rsvd1;
+       int tms;
+       int tdi;
+       int tdo;
+       int tck;
+       int ntrst;
+       int emu0;
+       int emu1;
+       int osc1_in;
+       int osc1_out;
+       int pmic_power_en;
+       int rtc_porz;
+       int rsvd2;
+       int ext_wakeup;
+       int enz_kaldo_1p8v;
+       int usb0_dm;
+       int usb0_dp;
+       int usb0_ce;
+       int usb0_id;
+       int usb0_vbus;
+       int usb0_drvvbus;
+       int usb1_dm;
+       int usb1_dp;
+       int usb1_ce;
+       int usb1_id;
+       int usb1_vbus;
+       int usb1_drvvbus;
+       int ddr_resetn;
+       int ddr_csn0;
+       int ddr_cke;
+       int ddr_ck;
+       int ddr_nck;
+       int ddr_casn;
+       int ddr_rasn;
+       int ddr_wen;
+       int ddr_ba0;
+       int ddr_ba1;
+       int ddr_ba2;
+       int ddr_a0;
+       int ddr_a1;
+       int ddr_a2;
+       int ddr_a3;
+       int ddr_a4;
+       int ddr_a5;
+       int ddr_a6;
+       int ddr_a7;
+       int ddr_a8;
+       int ddr_a9;
+       int ddr_a10;
+       int ddr_a11;
+       int ddr_a12;
+       int ddr_a13;
+       int ddr_a14;
+       int ddr_a15;
+       int ddr_odt;
+       int ddr_d0;
+       int ddr_d1;
+       int ddr_d2;
+       int ddr_d3;
+       int ddr_d4;
+       int ddr_d5;
+       int ddr_d6;
+       int ddr_d7;
+       int ddr_d8;
+       int ddr_d9;
+       int ddr_d10;
+       int ddr_d11;
+       int ddr_d12;
+       int ddr_d13;
+       int ddr_d14;
+       int ddr_d15;
+       int ddr_dqm0;
+       int ddr_dqm1;
+       int ddr_dqs0;
+       int ddr_dqsn0;
+       int ddr_dqs1;
+       int ddr_dqsn1;
+       int ddr_vref;
+       int ddr_vtp;
+       int ddr_strben0;
+       int ddr_strben1;
+       int ain7;
+       int ain6;
+       int ain5;
+       int ain4;
+       int ain3;
+       int ain2;
+       int ain1;
+       int ain0;
+       int vrefp;
+       int vrefn;
+};
+
+struct module_pin_mux {
+       short reg_offset;
+       unsigned char val;
+};
+
+/* Pad control register offset */
+#define PAD_CTRL_BASE  0x800
+#define OFFSET(x)      (unsigned int) (&((struct pad_signals *) \
+                               (PAD_CTRL_BASE))->x)
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
+
+#endif
index 63ed10b257a01cacccc85858ffa6e09e116f80d1..644ff353febdfea316bc6d0978995367743faa82 100644 (file)
@@ -27,6 +27,7 @@
 #define BOOT_DEVICE_NAND       5
 #define BOOT_DEVICE_MMC1       8
 #define BOOT_DEVICE_MMC2       9       /* eMMC or daughter card */
+#define BOOT_DEVICE_SPI                11
 #define BOOT_DEVICE_UART       65
 #define BOOT_DEVICE_CPGMAC     70
 #define BOOT_DEVICE_MMC2_2      0xFF
index 819ea650f00245069f5b93617de43e2d52c8834c..9cf35e0257838bb5cfca49cc885b86e25fed1cd8 100644 (file)
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-/*
- * AM335x parts define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR     3
-#define HDR_ETH_ALEN           6
-#define HDR_NAME_LEN           8
-
-struct am335x_baseboard_id {
-       unsigned int  magic;
-       char name[HDR_NAME_LEN];
-       char version[4];
-       char serial[12];
-       char config[32];
-       char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
 #define BOARD_REV_ID   0x0
 
 u32 get_cpu_rev(void);
@@ -51,13 +33,4 @@ u32 get_device_type(void);
 void setup_clocks_for_console(void);
 void ddr_pll_config(unsigned int ddrpll_M);
 
-/*
- * We have three pin mux functions that must exist.  We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(struct am335x_baseboard_id *header);
 #endif
index 0a357b1e0a42825270cdc36fa282719849a0b4d3..0a766108a610b89c1033c1da65957727ec5e0513 100644 (file)
@@ -24,9 +24,7 @@
  * MA 02111-1307 USA
  */
 
-#if defined(CONFIG_NETARM)
-#include <asm/arch-arm720t/netarm_registers.h>
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 /* include IntegratorCP/CM720T specific hardware file if there was one */
 #else
 #error No hardware file defined for this configuration
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h b/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h
deleted file mode 100644 (file)
index 328eaf0..0000000
+++ /dev/null
@@ -1,182 +0,0 @@
-/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *             David Smith
- */
-
-#ifndef __NETARM_DMA_MODULE_REGISTERS_H
-#define __NETARM_DMA_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define        NETARM_DMA_MODULE_BASE          (0xFF900000)
-
-#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c)))
-
-#define        NETARM_DMA1A_BFR_DESCRPTOR_PTR  (0x00)
-#define        NETARM_DMA1A_CONTROL            (0x10)
-#define        NETARM_DMA1A_STATUS             (0x14)
-#define        NETARM_DMA1B_BFR_DESCRPTOR_PTR  (0x20)
-#define        NETARM_DMA1B_CONTROL            (0x30)
-#define        NETARM_DMA1B_STATUS             (0x34)
-#define        NETARM_DMA1C_BFR_DESCRPTOR_PTR  (0x40)
-#define        NETARM_DMA1C_CONTROL            (0x50)
-#define        NETARM_DMA1C_STATUS             (0x54)
-#define        NETARM_DMA1D_BFR_DESCRPTOR_PTR  (0x60)
-#define        NETARM_DMA1D_CONTROL            (0x70)
-#define        NETARM_DMA1D_STATUS             (0x74)
-
-#define        NETARM_DMA2_BFR_DESCRPTOR_PTR   (0x80)
-#define        NETARM_DMA2_CONTROL             (0x90)
-#define        NETARM_DMA2_STATUS              (0x94)
-
-#define        NETARM_DMA3_BFR_DESCRPTOR_PTR   (0xA0)
-#define        NETARM_DMA3_CONTROL             (0xB0)
-#define        NETARM_DMA3_STATUS              (0xB4)
-
-#define        NETARM_DMA4_BFR_DESCRPTOR_PTR   (0xC0)
-#define        NETARM_DMA4_CONTROL             (0xD0)
-#define        NETARM_DMA4_STATUS              (0xD4)
-
-#define        NETARM_DMA5_BFR_DESCRPTOR_PTR   (0xE0)
-#define        NETARM_DMA5_CONTROL             (0xF0)
-#define        NETARM_DMA5_STATUS              (0xF4)
-
-#define        NETARM_DMA6_BFR_DESCRPTOR_PTR   (0x100)
-#define        NETARM_DMA6_CONTROL             (0x110)
-#define        NETARM_DMA6_STATUS              (0x114)
-
-#define        NETARM_DMA7_BFR_DESCRPTOR_PTR   (0x120)
-#define        NETARM_DMA7_CONTROL             (0x130)
-#define        NETARM_DMA7_STATUS              (0x134)
-
-#define        NETARM_DMA8_BFR_DESCRPTOR_PTR   (0x140)
-#define        NETARM_DMA8_CONTROL             (0x150)
-#define        NETARM_DMA8_STATUS              (0x154)
-
-#define        NETARM_DMA9_BFR_DESCRPTOR_PTR   (0x160)
-#define        NETARM_DMA9_CONTROL             (0x170)
-#define        NETARM_DMA9_STATUS              (0x174)
-
-#define        NETARM_DMA10_BFR_DESCRPTOR_PTR  (0x180)
-#define        NETARM_DMA10_CONTROL            (0x190)
-#define        NETARM_DMA10_STATUS             (0x194)
-
-/* select bitfield defintions */
-
-/* DMA Control Register ( 0xFF90_0XX0 ) */
-
-#define NETARM_DMA_CTL_ENABLE          (0x80000000)
-
-#define NETARM_DMA_CTL_ABORT           (0x40000000)
-
-#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000)
-#define NETARM_DMA_CTL_BUS_75_PERCENT  (0x10000000)
-#define NETARM_DMA_CTL_BUS_50_PERCENT  (0x20000000)
-#define NETARM_DMA_CTL_BUS_25_PERCENT  (0x30000000)
-
-#define NETARM_DMA_CTL_BUS_MASK                (0x30000000)
-
-#define NETARM_DMA_CTL_MODE_FB_TO_MEM  (0x00000000)
-#define NETARM_DMA_CTL_MODE_FB_FROM_MEM        (0x04000000)
-#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000)
-
-#define NETARM_DMA_CTL_BURST_NONE      (0x00000000)
-#define NETARM_DMA_CTL_BURST_8_BYTE    (0x01000000)
-#define NETARM_DMA_CTL_BURST_16_BYTE   (0x02000000)
-
-#define NETARM_DMA_CTL_BURST_MASK      (0x03000000)
-
-#define NETARM_DMA_CTL_SRC_INCREMENT   (0x00200000)
-
-#define NETARM_DMA_CTL_DST_INCREMENT   (0x00100000)
-
-/* these apply only to ext xfers on DMA 3 or 4 */
-
-#define NETARM_DMA_CTL_CH_3_4_REQ_EXT  (0x00800000)
-
-#define NETARM_DMA_CTL_CH_3_4_DATA_32  (0x00000000)
-#define NETARM_DMA_CTL_CH_3_4_DATA_16  (0x00010000)
-#define NETARM_DMA_CTL_CH_3_4_DATA_8   (0x00020000)
-
-#define NETARM_DMA_CTL_STATE(X)        ((X) & 0xFC00)
-#define NETARM_DMA_CTL_INDEX(X)        ((X) & 0x03FF)
-
-/* DMA Status Register ( 0xFF90_0XX4 ) */
-
-#define NETARM_DMA_STAT_NC_INTPEN      (0x80000000)
-#define NETARM_DMA_STAT_EC_INTPEN      (0x40000000)
-#define NETARM_DMA_STAT_NR_INTPEN      (0x20000000)
-#define NETARM_DMA_STAT_CA_INTPEN      (0x10000000)
-#define NETARM_DMA_STAT_INTPEN_MASK    (0xF0000000)
-
-#define NETARM_DMA_STAT_NC_INT_EN      (0x00800000)
-#define NETARM_DMA_STAT_EC_INT_EN      (0x00400000)
-#define NETARM_DMA_STAT_NR_INT_EN      (0x00200000)
-#define NETARM_DMA_STAT_CA_INT_EN      (0x00100000)
-#define NETARM_DMA_STAT_INT_EN_MASK    (0x00F00000)
-
-#define NETARM_DMA_STAT_WRAP           (0x00080000)
-#define NETARM_DMA_STAT_IDONE          (0x00040000)
-#define NETARM_DMA_STAT_LAST           (0x00020000)
-#define NETARM_DMA_STAT_FULL           (0x00010000)
-
-#define        NETARM_DMA_STAT_BUFLEN(X)       ((X) & 0x7FFF)
-
-/* DMA Buffer Descriptor Word 0 bitfields. */
-
-#define NETARM_DMA_BD0_WRAP            (0x80000000)
-#define NETARM_DMA_BD0_IDONE           (0x40000000)
-#define NETARM_DMA_BD0_LAST            (0x20000000)
-#define NETARM_DMA_BD0_BUFPTR_MASK     (0x1FFFFFFF)
-
-/* DMA Buffer Descriptor Word 1 bitfields. */
-
-#define NETARM_DMA_BD1_STATUS_MASK     (0xFFFF0000)
-#define NETARM_DMA_BD1_FULL            (0x00008000)
-#define NETARM_DMA_BD1_BUFLEN_MASK     (0x00007FFF)
-
-#ifndef        __ASSEMBLER__
-
-typedef        struct __NETARM_DMA_Buff_Desc_FlyBy
-{
-       unsigned int word0;
-       unsigned int word1;
-} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ;
-
-typedef        struct __NETARM_DMA_Buff_Desc_M_to_M
-{
-       unsigned int word0;
-       unsigned int word1;
-       unsigned int word2;
-       unsigned int word3;
-} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ;
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h
deleted file mode 100644 (file)
index 317b354..0000000
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_eni_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : David Smith
- */
-
-#ifndef __NETARM_ENI_MODULE_REGISTERS_H
-#define __NETARM_ENI_MODULE_REGISTERS_H
-
-/* ENI unit register offsets */
-
-/* #ifdef CONFIG_ARCH_NETARM */
-#define        NETARM_ENI_MODULE_BASE          (0xFFA00000)
-/* #endif / * CONFIG_ARCH_NETARM */
-
-#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c)))
-#define get_eni_ctl_reg_addr(minor) \
-       (get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor))
-
-#define        NETARM_ENI_GENERAL_CONTROL      (0x00)
-#define        NETARM_ENI_STATUS_CONTROL       (0x04)
-#define        NETARM_ENI_FIFO_MODE_DATA       (0x08)
-
-#define        NETARM_ENI_1284_PORT1_CONTROL   (0x10)
-#define        NETARM_ENI_1284_PORT2_CONTROL   (0x14)
-#define        NETARM_ENI_1284_PORT3_CONTROL   (0x18)
-#define        NETARM_ENI_1284_PORT4_CONTROL   (0x1c)
-
-#define        NETARM_ENI_1284_CHANNEL1_DATA   (0x20)
-#define        NETARM_ENI_1284_CHANNEL2_DATA   (0x24)
-#define        NETARM_ENI_1284_CHANNEL3_DATA   (0x28)
-#define        NETARM_ENI_1284_CHANNEL4_DATA   (0x2c)
-
-#define        NETARM_ENI_ENI_CONTROL          (0x30)
-#define        NETARM_ENI_ENI_PULSED_INTR      (0x34)
-#define        NETARM_ENI_ENI_SHARED_RAM_ADDR  (0x38)
-#define        NETARM_ENI_ENI_SHARED           (0x3c)
-
-/* select bitfield defintions */
-
-/* General Control Register (0xFFA0_0000) */
-
-#define NETARM_ENI_GCR_ENIMODE_IEEE1284        (0x00000001)
-#define NETARM_ENI_GCR_ENIMODE_SHRAM16 (0x00000004)
-#define NETARM_ENI_GCR_ENIMODE_SHRAM8  (0x00000005)
-#define NETARM_ENI_GCR_ENIMODE_FIFO16  (0x00000006)
-#define NETARM_ENI_GCR_ENIMODE_FIFO8   (0x00000007)
-
-#define NETARM_ENI_GCR_ENIMODE_MASK    (0x00000007)
-
-/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014,
-   0xFFA0_0018, 0xFFA0_001c) */
-
-#define NETARM_ENI_1284PC_PORT_ENABLE  (0x80000000)
-#define NETARM_ENI_1284PC_DMA_ENABLE   (0x40000000)
-#define NETARM_ENI_1284PC_OBE_INT_EN   (0x20000000)
-#define NETARM_ENI_1284PC_ACK_INT_EN   (0x10000000)
-#define NETARM_ENI_1284PC_ECP_MODE     (0x08000000)
-#define NETARM_ENI_1284PC_LOOPBACK_MODE        (0x04000000)
-
-#define NETARM_ENI_1284PC_STROBE_TIME0 (0x00000000) /* 0.5 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME1 (0x01000000) /* 1.0 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME2 (0x02000000) /* 5.0 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME3 (0x03000000) /* 10.0 uS */
-#define NETARM_ENI_1284PC_STROBE_MASK  (0x03000000)
-
-#define NETARM_ENI_1284PC_MAN_STROBE_EN        (0x00800000)
-#define NETARM_ENI_1284PC_FAST_MODE    (0x00400000)
-#define NETARM_ENI_1284PC_BIDIR_MODE   (0x00200000)
-
-#define NETARM_ENI_1284PC_MAN_STROBE   (0x00080000)
-#define NETARM_ENI_1284PC_AUTO_FEED    (0x00040000)
-#define NETARM_ENI_1284PC_INIT         (0x00020000)
-#define NETARM_ENI_1284PC_HSELECT      (0x00010000)
-#define NETARM_ENI_1284PC_FE_INT_EN    (0x00008000)
-#define NETARM_ENI_1284PC_EPP_MODE     (0x00004000)
-#define NETARM_ENI_1284PC_IBR_INT_EN   (0x00002000)
-#define NETARM_ENI_1284PC_IBR          (0x00001000)
-
-#define NETARM_ENI_1284PC_RXFDB_1BYTE  (0x00000400)
-#define NETARM_ENI_1284PC_RXFDB_2BYTE  (0x00000800)
-#define NETARM_ENI_1284PC_RXFDB_3BYTE  (0x00000c00)
-#define NETARM_ENI_1284PC_RXFDB_4BYTE  (0x00000000)
-
-#define NETARM_ENI_1284PC_RBCC         (0x00000200)
-#define NETARM_ENI_1284PC_RBCT         (0x00000100)
-#define NETARM_ENI_1284PC_ACK          (0x00000080)
-#define NETARM_ENI_1284PC_FIFO_E       (0x00000040)
-#define NETARM_ENI_1284PC_OBE          (0x00000020)
-#define NETARM_ENI_1284PC_ACK_INT      (0x00000010)
-#define NETARM_ENI_1284PC_BUSY         (0x00000008)
-#define NETARM_ENI_1284PC_PE           (0x00000004)
-#define NETARM_ENI_1284PC_PSELECT      (0x00000002)
-#define NETARM_ENI_1284PC_FAULT                (0x00000001)
-
-#endif /* __NETARM_ENI_MODULE_REGISTERS_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h
deleted file mode 100644 (file)
index 8f2f369..0000000
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_eth_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Jackie Smith Cashion
- *             David Smith
- */
-
-#ifndef __NETARM_ETH_MODULE_REGISTERS_H
-#define __NETARM_ETH_MODULE_REGISTERS_H
-
-/* ETH unit register offsets */
-
-#define        NETARM_ETH_MODULE_BASE          (0xFF800000)
-
-#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c)))
-
-#define NETARM_ETH_GEN_CTRL            (0x000) /* Ethernet Gen Control Reg */
-#define NETARM_ETH_GEN_STAT            (0x004) /* Ethernet Gen Status Reg */
-#define NETARM_ETH_FIFO_DAT1            (0x008) /* Fifo Data Reg 1 */
-#define NETARM_ETH_FIFO_DAT2            (0x00C) /* Fifo Data Reg 2 */
-#define NETARM_ETH_TX_STAT              (0x010) /* Transmit Status Reg */
-#define NETARM_ETH_RX_STAT              (0x014) /* Receive Status Reg */
-
-#define NETARM_ETH_MAC_CFG             (0x400) /* MAC Configuration Reg */
-#define NETARM_ETH_PCS_CFG             (0x408) /* PCS Configuration Reg */
-#define NETARM_ETH_STL_CFG             (0x410) /* STL Configuration Reg */
-#define NETARM_ETH_B2B_IPG_GAP_TMR     (0x440) /* Back-to-back IPG
-                                                  Gap Timer Reg */
-#define NETARM_ETH_NB2B_IPG_GAP_TMR    (0x444) /* Non Back-to-back
-                                                  IPG Gap Timer Reg */
-#define NETARM_ETH_MII_CMD             (0x540) /* MII (PHY) Command Reg */
-#define NETARM_ETH_MII_ADDR            (0x544) /* MII Address Reg */
-#define NETARM_ETH_MII_WRITE           (0x548) /* MII Write Data Reg */
-#define NETARM_ETH_MII_READ            (0x54C) /* MII Read Data Reg */
-#define NETARM_ETH_MII_IND             (0x550) /* MII Indicators Reg */
-#define NETARM_ETH_MIB_CRCEC           (0x580) /* (MIB) CRC Error Counter */
-#define NETARM_ETH_MIB_AEC             (0x584) /* Alignment Error Counter */
-#define NETARM_ETH_MIB_CEC             (0x588) /* Code Error Counter */
-#define NETARM_ETH_MIB_LFC             (0x58C) /* Long Frame Counter */
-#define NETARM_ETH_MIB_SFC             (0x590) /* Short Frame Counter */
-#define NETARM_ETH_MIB_LCC             (0x594) /* Late Collision Counter */
-#define NETARM_ETH_MIB_EDC             (0x598) /* Excessive Deferral
-                                                  Counter */
-#define NETARM_ETH_MIB_MCC             (0x59C) /* Maximum Collision Counter */
-#define NETARM_ETH_SAL_FILTER          (0x5C0) /* SAL Station Address
-                                                  Filter Reg */
-#define NETARM_ETH_SAL_STATION_ADDR_1  (0x5C4) /* SAL Station Address
-                                                  Reg */
-#define NETARM_ETH_SAL_STATION_ADDR_2  (0x5C8)
-#define NETARM_ETH_SAL_STATION_ADDR_3  (0x5CC)
-#define NETARM_ETH_SAL_HASH_TBL_1      (0x5D0) /* SAL Multicast Hash Table*/
-#define NETARM_ETH_SAL_HASH_TBL_2      (0x5D4)
-#define NETARM_ETH_SAL_HASH_TBL_3      (0x5D8)
-#define NETARM_ETH_SAL_HASH_TBL_4      (0x5DC)
-
-/* select bitfield defintions */
-
-/* Ethernet General Control Register (0xFF80_0000) */
-
-#define NETARM_ETH_GCR_ERX             (0x80000000) /* Enable Receive FIFO */
-#define NETARM_ETH_GCR_ERXDMA          (0x40000000) /* Enable Receive DMA */
-#define NETARM_ETH_GCR_ETX             (0x00800000) /* Enable Transmit FIFO */
-#define NETARM_ETH_GCR_ETXDMA          (0x00400000) /* Enable Transmit DMA */
-#define NETARM_ETH_GCR_ETXWM_50                (0x00100000) /* Transmit FIFO Water
-                                                       Mark.  Start transmit
-                                                       when FIFO is 50%
-                                                       full. */
-#define NETARM_ETH_GCR_PNA             (0x00000400) /* pSOS pNA Buffer
-                                                       Descriptor Format */
-
-/* Ethernet General Status Register (0xFF80_0004) */
-
-#define NETARM_ETH_GST_RXFDB            (0x30000000)
-#define NETARM_ETH_GST_RXREGR          (0x08000000) /* Receive Register
-                                                       Ready */
-#define NETARM_ETH_GST_RXFIFOH         (0x04000000)
-#define NETARM_ETH_GST_RXBR            (0x02000000)
-#define NETARM_ETH_GST_RXSKIP          (0x01000000)
-
-#define NETARM_ETH_GST_TXBC             (0x00020000)
-
-
-/* Ethernet Transmit Status Register (0xFF80_0010) */
-
-#define NETARM_ETH_TXSTAT_TXOK          (0x00008000)
-
-
-/* Ethernet Receive Status Register (0xFF80_0014) */
-
-#define NETARM_ETH_RXSTAT_SIZE          (0xFFFF0000)
-#define NETARM_ETH_RXSTAT_RXOK          (0x00002000)
-
-
-/* PCS Configuration Register (0xFF80_0408) */
-
-#define NETARM_ETH_PCSC_NOCFR          (0x1) /* Disable Ciphering */
-#define NETARM_ETH_PCSC_ENJAB          (0x2) /* Enable Jabber Protection */
-#define NETARM_ETH_PCSC_CLKS_25M       (0x0) /* 25 MHz Clock Speed Select */
-#define NETARM_ETH_PCSC_CLKS_33M       (0x4) /* 33 MHz Clock Speed Select */
-
-/* STL Configuration Register (0xFF80_0410) */
-
-#define NETARM_ETH_STLC_RXEN           (0x2) /* Enable Packet Receiver */
-#define NETARM_ETH_STLC_AUTOZ          (0x4) /* Auto Zero Statistics */
-
-/* MAC Configuration Register (0xFF80_0400) */
-
-#define NETARM_ETH_MACC_HUGEN          (0x1) /* Enable Unlimited Transmit
-                                                Frame Sizes */
-#define NETARM_ETH_MACC_PADEN          (0x4) /* Automatic Pad Fill Frames
-                                                to 64 Bytes */
-#define NETARM_ETH_MACC_CRCEN          (0x8) /* Append CRC to Transmit
-                                                Frames */
-
-/* MII (PHY) Command Register (0xFF80_0540) */
-
-#define NETARM_ETH_MIIC_RSTAT          (0x1) /* Single Scan for Read Data */
-
-/* MII Indicators Register (0xFF80_0550) */
-
-#define NETARM_ETH_MIII_BUSY           (0x1) /* MII I/F Busy with
-                                                Read/Write */
-
-/* SAL Station Address Filter Register (0xFF80_05C0) */
-
-#define NETARM_ETH_SALF_PRO            (0x8) /* Enable Promiscuous Mode */
-#define NETARM_ETH_SALF_PRM            (0x4) /* Accept All Multicast
-                                                Packets */
-#define NETARM_ETH_SALF_PRA            (0x2) /* Accept Mulitcast Packets
-                                                using Hash Table */
-#define NETARM_ETH_SALF_BROAD          (0x1) /* Accept All Broadcast
-                                                Packets */
-
-
-#endif /* __NETARM_GEN_MODULE_REGISTERS_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h b/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h
deleted file mode 100644 (file)
index 13656a3..0000000
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_gen_module.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NETARM_GEN_MODULE_REGISTERS_H
-#define __NETARM_GEN_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define NETARM_GEN_MODULE_BASE         (0xFFB00000)
-
-#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
-
-#define NETARM_GEN_SYSTEM_CONTROL      (0x00)
-#define NETARM_GEN_STATUS_CONTROL      (0x04)
-#define NETARM_GEN_PLL_CONTROL         (0x08)
-#define NETARM_GEN_SOFTWARE_SERVICE    (0x0c)
-
-#define NETARM_GEN_TIMER1_CONTROL      (0x10)
-#define NETARM_GEN_TIMER1_STATUS       (0x14)
-#define NETARM_GEN_TIMER2_CONTROL      (0x18)
-#define NETARM_GEN_TIMER2_STATUS       (0x1c)
-
-#define NETARM_GEN_PORTA               (0x20)
-#ifndef CONFIG_NETARM_NS7520
-#define NETARM_GEN_PORTB               (0x24)
-#endif
-#define NETARM_GEN_PORTC               (0x28)
-
-#define NETARM_GEN_INTR_ENABLE         (0x30)
-#define NETARM_GEN_INTR_ENABLE_SET     (0x34)
-#define NETARM_GEN_INTR_ENABLE_CLR     (0x38)
-#define NETARM_GEN_INTR_STATUS_EN      (0x34)
-#define NETARM_GEN_INTR_STATUS_RAW     (0x38)
-
-#define NETARM_GEN_CACHE_CONTROL1      (0x40)
-#define NETARM_GEN_CACHE_CONTROL2      (0x44)
-
-/* select bitfield definitions */
-
-/* System Control Register ( 0xFFB0_0000 ) */
-
-#define NETARM_GEN_SYS_CFG_LENDIAN     (0x80000000)
-#define NETARM_GEN_SYS_CFG_BENDIAN     (0x00000000)
-
-#define NETARM_GEN_SYS_CFG_BUSQRTR     (0x00000000)
-#define NETARM_GEN_SYS_CFG_BUSHALF     (0x20000000)
-#define NETARM_GEN_SYS_CFG_BUSFULL     (0x40000000)
-
-#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
-
-#define NETARM_GEN_SYS_CFG_WDOG_EN     (0x01000000)
-#define NETARM_GEN_SYS_CFG_WDOG_IRQ    (0x00000000)
-#define NETARM_GEN_SYS_CFG_WDOG_FIQ    (0x00400000)
-#define NETARM_GEN_SYS_CFG_WDOG_RST    (0x00800000)
-#define NETARM_GEN_SYS_CFG_WDOG_24     (0x00000000)
-#define NETARM_GEN_SYS_CFG_WDOG_26     (0x00100000)
-#define NETARM_GEN_SYS_CFG_WDOG_28     (0x00200000)
-#define NETARM_GEN_SYS_CFG_WDOG_29     (0x00300000)
-
-#define NETARM_GEN_SYS_CFG_BUSMON_EN   (0x00040000)
-#define NETARM_GEN_SYS_CFG_BUSMON_128  (0x00000000)
-#define NETARM_GEN_SYS_CFG_BUSMON_64   (0x00010000)
-#define NETARM_GEN_SYS_CFG_BUSMON_32   (0x00020000)
-#define NETARM_GEN_SYS_CFG_BUSMON_16   (0x00030000)
-
-#define NETARM_GEN_SYS_CFG_USER_EN     (0x00008000)
-#define NETARM_GEN_SYS_CFG_BUSER_EN    (0x00004000)
-
-#define NETARM_GEN_SYS_CFG_BUSARB_INT  (0x00002000)
-#define NETARM_GEN_SYS_CFG_BUSARB_EXT  (0x00000000)
-
-#define NETARM_GEN_SYS_CFG_DMATST      (0x00001000)
-
-#define NETARM_GEN_SYS_CFG_TEALAST     (0x00000800)
-
-#define NETARM_GEN_SYS_CFG_ALIGN_ABORT (0x00000400)
-
-#define NETARM_GEN_SYS_CFG_CACHE_EN    (0x00000200)
-
-#define NETARM_GEN_SYS_CFG_WRI_BUF_EN  (0x00000100)
-
-#define NETARM_GEN_SYS_CFG_CACHE_INIT  (0x00000080)
-
-/* PLL Control Register ( 0xFFB0_0008 ) */
-
-#define NETARM_GEN_PLL_CTL_PLLCNT_MASK (0x0F000000)
-
-#define NETARM_GEN_PLL_CTL_PLLCNT(x)   (((x)<<24) & \
-                                        NETARM_GEN_PLL_CTL_PLLCNT_MASK)
-
-/* Defaults for POLTST and ICP Fields in PLL CTL */
-#define NETARM_GEN_PLL_CTL_OUTDIV(x)   (x)
-#define NETARM_GEN_PLL_CTL_INDIV(x)    ((x)<<6)
-#define NETARM_GEN_PLL_CTL_POLTST_DEF  (0x00000E00)
-#define NETARM_GEN_PLL_CTL_ICP_DEF     (0x0000003C)
-
-
-/* Software Service Register ( 0xFFB0_000C ) */
-
-#define NETARM_GEN_SW_SVC_RESETA       (0x123)
-#define NETARM_GEN_SW_SVC_RESETB       (0x321)
-
-/* PORT C Register ( 0xFFB0_0028 ) */
-
-#ifndef CONFIG_NETARM_NS7520
-#define NETARM_GEN_PORT_MODE(x)                (((x)<<24) + (0xFF00))
-#define NETARM_GEN_PORT_DIR(x)         (((x)<<16) + (0xFF00))
-#else
-#define NETARM_GEN_PORT_MODE(x)                ((x)<<24)
-#define NETARM_GEN_PORT_DIR(x)         ((x)<<16)
-#define NETARM_GEN_PORT_CSF(x)         ((x)<<8)
-#endif
-
-/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
-
-#define NETARM_GEN_TCTL_ENABLE         (0x80000000)
-#define NETARM_GEN_TCTL_INT_ENABLE     (0x40000000)
-
-#define NETARM_GEN_TCTL_USE_IRQ                (0x00000000)
-#define NETARM_GEN_TCTL_USE_FIQ                (0x20000000)
-
-#define NETARM_GEN_TCTL_USE_PRESCALE   (0x10000000)
-#define NETARM_GEN_TCTL_INIT_COUNT(x)  ((x) & 0x1FF)
-
-#define NETARM_GEN_TSTAT_INTPEN                (0x40000000)
-#if ~defined(CONFIG_NETARM_NS7520)
-#define NETARM_GEN_TSTAT_CTC_MASK      (0x000001FF)
-#else
-#define NETARM_GEN_TSTAT_CTC_MASK      (0x0FFFFFFF)
-#endif
-
-/* prescale to msecs conversion */
-
-#if !defined(CONFIG_NETARM_PLL_BYPASS)
-#define NETARM_GEN_TIMER_MSEC_P(x)     ( ( ( 20480 ) * ( 0x1FF - ( (x) &           \
-                                           NETARM_GEN_TSTAT_CTC_MASK ) +   \
-                                           1 ) ) / (NETARM_XTAL_FREQ/1000) )
-
-#define NETARM_GEN_TIMER_SET_HZ(x)     ( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
-                                         NETARM_GEN_TSTAT_CTC_MASK ) | \
-                                         NETARM_GEN_TCTL_USE_PRESCALE )
-
-#else
-#define NETARM_GEN_TIMER_MSEC_P(x)     ( ( ( 4096 ) * ( 0x1FF - ( (x) &    \
-                                           NETARM_GEN_TSTAT_CTC_MASK ) +   \
-                                           1 ) ) / (NETARM_XTAL_FREQ/1000) )
-
-#define NETARM_GEN_TIMER_SET_HZ(x)     ( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
-                                         NETARM_GEN_TSTAT_CTC_MASK ) | \
-                                         NETARM_GEN_TCTL_USE_PRESCALE )
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h b/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h
deleted file mode 100644 (file)
index c650c3b..0000000
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_mem_module.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NETARM_MEM_MODULE_REGISTERS_H
-#define __NETARM_MEM_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define        NETARM_MEM_MODULE_BASE          (0xFFC00000)
-
-#define        NETARM_MEM_MODULE_CONFIG        (0x00)
-#define        NETARM_MEM_CS0_BASE_ADDR        (0x10)
-#define        NETARM_MEM_CS0_OPTIONS          (0x14)
-#define        NETARM_MEM_CS1_BASE_ADDR        (0x20)
-#define        NETARM_MEM_CS1_OPTIONS          (0x24)
-#define        NETARM_MEM_CS2_BASE_ADDR        (0x30)
-#define        NETARM_MEM_CS2_OPTIONS          (0x34)
-#define        NETARM_MEM_CS3_BASE_ADDR        (0x40)
-#define        NETARM_MEM_CS3_OPTIONS          (0x44)
-#define        NETARM_MEM_CS4_BASE_ADDR        (0x50)
-#define        NETARM_MEM_CS4_OPTIONS          (0x54)
-
-/* select bitfield defintions */
-
-/* Module Configuration Register ( 0xFFC0_0000 ) */
-
-#define NETARM_MEM_CFG_REFR_COUNT_MASK (0xFF000000)
-#define NETARM_MEM_CFG_REFRESH_EN      (0x00800000)
-
-#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS        (0x00000000)
-#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS        (0x00200000)
-#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS        (0x00400000)
-#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS        (0x00600000)
-
-#define NETARM_MEM_CFG_PORTC_AMUX      (0x00100000)
-
-#define NETARM_MEM_CFG_A27_ADDR                (0x00080000)
-#define NETARM_MEM_CFG_A27_CS0OE       (0x00000000)
-
-#define NETARM_MEM_CFG_A26_ADDR                (0x00040000)
-#define NETARM_MEM_CFG_A26_CS0WE       (0x00000000)
-
-#define NETARM_MEM_CFG_A25_ADDR                (0x00020000)
-#define NETARM_MEM_CFG_A25_BLAST       (0x00000000)
-
-#define NETARM_MEM_CFG_PORTC_AMUX2     (0x00010000)
-
-
-/* range on this period is about 1 to 275 usec (with 18.432MHz clock)   */
-/* the expression will round down, so make sure to reverse it to verify */
-/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal        */
-/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
-
-#define        NETARM_MEM_REFR_PERIOD_USEC(p)  (NETARM_MEM_CFG_REFR_COUNT_MASK & \
-                                        (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
-                                           ) - (1) ) << (24)))
-
-#if 0
-/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
-/* the expression will round down, so make sure to reverse it toverify */
-/* it is what you want. period = [( count + 1 ) * 4] / Fxtal          */
-
-#define        NETARM_MEM_REFR_PERIOD_USEC(p)  (NETARM_MEM_CFG_REFR_COUNT_MASK & \
-                                        (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
-                                           ) - (1) ) << (24)))
-#endif
-
-/* Base Address Registers (0xFFC0_00X0) */
-
-#define NETARM_MEM_BAR_BASE_MASK       (0xFFFFF000)
-
-/* macro to define base */
-
-#define NETARM_MEM_BAR_BASE(x)         ((x) & NETARM_MEM_BAR_BASE_MASK)
-
-#define NETARM_MEM_BAR_DRAM_FP         (0x00000000)
-#define NETARM_MEM_BAR_DRAM_EDO                (0x00000100)
-#define NETARM_MEM_BAR_DRAM_SYNC       (0x00000200)
-
-#define NETARM_MEM_BAR_DRAM_MUX_INT    (0x00000000)
-#define NETARM_MEM_BAR_DRAM_MUX_EXT    (0x00000080)
-
-#define NETARM_MEM_BAR_DRAM_MUX_BAL    (0x00000000)
-#define NETARM_MEM_BAR_DRAM_MUX_UNBAL  (0x00000020)
-
-#define NETARM_MEM_BAR_1BCLK_IDLE      (0x00000010)
-
-#define NETARM_MEM_BAR_DRAM_SEL                (0x00000008)
-
-#define NETARM_MEM_BAR_BURST_EN                (0x00000004)
-
-#define NETARM_MEM_BAR_WRT_PROT                (0x00000002)
-
-#define NETARM_MEM_BAR_VALID           (0x00000001)
-
-/* Option Registers (0xFFC0_00X4) */
-
-/* macro to define which bits of the base are significant */
-
-#define NETARM_MEM_OPT_BASE_USE(x)     ((x) & NETARM_MEM_BAR_BASE_MASK)
-
-#define NETARM_MEM_OPT_WAIT_MASK       (0x00000F00)
-
-#define        NETARM_MEM_OPT_WAIT_STATES(x)   (((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
-
-#define NETARM_MEM_OPT_BCYC_1          (0x00000000)
-#define NETARM_MEM_OPT_BCYC_2          (0x00000040)
-#define NETARM_MEM_OPT_BCYC_3          (0x00000080)
-#define NETARM_MEM_OPT_BCYC_4          (0x000000C0)
-
-#define NETARM_MEM_OPT_BSIZE_2         (0x00000000)
-#define NETARM_MEM_OPT_BSIZE_4         (0x00000010)
-#define NETARM_MEM_OPT_BSIZE_8         (0x00000020)
-#define NETARM_MEM_OPT_BSIZE_16                (0x00000030)
-
-#define NETARM_MEM_OPT_32BIT           (0x00000000)
-#define NETARM_MEM_OPT_16BIT           (0x00000004)
-#define NETARM_MEM_OPT_8BIT            (0x00000008)
-#define NETARM_MEM_OPT_32BIT_EXT_ACK   (0x0000000C)
-
-#define NETARM_MEM_OPT_BUS_SIZE_MASK   (0x0000000C)
-
-#define NETARM_MEM_OPT_READ_ASYNC      (0x00000000)
-#define NETARM_MEM_OPT_READ_SYNC       (0x00000002)
-
-#define NETARM_MEM_OPT_WRITE_ASYNC     (0x00000000)
-#define NETARM_MEM_OPT_WRITE_SYNC      (0x00000001)
-
-#ifdef CONFIG_NETARM_NS7520
-/* The NS7520 has a second options register for each chip select */
-#define        NETARM_MEM_CS0_OPTIONS_B  (0x18)
-#define        NETARM_MEM_CS1_OPTIONS_B  (0x28)
-#define        NETARM_MEM_CS2_OPTIONS_B  (0x38)
-#define        NETARM_MEM_CS3_OPTIONS_B  (0x48)
-#define        NETARM_MEM_CS4_OPTIONS_B  (0x58)
-
-/* Option B Registers (0xFFC0_00x8) */
-#define NETARM_MEM_OPTB_SYNC_1_STAGE   (0x00000001)
-#define NETARM_MEM_OPTB_SYNC_2_STAGE   (0x00000002)
-#define NETARM_MEM_OPTB_BCYC_PLUS0     (0x00000000)
-#define NETARM_MEM_OPTB_BCYC_PLUS4     (0x00000004)
-#define NETARM_MEM_OPTB_BCYC_PLUS8     (0x00000008)
-#define NETARM_MEM_OPTB_BCYC_PLUS12    (0x0000000C)
-
-#define NETARM_MEM_OPTB_WAIT_PLUS0     (0x00000000)
-#define NETARM_MEM_OPTB_WAIT_PLUS16    (0x00000010)
-#define NETARM_MEM_OPTB_WAIT_PLUS32    (0x00000020)
-#define NETARM_MEM_OPTB_WAIT_PLUS48    (0x00000030)
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_registers.h b/arch/arm/include/asm/arch-arm720t/netarm_registers.h
deleted file mode 100644 (file)
index fa88128..0000000
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * linux/include/asm-arm/arch-netarm/netarm_registers.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NET_ARM_REGISTERS_H
-#define __NET_ARM_REGISTERS_H
-
-#include <config.h>
-
-/* fundamental constants : */
-/* the input crystal/clock frequency ( in Hz ) */
-#define        NETARM_XTAL_FREQ_25MHz          (18432000)
-#define        NETARM_XTAL_FREQ_33MHz          (23698000)
-#define        NETARM_XTAL_FREQ_48MHz          (48000000)
-#define        NETARM_XTAL_FREQ_55MHz          (55000000)
-#define NETARM_XTAL_FREQ_EMLIN1                (20000000)
-
-/* the frequency of SYS_CLK */
-#if defined(CONFIG_NETARM_EMLIN)
-
-/* EMLIN board:  33 MHz (exp.) */
-#define        NETARM_PLL_COUNT_VAL            6
-#define NETARM_XTAL_FREQ               NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET40_REV2)
-
-/* NET+40 Rev2 boards:  33 MHz (with NETARM_XTAL_FREQ_25MHz) */
-#define        NETARM_PLL_COUNT_VAL            6
-#define        NETARM_XTAL_FREQ                NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET40_REV4)
-
-/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with
-   NETARM_XTAL_FREQ_25MHz) 4 */
-#define        NETARM_PLL_COUNT_VAL            4
-#define        NETARM_XTAL_FREQ                NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET50)
-
-/* NET+50 boards:  40 MHz (with NETARM_XTAL_FREQ_25MHz) */
-#define NETARM_PLL_COUNT_VAL           8
-#define        NETARM_XTAL_FREQ                NETARM_XTAL_FREQ_25MHz
-
-#else  /* CONFIG_NETARM_NS7520 */
-
-#define        NETARM_PLL_COUNT_VAL            0
-
-#if defined(CONFIG_BOARD_UNC20)
-#define        NETARM_XTAL_FREQ                NETARM_XTAL_FREQ_48MHz
-#else
-#define        NETARM_XTAL_FREQ                NETARM_XTAL_FREQ_55MHz
-#endif
-
-#endif
-
-/* #include "arm_registers.h" */
-#include <asm/arch/netarm_gen_module.h>
-#include <asm/arch/netarm_mem_module.h>
-#include <asm/arch/netarm_ser_module.h>
-#include <asm/arch/netarm_eni_module.h>
-#include <asm/arch/netarm_dma_module.h>
-#include <asm/arch/netarm_eth_module.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h b/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h
deleted file mode 100644 (file)
index 6fbae11..0000000
+++ /dev/null
@@