Merge remote-tracking branch 'u-boot-imx/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 27 Oct 2012 09:43:17 +0000 (11:43 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sat, 27 Oct 2012 09:43:17 +0000 (11:43 +0200)
43 files changed:
arch/arm/cpu/arm1136/mx35/generic.c
arch/arm/cpu/armv7/mx5/clock.c
arch/arm/cpu/armv7/mx5/lowlevel_init.S
arch/arm/imx-common/iomux-v3.c
arch/arm/include/asm/arch-mx25/imx-regs.h
arch/arm/include/asm/arch-mx35/clock.h
arch/arm/include/asm/arch-mx35/lowlevel_macro.S
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/mx6x_pins.h
arch/arm/include/asm/arch-mx6/mxc_hdmi.h [new file with mode: 0644]
arch/arm/include/asm/imx-common/iomux-v3.h
board/CarMediaLab/flea3/lowlevel_init.S
board/esg/ima3-mx53/ima3-mx53.c
board/freescale/mx35pdk/lowlevel_init.S
board/freescale/mx35pdk/mx35pdk.c
board/freescale/mx35pdk/mx35pdk.h
board/freescale/mx51evk/mx51evk.c
board/freescale/mx53ard/mx53ard.c
board/freescale/mx53evk/mx53evk.c
board/freescale/mx53loco/mx53loco.c
board/freescale/mx53smd/mx53smd.c
board/freescale/mx6qarm2/mx6qarm2.c
board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6qsabrelite/mx6qsabrelite.c
board/freescale/mx6qsabresd/mx6qsabresd.c
board/genesi/mx51_efikamx/efikamx.c
board/ttcontrol/vision2/vision2.c
drivers/mmc/fsl_esdhc.c
drivers/video/mxc_ipuv3_fb.c
include/configs/mx25pdk.h
include/configs/mx51evk.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx6qarm2.h
include/configs/mx6qsabre_common.h
include/configs/mx6qsabreauto.h
include/configs/mx6qsabrelite.h
include/configs/mx6qsabresd.h
include/fsl_esdhc.h
include/ipu_pixfmt.h
tools/imximage.c
tools/imximage.h

index 7dc1a8ec58482fe03d46935d67593d83d06e8310..41e9639d9c4cd92cfcaded97a12c5d448f75a7dd 100644 (file)
@@ -361,8 +361,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                return get_ipg_per_clk();
        case MXC_UART_CLK:
                return imx_get_uartclk();
-       case MXC_ESDHC_CLK:
+       case MXC_ESDHC1_CLK:
                return mxc_get_peri_clock(ESDHC1_CLK);
+       case MXC_ESDHC2_CLK:
+               return mxc_get_peri_clock(ESDHC2_CLK);
+       case MXC_ESDHC3_CLK:
+               return mxc_get_peri_clock(ESDHC3_CLK);
        case MXC_USB_CLK:
                return mxc_get_main_clock(USB_CLK);
        case MXC_FEC_CLK:
@@ -472,7 +476,13 @@ int cpu_mmc_init(bd_t *bis)
 int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
-       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
 #endif
        return 0;
 }
index 2709860ca274884302c88a895faf00ed97cdb999..1c9223fa0783072f77a4aabdb4db225c0ae49856 100644 (file)
@@ -338,7 +338,7 @@ static u32 get_ipg_per_clk(void)
 /* Get the output clock rate of a standard PLL MUX for peripherals. */
 static u32 get_standard_pll_sel_clk(u32 clk_sel)
 {
-       u32 freq;
+       u32 freq = 0;
 
        switch (clk_sel & 0x3) {
        case 0:
index 529e35b4405aa5f611e5232ad8c6dec49bd4eb91..29ec95797baebacf4ea849da93291f624cf9abf5 100644 (file)
 
 .section ".text.init", "x"
 
+.macro init_arm_erratum
+       /* ARM erratum ID #468414 */
+       mrc 15, 0, r1, c1, c0, 1
+       orr r1, r1, #(1 << 5)    /* enable L1NEON bit */
+       mcr 15, 0, r1, c1, c0, 1
+.endm
+
 /*
  * L2CC Cache setup/invalidation/disable
  */
@@ -162,9 +169,9 @@ setup_pll_func:
 .endm
 
 .macro init_clock
+#if defined (CONFIG_MX51)
        ldr r0, =CCM_BASE_ADDR
 
-#if defined(CONFIG_MX51)
        /* Gate of clocks to the peripherals first */
        ldr r1, =0x3FFFFFFF
        str r1, [r0, #CLKCTL_CCGR0]
@@ -190,21 +197,6 @@ setup_pll_func:
 1:     ldr r1, [r0, #CLKCTL_CDHIPR]
        cmp r1, #0x0
        bne 1b
-#else
-       ldr r1, =0x3FFFFFFF
-       str r1, [r0, #CLKCTL_CCGR0]
-       str r4, [r0, #CLKCTL_CCGR1]
-       str r4, [r0, #CLKCTL_CCGR2]
-       str r4, [r0, #CLKCTL_CCGR3]
-       str r4, [r0, #CLKCTL_CCGR7]
-
-       ldr r1, =0x00030000
-       str r1, [r0, #CLKCTL_CCGR4]
-       ldr r1, =0x00FFF030
-       str r1, [r0, #CLKCTL_CCGR5]
-       ldr r1, =0x0F00030F
-       str r1, [r0, #CLKCTL_CCGR6]
-#endif
 
        /* Switch ARM to step clock */
        mov r1, #0x4
@@ -217,7 +209,6 @@ setup_pll_func:
        setup_pll PLL1_BASE_ADDR, 800
 #endif
 
-#if defined(CONFIG_MX51)
        setup_pll PLL3_BASE_ADDR, 665
 
        /* Switch peripheral to PLL 3 */
@@ -234,7 +225,7 @@ setup_pll_func:
        str r1, [r0, #CLKCTL_CBCDR]
        ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
        str r1, [r0, #CLKCTL_CBCMR]
-#endif
+
        setup_pll PLL3_BASE_ADDR, 216
 
        /* Set the platform clock dividers */
@@ -244,21 +235,17 @@ setup_pll_func:
 
        ldr r0, =CCM_BASE_ADDR
 
-#if defined(CONFIG_MX51)
        /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
        ldr r3, [r4, #ROM_SI_REV]
        cmp r3, #0x10
        movls r1, #0x1
        movhi r1, #0
-#else
-       mov r1, #0
-#endif
+
        str r1, [r0, #CLKCTL_CACRR]
 
        /* Switch ARM back to PLL 1 */
        str r4, [r0, #CLKCTL_CCSR]
 
-#if defined(CONFIG_MX51)
        /* setup the rest */
        /* Use lp_apm (24MHz) source for perclk */
        ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
@@ -266,7 +253,6 @@ setup_pll_func:
        /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
        ldr r1, =CONFIG_SYS_CLKTL_CBCDR
        str r1, [r0, #CLKCTL_CBCDR]
-#endif
 
        /* Restore the default values in the Gate registers */
        ldr r1, =0xFFFFFFFF
@@ -277,47 +263,127 @@ setup_pll_func:
        str r1, [r0, #CLKCTL_CCGR4]
        str r1, [r0, #CLKCTL_CCGR5]
        str r1, [r0, #CLKCTL_CCGR6]
-#if defined(CONFIG_MX53)
-       str r1, [r0, #CLKCTL_CCGR7]
-#endif
 
-#if defined(CONFIG_MX51)
        /* Use PLL 2 for UART's, get 66.5MHz from it */
        ldr r1, =0xA5A2A020
        str r1, [r0, #CLKCTL_CSCMR1]
        ldr r1, =0x00C30321
        str r1, [r0, #CLKCTL_CSCDR1]
-#elif defined(CONFIG_MX53)
+       /* make sure divider effective */
+1:     ldr r1, [r0, #CLKCTL_CDHIPR]
+       cmp r1, #0x0
+       bne 1b
+
+       str r4, [r0, #CLKCTL_CCDR]
+
+       /* for cko - for ARM div by 8 */
+       mov r1, #0x000A0000
+       add r1, r1, #0x00000F0
+       str r1, [r0, #CLKCTL_CCOSR]
+#else  /* CONFIG_MX53 */
+       ldr r0, =CCM_BASE_ADDR
+
+       /* Gate of clocks to the peripherals first */
+       ldr r1, =0x3FFFFFFF
+       str r1, [r0, #CLKCTL_CCGR0]
+       str r4, [r0, #CLKCTL_CCGR1]
+       str r4, [r0, #CLKCTL_CCGR2]
+       str r4, [r0, #CLKCTL_CCGR3]
+       str r4, [r0, #CLKCTL_CCGR7]
+       ldr r1, =0x00030000
+       str r1, [r0, #CLKCTL_CCGR4]
+       ldr r1, =0x00FFF030
+       str r1, [r0, #CLKCTL_CCGR5]
+       ldr r1, =0x0F00030F
+       str r1, [r0, #CLKCTL_CCGR6]
+
+       /* Switch ARM to step clock */
+       mov r1, #0x4
+       str r1, [r0, #CLKCTL_CCSR]
+
+       setup_pll PLL1_BASE_ADDR, 800
+
+        setup_pll PLL3_BASE_ADDR, 400
+
+        /* Switch peripheral to PLL3 */
+        ldr r0, =CCM_BASE_ADDR
+        ldr r1, =0x00015154
+        str r1, [r0, #CLKCTL_CBCMR]
+        ldr r1, =0x02888945
+        orr r1, r1, #(1 << 16)
+        str r1, [r0, #CLKCTL_CBCDR]
+        /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+        cmp r1, #0x0
+        bne 1b
+
+        setup_pll PLL2_BASE_ADDR, 400
+
        /* Switch peripheral to PLL2 */
        ldr r0, =CCM_BASE_ADDR
        ldr r1, =0x00808145
-       orr r1, r1, #2 << 10
-       orr r1, r1, #1 << 19
+       orr r1, r1, #(2 << 10)
+       orr r1, r1, #(0 << 16)
+       orr r1, r1, #(1 << 19)
        str r1, [r0, #CLKCTL_CBCDR]
 
        ldr r1, =0x00016154
        str r1, [r0, #CLKCTL_CBCMR]
-       /* Change uart clk parent to pll2*/
+
+       /*change uart clk parent to pll2*/
        ldr r1, [r0, #CLKCTL_CSCMR1]
        and r1, r1, #0xfcffffff
        orr r1, r1, #0x01000000
        str r1, [r0, #CLKCTL_CSCMR1]
+
+       /* make sure change is effective */
+1:      ldr r1, [r0, #CLKCTL_CDHIPR]
+       cmp r1, #0x0
+       bne 1b
+
+        setup_pll PLL3_BASE_ADDR, 216
+
+       setup_pll PLL4_BASE_ADDR, 455
+
+       /* Set the platform clock dividers */
+       ldr r0, =ARM_BASE_ADDR
+       ldr r1, =0x00000124
+       str r1, [r0, #0x14]
+
+       ldr r0, =CCM_BASE_ADDR
+       mov r1, #0
+       str r1, [r0, #CLKCTL_CACRR]
+
+       /* Switch ARM back to PLL 1. */
+       mov r1, #0x0
+       str r1, [r0, #CLKCTL_CCSR]
+
+       /* make uart div=6 */
        ldr r1, [r0, #CLKCTL_CSCDR1]
        and r1, r1, #0xffffffc0
        orr r1, r1, #0x0a
        str r1, [r0, #CLKCTL_CSCDR1]
-#endif
-       /* make sure divider effective */
-1:     ldr r1, [r0, #CLKCTL_CDHIPR]
-       cmp r1, #0x0
-       bne 1b
 
-       str r4, [r0, #CLKCTL_CCDR]
+       /* Restore the default values in the Gate registers */
+       ldr r1, =0xFFFFFFFF
+       str r1, [r0, #CLKCTL_CCGR0]
+       str r1, [r0, #CLKCTL_CCGR1]
+       str r1, [r0, #CLKCTL_CCGR2]
+       str r1, [r0, #CLKCTL_CCGR3]
+       str r1, [r0, #CLKCTL_CCGR4]
+       str r1, [r0, #CLKCTL_CCGR5]
+       str r1, [r0, #CLKCTL_CCGR6]
+       str r1, [r0, #CLKCTL_CCGR7]
 
-       /* for cko - for ARM div by 8 */
-       mov r1, #0x000A0000
-       add r1, r1, #0x00000F0
-       str r1, [r0, #CLKCTL_CCOSR]
+        mov r1, #0x00000
+        str r1, [r0, #CLKCTL_CCDR]
+
+        /* for cko - for ARM div by 8 */
+        mov r1, #0x000A0000
+        add r1, r1, #0x00000F0
+        str r1, [r0, #CLKCTL_CCOSR]
+
+#endif /* CONFIG_MX53 */
 .endm
 
 .macro setup_wdog
@@ -340,6 +406,8 @@ ENTRY(lowlevel_init)
        str r1, [r0, #0x4]
 #endif
 
+       init_arm_erratum
+
        init_l2cc
 
        init_aips
@@ -370,3 +438,9 @@ W_DP_665:           .word DP_OP_665
 W_DP_216:              .word DP_OP_216
                        .word DP_MFD_216
                        .word DP_MFN_216
+W_DP_400:               .word DP_OP_400
+                       .word DP_MFD_400
+                       .word DP_MFN_400
+W_DP_455:               .word DP_OP_455
+                       .word DP_MFD_455
+                       .word DP_MFN_455
index da093fbe1489ec516dfd41ea136377f0529563df..08fad7851c98e8d64ddc05b06b356884b3f7a75f 100644 (file)
@@ -54,9 +54,10 @@ int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
        return 0;
 }
 
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
+int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+                                    unsigned count)
 {
-       iomux_v3_cfg_t *p = pad_list;
+       iomux_v3_cfg_t const *p = pad_list;
        int i;
        int ret;
 
index e78029604b71d962babcef4575f8e63f38134a98..53aafe3075f4af9fbbea20f6a8a1e5444a95595a 100644 (file)
@@ -2,7 +2,7 @@
  * Copyright (C) 2009, DENX Software Engineering
  * Author: John Rigby <jcrigby@gmail.com
  *
- *   Based on arch-mx31/mx31-regs.h
+ *   Based on arch-mx31/imx-regs.h
  *     Copyright (C) 2009 Ilya Yanok,
  *             Emcraft Systems <yanok@emcraft.com>
  *   and arch-mx27/imx-regs.h
@@ -33,8 +33,7 @@
 #ifndef _IMX_REGS_H
 #define _IMX_REGS_H
 
-#ifndef __ASSEMBLY__
-
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
 #ifdef CONFIG_FEC_MXC
@@ -254,6 +253,7 @@ struct aips_regs {
 
 /* 128K Internal Static RAM */
 #define IMX_RAM_BASE           (0x78000000)
+#define IMX_RAM_SIZE           (128 * 1024)
 
 /* SDRAM BANKS */
 #define IMX_SDRAM_BANK0_BASE   (0x80000000)
index 2eff08d1d49a681aed726f7a15e0987f39a7d78f..00679ef6a91a47a3a1e761bd18fd9ac13643644a 100644 (file)
@@ -44,7 +44,9 @@ enum mxc_clock {
        MXC_IPG_CLK,
        MXC_IPG_PERCLK,
        MXC_UART_CLK,
-       MXC_ESDHC_CLK,
+       MXC_ESDHC1_CLK,
+       MXC_ESDHC2_CLK,
+       MXC_ESDHC3_CLK,
        MXC_USB_CLK,
        MXC_CSPI_CLK,
        MXC_FEC_CLK,
index 05aa951d10b2a9e025dc1adf6a269eea74d6bbaf..bc6dbea665558f8fb2d05f6420cd27ec47b77381 100644 (file)
  * MA 02111-1307 USA
  */
 
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+#include <asm/macro.h>
+
 /*
  * AIPS setup - Only setup MPROTx registers.
  * The PACR default values are good.
+ *
+ * Default argument values:
+ *  - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
+ *    user-mode.
+ *  - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
+ *    SDMA to access them.
  */
-.macro init_aips
-       /*
-        * Set all MPROTx to be non-bufferable, trusted for R/W,
-        * not forced to user-mode.
-        */
-       ldr r0, =AIPS1_BASE_ADDR
-       ldr r1, =AIPS_MPR_CONFIG
-       str r1, [r0, #0x00]
-       str r1, [r0, #0x04]
-       ldr r0, =AIPS2_BASE_ADDR
-       str r1, [r0, #0x00]
-       str r1, [r0, #0x04]
+.macro init_aips mpr=0x77777777, opacr=0x00000000
+       ldr     r0, =AIPS1_BASE_ADDR
+       ldr     r1, =\mpr
+       str     r1, [r0, #AIPS_MPR_0_7]
+       str     r1, [r0, #AIPS_MPR_8_15]
+       ldr     r2, =AIPS2_BASE_ADDR
+       str     r1, [r2, #AIPS_MPR_0_7]
+       str     r1, [r2, #AIPS_MPR_8_15]
 
-       /*
-        * Clear the on and off peripheral modules Supervisor Protect bit
-        * for SDMA to access them. Did not change the AIPS control registers
-        * (offset 0x20) access type
-        */
-       ldr r0, =AIPS1_BASE_ADDR
-       ldr r1, =AIPS_OPACR_CONFIG
-       str r1, [r0, #0x40]
-       str r1, [r0, #0x44]
-       str r1, [r0, #0x48]
-       str r1, [r0, #0x4C]
-       str r1, [r0, #0x50]
-       ldr r0, =AIPS2_BASE_ADDR
-       str r1, [r0, #0x40]
-       str r1, [r0, #0x44]
-       str r1, [r0, #0x48]
-       str r1, [r0, #0x4C]
-       str r1, [r0, #0x50]
+       /* Did not change the AIPS control registers access type. */
+       ldr     r1, =\opacr
+       str     r1, [r0, #AIPS_OPACR_0_7]
+       str     r1, [r0, #AIPS_OPACR_8_15]
+       str     r1, [r0, #AIPS_OPACR_16_23]
+       str     r1, [r0, #AIPS_OPACR_24_31]
+       str     r1, [r0, #AIPS_OPACR_32_39]
+       str     r1, [r2, #AIPS_OPACR_0_7]
+       str     r1, [r2, #AIPS_OPACR_8_15]
+       str     r1, [r2, #AIPS_OPACR_16_23]
+       str     r1, [r2, #AIPS_OPACR_24_31]
+       str     r1, [r2, #AIPS_OPACR_32_39]
 .endm
 
-/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-.macro init_max
-       ldr r0, =MAX_BASE_ADDR
-       /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-       ldr r1, =MAX_MPR_CONFIG
-       str r1, [r0, #0x000]        /* for S0 */
-       str r1, [r0, #0x100]        /* for S1 */
-       str r1, [r0, #0x200]        /* for S2 */
-       str r1, [r0, #0x300]        /* for S3 */
-       str r1, [r0, #0x400]        /* for S4 */
-       /* SGPCR - always park on last master */
-       ldr r1, =MAX_SGPCR_CONFIG
-       str r1, [r0, #0x010]        /* for S0 */
-       str r1, [r0, #0x110]        /* for S1 */
-       str r1, [r0, #0x210]        /* for S2 */
-       str r1, [r0, #0x310]        /* for S3 */
-       str r1, [r0, #0x410]        /* for S4 */
-       /* MGPCR - restore default values */
-       ldr r1, =MAX_MGPCR_CONFIG
-       str r1, [r0, #0x800]        /* for M0 */
-       str r1, [r0, #0x900]        /* for M1 */
-       str r1, [r0, #0xA00]        /* for M2 */
-       str r1, [r0, #0xB00]        /* for M3 */
-       str r1, [r0, #0xC00]        /* for M4 */
-       str r1, [r0, #0xD00]        /* for M5 */
+/*
+ * MAX (Multi-Layer AHB Crossbar Switch) setup
+ *
+ * Default argument values:
+ *  - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
+ *  - SGPCR: always park on last master
+ *  - MGPCR: restore default values
+ */
+.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
+       ldr     r0, =MAX_BASE_ADDR
+       ldr     r1, =\mpr
+       str     r1, [r0, #MAX_MPR0]     /* for S0 */
+       str     r1, [r0, #MAX_MPR1]     /* for S1 */
+       str     r1, [r0, #MAX_MPR2]     /* for S2 */
+       str     r1, [r0, #MAX_MPR3]     /* for S3 */
+       str     r1, [r0, #MAX_MPR4]     /* for S4 */
+       ldr     r1, =\sgpcr
+       str     r1, [r0, #MAX_SGPCR0]   /* for S0 */
+       str     r1, [r0, #MAX_SGPCR1]   /* for S1 */
+       str     r1, [r0, #MAX_SGPCR2]   /* for S2 */
+       str     r1, [r0, #MAX_SGPCR3]   /* for S3 */
+       str     r1, [r0, #MAX_SGPCR4]   /* for S4 */
+       ldr     r1, =\mgpcr
+       str     r1, [r0, #MAX_MGPCR0]   /* for M0 */
+       str     r1, [r0, #MAX_MGPCR1]   /* for M1 */
+       str     r1, [r0, #MAX_MGPCR2]   /* for M2 */
+       str     r1, [r0, #MAX_MGPCR3]   /* for M3 */
+       str     r1, [r0, #MAX_MGPCR4]   /* for M4 */
+       str     r1, [r0, #MAX_MGPCR5]   /* for M5 */
 .endm
 
-/* M3IF setup */
-.macro init_m3if
-       /* Configure M3IF registers */
-       ldr r1, =M3IF_BASE_ADDR
-       /*
-       * M3IF Control Register (M3IFCTL)
      * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
      * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
      * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
      * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
      * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
      * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
      * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
-       * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
-       *                                               ------------
-       *                                                 0x00000040
-       */
-       ldr r0, =M3IF_CONFIG
-       str r0, [r1]  /* M3IF control reg */
+/*
+ * M3IF setup
+ *
+ * Default argument values:
+ *  - CTL:
+ * MRRP[0] = L2CC0 not on priority list (0 << 0)       = 0x00000000
* MRRP[1] = L2CC1 not on priority list (0 << 1)       = 0x00000000
* MRRP[2] = MBX not on priority list (0 << 2)         = 0x00000000
* MRRP[3] = MAX1 not on priority list (0 << 3)                = 0x00000000
* MRRP[4] = SDMA not on priority list (0 << 4)                = 0x00000000
* MRRP[5] = MPEG4 not on priority list (0 << 5)       = 0x00000000
* MRRP[6] = IPU1 on priority list (1 << 6)            = 0x00000040
* MRRP[7] = IPU2 not on priority list (0 << 7)                = 0x00000000
+ *                                                     ------------
+ *                                                       0x00000040
+ */
+.macro init_m3if ctl=0x00000040
+       /* M3IF Control Register (M3IFCTL) */
+       write32 M3IF_BASE_ADDR, \ctl
 .endm
 
 .macro core_init
-       mrc 15, 0, r1, c1, c0, 0
+       mrc     p15, 0, r1, c1, c0, 0
 
-       mrc 15, 0, r0, c1, c0, 1
-       orr r0, r0, #7
-       mcr 15, 0, r0, c1, c0, 1
-       orr r1, r1, #(1<<11)
+       /* Set branch prediction enable */
+       mrc     p15, 0, r0, c1, c0, 1
+       orr     r0, r0, #7
+       mcr     p15, 0, r0, c1, c0, 1
+       orr     r1, r1, #1 << 11
 
        /* Set unaligned access enable */
-       orr r1, r1, #(1<<22)
+       orr     r1, r1, #1 << 22
 
        /* Set low int latency enable */
-       orr r1, r1, #(1<<21)
+       orr     r1, r1, #1 << 21
 
-       mcr 15, 0, r1, c1, c0, 0
+       mcr     p15, 0, r1, c1, c0, 0
 
-       mov r0, #0
+       mov     r0, #0
 
-       /* Set branch prediction enable */
-       mcr 15, 0, r0, c15, c2, 4
+       mcr     p15, 0, r0, c15, c2, 4
 
-       mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
-       mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
-       mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
+       mcr     p15, 0, r0, c7, c7, 0   /* Invalidate I cache and D cache */
+       mcr     p15, 0, r0, c8, c7, 0   /* Invalidate TLBs */
+       mcr     p15, 0, r0, c7, c10, 4  /* Drain the write buffer */
 
-       /*
-        * initializes very early AIPS
-        * Then it also initializes Multi-Layer AHB Crossbar Switch,
-        * M3IF
-        * Also setup the Peripheral Port Remap register inside the core
-        */
-       ldr r0, =0x40000015        /* start from AIPS 2GB region */
-       mcr p15, 0, r0, c15, c2, 4
+       /* Setup the Peripheral Port Memory Remap Register */
+       ldr     r0, =0x40000015         /* Start from AIPS 2-GB region */
+       mcr     p15, 0, r0, c15, c2, 4
 .endm
index 46017f4ad062a5289e007ab4507bef43db6a5216..1d060fd23ed0b13c8780a299c287d1450b22c604 100644 (file)
 #define DP_MFD_400     (3 - 1)
 #define DP_MFN_400     1
 
+#define DP_OP_455      ((9 << 4) + ((2 - 1)  << 0))
+#define DP_MFD_455     (48 - 1)
+#define DP_MFN_455     23
+
 #define DP_OP_216      ((6 << 4) + ((3 - 1)  << 0))
 #define DP_MFD_216     (4 - 1)
 #define DP_MFN_216     3
index dc737ba12721999206ceaae34dd4cae36ee06c87..09ab010138b965950fb45679e84f5bad8ac36908 100644 (file)
@@ -200,6 +200,12 @@ struct src {
        u32     gpr10;
 };
 
+/* OCOTP Registers */
+struct ocotp_regs {
+       u32     reserved[0x198];
+       u32     gp1;    /* 0x660 */
+};
+
 /* GPR3 bitfields */
 #define IOMUXC_GPR3_GPU_DBG_OFFSET             29
 #define IOMUXC_GPR3_GPU_DBG_MASK               (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
index 3d66d64d209019c40d749efed5ab49ee982fa431..3ade8dc4337e0b6b310aaf9532bfa117f2a7576a 100644 (file)
@@ -530,20 +530,20 @@ enum {
        MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16       = IOMUX_PAD(0x046C, 0x0158, 1, 0x0000, 0, 0),
        MX6Q_PAD_EIM_BCLK__GPIO_6_31            = IOMUX_PAD(0x046C, 0x0158, 5, 0x0000, 0, 0),
        MX6Q_PAD_EIM_BCLK__TPSMP_HDATA_31       = IOMUX_PAD(0x046C, 0x0158, 6, 0x0000, 0, 0),
-       MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK = IOMUX_PAD(0x0470, 0x015C, 1, 0x0000, 0, 0),
        MX6Q_PAD_DI0_DISP_CLK__MIPI_CR_DPY_OT28 = IOMUX_PAD(0x0470, 0x015C, 3, 0x0000, 0, 0),
        MX6Q_PAD_DI0_DISP_CLK__SDMA_DBG_CR_STA0 = IOMUX_PAD(0x0470, 0x015C, 4, 0x0000, 0, 0),
        MX6Q_PAD_DI0_DISP_CLK__GPIO_4_16        = IOMUX_PAD(0x0470, 0x015C, 5, 0x0000, 0, 0),
        MX6Q_PAD_DI0_DISP_CLK__MMDC_DEBUG_0     = IOMUX_PAD(0x0470, 0x015C, 6, 0x0000, 0, 0),
-       MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15      = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15      = IOMUX_PAD(0x0474, 0x0160, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15      = IOMUX_PAD(0x0474, 0x0160, 1, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN15__AUDMUX_AUD6_TXC     = IOMUX_PAD(0x0474, 0x0160, 2, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN15__MIPI_CR_DPHY_OUT_29 = IOMUX_PAD(0x0474, 0x0160, 3, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN15__SDMA_DBG_CORE_STA_1 = IOMUX_PAD(0x0474, 0x0160, 4, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN15__GPIO_4_17           = IOMUX_PAD(0x0474, 0x0160, 5, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1   = IOMUX_PAD(0x0474, 0x0160, 6, 0x0000, 0, 0),
-       MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2        = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2        = IOMUX_PAD(0x0478, 0x0164, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN2        = IOMUX_PAD(0x0478, 0x0164, 1, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN2__AUDMUX_AUD6_TXD      = IOMUX_PAD(0x0478, 0x0164, 2, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN2__MIPI_CR_DPHY_OUT_30  = IOMUX_PAD(0x0478, 0x0164, 3, 0x0000, 0, 0),
@@ -551,7 +551,7 @@ enum {
        MX6Q_PAD_DI0_PIN2__GPIO_4_18            = IOMUX_PAD(0x0478, 0x0164, 5, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN2__MMDC_DEBUG_2         = IOMUX_PAD(0x0478, 0x0164, 6, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN2__PL301_PER1_HADDR_9   = IOMUX_PAD(0x0478, 0x0164, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3        = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3        = IOMUX_PAD(0x047C, 0x0168, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN3        = IOMUX_PAD(0x047C, 0x0168, 1, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS     = IOMUX_PAD(0x047C, 0x0168, 2, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN3__MIPI_CORE_DPHY_OUT31 = IOMUX_PAD(0x047C, 0x0168, 3, 0x0000, 0, 0),
@@ -564,17 +564,17 @@ enum {
        MX6Q_PAD_DI0_PIN4__AUDMUX_AUD6_RXD      = IOMUX_PAD(0x0480, 0x016C, 2, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN4__USDHC1_WP            = IOMUX_PAD(0x0480, 0x016C, 3, 0x094C, 0, 0),
        MX6Q_PAD_DI0_PIN4__SDMA_DEBUG_YIELD     = IOMUX_PAD(0x0480, 0x016C, 4, 0x0000, 0, 0),
-       MX6Q_PAD_DI0_PIN4__GPIO_4_20            = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, 0),
+       MX6Q_PAD_DI0_PIN4__GPIO_4_20            = IOMUX_PAD(0x0480, 0x016C, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4    = IOMUX_PAD(0x0480, 0x016C, 6, 0x0000, 0, 0),
        MX6Q_PAD_DI0_PIN4__PL301_PER1_HADDR_11  = IOMUX_PAD(0x0480, 0x016C, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0   = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0   = IOMUX_PAD(0x0484, 0x0170, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DAT_0   = IOMUX_PAD(0x0484, 0x0170, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK        = IOMUX_PAD(0x0484, 0x0170, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT0__USDHC1_USDHC_DBG_0 = IOMUX_PAD(0x0484, 0x0170, 3, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT0__SDMA_DBG_CORE_RUN  = IOMUX_PAD(0x0484, 0x0170, 4, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT0__GPIO_4_21          = IOMUX_PAD(0x0484, 0x0170, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5  = IOMUX_PAD(0x0484, 0x0170, 6, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1   = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1   = IOMUX_PAD(0x0488, 0x0174, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DAT_1   = IOMUX_PAD(0x0488, 0x0174, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI        = IOMUX_PAD(0x0488, 0x0174, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT1__USDHC1_USDHC_DBG_1 = IOMUX_PAD(0x0488, 0x0174, 3, 0x0000, 0, 0),
@@ -582,7 +582,7 @@ enum {
        MX6Q_PAD_DISP0_DAT1__GPIO_4_22          = IOMUX_PAD(0x0488, 0x0174, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT1__MMDC_DEBUG_6       = IOMUX_PAD(0x0488, 0x0174, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2   = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2   = IOMUX_PAD(0x048C, 0x0178, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2   = IOMUX_PAD(0x048C, 0x0178, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO        = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT2__USDHC1_USDHC_DBG_2 = IOMUX_PAD(0x048C, 0x0178, 3, 0x0000, 0, 0),
@@ -590,7 +590,7 @@ enum {
        MX6Q_PAD_DISP0_DAT2__GPIO_4_23          = IOMUX_PAD(0x048C, 0x0178, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT2__MMDC_DEBUG_7       = IOMUX_PAD(0x048C, 0x0178, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3   = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3   = IOMUX_PAD(0x0490, 0x017C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3   = IOMUX_PAD(0x0490, 0x017C, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0         = IOMUX_PAD(0x0490, 0x017C, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT3__USDHC1_USDHC_DBG_3 = IOMUX_PAD(0x0490, 0x017C, 3, 0x0000, 0, 0),
@@ -598,7 +598,7 @@ enum {
        MX6Q_PAD_DISP0_DAT3__GPIO_4_24          = IOMUX_PAD(0x0490, 0x017C, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8    = IOMUX_PAD(0x0490, 0x017C, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4   = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4   = IOMUX_PAD(0x0494, 0x0180, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4   = IOMUX_PAD(0x0494, 0x0180, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1         = IOMUX_PAD(0x0494, 0x0180, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT4__USDHC1_USDHC_DBG_4 = IOMUX_PAD(0x0494, 0x0180, 3, 0x0000, 0, 0),
@@ -606,7 +606,7 @@ enum {
        MX6Q_PAD_DISP0_DAT4__GPIO_4_25          = IOMUX_PAD(0x0494, 0x0180, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9  = IOMUX_PAD(0x0494, 0x0180, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5   = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5   = IOMUX_PAD(0x0498, 0x0184, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5   = IOMUX_PAD(0x0498, 0x0184, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2         = IOMUX_PAD(0x0498, 0x0184, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT5__AUDMUX_AUD6_RXFS   = IOMUX_PAD(0x0498, 0x0184, 3, 0x0000, 0, 0),
@@ -614,7 +614,7 @@ enum {
        MX6Q_PAD_DISP0_DAT5__GPIO_4_26          = IOMUX_PAD(0x0498, 0x0184, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT5__MMDC_DEBUG_10      = IOMUX_PAD(0x0498, 0x0184, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6   = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6   = IOMUX_PAD(0x049C, 0x0188, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6   = IOMUX_PAD(0x049C, 0x0188, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3         = IOMUX_PAD(0x049C, 0x0188, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT6__AUDMUX_AUD6_RXC    = IOMUX_PAD(0x049C, 0x0188, 3, 0x0000, 0, 0),
@@ -622,7 +622,7 @@ enum {
        MX6Q_PAD_DISP0_DAT6__GPIO_4_27          = IOMUX_PAD(0x049C, 0x0188, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT6__MMDC_DEBUG_11      = IOMUX_PAD(0x049C, 0x0188, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7   = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7   = IOMUX_PAD(0x04A0, 0x018C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7   = IOMUX_PAD(0x04A0, 0x018C, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY         = IOMUX_PAD(0x04A0, 0x018C, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT7__USDHC1_USDHC_DBG_5 = IOMUX_PAD(0x04A0, 0x018C, 3, 0x0000, 0, 0),
@@ -630,7 +630,7 @@ enum {
        MX6Q_PAD_DISP0_DAT7__GPIO_4_28          = IOMUX_PAD(0x04A0, 0x018C, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT7__MMDC_DEBUG_12      = IOMUX_PAD(0x04A0, 0x018C, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8   = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8   = IOMUX_PAD(0x04A4, 0x0190, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8   = IOMUX_PAD(0x04A4, 0x0190, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT8__PWM1_PWMO          = IOMUX_PAD(0x04A4, 0x0190, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT8__WDOG1_WDOG_B       = IOMUX_PAD(0x04A4, 0x0190, 3, 0x0000, 0, 0),
@@ -638,7 +638,7 @@ enum {
        MX6Q_PAD_DISP0_DAT8__GPIO_4_29          = IOMUX_PAD(0x04A4, 0x0190, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT8__MMDC_DEBUG_13      = IOMUX_PAD(0x04A4, 0x0190, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9   = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9   = IOMUX_PAD(0x04A8, 0x0194, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9   = IOMUX_PAD(0x04A8, 0x0194, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT9__PWM2_PWMO          = IOMUX_PAD(0x04A8, 0x0194, 2, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT9__WDOG2_WDOG_B       = IOMUX_PAD(0x04A8, 0x0194, 3, 0x0000, 0, 0),
@@ -646,41 +646,41 @@ enum {
        MX6Q_PAD_DISP0_DAT9__GPIO_4_30          = IOMUX_PAD(0x04A8, 0x0194, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT9__MMDC_DEBUG_14      = IOMUX_PAD(0x04A8, 0x0194, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT10__USDHC1_DBG_6      = IOMUX_PAD(0x04AC, 0x0198, 3, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT10__SDMA_DBG_EVT_CHN3 = IOMUX_PAD(0x04AC, 0x0198, 4, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT10__GPIO_4_31         = IOMUX_PAD(0x04AC, 0x0198, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT10__MMDC_DEBUG_15     = IOMUX_PAD(0x04AC, 0x0198, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT11__SDMA_DBG_EVT_CHN4 = IOMUX_PAD(0x04B0, 0x019C, 4, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT11__GPIO_5_5          = IOMUX_PAD(0x04B0, 0x019C, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT11__MMDC_DEBUG_16     = IOMUX_PAD(0x04B0, 0x019C, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT12__SDMA_DBG_EVT_CHN5 = IOMUX_PAD(0x04B4, 0x01A0, 4, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT12__GPIO_5_6          = IOMUX_PAD(0x04B4, 0x01A0, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT12__MMDC_DEBUG_17     = IOMUX_PAD(0x04B4, 0x01A0, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS  = IOMUX_PAD(0x04B8, 0x01A4, 3, 0x07D8, 1, 0),
        MX6Q_PAD_DISP0_DAT13__SDMA_DBG_EVT_CHN0 = IOMUX_PAD(0x04B8, 0x01A4, 4, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT13__GPIO_5_7          = IOMUX_PAD(0x04B8, 0x01A4, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT13__MMDC_DEBUG_18     = IOMUX_PAD(0x04B8, 0x01A4, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC   = IOMUX_PAD(0x04BC, 0x01A8, 3, 0x07D4, 1, 0),
        MX6Q_PAD_DISP0_DAT14__SDMA_DBG_EVT_CHN1 = IOMUX_PAD(0x04BC, 0x01A8, 4, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT14__GPIO_5_8          = IOMUX_PAD(0x04BC, 0x01A8, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT14__MMDC_DEBUG_19     = IOMUX_PAD(0x04BC, 0x01A8, 6, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DAT_15 = IOMUX_PAD(0x04C0, 0x01AC, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1        = IOMUX_PAD(0x04C0, 0x01AC, 2, 0x0804, 1, 0),
        MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1        = IOMUX_PAD(0x04C0, 0x01AC, 3, 0x0820, 1, 0),
@@ -688,7 +688,7 @@ enum {
        MX6Q_PAD_DISP0_DAT15__GPIO_5_9          = IOMUX_PAD(0x04C0, 0x01AC, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT15__MMDC_DEBUG_20     = IOMUX_PAD(0x04C0, 0x01AC, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI       = IOMUX_PAD(0x04C4, 0x01B0, 2, 0x0818, 1, 0),
        MX6Q_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC   = IOMUX_PAD(0x04C4, 0x01B0, 3, 0x07DC, 0, 0),
@@ -696,7 +696,7 @@ enum {
        MX6Q_PAD_DISP0_DAT16__GPIO_5_10         = IOMUX_PAD(0x04C4, 0x01B0, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT16__MMDC_DEBUG_21     = IOMUX_PAD(0x04C4, 0x01B0, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO       = IOMUX_PAD(0x04C8, 0x01B4, 2, 0x0814, 1, 0),
        MX6Q_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD   = IOMUX_PAD(0x04C8, 0x01B4, 3, 0x07D0, 0, 0),
@@ -704,7 +704,7 @@ enum {
        MX6Q_PAD_DISP0_DAT17__GPIO_5_11         = IOMUX_PAD(0x04C8, 0x01B4, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT17__MMDC_DEBUG_22     = IOMUX_PAD(0x04C8, 0x01B4, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0        = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C, 1, 0),
        MX6Q_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS  = IOMUX_PAD(0x04CC, 0x01B8, 3, 0x07E0, 0, 0),
@@ -712,7 +712,7 @@ enum {
        MX6Q_PAD_DISP0_DAT18__GPIO_5_12         = IOMUX_PAD(0x04CC, 0x01B8, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT18__MMDC_DEBUG_23     = IOMUX_PAD(0x04CC, 0x01B8, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT18__WEIM_WEIM_CS_2    = IOMUX_PAD(0x04CC, 0x01B8, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DAT_19 = IOMUX_PAD(0x04D0, 0x01BC, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK       = IOMUX_PAD(0x04D0, 0x01BC, 2, 0x0810, 1, 0),
        MX6Q_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD   = IOMUX_PAD(0x04D0, 0x01BC, 3, 0x07CC, 0, 0),
@@ -720,7 +720,7 @@ enum {
        MX6Q_PAD_DISP0_DAT19__GPIO_5_13         = IOMUX_PAD(0x04D0, 0x01BC, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT19__MMDC_DEBUG_24     = IOMUX_PAD(0x04D0, 0x01BC, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT19__WEIM_WEIM_CS_3    = IOMUX_PAD(0x04D0, 0x01BC, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DAT_20 = IOMUX_PAD(0x04D4, 0x01C0, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK       = IOMUX_PAD(0x04D4, 0x01C0, 2, 0x07F4, 1, 0),
        MX6Q_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC   = IOMUX_PAD(0x04D4, 0x01C0, 3, 0x07C4, 0, 0),
@@ -728,7 +728,7 @@ enum {
        MX6Q_PAD_DISP0_DAT20__GPIO_5_14         = IOMUX_PAD(0x04D4, 0x01C0, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT20__MMDC_DEBUG_25     = IOMUX_PAD(0x04D4, 0x01C0, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI       = IOMUX_PAD(0x04D8, 0x01C4, 2, 0x07FC, 1, 0),
        MX6Q_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD   = IOMUX_PAD(0x04D8, 0x01C4, 3, 0x07B8, 1, 0),
@@ -736,7 +736,7 @@ enum {
        MX6Q_PAD_DISP0_DAT21__GPIO_5_15         = IOMUX_PAD(0x04D8, 0x01C4, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT21__MMDC_DEBUG_26     = IOMUX_PAD(0x04D8, 0x01C4, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO       = IOMUX_PAD(0x04DC, 0x01C8, 2, 0x07F8, 1, 0),
        MX6Q_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS  = IOMUX_PAD(0x04DC, 0x01C8, 3, 0x07C8, 1, 0),
@@ -744,7 +744,7 @@ enum {
        MX6Q_PAD_DISP0_DAT22__GPIO_5_16         = IOMUX_PAD(0x04DC, 0x01C8, 5, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT22__MMDC_DEBUG_27     = IOMUX_PAD(0x04DC, 0x01C8, 6, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7, 0x0000, 0, 0),
-       MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, 0),
+       MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1, 0x0000, 0, 0),
        MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0        = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800, 1, 0),
        MX6Q_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD   = IOMUX_PAD(0x04E0, 0x01CC, 3, 0x07B4, 1, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
new file mode 100644 (file)
index 0000000..02a413f
--- /dev/null
@@ -0,0 +1,1053 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MXC_HDMI_H__
+#define __MXC_HDMI_H__
+
+/*
+ * Hdmi controller registers
+ */
+
+/* Identification Registers */
+#define HDMI_DESIGN_ID                          0x0000
+#define HDMI_REVISION_ID                        0x0001
+#define HDMI_PRODUCT_ID0                        0x0002
+#define HDMI_PRODUCT_ID1                        0x0003
+#define HDMI_CONFIG0_ID                         0x0004
+#define HDMI_CONFIG1_ID                         0x0005
+#define HDMI_CONFIG2_ID                         0x0006
+#define HDMI_CONFIG3_ID                         0x0007
+
+/* Interrupt Registers */
+#define HDMI_IH_FC_STAT0                        0x0100
+#define HDMI_IH_FC_STAT1                        0x0101
+#define HDMI_IH_FC_STAT2                        0x0102
+#define HDMI_IH_AS_STAT0                        0x0103
+#define HDMI_IH_PHY_STAT0                       0x0104
+#define HDMI_IH_I2CM_STAT0                      0x0105
+#define HDMI_IH_CEC_STAT0                       0x0106
+#define HDMI_IH_VP_STAT0                        0x0107
+#define HDMI_IH_I2CMPHY_STAT0                   0x0108
+#define HDMI_IH_AHBDMAAUD_STAT0                 0x0109
+
+#define HDMI_IH_MUTE_FC_STAT0                   0x0180
+#define HDMI_IH_MUTE_FC_STAT1                   0x0181
+#define HDMI_IH_MUTE_FC_STAT2                   0x0182
+#define HDMI_IH_MUTE_AS_STAT0                   0x0183
+#define HDMI_IH_MUTE_PHY_STAT0                  0x0184
+#define HDMI_IH_MUTE_I2CM_STAT0                 0x0185
+#define HDMI_IH_MUTE_CEC_STAT0                  0x0186
+#define HDMI_IH_MUTE_VP_STAT0                   0x0187
+#define HDMI_IH_MUTE_I2CMPHY_STAT0              0x0188
+#define HDMI_IH_MUTE_AHBDMAAUD_STAT0            0x0189
+#define HDMI_IH_MUTE                            0x01FF
+
+/* Video Sample Registers */
+#define HDMI_TX_INVID0                          0x0200
+#define HDMI_TX_INSTUFFING                      0x0201
+#define HDMI_TX_GYDATA0                         0x0202
+#define HDMI_TX_GYDATA1                         0x0203
+#define HDMI_TX_RCRDATA0                        0x0204
+#define HDMI_TX_RCRDATA1                        0x0205
+#define HDMI_TX_BCBDATA0                        0x0206
+#define HDMI_TX_BCBDATA1                        0x0207
+
+/* Video Packetizer Registers */
+#define HDMI_VP_STATUS                          0x0800
+#define HDMI_VP_PR_CD                           0x0801
+#define HDMI_VP_STUFF                           0x0802
+#define HDMI_VP_REMAP                           0x0803
+#define HDMI_VP_CONF                            0x0804
+#define HDMI_VP_STAT                            0x0805
+#define HDMI_VP_INT                             0x0806
+#define HDMI_VP_MASK                            0x0807
+#define HDMI_VP_POL                             0x0808
+
+/* Frame Composer Registers */
+#define HDMI_FC_INVIDCONF                       0x1000
+#define HDMI_FC_INHACTV0                        0x1001
+#define HDMI_FC_INHACTV1                        0x1002
+#define HDMI_FC_INHBLANK0                       0x1003
+#define HDMI_FC_INHBLANK1                       0x1004
+#define HDMI_FC_INVACTV0                        0x1005
+#define HDMI_FC_INVACTV1                        0x1006
+#define HDMI_FC_INVBLANK                        0x1007
+#define HDMI_FC_HSYNCINDELAY0                   0x1008
+#define HDMI_FC_HSYNCINDELAY1                   0x1009
+#define HDMI_FC_HSYNCINWIDTH0                   0x100A
+#define HDMI_FC_HSYNCINWIDTH1                   0x100B
+#define HDMI_FC_VSYNCINDELAY                    0x100C
+#define HDMI_FC_VSYNCINWIDTH                    0x100D
+#define HDMI_FC_INFREQ0                         0x100E
+#define HDMI_FC_INFREQ1                         0x100F
+#define HDMI_FC_INFREQ2                         0x1010
+#define HDMI_FC_CTRLDUR                         0x1011
+#define HDMI_FC_EXCTRLDUR                       0x1012
+#define HDMI_FC_EXCTRLSPAC                      0x1013
+#define HDMI_FC_CH0PREAM                        0x1014
+#define HDMI_FC_CH1PREAM                        0x1015
+#define HDMI_FC_CH2PREAM                        0x1016
+#define HDMI_FC_AVICONF3                        0x1017
+#define HDMI_FC_GCP                             0x1018
+#define HDMI_FC_AVICONF0                        0x1019
+#define HDMI_FC_AVICONF1                        0x101A
+#define HDMI_FC_AVICONF2                        0x101B
+#define HDMI_FC_AVIVID                          0x101C
+#define HDMI_FC_AVIETB0                         0x101D
+#define HDMI_FC_AVIETB1                         0x101E
+#define HDMI_FC_AVISBB0                         0x101F
+#define HDMI_FC_AVISBB1                         0x1020
+#define HDMI_FC_AVIELB0                         0x1021
+#define HDMI_FC_AVIELB1                         0x1022
+#define HDMI_FC_AVISRB0                         0x1023
+#define HDMI_FC_AVISRB1                         0x1024
+#define HDMI_FC_AUDICONF0                       0x1025
+#define HDMI_FC_AUDICONF1                       0x1026
+#define HDMI_FC_AUDICONF2                       0x1027
+#define HDMI_FC_AUDICONF3                       0x1028
+#define HDMI_FC_VSDIEEEID0                      0x1029
+#define HDMI_FC_VSDSIZE                         0x102A
+#define HDMI_FC_VSDIEEEID1                      0x1030
+#define HDMI_FC_VSDIEEEID2                      0x1031
+#define HDMI_FC_VSDPAYLOAD0                     0x1032
+#define HDMI_FC_VSDPAYLOAD1                     0x1033
+#define HDMI_FC_VSDPAYLOAD2                     0x1034
+#define HDMI_FC_VSDPAYLOAD3                     0x1035
+#define HDMI_FC_VSDPAYLOAD4                     0x1036
+#define HDMI_FC_VSDPAYLOAD5                     0x1037
+#define HDMI_FC_VSDPAYLOAD6                     0x1038
+#define HDMI_FC_VSDPAYLOAD7                     0x1039
+#define HDMI_FC_VSDPAYLOAD8                     0x103A
+#define HDMI_FC_VSDPAYLOAD9                     0x103B
+#define HDMI_FC_VSDPAYLOAD10                    0x103C
+#define HDMI_FC_VSDPAYLOAD11                    0x103D
+#define HDMI_FC_VSDPAYLOAD12                    0x103E
+#define HDMI_FC_VSDPAYLOAD13                    0x103F
+#define HDMI_FC_VSDPAYLOAD14                    0x1040
+#define HDMI_FC_VSDPAYLOAD15                    0x1041
+#define HDMI_FC_VSDPAYLOAD16                    0x1042
+#define HDMI_FC_VSDPAYLOAD17                    0x1043
+#define HDMI_FC_VSDPAYLOAD18                    0x1044
+#define HDMI_FC_VSDPAYLOAD19                    0x1045
+#define HDMI_FC_VSDPAYLOAD20                    0x1046
+#define HDMI_FC_VSDPAYLOAD21                    0x1047
+#define HDMI_FC_VSDPAYLOAD22                    0x1048
+#define HDMI_FC_VSDPAYLOAD23                    0x1049
+#define HDMI_FC_SPDVENDORNAME0                  0x104A
+#define HDMI_FC_SPDVENDORNAME1                  0x104B
+#define HDMI_FC_SPDVENDORNAME2                  0x104C
+#define HDMI_FC_SPDVENDORNAME3                  0x104D
+#define HDMI_FC_SPDVENDORNAME4                  0x104E
+#define HDMI_FC_SPDVENDORNAME5                  0x104F
+#define HDMI_FC_SPDVENDORNAME6                  0x1050
+#define HDMI_FC_SPDVENDORNAME7                  0x1051
+#define HDMI_FC_SDPPRODUCTNAME0                 0x1052
+#define HDMI_FC_SDPPRODUCTNAME1                 0x1053
+#define HDMI_FC_SDPPRODUCTNAME2                 0x1054
+#define HDMI_FC_SDPPRODUCTNAME3                 0x1055
+#define HDMI_FC_SDPPRODUCTNAME4                 0x1056
+#define HDMI_FC_SDPPRODUCTNAME5                 0x1057
+#define HDMI_FC_SDPPRODUCTNAME6                 0x1058
+#define HDMI_FC_SDPPRODUCTNAME7                 0x1059
+#define HDMI_FC_SDPPRODUCTNAME8                 0x105A
+#define HDMI_FC_SDPPRODUCTNAME9                 0x105B
+#define HDMI_FC_SDPPRODUCTNAME10                0x105C
+#define HDMI_FC_SDPPRODUCTNAME11                0x105D
+#define HDMI_FC_SDPPRODUCTNAME12                0x105E
+#define HDMI_FC_SDPPRODUCTNAME13                0x105F
+#define HDMI_FC_SDPPRODUCTNAME14                0x1060
+#define HDMI_FC_SPDPRODUCTNAME15                0x1061
+#define HDMI_FC_SPDDEVICEINF                    0x1062
+#define HDMI_FC_AUDSCONF                        0x1063
+#define HDMI_FC_AUDSSTAT                        0x1064
+#define HDMI_FC_DATACH0FILL                     0x1070
+#define HDMI_FC_DATACH1FILL                     0x1071
+#define HDMI_FC_DATACH2FILL                     0x1072
+#define HDMI_FC_CTRLQHIGH                       0x1073
+#define HDMI_FC_CTRLQLOW                        0x1074
+#define HDMI_FC_ACP0                            0x1075
+#define HDMI_FC_ACP28                           0x1076
+#define HDMI_FC_ACP27                           0x1077
+#define HDMI_FC_ACP26                           0x1078
+#define HDMI_FC_ACP25                           0x1079
+#define HDMI_FC_ACP24                           0x107A
+#define HDMI_FC_ACP23                           0x107B
+#define HDMI_FC_ACP22                           0x107C
+#define HDMI_FC_ACP21                           0x107D
+#define HDMI_FC_ACP20                           0x107E
+#define HDMI_FC_ACP19                           0x107F
+#define HDMI_FC_ACP18                           0x1080
+#define HDMI_FC_ACP17                           0x1081
+#define HDMI_FC_ACP16                           0x1082
+#define HDMI_FC_ACP15                           0x1083
+#define HDMI_FC_ACP14                           0x1084
+#define HDMI_FC_ACP13                           0x1085
+#define HDMI_FC_ACP12                           0x1086
+#define HDMI_FC_ACP11                           0x1087
+#define HDMI_FC_ACP10                           0x1088
+#define HDMI_FC_ACP9                            0x1089
+#define HDMI_FC_ACP8                            0x108A
+#define HDMI_FC_ACP7                            0x108B
+#define HDMI_FC_ACP6                            0x108C
+#define HDMI_FC_ACP5                            0x108D
+#define HDMI_FC_ACP4                            0x108E
+#define HDMI_FC_ACP3                            0x108F
+#define HDMI_FC_ACP2                            0x1090
+#define HDMI_FC_ACP1                            0x1091
+#define HDMI_FC_ISCR1_0                         0x1092
+#define HDMI_FC_ISCR1_16                        0x1093
+#define HDMI_FC_ISCR1_15                        0x1094
+#define HDMI_FC_ISCR1_14                        0x1095
+#define HDMI_FC_ISCR1_13                        0x1096
+#define HDMI_FC_ISCR1_12                        0x1097
+#define HDMI_FC_ISCR1_11                        0x1098
+#define HDMI_FC_ISCR1_10                        0x1099
+#define HDMI_FC_ISCR1_9                         0x109A
+#define HDMI_FC_ISCR1_8                         0x109B
+#define HDMI_FC_ISCR1_7                         0x109C
+#define HDMI_FC_ISCR1_6                         0x109D
+#define HDMI_FC_ISCR1_5                         0x109E
+#define HDMI_FC_ISCR1_4                         0x109F
+#define HDMI_FC_ISCR1_3                         0x10A0
+#define HDMI_FC_ISCR1_2                         0x10A1
+#define HDMI_FC_ISCR1_1                         0x10A2
+#define HDMI_FC_ISCR2_15                        0x10A3
+#define HDMI_FC_ISCR2_14                        0x10A4
+#define HDMI_FC_ISCR2_13                        0x10A5
+#define HDMI_FC_ISCR2_12                        0x10A6
+#define HDMI_FC_ISCR2_11                        0x10A7
+#define HDMI_FC_ISCR2_10                        0x10A8
+#define HDMI_FC_ISCR2_9                         0x10A9
+#define HDMI_FC_ISCR2_8                         0x10AA
+#define HDMI_FC_ISCR2_7                         0x10AB
+#define HDMI_FC_ISCR2_6                         0x10AC
+#define HDMI_FC_ISCR2_5                         0x10AD
+#define HDMI_FC_ISCR2_4                         0x10AE
+#define HDMI_FC_ISCR2_3                         0x10AF
+#define HDMI_FC_ISCR2_2                         0x10B0
+#define HDMI_FC_ISCR2_1                         0x10B1
+#define HDMI_FC_ISCR2_0                         0x10B2
+#define HDMI_FC_DATAUTO0                        0x10B3
+#define HDMI_FC_DATAUTO1                        0x10B4
+#define HDMI_FC_DATAUTO2                        0x10B5
+#define HDMI_FC_DATMAN                          0x10B6
+#define HDMI_FC_DATAUTO3                        0x10B7
+#define HDMI_FC_RDRB0                           0x10B8
+#define HDMI_FC_RDRB1                           0x10B9
+#define HDMI_FC_RDRB2                           0x10BA
+#define HDMI_FC_RDRB3                           0x10BB
+#define HDMI_FC_RDRB4                           0x10BC
+#define HDMI_FC_RDRB5                           0x10BD
+#define HDMI_FC_RDRB6                           0x10BE
+#define HDMI_FC_RDRB7                           0x10BF
+#define HDMI_FC_STAT0                           0x10D0
+#define HDMI_FC_INT0                            0x10D1
+#define HDMI_FC_MASK0                           0x10D2
+#define HDMI_FC_POL0                            0x10D3
+#define HDMI_FC_STAT1                           0x10D4
+#define HDMI_FC_INT1                            0x10D5
+#define HDMI_FC_MASK1                           0x10D6
+#define HDMI_FC_POL1                            0x10D7
+#define HDMI_FC_STAT2                           0x10D8
+#define HDMI_FC_INT2                            0x10D9
+#define HDMI_FC_MASK2                           0x10DA
+#define HDMI_FC_POL2                            0x10DB
+#define HDMI_FC_PRCONF                          0x10E0
+
+#define HDMI_FC_GMD_STAT                        0x1100
+#define HDMI_FC_GMD_EN                          0x1101
+#define HDMI_FC_GMD_UP                          0x1102
+#define HDMI_FC_GMD_CONF                        0x1103
+#define HDMI_FC_GMD_HB                          0x1104
+#define HDMI_FC_GMD_PB0                         0x1105
+#define HDMI_FC_GMD_PB1                         0x1106
+#define HDMI_FC_GMD_PB2                         0x1107
+#define HDMI_FC_GMD_PB3                         0x1108
+#define HDMI_FC_GMD_PB4                         0x1109
+#define HDMI_FC_GMD_PB5                         0x110A
+#define HDMI_FC_GMD_PB6                         0x110B
+#define HDMI_FC_GMD_PB7                         0x110C
+#define HDMI_FC_GMD_PB8                         0x110D
+#define HDMI_FC_GMD_PB9                         0x110E
+#define HDMI_FC_GMD_PB10                        0x110F
+#define HDMI_FC_GMD_PB11                        0x1110
+#define HDMI_FC_GMD_PB12                        0x1111
+#define HDMI_FC_GMD_PB13                        0x1112
+#define HDMI_FC_GMD_PB14                        0x1113
+#define HDMI_FC_GMD_PB15                        0x1114
+#define HDMI_FC_GMD_PB16                        0x1115
+#define HDMI_FC_GMD_PB17                        0x1116
+#define HDMI_FC_GMD_PB18                        0x1117
+#define HDMI_FC_GMD_PB19                        0x1118
+#define HDMI_FC_GMD_PB20                        0x1119
+#define HDMI_FC_GMD_PB21                        0x111A
+#define HDMI_FC_GMD_PB22                        0x111B
+#define HDMI_FC_GMD_PB23                        0x111C
+#define HDMI_FC_GMD_PB24                        0x111D
+#define HDMI_FC_GMD_PB25                        0x111E
+#define HDMI_FC_GMD_PB26                        0x111F
+#define HDMI_FC_GMD_PB27                        0x1120
+
+#define HDMI_FC_DBGFORCE                        0x1200
+#define HDMI_FC_DBGAUD0CH0                      0x1201
+#define HDMI_FC_DBGAUD1CH0                      0x1202
+#define HDMI_FC_DBGAUD2CH0                      0x1203
+#define HDMI_FC_DBGAUD0CH1                      0x1204
+#define HDMI_FC_DBGAUD1CH1                      0x1205
+#define HDMI_FC_DBGAUD2CH1                      0x1206
+#define HDMI_FC_DBGAUD0CH2                      0x1207
+#define HDMI_FC_DBGAUD1CH2                      0x1208
+#define HDMI_FC_DBGAUD2CH2                      0x1209
+#define HDMI_FC_DBGAUD0CH3                      0x120A
+#define HDMI_FC_DBGAUD1CH3                      0x120B
+#define HDMI_FC_DBGAUD2CH3                      0x120C
+#define HDMI_FC_DBGAUD0CH4                      0x120D
+#define HDMI_FC_DBGAUD1CH4                      0x120E
+#define HDMI_FC_DBGAUD2CH4                      0x120F
+#define HDMI_FC_DBGAUD0CH5                      0x1210
+#define HDMI_FC_DBGAUD1CH5                      0x1211
+#define HDMI_FC_DBGAUD2CH5                      0x1212
+#define HDMI_FC_DBGAUD0CH6                      0x1213
+#define HDMI_FC_DBGAUD1CH6                      0x1214
+#define HDMI_FC_DBGAUD2CH6                      0x1215
+#define HDMI_FC_DBGAUD0CH7                      0x1216
+#define HDMI_FC_DBGAUD1CH7                      0x1217
+#define HDMI_FC_DBGAUD2CH7                      0x1218
+#define HDMI_FC_DBGTMDS0                        0x1219
+#define HDMI_FC_DBGTMDS1                        0x121A
+#define HDMI_FC_DBGTMDS2                        0x121B
+
+/* HDMI Source PHY Registers */
+#define HDMI_PHY_CONF0                          0x3000
+#define HDMI_PHY_TST0                           0x3001
+#define HDMI_PHY_TST1                           0x3002
+#define HDMI_PHY_TST2                           0x3003
+#define HDMI_PHY_STAT0                          0x3004
+#define HDMI_PHY_INT0                           0x3005
+#define HDMI_PHY_MASK0                          0x3006
+#define HDMI_PHY_POL0                           0x3007
+
+/* HDMI Master PHY Registers */
+#define HDMI_PHY_I2CM_SLAVE_ADDR                0x3020
+#define HDMI_PHY_I2CM_ADDRESS_ADDR              0x3021
+#define HDMI_PHY_I2CM_DATAO_1_ADDR              0x3022
+#define HDMI_PHY_I2CM_DATAO_0_ADDR              0x3023
+#define HDMI_PHY_I2CM_DATAI_1_ADDR              0x3024
+#define HDMI_PHY_I2CM_DATAI_0_ADDR              0x3025
+#define HDMI_PHY_I2CM_OPERATION_ADDR            0x3026
+#define HDMI_PHY_I2CM_INT_ADDR                  0x3027
+#define HDMI_PHY_I2CM_CTLINT_ADDR               0x3028
+#define HDMI_PHY_I2CM_DIV_ADDR                  0x3029
+#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR             0x302a
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR        0x302b
+#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR        0x302c
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR        0x302d
+#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR        0x302e
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR        0x302f
+#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR        0x3030
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR        0x3031
+#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR        0x3032
+
+/* Audio Sampler Registers */
+#define HDMI_AUD_CONF0                          0x3100
+#define HDMI_AUD_CONF1                          0x3101
+#define HDMI_AUD_INT                            0x3102
+#define HDMI_AUD_CONF2                          0x3103
+#define HDMI_AUD_N1                             0x3200
+#define HDMI_AUD_N2                             0x3201
+#define HDMI_AUD_N3                             0x3202
+#define HDMI_AUD_CTS1                           0x3203
+#define HDMI_AUD_CTS2                           0x3204
+#define HDMI_AUD_CTS3                           0x3205
+#define HDMI_AUD_INPUTCLKFS                     0x3206
+#define HDMI_AUD_SPDIFINT                      0x3302
+#define HDMI_AUD_CONF0_HBR                      0x3400
+#define HDMI_AUD_HBR_STATUS                     0x3401
+#define HDMI_AUD_HBR_INT                        0x3402
+#define HDMI_AUD_HBR_POL                        0x3403
+#define HDMI_AUD_HBR_MASK                       0x3404
+
+/* Generic Parallel Audio Interface Registers */
+/* Not used as GPAUD interface is not enabled in hw */
+#define HDMI_GP_CONF0                           0x3500
+#define HDMI_GP_CONF1                           0x3501
+#define HDMI_GP_CONF2                           0x3502
+#define HDMI_GP_STAT                            0x3503
+#define HDMI_GP_INT                             0x3504
+#define HDMI_GP_MASK                            0x3505
+#define HDMI_GP_POL                             0x3506
+
+/* Audio DMA Registers */
+#define HDMI_AHB_DMA_CONF0                      0x3600
+#define HDMI_AHB_DMA_START                      0x3601
+#define HDMI_AHB_DMA_STOP                       0x3602
+#define HDMI_AHB_DMA_THRSLD                     0x3603
+#define HDMI_AHB_DMA_STRADDR0                   0x3604
+#define HDMI_AHB_DMA_STRADDR1                   0x3605
+#define HDMI_AHB_DMA_STRADDR2                   0x3606
+#define HDMI_AHB_DMA_STRADDR3                   0x3607
+#define HDMI_AHB_DMA_STPADDR0                   0x3608
+#define HDMI_AHB_DMA_STPADDR1                   0x3609
+#define HDMI_AHB_DMA_STPADDR2                   0x360a
+#define HDMI_AHB_DMA_STPADDR3                   0x360b
+#define HDMI_AHB_DMA_BSTADDR0                   0x360c
+#define HDMI_AHB_DMA_BSTADDR1                   0x360d
+#define HDMI_AHB_DMA_BSTADDR2                   0x360e
+#define HDMI_AHB_DMA_BSTADDR3                   0x360f
+#define HDMI_AHB_DMA_MBLENGTH0                  0x3610
+#define HDMI_AHB_DMA_MBLENGTH1                  0x3611
+#define HDMI_AHB_DMA_STAT                       0x3612
+#define HDMI_AHB_DMA_INT                        0x3613
+#define HDMI_AHB_DMA_MASK                       0x3614
+#define HDMI_AHB_DMA_POL                        0x3615
+#define HDMI_AHB_DMA_CONF1                      0x3616
+#define HDMI_AHB_DMA_BUFFSTAT                   0x3617
+#define HDMI_AHB_DMA_BUFFINT                    0x3618
+#define HDMI_AHB_DMA_BUFFMASK                   0x3619
+#define HDMI_AHB_DMA_BUFFPOL                    0x361a
+
+/* Main Controller Registers */
+#define HDMI_MC_SFRDIV                          0x4000
+#define HDMI_MC_CLKDIS                          0x4001
+#define HDMI_MC_SWRSTZ                          0x4002
+#define HDMI_MC_OPCTRL                          0x4003
+#define HDMI_MC_FLOWCTRL                        0x4004
+#define HDMI_MC_PHYRSTZ                         0x4005
+#define HDMI_MC_LOCKONCLOCK                     0x4006
+#define HDMI_MC_HEACPHY_RST                     0x4007
+
+/* Color Space  Converter Registers */
+#define HDMI_CSC_CFG                            0x4100
+#define HDMI_CSC_SCALE                          0x4101
+#define HDMI_CSC_COEF_A1_MSB                    0x4102
+#define HDMI_CSC_COEF_A1_LSB                    0x4103
+#define HDMI_CSC_COEF_A2_MSB                    0x4104
+#define HDMI_CSC_COEF_A2_LSB                    0x4105
+#define HDMI_CSC_COEF_A3_MSB                    0x4106
+#define HDMI_CSC_COEF_A3_LSB                    0x4107
+#define HDMI_CSC_COEF_A4_MSB                    0x4108
+#define HDMI_CSC_COEF_A4_LSB                    0x4109
+#define HDMI_CSC_COEF_B1_MSB                    0x410A
+#define HDMI_CSC_COEF_B1_LSB                    0x410B
+#define HDMI_CSC_COEF_B2_MSB                    0x410C
+#define HDMI_CSC_COEF_B2_LSB                    0x410D
+#define HDMI_CSC_COEF_B3_MSB                    0x410E
+#define HDMI_CSC_COEF_B3_LSB                    0x410F
+#define HDMI_CSC_COEF_B4_MSB                    0x4110
+#define HDMI_CSC_COEF_B4_LSB                    0x4111
+#define HDMI_CSC_COEF_C1_MSB                    0x4112
+#define HDMI_CSC_COEF_C1_LSB                    0x4113
+#define HDMI_CSC_COEF_C2_MSB                    0x4114
+#define HDMI_CSC_COEF_C2_LSB                    0x4115
+#define HDMI_CSC_COEF_C3_MSB                    0x4116
+#define HDMI_CSC_COEF_C3_LSB                    0x4117
+#define HDMI_CSC_COEF_C4_MSB                    0x4118
+#define HDMI_CSC_COEF_C4_LSB                    0x4119
+
+/* HDCP Encryption Engine Registers */
+#define HDMI_A_HDCPCFG0                         0x5000
+#define HDMI_A_HDCPCFG1                         0x5001
+#define HDMI_A_HDCPOBS0                         0x5002
+#define HDMI_A_HDCPOBS1                         0x5003
+#define HDMI_A_HDCPOBS2                         0x5004
+#define HDMI_A_HDCPOBS3                         0x5005
+#define HDMI_A_APIINTCLR                        0x5006
+#define HDMI_A_APIINTSTAT                       0x5007
+#define HDMI_A_APIINTMSK                        0x5008
+#define HDMI_A_VIDPOLCFG                        0x5009
+#define HDMI_A_OESSWCFG                         0x500A
+#define HDMI_A_TIMER1SETUP0                     0x500B
+#define HDMI_A_TIMER1SETUP1                     0x500C
+#define HDMI_A_TIMER2SETUP0                     0x500D
+#define HDMI_A_TIMER2SETUP1                     0x500E
+#define HDMI_A_100MSCFG                         0x500F
+#define HDMI_A_2SCFG0                           0x5010
+#define HDMI_A_2SCFG1                           0x5011
+#define HDMI_A_5SCFG0                           0x5012
+#define HDMI_A_5SCFG1                           0x5013
+#define HDMI_A_SRMVERLSB                        0x5014
+#define HDMI_A_SRMVERMSB                        0x5015
+#define HDMI_A_SRMCTRL                          0x5016
+#define HDMI_A_SFRSETUP                         0x5017
+#define HDMI_A_I2CHSETUP                        0x5018
+#define HDMI_A_INTSETUP                         0x5019
+#define HDMI_A_PRESETUP                         0x501A
+#define HDMI_A_SRM_BASE                         0x5020
+
+/* CEC Engine Registers */
+#define HDMI_CEC_CTRL                           0x7D00
+#define HDMI_CEC_STAT                           0x7D01
+#define HDMI_CEC_MASK                           0x7D02
+#define HDMI_CEC_POLARITY                       0x7D03
+#define HDMI_CEC_INT                            0x7D04
+#define HDMI_CEC_ADDR_L                         0x7D05
+#define HDMI_CEC_ADDR_H                         0x7D06
+#define HDMI_CEC_TX_CNT                         0x7D07
+#define HDMI_CEC_RX_CNT                         0x7D08
+#define HDMI_CEC_TX_DATA0                       0x7D10
+#define HDMI_CEC_TX_DATA1                       0x7D11
+#define HDMI_CEC_TX_DATA2                       0x7D12
+#define HDMI_CEC_TX_DATA3                       0x7D13
+#define HDMI_CEC_TX_DATA4                       0x7D14
+#define HDMI_CEC_TX_DATA5                       0x7D15
+#define HDMI_CEC_TX_DATA6                       0x7D16
+#define HDMI_CEC_TX_DATA7                       0x7D17
+#define HDMI_CEC_TX_DATA8                       0x7D18
+#define HDMI_CEC_TX_DATA9                       0x7D19
+#define HDMI_CEC_TX_DATA10                      0x7D1a
+#define HDMI_CEC_TX_DATA11                      0x7D1b
+#define HDMI_CEC_TX_DATA12                      0x7D1c
+#define HDMI_CEC_TX_DATA13                      0x7D1d
+#define HDMI_CEC_TX_DATA14                      0x7D1e
+#define HDMI_CEC_TX_DATA15                      0x7D1f
+#define HDMI_CEC_RX_DATA0                       0x7D20
+#define HDMI_CEC_RX_DATA1                       0x7D21
+#define HDMI_CEC_RX_DATA2                       0x7D22
+#define HDMI_CEC_RX_DATA3                       0x7D23
+#define HDMI_CEC_RX_DATA4                       0x7D24
+#define HDMI_CEC_RX_DATA5                       0x7D25
+#define HDMI_CEC_RX_DATA6                       0x7D26
+#define HDMI_CEC_RX_DATA7                       0x7D27
+#define HDMI_CEC_RX_DATA8                       0x7D28
+#define HDMI_CEC_RX_DATA9                       0x7D29
+#define HDMI_CEC_RX_DATA10                      0x7D2a
+#define HDMI_CEC_RX_DATA11                      0x7D2b
+#define HDMI_CEC_RX_DATA12                      0x7D2c
+#define HDMI_CEC_RX_DATA13                      0x7D2d
+#define HDMI_CEC_RX_DATA14                      0x7D2e
+#define HDMI_CEC_RX_DATA15                      0x7D2f
+#define HDMI_CEC_LOCK                           0x7D30
+#define HDMI_CEC_WKUPCTRL                       0x7D31
+
+/* I2C Master Registers (E-DDC) */
+#define HDMI_I2CM_SLAVE                         0x7E00
+#define HDMI_I2CMESS                            0x7E01
+#define HDMI_I2CM_DATAO                         0x7E02
+#define HDMI_I2CM_DATAI                         0x7E03
+#define HDMI_I2CM_OPERATION                     0x7E04
+#define HDMI_I2CM_INT                           0x7E05
+#define HDMI_I2CM_CTLINT                        0x7E06
+#define HDMI_I2CM_DIV                           0x7E07
+#define HDMI_I2CM_SEGADDR                       0x7E08
+#define HDMI_I2CM_SOFTRSTZ                      0x7E09
+#define HDMI_I2CM_SEGPTR                        0x7E0A
+#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR            0x7E0B
+#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR            0x7E0C
+#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR            0x7E0D
+#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR            0x7E0E
+#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR            0x7E0F
+#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR            0x7E10
+#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
+#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
+
+/* Random Number Generator Registers (RNG) */
+#define HDMI_RNG_BASE                           0x8000
+
+
+/*
+ * Register field definitions
+ */
+enum {
+/* IH_FC_INT2 field values */
+       HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
+       HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
+       HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_FC_STAT2 field values */
+       HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
+       HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+       HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_PHY_STAT0 field values */
+       HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
+       HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
+       HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
+       HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
+       HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
+       HDMI_IH_PHY_STAT0_HPD = 0x1,
+
+/* IH_MUTE_I2CMPHY_STAT0 field values */
+       HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
+       HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
+
+/* IH_AHBDMAAUD_STAT0 field values */
+       HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
+       HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
+       HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
+       HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
+       HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
+       HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
+
+/* IH_MUTE_FC_STAT2 field values */
+       HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
+       HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+       HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* IH_MUTE_AHBDMAAUD_STAT0 field values */
+       HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
+       HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
+       HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
+       HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
+       HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
+       HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
+
+/* IH_MUTE field values */
+       HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
+       HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
+
+/* TX_INVID0 field values */
+       HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
+       HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
+       HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
+       HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
+       HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
+
+/* TX_INSTUFFING field values */
+       HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
+       HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
+       HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
+       HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
+       HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
+       HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
+       HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
+       HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
+       HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
+
+/* VP_PR_CD field values */
+       HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
+       HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
+       HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
+       HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
+
+/* VP_STUFF field values */
+       HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
+       HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
+       HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
+       HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
+       HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
+       HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
+       HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
+       HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
+       HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
+       HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
+       HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
+       HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
+       HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
+       HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
+       HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
+
+/* VP_CONF field values */
+       HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
+       HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
+       HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
+       HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
+       HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
+       HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
+       HDMI_VP_CONF_PR_EN_MASK = 0x10,
+       HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
+       HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
+       HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
+       HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
+       HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
+       HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
+       HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
+       HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
+       HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
+       HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
+       HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
+       HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
+
+/* VP_REMAP field values */
+       HDMI_VP_REMAP_MASK = 0x3,
+       HDMI_VP_REMAP_YCC422_24bit = 0x2,
+       HDMI_VP_REMAP_YCC422_20bit = 0x1,
+       HDMI_VP_REMAP_YCC422_16bit = 0x0,
+
+/* FC_INVIDCONF field values */
+       HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
+       HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
+       HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
+       HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
+       HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
+       HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+       HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
+       HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
+       HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
+       HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
+       HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
+       HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
+       HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
+       HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
+       HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
+       HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
+       HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
+       HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
+       HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
+       HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
+       HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
+
+/* FC_AUDICONF0 field values */
+       HDMI_FC_AUDICONF0_CC_OFFSET = 4,
+       HDMI_FC_AUDICONF0_CC_MASK = 0x70,
+       HDMI_FC_AUDICONF0_CT_OFFSET = 0,
+       HDMI_FC_AUDICONF0_CT_MASK = 0xF,
+
+/* FC_AUDICONF1 field values */
+       HDMI_FC_AUDICONF1_SS_OFFSET = 3,
+       HDMI_FC_AUDICONF1_SS_MASK = 0x18,
+       HDMI_FC_AUDICONF1_SF_OFFSET = 0,
+       HDMI_FC_AUDICONF1_SF_MASK = 0x7,
+
+/* FC_AUDICONF3 field values */
+       HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
+       HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
+       HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
+       HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
+       HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
+       HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
+
+/* FC_AUDSCHNLS0 field values */
+       HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
+       HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
+       HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
+       HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
+
+/* FC_AUDSCHNLS3-6 field values */
+       HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
+       HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
+       HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
+       HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
+       HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
+       HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
+       HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
+       HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
+
+       HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
+       HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
+       HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
+       HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
+       HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
+       HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
+       HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
+       HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
+
+/* HDMI_FC_AUDSCHNLS7 field values */
+       HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
+       HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
+
+/* HDMI_FC_AUDSCHNLS8 field values */
+       HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
+       HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
+       HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
+       HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
+
+/* FC_AUDSCONF field values */
+       HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
+       HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
+       HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
+       HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
+       HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
+       HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
+
+/* FC_STAT2 field values */
+       HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
+       HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
+       HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_INT2 field values */
+       HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
+       HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
+       HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_MASK2 field values */
+       HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
+       HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
+       HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
+
+/* FC_PRCONF field values */
+       HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
+       HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
+       HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
+       HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
+
+/* FC_AVICONF0-FC_AVICONF3 field values */
+       HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
+       HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
+       HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
+       HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
+       HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
+       HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
+       HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
+       HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
+       HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
+       HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
+       HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
+       HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
+       HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
+       HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
+       HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
+       HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
+
+       HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
+       HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
+       HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
+       HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
+       HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
+       HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
+       HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
+       HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
+       HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
+       HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
+       HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
+       HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
+       HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
+       HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
+
+       HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
+       HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
+       HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
+       HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
+       HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
+       HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
+       HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
+       HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
+       HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
+       HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
+       HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
+       HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
+       HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
+       HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
+       HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
+       HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
+       HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
+       HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
+
+       HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
+       HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
+       HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
+       HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
+       HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
+       HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
+       HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
+       HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
+
+/* FC_DBGFORCE field values */
+       HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
+       HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
+
+/* PHY_CONF0 field values */
+       HDMI_PHY_CONF0_PDZ_MASK = 0x80,
+       HDMI_PHY_CONF0_PDZ_OFFSET = 7,
+       HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
+       HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
+       HDMI_PHY_CONF0_SPARECTRL = 0x20,
+       HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
+       HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
+       HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
+       HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
+       HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
+       HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
+       HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
+       HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
+       HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
+       HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
+
+/* PHY_TST0 field values */
+       HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
+       HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
+       HDMI_PHY_TST0_TSTEN_MASK = 0x10,
+       HDMI_PHY_TST0_TSTEN_OFFSET = 4,
+       HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
+       HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
+
+/* PHY_STAT0 field values */
+       HDMI_PHY_RX_SENSE3 = 0x80,
+       HDMI_PHY_RX_SENSE2 = 0x40,
+       HDMI_PHY_RX_SENSE1 = 0x20,
+       HDMI_PHY_RX_SENSE0 = 0x10,
+       HDMI_PHY_HPD = 0x02,
+       HDMI_PHY_TX_PHY_LOCK = 0x01,
+
+/* PHY_I2CM_SLAVE_ADDR field values */
+       HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
+       HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
+
+/* PHY_I2CM_OPERATION_ADDR field values */
+       HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
+       HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
+
+/* HDMI_PHY_I2CM_INT_ADDR */
+       HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
+       HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
+
+/* HDMI_PHY_I2CM_CTLINT_ADDR */
+       HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
+       HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
+       HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
+       HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
+
+/* AUD_CTS3 field values */
+       HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
+       HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
+       HDMI_AUD_CTS3_N_SHIFT_1 = 0,
+       HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
+       HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
+       HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
+       HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
+       HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
+       /* note that the CTS3 MANUAL bit has been removed
+          from our part. Can't set it, will read as 0. */
+       HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
+       HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
+
+/* AHB_DMA_CONF0 field values */
+       HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
+       HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
+       HDMI_AHB_DMA_CONF0_HBR = 0x10,
+       HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
+       HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
+       HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
+       HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
+       HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
+       HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
+       HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
+       HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
+
+/* HDMI_AHB_DMA_START field values */
+       HDMI_AHB_DMA_START_START_OFFSET = 0,
+       HDMI_AHB_DMA_START_START_MASK = 0x01,
+
+/* HDMI_AHB_DMA_STOP field values */
+       HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
+       HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
+
+/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
+       HDMI_AHB_DMA_DONE = 0x80,
+       HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
+       HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
+       HDMI_AHB_DMA_ERROR = 0x10,
+       HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
+       HDMI_AHB_DMA_FIFO_FULL = 0x02,
+       HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
+
+/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
+       HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
+       HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
+
+/* MC_CLKDIS field values */
+       HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
+       HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
+       HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
+       HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
+       HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
+       HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
+       HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
+
+/* MC_SWRSTZ field values */
+       HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
+
+/* MC_FLOWCTRL field values */
+       HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
+       HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
+       HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
+
+/* MC_PHYRSTZ field values */
+       HDMI_MC_PHYRSTZ_ASSERT = 0x0,
+       HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
+
+/* MC_HEACPHY_RST field values */
+       HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
+       HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
+
+/* CSC_CFG field values */
+       HDMI_CSC_CFG_INTMODE_MASK = 0x30,
+       HDMI_CSC_CFG_INTMODE_OFFSET = 4,
+       HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
+       HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
+       HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
+       HDMI_CSC_CFG_DECMODE_MASK = 0x3,
+       HDMI_CSC_CFG_DECMODE_OFFSET = 0,
+       HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
+       HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
+       HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
+       HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
+
+/* CSC_SCALE field values */
+       HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
+       HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
+       HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
+       HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
+       HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
+       HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
+
+/* A_HDCPCFG0 field values */
+       HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
+       HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
+       HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
+       HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
+       HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
+       HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
+       HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
+       HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
+       HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
+       HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
+       HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
+       HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
+       HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
+       HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
+       HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
+       HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
+       HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
+       HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
+       HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
+       HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
+       HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
+       HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
+       HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
+       HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
+
+/* A_HDCPCFG1 field values */
+       HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
+       HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
+       HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
+       HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
+       HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
+       HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
+       HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
+       HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
+       HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
+       HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
+       HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
+
+/* A_VIDPOLCFG field values */
+       HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
+       HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
+       HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
+       HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
+       HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
+       HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
+       HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
+       HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
+       HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
+       HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
+       HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
+};
+
+#endif /* __MXC_HDMI_H__ */
index 4558f4fba251c26172634d5180dc6e8d1f44c46b..c34bb76ad453d51292bee52003974c24fa057688 100644 (file)
@@ -98,6 +98,7 @@ typedef u64 iomux_v3_cfg_t;
 #define MUX_CONFIG_SION                (0x1 << 4)
 
 int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
-int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
+int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
+                                    unsigned count);
 
 #endif /* __MACH_IOMUX_V3_H__*/
index 2f42fc97af46db26987c48581dbb2ddae0a749f8..57fb1b139e7a0bb9f21fa84139289338bd21d7ac 100644 (file)
  */
 
 #include <config.h>
-#include <asm-offsets.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-
-/*
- * Configuration for the flea3 board.
- * These defines are used by the included macros and must
- * be defined first
- */
-#define AIPS_MPR_CONFIG                0x77777777
-#define AIPS_OPACR_CONFIG      0x00000000
-
-/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-#define MAX_MPR_CONFIG         0x00302154
-
-/* SGPCR - always park on last master */
-#define MAX_SGPCR_CONFIG       0x00000010
-
-/* MGPCR - restore default values */
-#define MAX_MGPCR_CONFIG       0x00000000
-
-/*
- * M3IF Control Register (M3IFCTL)
- * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
- * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
- * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
- * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
- * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
- * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
- * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
- *                                               ------------
- *                                                 0x00000040
- */
-#define M3IF_CONFIG            0x00000040
-
-#define CCM_PDR0_CONFIG                0x00801000
-
-/*
- * includes MX35 utility macros
- */
 #include <asm/arch/lowlevel_macro.S>
 
 .globl lowlevel_init
index e947330a1030a0e7442ddbc8d7bc0f060fc78503..41d6bb6a9c95cd1a2fcda6df7c8556c09dbb6239 100644 (file)
@@ -217,6 +217,7 @@ int board_mmc_init(bd_t *bis)
                PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
                PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 
+       esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
        return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }
 #endif
index 698c4cf0c511e7bf507a8f62549ca3de3a3703af..75bb95861968668fde102df20f6a9adfbd6c3716 100644 (file)
@@ -23,6 +23,7 @@
 #include <asm/arch/imx-regs.h>
 #include <generated/asm-offsets.h>
 #include "mx35pdk.h"
+#include <asm/arch/lowlevel_macro.S>
 
 /*
  * return soc version
        addne \ret, \ret, #0x10
 .endm
 
-/*
- * AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.
- */
-.macro init_aips
-       /*
-        * Set all MPROTx to be non-bufferable, trusted for R/W,
-        * not forced to user-mode.
-        */
-       ldr r0, =AIPS1_BASE_ADDR
-       ldr r1, =AIPS_MPR_CONFIG
-       str r1, [r0, #0x00]
-       str r1, [r0, #0x04]
-       ldr r0, =AIPS2_BASE_ADDR
-       str r1, [r0, #0x00]
-       str r1, [r0, #0x04]
-
-       /*
-        * Clear the on and off peripheral modules Supervisor Protect bit
-        * for SDMA to access them. Did not change the AIPS control registers
-        * (offset 0x20) access type
-        */
-       ldr r0, =AIPS1_BASE_ADDR
-       ldr r1, =AIPS_OPACR_CONFIG
-       str r1, [r0, #0x40]
-       str r1, [r0, #0x44]
-       str r1, [r0, #0x48]
-       str r1, [r0, #0x4C]
-       str r1, [r0, #0x50]
-       ldr r0, =AIPS2_BASE_ADDR
-       str r1, [r0, #0x40]
-       str r1, [r0, #0x44]
-       str r1, [r0, #0x48]
-       str r1, [r0, #0x4C]
-       str r1, [r0, #0x50]
-.endm
-
-/* MAX (Multi-Layer AHB Crossbar Switch) setup */
-.macro init_max
-       ldr r0, =MAX_BASE_ADDR
-       /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-       ldr r1, =MAX_MPR_CONFIG
-       str r1, [r0, #0x000]        /* for S0 */
-       str r1, [r0, #0x100]        /* for S1 */
-       str r1, [r0, #0x200]        /* for S2 */
-       str r1, [r0, #0x300]        /* for S3 */
-       str r1, [r0, #0x400]        /* for S4 */
-       /* SGPCR - always park on last master */
-       ldr r1, =MAX_SGPCR_CONFIG
-       str r1, [r0, #0x010]        /* for S0 */
-       str r1, [r0, #0x110]        /* for S1 */
-       str r1, [r0, #0x210]        /* for S2 */
-       str r1, [r0, #0x310]        /* for S3 */
-       str r1, [r0, #0x410]        /* for S4 */
-       /* MGPCR - restore default values */
-       ldr r1, =MAX_MGPCR_CONFIG
-       str r1, [r0, #0x800]        /* for M0 */
-       str r1, [r0, #0x900]        /* for M1 */
-       str r1, [r0, #0xA00]        /* for M2 */
-       str r1, [r0, #0xB00]        /* for M3 */
-       str r1, [r0, #0xC00]        /* for M4 */
-       str r1, [r0, #0xD00]        /* for M5 */
-.endm
-
-/* M3IF setup */
-.macro init_m3if
-       /* Configure M3IF registers */
-       ldr r1, =M3IF_BASE_ADDR
-       /*
-       * M3IF Control Register (M3IFCTL)
-       * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
-       * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
-       * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
-       * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
-       * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
-       * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
-       * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
-       * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
-       *                                               ------------
-       *                                                 0x00000040
-       */
-       ldr r0, =M3IF_CONFIG
-       str r0, [r1]  /* M3IF control reg */
-.endm
-
 /* CPLD on CS5 setup */
 .macro init_debug_board
        ldr r0, =DBG_BASE_ADDR
 lowlevel_init:
        mov r10, lr
 
-       mrc 15, 0, r1, c1, c0, 0
-
-       mrc 15, 0, r0, c1, c0, 1
-       orr r0, r0, #7
-       mcr 15, 0, r0, c1, c0, 1
-       orr r1, r1, #(1<<11)
-
-       /* Set unaligned access enable */
-       orr r1, r1, #(1<<22)
-
-       /* Set low int latency enable */
-       orr r1, r1, #(1<<21)
-
-       mcr 15, 0, r1, c1, c0, 0
-
-       mov r0, #0
-
-       /* Set branch prediction enable */
-       mcr 15, 0, r0, c15, c2, 4
-
-       mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
-       mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
-       mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */
-
-       /*
-        * initializes very early AIPS
-        * Then it also initializes Multi-Layer AHB Crossbar Switch,
-        * M3IF
-        * Also setup the Peripheral Port Remap register inside the core
-        */
-       ldr r0, =0x40000015        /* start from AIPS 2GB region */
-       mcr p15, 0, r0, c15, c2, 4
+       core_init
 
        init_aips
 
index 7cb6b3086f1d79088aeb3531fc6c0acda83cae9c..a12531fb892cf5dc7b0fb5e234fec6361f60a3b5 100644 (file)
@@ -27,6 +27,7 @@
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/mx35_pins.h>
 #include <asm/arch/iomux.h>
 #include <i2c.h>
@@ -292,6 +293,7 @@ int board_mmc_init(bd_t *bis)
        mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
        mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
 
+       esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
        return fsl_esdhc_initialize(bis, &esdhc_cfg);
 }
 
index 6aeb21835b1e1055d37ac9b6e871dbd2ad2a2a3c..f15aa4f7bed5a162d7f10d9112102a503621f0fb 100644 (file)
 #ifndef __BOARD_MX35_3STACK_H
 #define __BOARD_MX35_3STACK_H
 
-#define AIPS_MPR_CONFIG                0x77777777
-#define AIPS_OPACR_CONFIG      0x00000000
-
-/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-#define MAX_MPR_CONFIG         0x00302154
-/* SGPCR - always park on last master */
-#define MAX_SGPCR_CONFIG       0x00000010
-/* MGPCR - restore default values */
-#define MAX_MGPCR_CONFIG       0x00000000
-
-/*
- * M3IF Control Register (M3IFCTL)
- * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
- * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
- * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
- * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
- * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
- * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
- * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
- *                                               ------------
- *                                                 0x00000040
- */
-#define M3IF_CONFIG    0x00000040
-
 #define DBG_BASE_ADDR          WEIM_CTRL_CS5
 #define DBG_CSCR_U_CONFIG      0x0000D843
 #define DBG_CSCR_L_CONFIG      0x22252521
index a94701cbf1757d04ad0b894c039072d5cf8fd399..421d8c224444e4ba935f71e6cf9fde39307e385a 100644 (file)
@@ -29,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -358,6 +359,9 @@ int board_mmc_init(bd_t *bis)
        u32 index;
        s32 status = 0;
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
                        index++) {
                switch (index) {
@@ -467,7 +471,7 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-static struct fb_videomode claa_wvga = {
+static struct fb_videomode const claa_wvga = {
        .name           = "CLAA07LC0ACW",
        .refresh        = 57,
        .xres           = 800,
index 08c779559a4443530be854cf1fa2820aadea6198..2fc8570f23b5a1f496be27f114852260d7024f38 100644 (file)
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <netdev.h>
@@ -106,6 +107,9 @@ int board_mmc_init(bd_t *bis)
        u32 index;
        s32 status = 0;
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
                switch (index) {
                case 0:
index b11a94c652fd03effeaa23b551b45da398dd0baf..bb4621d62ece80a139b2138a991360867540a8d5 100644 (file)
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <asm/imx-common/boot_mode.h>
@@ -232,6 +233,9 @@ int board_mmc_init(bd_t *bis)
        u32 index;
        s32 status = 0;
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
                switch (index) {
                case 0:
index 65432099a1e3ef741c502da7dbcf51ebb8fe7211..a11e8831866cfa143bb18ba0f6aeac3fec71b8a1 100644 (file)
@@ -192,6 +192,9 @@ int board_mmc_init(bd_t *bis)
        u32 index;
        s32 status = 0;
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
                switch (index) {
                case 0:
@@ -409,7 +412,7 @@ static void clock_1GHz(void)
                printf("CPU:   Switch DDR clock to 400MHz failed\n");
 }
 
-static struct fb_videomode claa_wvga = {
+static struct fb_videomode const claa_wvga = {
        .name           = "CLAA07LC0ACW",
        .refresh        = 57,
        .xres           = 800,
index 7f35dddb8488d59a79ed87b5c43fcc663edc9d8c..761f727d0861637ae1506566c9dcb0934de25ae9 100644 (file)
@@ -26,6 +26,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
 #include <netdev.h>
@@ -144,6 +145,8 @@ int board_mmc_init(bd_t *bis)
        u32 index;
        s32 status = 0;
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
                switch (index) {
                case 0:
index d43b3271b8435eee792a19618f17e06678097b47..ee20d4fc28890bfbbdcde382818123de36d0d8ac 100644 (file)
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
@@ -53,12 +54,12 @@ int dram_init(void)
        return 0;
 }
 
-iomux_v3_cfg_t uart4_pads[] = {
+iomux_v3_cfg_t const uart4_pads[] = {
        MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-iomux_v3_cfg_t usdhc3_pads[] = {
+iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -72,7 +73,7 @@ iomux_v3_cfg_t usdhc3_pads[] = {
        MX6Q_PAD_NANDF_CS0__GPIO_6_11  | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
-iomux_v3_cfg_t usdhc4_pads[] = {
+iomux_v3_cfg_t const usdhc4_pads[] = {
        MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -85,7 +86,7 @@ iomux_v3_cfg_t usdhc4_pads[] = {
        MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
-iomux_v3_cfg_t enet_pads[] = {
+iomux_v3_cfg_t const enet_pads[] = {
        MX6Q_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -139,6 +140,9 @@ int board_mmc_init(bd_t *bis)
        s32 status = 0;
        u32 index = 0;
 
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
                switch (index) {
                case 0:
index fcd83dc59b97227d054b886de2b0e376db62e4cd..9e3700e1ee4d5ebf34eb0f71c8a07e32ed67a3c0 100644 (file)
@@ -30,6 +30,8 @@
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <asm/arch/sys_proto.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
@@ -51,12 +53,12 @@ int dram_init(void)
        return 0;
 }
 
-iomux_v3_cfg_t uart4_pads[] = {
+iomux_v3_cfg_t const uart4_pads[] = {
        MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-iomux_v3_cfg_t enet_pads[] = {
+iomux_v3_cfg_t const enet_pads[] = {
        MX6Q_PAD_KEY_COL1__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_KEY_COL2__ENET_MDC             | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -79,7 +81,7 @@ static void setup_iomux_enet(void)
        imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 }
 
-iomux_v3_cfg_t usdhc3_pads[] = {
+iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6Q_PAD_SD3_CLK__USDHC3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_CMD__USDHC3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_DAT0__USDHC3_DAT0  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -114,6 +116,7 @@ int board_mmc_init(bd_t *bis)
 {
        imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
        return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 #endif
@@ -164,9 +167,38 @@ int board_eth_init(bd_t *bis)
        return 0;
 }
 
+#define BOARD_REV_B  0x200
+#define BOARD_REV_A  0x100
+
+static int mx6sabre_rev(void)
+{
+       /*
+        * Get Board ID information from OCOTP_GP1[15:8]
+        * i.MX6Q ARD RevA: 0x01
+        * i.MX6Q ARD RevB: 0x02
+        */
+       struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+       int reg = readl(&ocotp->gp1);
+       int ret;
+
+       switch (reg >> 8 & 0x0F) {
+       case 0x02:
+               ret = BOARD_REV_B;
+               break;
+       case 0x01:
+       default:
+               ret = BOARD_REV_A;
+               break;
+       }
+
+       return ret;
+}
+
 u32 get_board_rev(void)
 {
-       return 0x63000;
+       int rev = mx6sabre_rev();
+
+       return (get_cpu_rev() & ~(0xF << 8)) | rev;
 }
 
 int board_early_init_f(void)
@@ -186,7 +218,20 @@ int board_init(void)
 
 int checkboard(void)
 {
-       puts("Board: MX6Q-Sabreauto\n");
+       int rev = mx6sabre_rev();
+       char *revname;
+
+       switch (rev) {
+       case BOARD_REV_B:
+               revname = "B";
+               break;
+       case BOARD_REV_A:
+       default:
+               revname = "A";
+               break;
+       }
+
+       printf("Board: MX6Q-Sabreauto rev%s\n", revname);
 
        return 0;
 }
index 4b4e89b0e2285f8eb2348690b9e4d75b093e1dec..af6f9174d5876665a2715f80ca573f06b5609c36 100644 (file)
 #include <micrel.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <i2c.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |           \
@@ -70,12 +76,12 @@ int dram_init(void)
        return 0;
 }
 
-iomux_v3_cfg_t uart1_pads[] = {
+iomux_v3_cfg_t const uart1_pads[] = {
        MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-iomux_v3_cfg_t uart2_pads[] = {
+iomux_v3_cfg_t const uart2_pads[] = {
        MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
@@ -124,7 +130,7 @@ struct i2c_pads_info i2c_pad_info2 = {
        }
 };
 
-iomux_v3_cfg_t usdhc3_pads[] = {
+iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -134,7 +140,7 @@ iomux_v3_cfg_t usdhc3_pads[] = {
        MX6Q_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
-iomux_v3_cfg_t usdhc4_pads[] = {
+iomux_v3_cfg_t const usdhc4_pads[] = {
        MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -144,7 +150,7 @@ iomux_v3_cfg_t usdhc4_pads[] = {
        MX6Q_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
-iomux_v3_cfg_t enet_pads1[] = {
+iomux_v3_cfg_t const enet_pads1[] = {
        MX6Q_PAD_ENET_MDIO__ENET_MDIO           | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_ENET_MDC__ENET_MDC             | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -170,7 +176,7 @@ iomux_v3_cfg_t enet_pads1[] = {
        MX6Q_PAD_EIM_D23__GPIO_3_23             | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-iomux_v3_cfg_t enet_pads2[] = {
+iomux_v3_cfg_t const enet_pads2[] = {
        MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0      | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1      | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -180,7 +186,7 @@ iomux_v3_cfg_t enet_pads2[] = {
 };
 
 /* Button assignments for J14 */
-static iomux_v3_cfg_t button_pads[] = {
+static iomux_v3_cfg_t const button_pads[] = {
        /* Menu */
        MX6Q_PAD_NANDF_D1__GPIO_2_1     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
        /* Back */
@@ -213,7 +219,7 @@ static void setup_iomux_enet(void)
        imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 }
 
-iomux_v3_cfg_t usb_pads[] = {
+iomux_v3_cfg_t const usb_pads[] = {
        MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
@@ -264,6 +270,9 @@ int board_mmc_init(bd_t *bis)
        s32 status = 0;
        u32 index = 0;
 
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+       usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
               switch (index) {
               case 0:
@@ -294,7 +303,7 @@ u32 get_board_rev(void)
 }
 
 #ifdef CONFIG_MXC_SPI
-iomux_v3_cfg_t ecspi1_pads[] = {
+iomux_v3_cfg_t const ecspi1_pads[] = {
        /* SS1 */
        MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
        MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
@@ -372,14 +381,337 @@ int setup_sata(void)
 }
 #endif
 
+#if defined(CONFIG_VIDEO_IPUV3)
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+       /* Backlight on RGB connector: J15 */
+       MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
+
+       /* Backlight on LVDS connector: J6 */
+       MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
+};
+
+static iomux_v3_cfg_t const rgb_pads[] = {
+       MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
+       MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+       MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
+       MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
+       MX6Q_PAD_DI0_PIN4__GPIO_4_20,
+       MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
+       MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
+       MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
+       MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
+       MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
+       MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
+       MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
+       MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
+       MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
+       MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
+       MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
+       MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
+       MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
+       MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
+       MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
+       MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
+       MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
+       MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
+       MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
+       MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
+       MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
+       MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
+       MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
+       MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
+};
+
+struct display_info_t {
+       int     bus;
+       int     addr;
+       int     pixfmt;
+       int     (*detect)(struct display_info_t const *dev);
+       void    (*enable)(struct display_info_t const *dev);
+       struct  fb_videomode mode;
+};
+
+
+static int detect_hdmi(struct display_info_t const *dev)
+{
+       return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD;
+}
+
+static void enable_hdmi(struct display_info_t const *dev)
+{
+       u8 reg;
+       printf("%s: setup HDMI monitor\n", __func__);
+       reg = __raw_readb(
+                       HDMI_ARB_BASE_ADDR
+                       +HDMI_PHY_CONF0);
+       reg |= HDMI_PHY_CONF0_PDZ_MASK;
+       __raw_writeb(reg,
+                    HDMI_ARB_BASE_ADDR
+                       +HDMI_PHY_CONF0);
+       udelay(3000);
+       reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+       __raw_writeb(reg,
+                    HDMI_ARB_BASE_ADDR
+                       +HDMI_PHY_CONF0);
+       udelay(3000);
+       reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+       __raw_writeb(reg,
+                    HDMI_ARB_BASE_ADDR
+                       +HDMI_PHY_CONF0);
+       __raw_writeb(HDMI_MC_PHYRSTZ_ASSERT,
+                    HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+       return ((0 == i2c_set_bus_num(dev->bus))
+               &&
+               (0 == i2c_probe(dev->addr)));
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+       struct iomuxc *iomux = (struct iomuxc *)
+                               IOMUXC_BASE_ADDR;
+       u32 reg = readl(&iomux->gpr[2]);
+       reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+       writel(reg, &iomux->gpr[2]);
+       gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+}
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+       imx_iomux_v3_setup_multiple_pads(
+               rgb_pads,
+                ARRAY_SIZE(rgb_pads));
+       gpio_direction_output(RGB_BACKLIGHT_GP, 1);
+}
+
+static struct display_info_t const displays[] = {{
+       .bus    = -1,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_RGB24,
+       .detect = detect_hdmi,
+       .enable = enable_hdmi,
+       .mode   = {
+               .name           = "HDMI",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 768,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 2,
+       .addr   = 0x4,
+       .pixfmt = IPU_PIX_FMT_LVDS666,
+       .detect = detect_i2c,
+       .enable = enable_lvds,
+       .mode   = {
+               .name           = "Hannstar-XGA",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 768,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 2,
+       .addr   = 0x38,
+       .pixfmt = IPU_PIX_FMT_LVDS666,
+       .detect = detect_i2c,
+       .enable = enable_lvds,
+       .mode   = {
+               .name           = "wsvga-lvds",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 600,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 2,
+       .addr   = 0x48,
+       .pixfmt = IPU_PIX_FMT_RGB666,
+       .detect = detect_i2c,
+       .enable = enable_rgb,
+       .mode   = {
+               .name           = "wvga-rgb",
+               .refresh        = 57,
+               .xres           = 800,
+               .yres           = 480,
+               .pixclock       = 37037,
+               .left_margin    = 40,
+               .right_margin   = 60,
+               .upper_margin   = 10,
+               .lower_margin   = 10,
+               .hsync_len      = 20,
+               .vsync_len      = 10,
+               .sync           = 0,
+               .vmode          = FB_VMODE_NONINTERLACED
+} } };
+
+int board_video_skip(void)
+{
+       int i;
+       int ret;
+       char const *panel = getenv("panel");
+       if (!panel) {
+               for (i = 0; i < ARRAY_SIZE(displays); i++) {
+                       struct display_info_t const *dev = displays+i;
+                       if (dev->detect(dev)) {
+                               panel = dev->mode.name;
+                               printf("auto-detected panel %s\n", panel);
+                               break;
+                       }
+               }
+               if (!panel) {
+                       panel = displays[0].mode.name;
+                       printf("No panel detected: default to %s\n", panel);
+               }
+       } else {
+               for (i = 0; i < ARRAY_SIZE(displays); i++) {
+                       if (!strcmp(panel, displays[i].mode.name))
+                               break;
+               }
+       }
+       if (i < ARRAY_SIZE(displays)) {
+               ret = ipuv3_fb_init(&displays[i].mode, 0,
+                                   displays[i].pixfmt);
+               if (!ret) {
+                       displays[i].enable(displays+i);
+                       printf("Display: %s (%ux%u)\n",
+                              displays[i].mode.name,
+                              displays[i].mode.xres,
+                              displays[i].mode.yres);
+               } else
+                       printf("LCD %s cannot be configured: %d\n",
+                              displays[i].mode.name, ret);
+       } else {
+               printf("unsupported panel %s\n", panel);
+               ret = -EINVAL;
+       }
+       return (0 != ret);
+}
+
+static void setup_display(void)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+       int reg;
+
+       /* Turn on LDB0,IPU,IPU DI0 clocks */
+       reg = __raw_readl(&mxc_ccm->CCGR3);
+       reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
+               |MXC_CCM_CCGR3_LDB_DI0_MASK;
+       writel(reg, &mxc_ccm->CCGR3);
+
+       /* Turn on HDMI PHY clock */
+       reg = __raw_readl(&mxc_ccm->CCGR2);
+       reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
+              |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+       writel(reg, &mxc_ccm->CCGR2);
+
+       /* clear HDMI PHY reset */
+       __raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT,
+                    HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
+
+       /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
+       writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
+       writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
+
+       /* set LDB0, LDB1 clk select to 011/011 */
+       reg = readl(&mxc_ccm->cs2cdr);
+       reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+                |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+       reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+             |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+       writel(reg, &mxc_ccm->cs2cdr);
+
+       reg = readl(&mxc_ccm->cscmr2);
+       reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+       writel(reg, &mxc_ccm->cscmr2);
+
+       reg = readl(&mxc_ccm->chsccdr);
+       reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
+               |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
+               |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+       reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+               <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
+             |(CHSCCDR_PODF_DIVIDE_BY_3
+               <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+             |(CHSCCDR_IPU_PRE_CLK_540M_PFD
+               <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+       writel(reg, &mxc_ccm->chsccdr);
+
+       reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+            |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+            |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+            |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+            |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+            |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+            |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+            |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+            |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+       writel(reg, &iomux->gpr[2]);
+
+       reg = readl(&iomux->gpr[3]);
+       reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+           | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+              <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+       writel(reg, &iomux->gpr[3]);
+
+       /* backlights off until needed */
+       imx_iomux_v3_setup_multiple_pads(backlight_pads,
+                                        ARRAY_SIZE(backlight_pads));
+       gpio_direction_input(LVDS_BACKLIGHT_GP);
+       gpio_direction_input(RGB_BACKLIGHT_GP);
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
        setup_buttons();
 
+#if defined(CONFIG_VIDEO_IPUV3)
+       setup_display();
+#endif
        return 0;
 }
 
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+       return 1;
+}
+
 int board_init(void)
 {
        /* address of boot parameters */
index 03a68573235824e232d8f04c344cd9ebf468976a..0240fb54792bb259ad3bbc95aac6574f8dcd9e27 100644 (file)
@@ -51,12 +51,12 @@ int dram_init(void)
        return 0;
 }
 
-iomux_v3_cfg_t uart1_pads[] = {
+iomux_v3_cfg_t const uart1_pads[] = {
        MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-iomux_v3_cfg_t enet_pads[] = {
+iomux_v3_cfg_t const enet_pads[] = {
        MX6Q_PAD_ENET_MDIO__ENET_MDIO           | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_ENET_MDC__ENET_MDC             | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -86,7 +86,7 @@ static void setup_iomux_enet(void)
        gpio_set_value(IMX_GPIO_NR(1, 25), 1);
 }
 
-iomux_v3_cfg_t usdhc3_pads[] = {
+iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -120,6 +120,7 @@ int board_mmc_init(bd_t *bis)
 {
        imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
        return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 #endif
index cfd2e938b94c46e841e3ce4413f6c2e8ff16575f..c2b2823ef9dab8fe146af8c5ada34b9fe08fa86a 100644 (file)
@@ -29,6 +29,7 @@
 #include <asm/errno.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
@@ -93,7 +94,7 @@ static u32 get_mx_rev(void)
        return (~rev & 0x7) + 1;
 }
 
-static iomux_v3_cfg_t efikasb_revision_pads[] = {
+static iomux_v3_cfg_t const efikasb_revision_pads[] = {
        MX51_PAD_EIM_CS3__GPIO2_28,
        MX51_PAD_EIM_CS4__GPIO2_29,
 };
@@ -140,7 +141,7 @@ int dram_init(void)
 /*
  * UART configuration
  */
-static iomux_v3_cfg_t efikamx_uart_pads[] = {
+static iomux_v3_cfg_t const efikamx_uart_pads[] = {
        MX51_PAD_UART1_RXD__UART1_RXD,
        MX51_PAD_UART1_TXD__UART1_TXD,
        MX51_PAD_UART1_RTS__UART1_RTS,
@@ -150,7 +151,7 @@ static iomux_v3_cfg_t efikamx_uart_pads[] = {
 /*
  * SPI configuration
  */
-static iomux_v3_cfg_t efikamx_spi_pads[] = {
+static iomux_v3_cfg_t const efikamx_spi_pads[] = {
        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
@@ -272,7 +273,7 @@ struct fsl_esdhc_cfg esdhc_cfg[2] = {
        {MMC_SDHC2_BASE_ADDR},
 };
 
-static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
+static iomux_v3_cfg_t const efikamx_sdhc1_pads[] = {
        MX51_PAD_SD1_CMD__SD1_CMD,
        MX51_PAD_SD1_CLK__SD1_CLK,
        MX51_PAD_SD1_DATA0__SD1_DATA0,
@@ -284,7 +285,7 @@ static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
 
 #define EFIKAMX_SDHC1_WP       IMX_GPIO_NR(1, 1)
 
-static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
+static iomux_v3_cfg_t const efikamx_sdhc1_cd_pads[] = {
        MX51_PAD_GPIO1_0__SD1_CD,
        MX51_PAD_EIM_CS2__SD1_CD,
 };
@@ -292,7 +293,7 @@ static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
 #define EFIKAMX_SDHC1_CD       IMX_GPIO_NR(1, 0)
 #define EFIKASB_SDHC1_CD       IMX_GPIO_NR(2, 27)
 
-static iomux_v3_cfg_t efikasb_sdhc2_pads[] = {
+static iomux_v3_cfg_t const efikasb_sdhc2_pads[] = {
        MX51_PAD_SD2_CMD__SD2_CMD,
        MX51_PAD_SD2_CLK__SD2_CLK,
        MX51_PAD_SD2_DATA0__SD2_DATA0,
@@ -349,6 +350,9 @@ int board_mmc_init(bd_t *bis)
                gpio_direction_input(EFIKASB_SDHC1_CD);
        }
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+       esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
        ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 
        if (machine_is_efikasb()) {
@@ -368,7 +372,7 @@ int board_mmc_init(bd_t *bis)
 /*
  * PATA
  */
-static iomux_v3_cfg_t efikamx_pata_pads[] = {
+static iomux_v3_cfg_t const efikamx_pata_pads[] = {
        MX51_PAD_NANDF_WE_B__PATA_DIOW,
        MX51_PAD_NANDF_RE_B__PATA_DIOR,
        MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
@@ -419,7 +423,7 @@ static inline void setup_iomux_usb(void) { }
 #define EFIKAMX_LED_GREEN      IMX_GPIO_NR(3, 14)
 #define EFIKAMX_LED_RED                IMX_GPIO_NR(3, 15)
 
-static iomux_v3_cfg_t efikasb_led_pads[] = {
+static iomux_v3_cfg_t const efikasb_led_pads[] = {
        MX51_PAD_GPIO1_3__GPIO1_3,
        MX51_PAD_EIM_CS0__GPIO2_25,
 };
index f28eab070bb1044a70bd4a39bfbc386a9233a83a..abdd1aac2b5dd9bda98fb0a664506b4e6ed54d68 100644 (file)
@@ -28,6 +28,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
@@ -43,7 +44,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct fb_videomode nec_nl6448bc26_09c = {
+static struct fb_videomode const nec_nl6448bc26_09c = {
        "NEC_NL6448BC26-09C",
        60,     /* Refresh */
        640,    /* xres */
@@ -590,6 +591,7 @@ int board_mmc_init(bd_t *bis)
        mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
                PAD_CTL_HYS_ENABLE);
 
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
        return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 }
 #endif
index 3f8d30db4c9c6199a8751014480f6f4f52ad0b7e..aa6a9f13ea3621617a27c35f7aba6454d9828013 100644 (file)
@@ -410,12 +410,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
        return 0;
 }
 
-void set_sysctl(struct mmc *mmc, uint clock)
+static void set_sysctl(struct mmc *mmc, uint clock)
 {
-       int sdhc_clk = gd->sdhc_clk;
        int div, pre_div;
        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
        volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+       int sdhc_clk = cfg->sdhc_clk;
        uint clk;
 
        if (clock < mmc->f_min)
@@ -598,6 +598,7 @@ int fsl_esdhc_mmc_init(bd_t *bis)
        cfg = malloc(sizeof(struct fsl_esdhc_cfg));
        memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
        cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+       cfg->sdhc_clk = gd->sdhc_clk;
        return fsl_esdhc_initialize(bis, cfg);
 }
 
index 47b336e7aa4fb7de28996b4921779162a42f3f27..ace226cececfa72a1202d24a67e49ed8e7507156 100644 (file)
@@ -45,7 +45,7 @@ static int mxcfb_unmap_video_memory(struct fb_info *fbi);
 
 /* graphics setup */
 static GraphicDevice panel;
-static struct fb_videomode *gmode;
+static struct fb_videomode const *gmode;
 static uint8_t gdisp;
 static uint32_t gpixfmt;
 
@@ -503,7 +503,7 @@ static struct fb_info *mxcfb_init_fbinfo(void)
  * @return      Appropriate error code to the kernel common code
  */
 static int mxcfb_probe(u32 interface_pix_fmt, uint8_t disp,
-                       struct fb_videomode *mode)
+                       struct fb_videomode const *mode)
 {
        struct fb_info *fbi;
        struct mxcfb_info *mxcfbi;
@@ -619,7 +619,9 @@ void video_set_lut(unsigned int index, /* color number */
        return;
 }
 
-int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt)
+int ipuv3_fb_init(struct fb_videomode const *mode,
+                 uint8_t disp,
+                 uint32_t pixfmt)
 {
        gmode = mode;
        gdisp = disp;
index 96c143efb97bd6396aa48c259023668607e5afc1..bd000a7f09d1027ba83c66f60346f50bfd6b01c9 100644 (file)
@@ -15,6 +15,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/imx-regs.h>
+
 /* High Level Configuration Options */
 
 #define CONFIG_SYS_HZ                  1000
 #define CONFIG_BOARD_EARLY_INIT_F
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
-                                               GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_ADDR       IMX_RAM_BASE
+#define CONFIG_SYS_INIT_RAM_SIZE       IMX_RAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /* Memory Test */
 #define CONFIG_SYS_MEMTEST_START       (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2)
index dcae53786bb2dd3bb4c275866136c843ae8107b8..225d359ecb762d8568a42b17239ff80644374178 100644 (file)
@@ -96,7 +96,6 @@
 /*
  * Eth Configs
  */
-#define CONFIG_HAS_ETH1
 #define CONFIG_MII
 
 #define CONFIG_FEC_MXC
index 69937d834e6902b19f14f5d1ac553a4c216f4d48..d1f684cbc5c1c7ee17203a75fce12dfccf863f84 100644 (file)
@@ -73,7 +73,6 @@
 #define CONFIG_DOS_PARTITION
 
 /* Eth Configs */
-#define CONFIG_HAS_ETH1
 #define CONFIG_MII
 
 #define CONFIG_FEC_MXC
index 55efeb741c3ba7a7b82c03efc3593f8be80502db..a1b27cef53569f9e9781ddc711ecfd9bfd0ae3d6 100644 (file)
@@ -58,7 +58,6 @@
 #define CONFIG_DOS_PARTITION
 
 /* Eth Configs */
-#define CONFIG_HAS_ETH1
 #define CONFIG_MII
 
 #define CONFIG_FEC_MXC
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
-#define CONFIG_IPUV3_CLK       133000000
+#define CONFIG_IPUV3_CLK       200000000
 
 #endif                         /* __CONFIG_H */
index fbc51625bad6721281b4779afe2928ab9c1736f2..23562a87769cc4e042eaf6d7179b2147b45e451d 100644 (file)
@@ -50,6 +50,7 @@
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_BOUNCE_BUFFER
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
-#define CONFIG_SYS_DCACHE_OFF
-
 #endif                         /* __CONFIG_H */
index 247e8d6dde98fa1e8bb325a257e1cff0475dd2ae..bfb9cd468ee78b9383e7c0e1da60bb1e717dec09 100644 (file)
@@ -45,6 +45,7 @@
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_BOUNCE_BUFFER
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
@@ -86,7 +87,7 @@
        "initrd_high=0xffffffff\0" \
        "mmcdev=0\0" \
        "mmcpart=1\0" \
-       "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+       "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
        "mmcargs=setenv bootargs console=${console},${baudrate} " \
                "root=${mmcroot}\0" \
        "loadbootscript=" \
 
 #define CONFIG_OF_LIBFDT
 
-#define CONFIG_SYS_DCACHE_OFF
-
 #ifndef CONFIG_SYS_DCACHE_OFF
 #define CONFIG_CMD_CACHE
 #endif
index a878dec89aa5922cf594a017d5c7e5a5100d39a4..760f3ce0c9a3810d790c541a4f647e5a7fb2d0cf 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2012 Freescale Semiconductor, Inc.
  *
- * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ * Configuration settings for the Freescale i.MX6Q SabreAuto board.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -15,6 +15,7 @@
 #define CONFIG_MACH_TYPE       3529
 #define CONFIG_MXC_UART_BASE   UART4_BASE
 #define CONFIG_CONSOLE_DEV             "ttymxc3"
+#define CONFIG_MMCROOT                 "/dev/mmcblk0p2"
 #define PHYS_SDRAM_SIZE                (2u * 1024 * 1024 * 1024)
 
 #include "mx6qsabre_common.h"
index ec9ab2649325ca11fcdbc17e2138b5b263fd98e5..b56d7ca8ca91c0c9c6f365046d6cc29fd1ae9e0f 100644 (file)
@@ -37,7 +37,7 @@
 #define CONFIG_REVISION_TAG
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN         (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN          (10 * 1024 * 1024)
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MISC_INIT_R
@@ -72,6 +72,7 @@
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_BOUNCE_BUFFER
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 /* Miscellaneous commands */
 #define CONFIG_CMD_BMODE
 
+/* Framebuffer and LCD */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX             1
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
-#define CONFIG_SYS_DCACHE_OFF
-
 #ifndef CONFIG_SYS_DCACHE_OFF
 #define CONFIG_CMD_CACHE
 #endif
index f2ce79e9ec4d148a5735c11af21a56fb89afae7f..771d1297f7a33863a57129861372d15ce000b49b 100644 (file)
@@ -20,6 +20,7 @@
 #define CONFIG_MACH_TYPE       3980
 #define CONFIG_MXC_UART_BASE   UART1_BASE
 #define CONFIG_CONSOLE_DEV             "ttymxc0"
+#define CONFIG_MMCROOT                 "/dev/mmcblk1p2"
 #define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
 
 #include "mx6qsabre_common.h"
index 4e321e762c0b96782889597d820387800be733bf..47d2fe4f188fa4a623c517ce5c01a84de6e7084b 100644 (file)
 
 struct fsl_esdhc_cfg {
        u32     esdhc_base;
+       u32     sdhc_clk;
 };
 
 /* Select the correct accessors depending on endianess */
index 4baa71187d9c1febd18980cbbc50d069ebb0b224..1163bf4b4e3e0b06fbe0cf3d88a951847c82dd38 100644 (file)
@@ -76,7 +76,9 @@
 #define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
 #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
 
-int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
+int ipuv3_fb_init(struct fb_videomode const *mode,
+                 uint8_t disp,
+                 uint32_t pixfmt);
 void ipuv3_fb_shutdown(void);
 
 #endif
index 03a771667327387ff454a855e6032d20f19b71ac..63f88b6c422390fa27b47b781f051776cc7978ff 100644 (file)
@@ -71,6 +71,8 @@ static uint32_t imximage_version;
 static set_dcd_val_t set_dcd_val;
 static set_dcd_rst_t set_dcd_rst;
 static set_imx_hdr_t set_imx_hdr;
+static uint32_t max_dcd_entries;
+static uint32_t *header_size_ptr;
 
 static uint32_t get_cfg_value(char *token, char *name,  int linenr)
 {
@@ -170,13 +172,6 @@ static void set_dcd_rst_v1(struct imx_header *imxhdr, uint32_t dcd_len,
 {
        dcd_v1_t *dcd_v1 = &imxhdr->header.hdr_v1.dcd_table;
 
-       if (dcd_len > MAX_HW_CFG_SIZE_V1) {
-               fprintf(stderr, "Error: %s[%d] -"
-                       "DCD table exceeds maximum size(%d)\n",
-                       name, lineno, MAX_HW_CFG_SIZE_V1);
-               exit(EXIT_FAILURE);
-       }
-
        dcd_v1->preamble.barker = DCD_BARKER;
        dcd_v1->preamble.length = dcd_len * sizeof(dcd_type_addr_data_t);
 }
@@ -190,13 +185,6 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
 {
        dcd_v2_t *dcd_v2 = &imxhdr->header.hdr_v2.dcd_table;
 
-       if (dcd_len > MAX_HW_CFG_SIZE_V2) {
-               fprintf(stderr, "Error: %s[%d] -"
-                       "DCD table exceeds maximum size(%d)\n",
-                       name, lineno, MAX_HW_CFG_SIZE_V2);
-               exit(EXIT_FAILURE);
-       }
-
        dcd_v2->header.tag = DCD_HEADER_TAG;
        dcd_v2->header.length = cpu_to_be16(
                        dcd_len * sizeof(dcd_addr_data_t) + 8);
@@ -208,84 +196,55 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
 }
 
 static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
-                                       struct stat *sbuf,
-                                       struct mkimage_params *params)
+               uint32_t entry_point, uint32_t flash_offset)
 {
        imx_header_v1_t *hdr_v1 = &imxhdr->header.hdr_v1;
        flash_header_v1_t *fhdr_v1 = &hdr_v1->fhdr;
        dcd_v1_t *dcd_v1 = &hdr_v1->dcd_table;
-       uint32_t base_offset;
-
-       /* Exit if there is no BOOT_FROM field specifying the flash_offset */
-       if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
-               fprintf(stderr, "Error: Header v1: No BOOT_FROM tag in %s\n",
-                       params->imagename);
-               exit(EXIT_FAILURE);
-       }
+       uint32_t hdr_base;
+       uint32_t header_length = (((char *)&dcd_v1->addr_data[dcd_len].addr)
+                       - ((char *)imxhdr));
 
        /* Set magic number */
        fhdr_v1->app_code_barker = APP_CODE_BARKER;
 
-       fhdr_v1->app_dest_ptr = params->addr;
-       fhdr_v1->app_dest_ptr = params->ep - imxhdr->flash_offset -
-               sizeof(struct imx_header);
-       fhdr_v1->app_code_jump_vector = params->ep;
-
-       base_offset = fhdr_v1->app_dest_ptr + imxhdr->flash_offset ;
-       fhdr_v1->dcd_ptr_ptr =
-               (uint32_t) (offsetof(flash_header_v1_t, dcd_ptr) -
-               offsetof(flash_header_v1_t, app_code_jump_vector) +
-               base_offset);
+       hdr_base = entry_point - sizeof(struct imx_header);
+       fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
+       fhdr_v1->app_code_jump_vector = entry_point;
 
-       fhdr_v1->dcd_ptr = base_offset +
-                       offsetof(imx_header_v1_t, dcd_table);
-
-       /* The external flash header must be at the end of the DCD table */
-       dcd_v1->addr_data[dcd_len].type = sbuf->st_size +
-                               imxhdr->flash_offset +
-                               sizeof(struct imx_header);
+       fhdr_v1->dcd_ptr_ptr = hdr_base + offsetof(flash_header_v1_t, dcd_ptr);
+       fhdr_v1->dcd_ptr = hdr_base + offsetof(imx_header_v1_t, dcd_table);
 
        /* Security feature are not supported */
        fhdr_v1->app_code_csf = 0;
        fhdr_v1->super_root_key = 0;
+       header_size_ptr = (uint32_t *)(((char *)imxhdr) + header_length - 4);
 }
 
 static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
-                                       struct stat *sbuf,
-                                       struct mkimage_params *params)
+               uint32_t entry_point, uint32_t flash_offset)
 {
        imx_header_v2_t *hdr_v2 = &imxhdr->header.hdr_v2;
        flash_header_v2_t *fhdr_v2 = &hdr_v2->fhdr;
-
-       /* Exit if there is no BOOT_FROM field specifying the flash_offset */
-       if(imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
-               fprintf(stderr, "Error: Header v2: No BOOT_FROM tag in %s\n",
-                       params->imagename);
-               exit(EXIT_FAILURE);
-       }
+       uint32_t hdr_base;
 
        /* Set magic number */
        fhdr_v2->header.tag = IVT_HEADER_TAG; /* 0xD1 */
        fhdr_v2->header.length = cpu_to_be16(sizeof(flash_header_v2_t));
        fhdr_v2->header.version = IVT_VERSION; /* 0x40 */
 
-       fhdr_v2->entry = params->ep;
+       fhdr_v2->entry = entry_point;
        fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
-       fhdr_v2->self = params->ep - sizeof(struct imx_header);
-
-       fhdr_v2->dcd_ptr = fhdr_v2->self +
-                       offsetof(imx_header_v2_t, dcd_table);
+       fhdr_v2->self = hdr_base = entry_point - sizeof(struct imx_header);
 
-       fhdr_v2->boot_data_ptr = fhdr_v2->self +
-                       offsetof(imx_header_v2_t, boot_data);
-
-       hdr_v2->boot_data.start = fhdr_v2->self - imxhdr->flash_offset;
-       hdr_v2->boot_data.size = sbuf->st_size +
-                       imxhdr->flash_offset +
-                       sizeof(struct imx_header);
+       fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table);
+       fhdr_v2->boot_data_ptr = hdr_base
+                       + offsetof(imx_header_v2_t, boot_data);
+       hdr_v2->boot_data.start = hdr_base - flash_offset;
 
        /* Security feature are not supported */
        fhdr_v2->csf = 0;
+       header_size_ptr = &hdr_v2->boot_data.size;
 }
 
 static void set_hdr_func(struct imx_header *imxhdr)
@@ -295,11 +254,13 @@ static void set_hdr_func(struct imx_header *imxhdr)
                set_dcd_val = set_dcd_val_v1;
                set_dcd_rst = set_dcd_rst_v1;
                set_imx_hdr = set_imx_hdr_v1;
+               max_dcd_entries = MAX_HW_CFG_SIZE_V1;
                break;
        case IMXIMAGE_V2:
                set_dcd_val = set_dcd_val_v2;
                set_dcd_rst = set_dcd_rst_v2;
                set_imx_hdr = set_imx_hdr_v2;
+               max_dcd_entries = MAX_HW_CFG_SIZE_V2;
                break;
        default:
                err_imximage_version(imximage_version);
@@ -426,8 +387,15 @@ static void parse_cfg_fld(struct imx_header *imxhdr, int32_t *cmd,
                value = get_cfg_value(token, name, lineno);
                (*set_dcd_val)(imxhdr, name, lineno, fld, value, *dcd_len);
 
-               if (fld == CFG_REG_VALUE)
+               if (fld == CFG_REG_VALUE) {
                        (*dcd_len)++;
+                       if (*dcd_len > max_dcd_entries) {
+                               fprintf(stderr, "Error: %s[%d] -"
+                                       "DCD table exceeds maximum size(%d)\n",
+                                       name, lineno, max_dcd_entries);
+                               exit(EXIT_FAILURE);
+                       }
+               }
                break;
        default:
                break;
@@ -480,6 +448,11 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
        (*set_dcd_rst)(imxhdr, dcd_len, name, lineno);
        fclose(fd);
 
+       /* Exit if there is no BOOT_FROM field specifying the flash_offset */
+       if (imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
+               fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
+               exit(EXIT_FAILURE);
+       }
        return dcd_len;
 }
 
@@ -541,7 +514,8 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
        dcd_len = parse_cfg_file(imxhdr, params->imagename);
 
        /* Set the imx header */
-       (*set_imx_hdr)(imxhdr, dcd_len, sbuf, params);
+       (*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
+       *header_size_ptr = sbuf->st_size + imxhdr->flash_offset;
 }
 
 int imximage_check_params(struct mkimage_params *params)
index 34f293d95afaaee218bad9a237666645d485a894..42b60906fd3adfef0e82caa38f0e77b01bc76af5 100644 (file)
@@ -168,9 +168,7 @@ typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
                                        uint32_t dcd_len,
                                        char *name, int lineno);
 
-typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr,
-                                       uint32_t dcd_len,
-                                       struct stat *sbuf,
-                                       struct mkimage_params *params);
+typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
+               uint32_t entry_point, uint32_t flash_offset);
 
 #endif /* _IMXIMAGE_H_ */