HACK: ARM: DRA7xx: crossbar: Add support for crossbar
authorAmarinder Bindra <a-bindra@ti.com>
Wed, 7 Aug 2013 15:30:18 +0000 (21:00 +0530)
committerSomnath Mukherjee <somnath@ti.com>
Thu, 8 Aug 2013 13:04:32 +0000 (18:34 +0530)
DRA7xx has a large number of interrupts/dma requests to service
the needs of its many peripherals and subsystems. All of the
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the controllers appropriately.
In such places a interrupt/dma controllers are preceded by an
IRQ/DMA CROSSBAR that provides flexibility in muxing the device
requests to the controller inputs.

This configures some of the MPU IRQs and SDMA DREQ at the u-boot
until this functionality is available at the kernel.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
arch/arm/cpu/armv7/omap-common/hwinit-common.c
arch/arm/include/asm/arch-omap5/sys_proto.h
board/ti/dra7xx/evm.c

index 5602b0e1998923b14e95f5baadf275e2c8c191dc..61cc99c6f79c6453ee48857d3603dc5674952a0c 100644 (file)
@@ -158,6 +158,10 @@ int arch_cpu_init(void)
 }
 #endif /* CONFIG_ARCH_CPU_INIT */
 
+void __weak set_crossbar_regs(void)
+{
+}
+
 /*
  * Routine: s_init
  * Description: Does early system init of watchdog, muxing,  andclocks
@@ -205,6 +209,9 @@ void s_init(void)
        /* For regular u-boot sdram_init() is called from dram_init() */
        sdram_init();
 #endif
+#ifndef CONFIG_SPL_BUILD
+       set_crossbar_regs();
+#endif
 }
 
 /*
index 36cfc6f74e2f97fa51115f8176094f132d0804cb..f8b9b3ae0401a5d723ab98829206e38fb41fd919 100644 (file)
@@ -68,6 +68,7 @@ void force_emif_self_refresh(void);
 void get_ioregs(const struct ctrl_ioregs **regs);
 void srcomp_enable(void);
 void setup_warmreset_time(void);
+void set_crossbar_regs(void);
 
 static inline u32 running_from_sdram(void)
 {
index bf7e0919665902d57e3c1195874bf06a1e5ab391..8214a7acb4a906784092b414df902c5ed3c69591 100644 (file)
 #include <asm/ehci-omap.h>
 #endif
 
+#define CTRL_CORE_MPU_IRQ_159_REG                      0x4a002b76
+#define CTRL_CORE_MPU_IRQ_155_REG                      0x4a002b6e
+#define CTRL_CORE_MPU_IRQ_154_REG                      0x4a002b6c
+#define CTRL_CORE_MPU_IRQ_156_REG                      0x4a002b70
+#define CTRL_CORE_MPU_IRQ_157_REG                      0x4a002b72
+#define CTRL_CORE_MPU_IRQ_136_REG                      0x4a002b48
+#define CTRL_CORE_MPU_IRQ_141_REG                      0x4a002b52
+#define CTRL_CORE_MPU_IRQ_142_REG                      0x4a002b54
+#define CTRL_CORE_MPU_IRQ_143_REG                      0x4a002b56
+#define CTRL_CORE_MPU_IRQ_144_REG                      0x4a002b58
+#define CTRL_CORE_MPU_IRQ_145_REG                      0x4a002b5a
+#define CTRL_CORE_MPU_IRQ_124_REG                      0x4a002b34
+
+#define CTRL_CORE_DMA_SYSTEM_DREQ_79_REG               0x4a002c16
+#define CTRL_CORE_DMA_SYSTEM_DREQ_78_REG               0x4a002c14
+#define CTRL_CORE_DMA_SYSTEM_DREQ_63_REG               0x4a002bf6
+#define CTRL_CORE_DMA_SYSTEM_DREQ_62_REG               0x4a002bf4
+
 DECLARE_GLOBAL_DATA_PTR;
 
 const struct omap_sysinfo sysinfo = {
@@ -101,3 +119,35 @@ int board_mmc_init(bd_t *bis)
        return 0;
 }
 #endif
+
+static void set_crossbar_mpu_irq()
+{
+       /* MPU_IRQ mapping to CROSSBAR_IRQ */
+       writew(217, CTRL_CORE_MPU_IRQ_159_REG); /* RTC_IRQ */
+       writew(150, CTRL_CORE_MPU_IRQ_155_REG); /* MCASP3_IRQ_AREVT */
+       writew(151, CTRL_CORE_MPU_IRQ_154_REG); /* MCASP3_IRQ_AXEVT */
+       writew(156, CTRL_CORE_MPU_IRQ_156_REG); /* MCASP6_IRQ_AREVT */
+       writew(157, CTRL_CORE_MPU_IRQ_157_REG); /* MCASP6_IRQ_AXEVT */
+       writew(251, CTRL_CORE_MPU_IRQ_136_REG); /* MAILBOX5 */
+       writew(255, CTRL_CORE_MPU_IRQ_141_REG); /* MAILBOX6 */
+       writew(396, CTRL_CORE_MPU_IRQ_142_REG); /* IPU2 MMU */
+       writew(145, CTRL_CORE_MPU_IRQ_143_REG); /* DSP1 MMU1 */
+       writew(146, CTRL_CORE_MPU_IRQ_144_REG); /* DSP2 MMU0 */
+       writew(147, CTRL_CORE_MPU_IRQ_145_REG); /* DSP2 MMU1 */
+       writew(343, CTRL_CORE_MPU_IRQ_124_REG); /* QSPI */
+}
+
+static void set_crossbar_sdma_dreq()
+{
+       /* SDMA_DREQ mapping to CROSSBAR_IRQ */
+       writew(132, CTRL_CORE_DMA_SYSTEM_DREQ_79_REG);  /* MCASP3_DREQ_RX */
+       writew(133, CTRL_CORE_DMA_SYSTEM_DREQ_78_REG);  /* MCASP3_DREQ_TX */
+       writew(138, CTRL_CORE_DMA_SYSTEM_DREQ_63_REG);  /* MCASP6_DREQ_RX */
+       writew(139, CTRL_CORE_DMA_SYSTEM_DREQ_62_REG);  /* MCASP6_DREQ_TX */
+}
+
+void set_crossbar_regs(void)
+{
+       set_crossbar_mpu_irq();
+       set_crossbar_sdma_dreq();
+}