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raw | patch | inline | side by side (parent: 38fcc71)
raw | patch | inline | side by side (parent: 38fcc71)
author | Stefano Babic <sbabic@denx.de> | |
Mon, 9 Apr 2012 11:33:04 +0000 (13:33 +0200) | ||
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | |
Mon, 16 Apr 2012 12:53:59 +0000 (14:53 +0200) |
As well as pushed for ARM926EJS, we certainly don't want
the compiler to reorganise the code for dcache flushing
Fix checkpatch warnings as well.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
the compiler to reorganise the code for dcache flushing
Fix checkpatch warnings as well.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
arch/arm/cpu/arm1136/cpu.c | patch | blob | history |
index f2e30b51985f2e2f1272d7115434f52f65abd509..f72bab6693cdaba3f4126ddedfa29e3d11339569 100644 (file)
static void cache_flush(void)
{
unsigned long i = 0;
-
- asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data cache */
- asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */
- asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
+ /* clean entire data cache */
+ asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
+ /* invalidate both caches and flush btb */
+ asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
+ /* mem barrier to sync things */
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
}
#ifndef CONFIG_SYS_DCACHE_OFF
void invalidate_dcache_all(void)
{
- asm ("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
}
void flush_dcache_all(void)
{
- asm ("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
- asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
static inline int bad_cache_range(unsigned long start, unsigned long stop)
return;
while (start < stop) {
- asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
+ asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
}
return;
while (start < stop) {
- asm ("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
+ asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
- asm ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+ asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
}
void flush_cache(unsigned long start, unsigned long size)