glsdk/glsdk-u-boot.git
9 years agoMerge remote-tracking branch 'u-boot-atmel/master'
Albert ARIBAUD [Fri, 26 Oct 2012 05:54:25 +0000 (07:54 +0200)]
Merge remote-tracking branch 'u-boot-atmel/master'

9 years agoMerge remote-tracking branch 'u-boot-ti/master'
Albert ARIBAUD [Fri, 26 Oct 2012 05:00:28 +0000 (07:00 +0200)]
Merge remote-tracking branch 'u-boot-ti/master'

9 years agoam33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbers
Peter Korsgaard [Thu, 18 Oct 2012 01:21:13 +0000 (01:21 +0000)]
am33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbers

So other parts can be added.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
9 years agoam33xx: support board specific ddr settings
Peter Korsgaard [Thu, 18 Oct 2012 01:21:12 +0000 (01:21 +0000)]
am33xx: support board specific ddr settings

Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make apply with rtc32k_enable() in the file]
Signed-off-by: Tom Rini <trini@ti.com>
9 years agoam33xx: move generic parts of pinmux handling out from board/ti/am335x
Peter Korsgaard [Thu, 18 Oct 2012 01:21:11 +0000 (01:21 +0000)]
am33xx: move generic parts of pinmux handling out from board/ti/am335x

So they are available for other boards.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
9 years agoam33xx/board: use cpu_mmc_init() for default mmc initialization
Peter Korsgaard [Thu, 18 Oct 2012 01:21:10 +0000 (01:21 +0000)]
am33xx/board: use cpu_mmc_init() for default mmc initialization

So platforms can override it with board_mmc_init() if needed.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
9 years agoam33xx: move ti i2c baseboard header handling to board/ti/am335x/
Peter Korsgaard [Thu, 18 Oct 2012 01:21:09 +0000 (01:21 +0000)]
am33xx: move ti i2c baseboard header handling to board/ti/am335x/

The i2c header is specific to ti(-derived) boards, and not generic for all
am335x boards.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make re-apply with rtc32k_enable() applied]
Signed-off-by: Tom Rini <trini@ti.com>
9 years agoam33xx/board.c: make wdtimer/uart_base static
Peter Korsgaard [Thu, 18 Oct 2012 01:21:08 +0000 (01:21 +0000)]
am33xx/board.c: make wdtimer/uart_base static

Only used here (and uart_base only for SPL).

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
9 years agoam33xx: Add SPI SPL as an option
Tom Rini [Tue, 16 Oct 2012 13:06:07 +0000 (13:06 +0000)]
am33xx: Add SPI SPL as an option

Add the required config.mk logic for this SoC as well as the BOOT_DEVICE
define.  Finally, enable the options on the am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoomapimage: Add support for byteswapped SPI images
Tom Rini [Tue, 16 Oct 2012 13:06:06 +0000 (13:06 +0000)]
omapimage: Add support for byteswapped SPI images

Add MLO.byteswap as a target to spl/Makefile and un-guard the first MLO
rule so we don't have to duplicate it.

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoomap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPED
Peter Korsgaard [Wed, 17 Oct 2012 09:20:46 +0000 (09:20 +0000)]
omap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPED

D0/D1 Swapped or not is a board property, not anything specific to
the am33xx SoC, so add a custom define for it.

At the same time correct the bit handling for the swapped mode
(DPE0 should be cleared and SI/DPE1 set).

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
9 years agoOMAP3: add video support to the mcx board
Stefano Babic [Sat, 20 Oct 2012 23:56:07 +0000 (23:56 +0000)]
OMAP3: add video support to the mcx board

Add video support to the board with the display
focaltech etm070003dh6.

Signed-off-by: Stefano Babic <sbabic@denx.de>
9 years agoVIDEO: add macro to set LCD size for DSS driver
Stefano Babic [Tue, 16 Oct 2012 04:07:05 +0000 (04:07 +0000)]
VIDEO: add macro to set LCD size for DSS driver

Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
9 years agoOMAP3: mcx: updated to new hardware revision
Stefano Babic [Tue, 16 Oct 2012 04:07:04 +0000 (04:07 +0000)]
OMAP3: mcx: updated to new hardware revision

Some GPIOs differ in the new revision board.
Previous revision are considered obsolete and
they will not anymore supported.

Signed-off-by: Stefano Babic <sbabic@denx.de>
9 years agoOMAP3: updated pinmux and environment for new revision of mcx board
Stefano Babic [Tue, 16 Oct 2012 04:07:03 +0000 (04:07 +0000)]
OMAP3: updated pinmux and environment for new revision of mcx board

The mcx board was slightly modified and the pinmux must be updated.
There is no need to support the old board, that becomes obsolete.

Signed-off-by: Stefano Babic <sbabic@denx.de>
9 years agoOMAP3: mt_ventoux: power on USB at startup
Stefano Babic [Tue, 16 Oct 2012 04:02:20 +0000 (04:02 +0000)]
OMAP3: mt_ventoux: power on USB at startup

Updated revision of the board uses GPIOs to activate
the USB ports.

Signed-off-by: Stefano Babic <sbabic@denx.de>
9 years agoam335x: Enable RTC 32K OSC clock
Vaibhav Hiremath [Thu, 8 Mar 2012 11:45:47 +0000 (17:15 +0530)]
am335x: Enable RTC 32K OSC clock

In order to support low power state, you must source kernel system
timers to persistent clock, available across suspend/resume.  In case of
AM335x device, the only source we have is, RTC32K, available in
wakeup/always-on domain.  Having said that, during validation it has
been observed that, RTC clock need couple of seconds delay to stabilize
the RTC OSC clock; and such a huge delay is not acceptable in kernel
especially during early init and also it will impact quick/fast boot
use-cases.

So, RTC32k OSC enable dependency has been shifted to
SPL/first-bootloader.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
9 years agoColdFire: Add Freescale MCF54418TWR ColdFire development board support
Alison Wang [Thu, 18 Oct 2012 19:25:52 +0000 (19:25 +0000)]
ColdFire: Add Freescale MCF54418TWR ColdFire development board support

Add Freescale MCF54418TWR ColdFire development board support.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
9 years agoColdFire: Add MCF5441x CPU support
Alison Wang [Thu, 18 Oct 2012 19:25:51 +0000 (19:25 +0000)]
ColdFire: Add MCF5441x CPU support

Add MCF5441x CPU support.

The MCF5441x devices are a family of highly-integrated 32-bit
microprocessors based on the Version 4m ColdFire microarchitecture,
comprising of the V4 integer core, memory management unit(MMU) and
enchanced multiply-accumulate unit(EMAC).

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
9 years agoColdFire: Fix unused variable in cpu_init.c
Alison Wang [Sun, 21 Oct 2012 21:27:48 +0000 (21:27 +0000)]
ColdFire: Fix unused variable in cpu_init.c

Fix the following build warnings in cpu_init.c:

cpu_init.c: In function 'cpu_init_f':
cpu_init.c:47:9: warning: unused variable 'pll'
cpu_init.c:46:10: warning: unused variable 'fbcs'
cpu_init.c:44:10: warning: unused variable 'scm1'

Signed-off-by: Alison Wang <b18965@freescale.com>
9 years agokm83xx: add kmvect1 board
Gerlando Falauto [Wed, 10 Oct 2012 22:13:10 +0000 (22:13 +0000)]
km83xx: add kmvect1 board

Add support for the new kmvect1 board powered by the mpc8309 processor.
As this board is very similar to the existing suvd3, instead of adding a
new config header file, just add a new config option to suvd3.h

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agokm83xx: add common support for km8309 boards
Gerlando Falauto [Wed, 10 Oct 2012 22:13:09 +0000 (22:13 +0000)]
km83xx: add common support for km8309 boards

Add support for Keymile boards based on mpc8309
(it would be only kmvect1 for now)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
[#elseif -> #if to allow kmcoge5ne and kmeter1 to build successfully]
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agompc83xx: add support for mpc8309
Gerlando Falauto [Wed, 10 Oct 2012 22:13:08 +0000 (22:13 +0000)]
mpc83xx: add support for mpc8309

This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agocleanup: introduce CONFIG_MPC830x
Gerlando Falauto [Wed, 10 Oct 2012 22:13:07 +0000 (22:13 +0000)]
cleanup: introduce CONFIG_MPC830x

Introduce a new configuration token CONFIG_MPC830x to be shared among
mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor
existing common code so to make future introduction of 8309 simpler.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agocleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x
Gerlando Falauto [Wed, 10 Oct 2012 22:13:06 +0000 (22:13 +0000)]
cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x

simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
for qe variables
with #if defined(CONFIG_QE)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agocosmetic: suvd3: align #defines
Gerlando Falauto [Wed, 10 Oct 2012 22:13:05 +0000 (22:13 +0000)]
cosmetic: suvd3: align #defines

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agocm-t35: clean unused defines from config
Igor Grinberg [Sun, 7 Oct 2012 01:17:34 +0000 (01:17 +0000)]
cm-t35: clean unused defines from config

Neither cm-t35, nor cm-t3730 is using OneNAND or flash.
Remove the related defines from config file.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoconfigs: Fix usage of mmc rescan
Andrew Bradford [Mon, 1 Oct 2012 05:06:52 +0000 (05:06 +0000)]
configs: Fix usage of mmc rescan

Fix usage of 'mmc rescan' by many configs.  Proper use is
'mmc dev ${mmcdev}; mmc rescan' to set the mmc device and then rescan
the device.  'mmc rescan' itself does not take any arguments.

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
9 years agoam33xx: Enable DDR3 for DDR3 version of beaglebone
Joel A Fernandes [Tue, 25 Sep 2012 06:49:47 +0000 (06:49 +0000)]
am33xx: Enable DDR3 for DDR3 version of beaglebone

DDR3 support is tested and working with beaglebone hardware. Include a check
for this board type and configure DDR3. The timings and other configuration
match EVM SK.

Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
Acked-by: Jason Kridner <jdk@ti.com>
9 years agoUSB: musb_udc: Make musb_peri_rx_ep check for MUSB_RXCSR_RXPKTRDY
Pankaj Bharadiya [Thu, 13 Sep 2012 09:38:16 +0000 (09:38 +0000)]
USB: musb_udc: Make musb_peri_rx_ep check for MUSB_RXCSR_RXPKTRDY

The endpoint rx count register value will be zero if it is read before
receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set.

Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before
reading endpoint rx count register. Proceed with rx count read and
FIFO read only if RXPKTRDY bit is set.

Signed-off-by: Pankaj Bharadiya <pankaj.bharadiya@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-fdt
Tom Rini [Tue, 23 Oct 2012 02:54:48 +0000 (19:54 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-fdt

9 years agoMerge branch 'next'
Gerald Van Baren [Tue, 23 Oct 2012 00:42:09 +0000 (20:42 -0400)]
Merge branch 'next'

9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Tom Rini [Mon, 22 Oct 2012 23:54:38 +0000 (16:54 -0700)]
Merge branch 'master' of git://denx.de/git/u-boot-mpc85xx

9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mmc
Tom Rini [Mon, 22 Oct 2012 23:53:19 +0000 (16:53 -0700)]
Merge branch 'master' of git://denx.de/git/u-boot-mmc

9 years ago85xx: Protect timeout_save variable with ifdefs
Andy Fleming [Mon, 22 Oct 2012 22:28:18 +0000 (17:28 -0500)]
85xx: Protect timeout_save variable with ifdefs

The timeout_save variable was only used by the DDR111_134
erratum code. It was being set, but never used. Newer compilers
will actually complain about this.

Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/boot: Change the compile macro for SRIO & PCIE boot master module
Liu Gang [Sun, 14 Oct 2012 20:55:17 +0000 (20:55 +0000)]
powerpc/boot: Change the compile macro for SRIO & PCIE boot master module

Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.

So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agophylib: Enable SMSC LAN87xx PHY support
Mingkai Hu [Fri, 12 Oct 2012 02:34:15 +0000 (02:34 +0000)]
phylib: Enable SMSC LAN87xx PHY support

LAN8720 PHY is used on Freescale C2X0QDS board.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/espi: remove write command length check
Shaohui Xie [Thu, 11 Oct 2012 20:31:46 +0000 (20:31 +0000)]
powerpc/espi: remove write command length check

Current espi controller driver assumes the command length of write command is
not equal to '1', it was made based on SPANSION SPI flash, but some SPI flash
driver such as SST does use write command length as '1', so write command on
SST SPI flash will not work. And the length check for write command is not
necessary for SPANSION, though it's harmless for SPANSION, it will stop write
operation on flashes like SST, so we remove the check.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/fm: fix TBI PHY address settings
shaohui xie [Thu, 11 Oct 2012 20:25:36 +0000 (20:25 +0000)]
powerpc/fm: fix TBI PHY address settings

TBI PHY address (TBIPA) register is set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and
it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1
isn't used directly, which provides MDIO for other ports. So
following code is wrong in case of FM2, which has a different
mac base.

struct dtsec *regs = (struct dtsec *)fm_eth->mac->base;
/* Assign a Physical address to the TBI */
out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopoweprc/85xx: add QMan frequency info and fdt fixup.
Haiying Wang [Thu, 11 Oct 2012 07:13:39 +0000 (07:13 +0000)]
poweprc/85xx: add QMan frequency info and fdt fixup.

Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel
driver can use it to calculate the shaper prescaler and rate.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agompc85xx/portals: Add qman and bman ip_cfg field into portal info
Haiying Wang [Thu, 11 Oct 2012 07:13:38 +0000 (07:13 +0000)]
mpc85xx/portals: Add qman and bman ip_cfg field into portal info

Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the
total portal number, buffer pool number etc, we can use this info to limit
those resources in kernel driver.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/t4qds: Add T4QDS board
York Sun [Thu, 11 Oct 2012 07:13:37 +0000 (07:13 +0000)]
powerpc/t4qds: Add T4QDS board

The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.

SERDES Connections
  32 lanes grouped into four 8-lane banks
  Two “front side” banks dedicated to Ethernet
  Two “back side” banks dedicated to other protocols
DDR Controllers
  Three independant 64-bit DDR3 controllers
  Supports rates up to 2133 MHz data-rate
  Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
QIXIS System Logic FPGA

Each DDR controller has two DIMM slots. The first slot of each controller
has up to 4 chip selects to support single-, dual- and quad-rank DIMMs.
The second slot has only 2 chip selects to support single- and dual-rank
DIMMs. At any given time, up to total 4 chip selects can be used.

Detail information can be found in doc/README.t4qds

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform
York Sun [Mon, 8 Oct 2012 07:44:31 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform

New corenet platforms with chassis2 have separated DDR clock inputs. Use
CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of
detecting and displaying synchronous vs asynchronous mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
York Sun [Mon, 8 Oct 2012 07:44:30 +0000 (07:44 +0000)]
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Remove R6 from spin table
York Sun [Mon, 8 Oct 2012 07:44:29 +0000 (07:44 +0000)]
powerpc/mpc85xx: Remove R6 from spin table

R6 was in ePAPR draft version but was dropped in official spec.
Removing it to comply.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Fix DDR SPD failed message
York Sun [Mon, 8 Oct 2012 07:44:28 +0000 (07:44 +0000)]
powerpc/mpc8xxx: Fix DDR SPD failed message

Since empty DIMM slot is allowed on other than the first slot, remove the
error message if SPD is not found in this case.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Add auto select bank interleaving mode
York Sun [Mon, 8 Oct 2012 07:44:27 +0000 (07:44 +0000)]
powerpc/mpc8xxx: Add auto select bank interleaving mode

Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
cs0_cs1 interleaving, or non-interleaving if not available.

Fix the message of interleaving disabled if controller interleaving
is enabled but DIMMs don't support it.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add workaround for DDR erratum A004934
York Sun [Mon, 8 Oct 2012 07:44:26 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add workaround for DDR erratum A004934

After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: software workaround for DDR erratum A-004468
York Sun [Mon, 8 Oct 2012 07:44:25 +0000 (07:44 +0000)]
powerpc/mpc85xx: software workaround for DDR erratum A-004468

Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT
York Sun [Mon, 8 Oct 2012 07:44:24 +0000 (07:44 +0000)]
powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT

When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation
York Sun [Mon, 8 Oct 2012 07:44:23 +0000 (07:44 +0000)]
powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation

Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-rank DIMM.

For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
registers need to be enabled to maintain proper ODT operation. The
inactive CS should have bnds registers cleared.

Fix the turnaround timing for systems with all chip-selects enabled. This
wasn't an issue before because DDR was running lower than 1600MT/s with
this interleaving mode.

Fix DDR address calculation. It wasn't an issue until we have multiple
controllers with each more than 4GB and interleaving is disabled.

It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
when debugging DDR and first DDR controller is disabled. With the fix,
the first enabled controller information will be displayed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Update DDR registers
York Sun [Mon, 8 Oct 2012 07:44:22 +0000 (07:44 +0000)]
powerpc/mpc8xxx: Update DDR registers

DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.

CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
000 -> Termsel off
001 -> 120 Ohm
010 -> 180 Ohm
011 -> 75 Ohm
100 -> 110 Ohm
101 -> 60 Ohm
110 -> 70 Ohm
111 -> 47 Ohm

Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.

Extend DDR register timing_cfg_1 to have 4 bits for each field.

DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agofm/mEMAC: add mEMAC frame work
Roy Zang [Mon, 8 Oct 2012 07:44:21 +0000 (07:44 +0000)]
fm/mEMAC: add mEMAC frame work

The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add B4860 and variant SoCs
York Sun [Mon, 8 Oct 2012 07:44:20 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add B4860 and variant SoCs

Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
    clusters-each core runs up to 1.2 GHz, with an architecture highly
    optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
    cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
    each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
    including Turbo or Viterbi decoding, Turbo encoding and rate matching,
    MIMO MMSE equalization scheme, matrix operations, CRC insertion and
    check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
    and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
    the e6500 cores, SC3900 FVP cores, memories and external interfaces.
    CoreNet fabric interconnect runs at 667 MHz and supports coherent and
    non-coherent out of order transactions with prioritization and
    bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
  Frame Manager (FMan), which supports in-line packet parsing and general
    classification to enable policing and QoS-based packet distribution
  Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
    of queue management, task management, load distribution, flow ordering,
    buffer management, and allocation tasks from the cores
  Security engine (SEC 5.3)-crypto-acceleration for protocols such as
    IPsec, SSL, and 802.16
  RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
    outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
    bandwidth saving and high utilization of processor elements. The
    9856-Kbyte internal memory space includes the following:
  32 Kbyte L1 ICache per e6500/SC3900 core
  32 Kbyte L1 DCache per e6500/SC3900 core
  2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  2048 Kbyte unified L2 cache for the e6500 cluster
  Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
  Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
    of up to 8 lanes
  Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
    less antenna connection
  Two 10-Gbit Ethernet controllers (10GEC)
  Six 1G/2.5-Gbit Ethernet controllers for network communications
  PCI Express controller
  Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add T4240 SoC
York Sun [Mon, 8 Oct 2012 07:44:19 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add T4240 SoC

Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add T4 device definitions
Andy Fleming [Mon, 8 Oct 2012 07:44:18 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add T4 device definitions

The T4 has added devices to previous corenet implementations:

* SEC has 3 more DECO units
* New PMAN device
* New DCE device

This doesn't add full support for the new devices. Just some
preliminary support.

Move PMAN LIODN to upper half of register

Despite having only one LIODN, the PMAN LIODN is stored in the
upper half of the register. Re-use the 2-LIODN code and just
set the LIODN as if the second one is 0. This results in the
actual LIODN being written to the upper half of the register.

Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agoboard/freescale/common: VSC3316/VSC3308 initialization code
Shaveta Leekha [Mon, 8 Oct 2012 07:44:17 +0000 (07:44 +0000)]
board/freescale/common: VSC3316/VSC3308 initialization code

Add code for configuring VSC3316/3308 crosspoint switches
Add README to understand the APIs

   - VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch
     capable of data rates upto 11.5Gbps. VSC3316 has 16 input and 16
     output ports whereas VSC3308 has 8 input and 8 output ports.
     Programming of these devices are performed by two-wire or four-wire
     serial interface.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/corenet2: fix mismatch DDR sync bit from RCW
York Sun [Mon, 8 Oct 2012 07:44:16 +0000 (07:44 +0000)]
powerpc/corenet2: fix mismatch DDR sync bit from RCW

Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/corenet2: Add SerDes for corenet2
York Sun [Mon, 8 Oct 2012 07:44:15 +0000 (07:44 +0000)]
powerpc/corenet2: Add SerDes for corenet2

Create new files to handle 2nd generation Chassis as the registers are
organized differently.

 - Add SerDes protocol parsing and detection
 - Add support of 4 SerDes
 - Add CPRI protocol in fsl_serdes.h
The Common Public Radio Interface (CPRI) is publicly available
specification that standardizes the protocol interface between the
radio equipment control (REC) and the radio equipment (RE) in wireless
basestations. This allows interoperability of equipment from different
vendors,and preserves the software investment made by wireless service
providers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2
York Sun [Mon, 8 Oct 2012 07:44:14 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2

Corenet 2nd generation Chassis has different RCW and registers for SerDes.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/e6500: Move QCSP registers for QMan v3
York Sun [Mon, 8 Oct 2012 07:44:13 +0000 (07:44 +0000)]
powerpc/e6500: Move QCSP registers for QMan v3

The QCSP registers are expanded and moved from offset 0 to offset 0x1000
for SoCs with QMan v3.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: expand SERDES reference clock select bit
York Sun [Mon, 8 Oct 2012 07:44:12 +0000 (07:44 +0000)]
powerpc/mpc85xx: expand SERDES reference clock select bit

Expand the reference clock select to three bits
000: 100 MHz
001: 125 MHz
010: 156.25MHz
011: 150 MHz
100: 161.1328125 MHz
All others reserved

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2
York Sun [Mon, 8 Oct 2012 07:44:11 +0000 (07:44 +0000)]
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2

Corenet based SoCs have different core clocks starting from Chassis
generation 2. Cores are organized into clusters. Each cluster has up to
4 cores sharing same clock, which can be chosen from one of three PLLs in
the cluster group with one of the devisors /1, /2 or /4. Two clusters are
put together as a cluster group. These two clusters share the PLLs but may
have different divisor. For example, core 0~3 are in cluster 1. Core 4~7
are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2
are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group
A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have
PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1.

PME and FMan blocks can take different PLLs, configured by RCW.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: check number of cores
York Sun [Mon, 8 Oct 2012 07:44:10 +0000 (07:44 +0000)]
powerpc/mpc85xx: check number of cores

Panic if the number of cores is more than CONFIG_MAX_CPUS because it will
surely overflow gd structure.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2
York Sun [Mon, 8 Oct 2012 07:44:09 +0000 (07:44 +0000)]
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2

Chassis generation 2 has different mask and shift. Use macro instead of
magic numbers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500
York Sun [Mon, 8 Oct 2012 07:44:08 +0000 (07:44 +0000)]
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500

Using E6500 L1 cache as initram requires L2 cache enabled.
Add l2-cache cluster enabling.

Setup stash id for L1 cache as (coreID) * 2 + 32 + 0
Setup stash id for L2 cache as (cluster) * 2 + 32 + 1
Stash id for L2 is only set for Chassis 2.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Introduce new macros to add and delete TLB entries
York Sun [Mon, 8 Oct 2012 07:44:07 +0000 (07:44 +0000)]
powerpc/mpc85xx: Introduce new macros to add and delete TLB entries

These assembly macros simplify codes to add and delete temporary TLB entries.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: Add determining and report IFC frequency
Kumar Gala [Mon, 8 Oct 2012 07:44:06 +0000 (07:44 +0000)]
powerpc/85xx: Add determining and report IFC frequency

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/DPAA: Fix compiling error
York Sun [Mon, 8 Oct 2012 07:44:05 +0000 (07:44 +0000)]
powerpc/DPAA: Fix compiling error

FSL_HW_PORTAL_PME is used even when CONFIG_SYS_DPAA_PME is not defined.
Remove the #ifdef.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agodriver/pci: Fix compiling error
York Sun [Mon, 8 Oct 2012 07:44:04 +0000 (07:44 +0000)]
driver/pci: Fix compiling error

Fix compiling error in case CONFIG_SYS_PCIE2_MEM_VIRT or CONFIG_SYS_PCIE3_MEM_VIRT
not defined.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/board: add present2 register definition for QIXIS
Shengzhou Liu [Sun, 7 Oct 2012 20:21:02 +0000 (20:21 +0000)]
powerpc/board: add present2 register definition for QIXIS

According to new QIXIS system definition, update QIXIS registers set
to add present2 register instead of obsolete ctl_sys2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: Add P5040 processor support
Timur Tabi [Fri, 5 Oct 2012 11:09:19 +0000 (11:09 +0000)]
powerpc/85xx: Add P5040 processor support

Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:

Four P5040 single-threaded e5500 cores built
    Up to 2.4 GHz with 64-bit ISA support
    Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
    2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
        support Up to 1600MT/s
    Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
    Packet parsing, classification, and distribution (FMAN)
    Queue management for scheduling, packet sequencing and
    congestion management (QMAN)
    Hardware buffer management for buffer allocation and
    de-allocation (BMAN)
    Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
    20 lanes at up to 5 Gbps
    Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
    Two 10 Gbps Ethernet MACs
    Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
    Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
    Two serial ATA (SATA 2.0) controllers
    Two high-speed USB 2.0 controllers with integrated PHY
    Enhanced secure digital host controller (SD/MMC/eMMC)
    Enhanced serial peripheral interface (eSPI)
    Two I2C controllers
    Four UARTs
    Integrated flash controller supporting NAND and NOR flash
DMA
    Dual four channel
Support for hardware virtualization and partitioning enforcement
    Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
    Secure boot, secure debug, tamper detection, volatile key storage

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/p5040ds: add per pci endpoint liodn offset list
Laurentiu Tudor [Fri, 5 Oct 2012 09:48:54 +0000 (09:48 +0000)]
powerpc/p5040ds: add per pci endpoint liodn offset list

Add a new device tree property named "fsl,liodn-offset-list"
holding a list of per pci endpoint permitted liodn offsets.
This property is useful in virtualization scenarios
that implement per pci endpoint partitioning.
The final liodn of a partitioned pci endpoint is
calculated by the hardware, by adding these offsets
to pci controller's base liodn, stored in the
"fsl,liodn" property of its node.
The liodn offsets are interleaved to get better cache
utilization. As an example, given 3 pci controllers,
the following liodns are generated for the pci endpoints:
    pci0: 193 256 259 262 265 268 271 274 277
    pci1: 194 257 260 263 266 269 272 275 278
    pci2: 195 258 261 264 267 270 273 276 279

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: move SRIO configuration out of corenet_ds.h
Timur Tabi [Fri, 5 Oct 2012 09:48:53 +0000 (09:48 +0000)]
powerpc/85xx: move SRIO configuration out of corenet_ds.h

The P5040 does not have SRIO, so don't put the SRIO definitions in
corenet_ds.h.  They belong in the board-specific header files.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: define SRIO LIODN functions only if SRIO is defined
Timur Tabi [Fri, 5 Oct 2012 09:48:52 +0000 (09:48 +0000)]
powerpc/85xx: define SRIO LIODN functions only if SRIO is defined

The P5040 does not have SRIO support, so there are no SRIO LIODNs.
Therefore, the functions that set the SRIO LIODNs should not be compiled.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs
Laurentiu Tudor [Fri, 5 Oct 2012 09:48:51 +0000 (09:48 +0000)]
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs

The liodn for the new PCIE controller included in P5040DS is no longer set
through a register in the guts register block but with one in the PCIE
register block itself.  Update the PCIE CCSR structure to add the new liodn
register and add a new dedicated SET_PCI_LIODN_BASE macro that puts
the liodn in the correct register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: fix Unicode characters in release.S
Timur Tabi [Fri, 5 Oct 2012 09:48:50 +0000 (09:48 +0000)]
powerpc/mpc85xx: fix Unicode characters in release.S

Commit 709389b6 unintentionally used the Unicode version of the
apostrophy.  Replace it with the normal ASCII version.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/srio: Workaround for srio erratrm a004034
Liu Gang [Fri, 28 Sep 2012 21:26:19 +0000 (21:26 +0000)]
powerpc/srio: Workaround for srio erratrm a004034

Erratum: A-004034
Affects: SRIO

Description: During port initialization, the SRIO port performs
lane synchronization (detecting valid symbols on a lane) and
lane alignment (coordinating multiple lanes to receive valid data
across lanes). Internal errors in lane synchronization and lane
alignment may cause failure to achieve link initialization at
the configured port width.

An SRIO port configured as a 4x port may see one of these scenarios:

1. One or more lanes fails to achieve lane synchronization.
Depending on which lanes fail, this may result in downtraining
from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane).

2. The link may fail to achieve lane alignment as a 4x, even
though all 4 lanes achieve lane synchronization, and downtrain
to a 1x. An SRIO port configured as a 1x port may fail to complete
port initialization (PnESCSR[PU] never deasserts) because of
scenario 1.

Impact: SRIO port may downtrain to 1x, or may fail to complete
link initialization. Once a port completes link initialization
successfully, it will operate normally.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Fix USB device-tree fixup
ramneek mehresh [Tue, 18 Sep 2012 22:28:51 +0000 (22:28 +0000)]
powerpc/mpc8xxx: Fix USB device-tree fixup

Fix usb device-tree fixup:
- wrong modification of dr_mode and phy_type when
  "usb1" is not mentioned inside hwconfig string;
   now allows hwconfig strings like:
"usb2:dr_mode=host,phy_type=ulpi"
- add warning message for using usb_dr_mode
  and usb_phy_type env variables (if either is used)

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agoARM : Remove unused CONFIG_DRIVER_SMC91111, CONFIG_DRIVER_LAN91C96
Ashok [Mon, 15 Oct 2012 07:00:14 +0000 (07:00 +0000)]
ARM : Remove unused CONFIG_DRIVER_SMC91111, CONFIG_DRIVER_LAN91C96

Remove unused CONFIG_DRIVER_SMC91111,CONFIG_DRIVER_LAN91C96,
if required implement smc_set_mac_addr() in board init.

Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
Acked-by: Tom Rini <trini@ti.com>
9 years agoomap2424:Rename CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C96 as CONFIG_DRIVER_LAN91C96...
Ashok [Mon, 15 Oct 2012 06:27:47 +0000 (06:27 +0000)]
omap2424:Rename CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C96 as CONFIG_DRIVER_LAN91C96 is obsolete.

Rename CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C9 as
CONFIG_DRIVER_LAN91C96 is obsolete.

Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
9 years agoREADME : Rename CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111, CONFIG_DRIVER_LAN91C96...
Ashok [Mon, 15 Oct 2012 06:20:47 +0000 (06:20 +0000)]
README : Rename CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111, CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C96

Rename CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111,
CONFIG_DRIVER_LAN91C96 to CONFIG_LAN91C96

Signed-off-by: Ashok Kumar Reddy <ashokkourla2000@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
9 years agoconfig: Enable CBFS, ext4 for coreboot
Simon Glass [Fri, 12 Oct 2012 14:26:12 +0000 (14:26 +0000)]
config: Enable CBFS, ext4 for coreboot

Enable Coreboot and EXT4 Filesystems on the coreboot board.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agofs: Add a Coreboot Filesystem (CBFS) driver and commands
Gabe Black [Fri, 12 Oct 2012 14:26:11 +0000 (14:26 +0000)]
fs: Add a Coreboot Filesystem (CBFS) driver and commands

This change adds CBFS support and some commands to use it to u-boot. These
commands are:

cbfsinit - Initialize CBFS support and pull all metadata into RAM. The end of
the ROM is an optional parameter which defaults to the standard 0xffffffff and
can be used to support multiple CBFSes in a system. The last one set up with
cbfsinit is the one that will be used.

cbfsinfo - Print information from the CBFS header.

cbfsls - Print out the size, type, and name of all the files in the current
CBFS. Recognized types are translated into symbolic names.

cbfsload - Load a file from CBFS into memory. Like the similar command for fat
filesystems, you can optionally provide a maximum size.

Support for CBFS is compiled in when the CONFIG_CMD_CBFS option is specified.

The CBFS driver can also be used programmatically from within u-boot.

If u-boot needs something out of CBFS very early before the heap is
configured, it won't be able to use the normal CBFS support which caches some
information in memory it allocates from the heap. The
cbfs_file_find_uncached function searches a CBFS instance without touching
the heap.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agodisk: Address cast and format errors
Taylor Hutt [Fri, 12 Oct 2012 14:26:09 +0000 (14:26 +0000)]
disk: Address cast and format errors

This change addresses a few printf-formatting errors, and a typecast
error.

Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agodisk: Make the disk partition code work with no specific partition types
Gabe Black [Fri, 12 Oct 2012 14:26:08 +0000 (14:26 +0000)]
disk: Make the disk partition code work with no specific partition types

Currently, if the disk partition code is compiled with all of the parition
types compiled out, it hits an #error which stops the build. This change
adjusts that file so that those functions will fall through to their defaults
in those cases instead of breaking the build. These functions are needed
because other code calls them, and that code is needed because other config
options are overly broad and bring in support we don't need along with
support we do.

Also reduce repetition of the 6-term #ifdef throughout the file.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoide: Add printf format string for CONFIG_SYS_64BIT_LBA option
Gabe Black [Fri, 12 Oct 2012 14:26:06 +0000 (14:26 +0000)]
ide: Add printf format string for CONFIG_SYS_64BIT_LBA option

The size of an LBA type changes depending on this option. We need to
use a different printf() string in each case, so create a define for
this.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agokerneldoc: tmpl: Implement template for LG-arrays
Marek Vasut [Fri, 12 Oct 2012 10:27:06 +0000 (10:27 +0000)]
kerneldoc: tmpl: Implement template for LG-arrays

Implement kerneldoc template for linker-generated arrays. This is
the first template in U-Boot that is used to generate kerneldoc
style documentation. This template is very basic.

Signed-off-by: Marek Vasut <marex@denx.de>
9 years agocommon: Discard the __u_boot_cmd section
Marek Vasut [Wed, 17 Oct 2012 00:45:46 +0000 (00:45 +0000)]
common: Discard the __u_boot_cmd section

The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
9 years agocommon: Convert the U-Boot commands to LG-arrays
Marek Vasut [Fri, 12 Oct 2012 10:27:04 +0000 (10:27 +0000)]
common: Convert the U-Boot commands to LG-arrays

This patch converts the old method of creating a list of command
onto the new LG-arrays code. The old u_boot_cmd section is converted
to new u_boot_list_cmd subsection and LG-array macros used as needed.

Minor adjustments had to be made to the common code to work with the
LG-array macros, mostly the fixup_cmdtable() calls are now passed the
ll_entry_start and ll_entry_count instead of linker-generated symbols.

The command.c had to be adjusted as well so it would use the newly
introduced LG-array API instead of directly using linker-generated
symbols.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
9 years agocommon: Add .u_boot_list into all linker files
Marek Vasut [Fri, 12 Oct 2012 10:27:03 +0000 (10:27 +0000)]
common: Add .u_boot_list into all linker files

Add section for the linker-generated lists into all possible linker
files, so that everyone can easily use these lists. This is mostly
a mechanical adjustment.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
9 years agocommon: Implement support for linker-generated arrays
Marek Vasut [Fri, 12 Oct 2012 10:27:02 +0000 (10:27 +0000)]
common: Implement support for linker-generated arrays

This patch adds support for linker-generated array. These arrays
are a generalization of the U-Boot command declaration approach.

Basically, the idea is to generate an array, where elements of the
array are statically initialized at compile time and each element
is declared separatelly at different place. Such array is assembled
together into continuous piece of memory by linker and a pointer to
it's first entry can then be retrieved via accessor.

The actual implementation relies on placing any variable that is to
represent an element of LG-array into particular subsection of the
.u_boot_list linker section . The subsection is determined by user
options. Once compiled, it is possible to dump all symbols placed
in .u_boot_list section and the subsections in which they should be
and generate appropriate bounds for each requested subsection of the
.u_boot_list section. Each such subsection thus contains __start and
__end entries at the begining and end respecitively.

This allows for simple run-time traversing of the array, since the
symbols are properly defined.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
9 years agocommon: Add symbol handling for generic lists into Makefile
Marek Vasut [Fri, 19 Oct 2012 05:00:10 +0000 (05:00 +0000)]
common: Add symbol handling for generic lists into Makefile

This patch adds essential components for generation of the contents of
the linker section that is used by the linker-generated array. All of
the contents is held in a separate file, u-boot.lst, which is generated
at runtime just before U-Boot is linked.

The purpose of this code is to especially generate the appropriate
boundary symbols around each subsection in the section carrying the
linker-generated arrays. Obviously, the interim linker code for actual
placement of the variables into the section is generated too. The
generated file, u-boot.lst, is included into u-boot.lds via the linker
INCLUDE directive in u-boot.lds .

Adjustments are made in the Makefile and spl/Makefile so that the
u-boot.lds and u-boot-spl.lds depend on their respective .lst files.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Joe Hershberger <joe.hershberger@ni.com>
9 years agoP4080/esdhc: make the P4080 ESDHC13 errata workaround conditional
Zang Roy-R61911 [Tue, 18 Sep 2012 09:50:08 +0000 (09:50 +0000)]
P4080/esdhc: make the P4080 ESDHC13 errata workaround conditional

P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the
workaround conditional.
In formal release document, the errata number should be ESDHC13 instead
of ESDHC136.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agoboard/freescale/common:QIXIS:Fix magic number usage
Prabhakar Kushwaha [Mon, 17 Sep 2012 17:30:31 +0000 (17:30 +0000)]
board/freescale/common:QIXIS:Fix magic number usage

QIXIS FPGA layout defines the  address of registers but The actual register bit
implementation is board-specific,

So avoid use of magic numbers as it may vary across different boards's QIXIS
FPGA implementation.
Also, Avoid board specific defines in common/qixis.h

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.
Mark Marshall [Sun, 9 Sep 2012 23:06:03 +0000 (23:06 +0000)]
powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.

We should only write TSR_WIS to the SPRN_TSR register in
reset_85xx_watchdog.

The old code would cause the timer interrupt to be acknowledged when the
watchdog was reset, and we would then get no more timer interrupts.
This bug would affect all mpc85xx boards that have the watchdog enabled.

Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agompc85xx: make gpio_direction_output respect value
Chris Packham [Thu, 6 Sep 2012 17:28:35 +0000 (17:28 +0000)]
mpc85xx: make gpio_direction_output respect value

Users of familiar with the Linux gpiolib API expect that value parameter
to gpio_direction_output reflects the initial state of the output pin.
gpio_direction_output was always driving the output low, now it drives
it high or low according to the value provided.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agofsl_pci: use 'Header Type' field to judge PCIE mode
Minghuan Lian [Tue, 21 Aug 2012 23:35:42 +0000 (23:35 +0000)]
fsl_pci: use 'Header Type' field to judge PCIE mode

The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is EP or RC mode.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agommc: dw-mmc: support DesignWare MMC Controller
Jaehoon Chung [Mon, 15 Oct 2012 19:10:29 +0000 (19:10 +0000)]
mmc: dw-mmc: support DesignWare MMC Controller

Support the DesginWare MMC Controller.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Rajeshawari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agommc: pxa: Remove the old non-generic PXA MMC driver
Marek Vasut [Sun, 30 Sep 2012 10:09:50 +0000 (10:09 +0000)]
mmc: pxa: Remove the old non-generic PXA MMC driver

This driver is no longer used and it's remaining users were converted
to the new generic PXA MMC driver. Thus, remove this driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>