glsdk/glsdk-u-boot.git
7 years agoResolved the conflicts from the merge. early_boot
Somnath Mukherjee [Thu, 5 Sep 2013 08:17:16 +0000 (13:47 +0530)]
Resolved the conflicts from the merge.

Conflicts resolved in: boards.cfg

Signed-off-by: Somnath Mukherjee <somnath@ti.com>
7 years agoHACK: ARM: DRA7xx: Add VPE crossbar setting
Somnath Mukherjee [Wed, 14 Aug 2013 17:36:28 +0000 (23:06 +0530)]
HACK: ARM: DRA7xx: Add VPE crossbar setting

Signed-off-by: Somnath Mukherjee <somnath@ti.com>
7 years agoMerge branch 'master' into early_boot
Somnath Mukherjee [Wed, 14 Aug 2013 16:09:48 +0000 (21:39 +0530)]
Merge branch 'master' into early_boot

7 years agoARM: DRA7xx: Enable CPSW Ethernet support
Mugunthan V N [Mon, 8 Jul 2013 10:34:43 +0000 (16:04 +0530)]
ARM: DRA7xx: Enable CPSW Ethernet support

Enabling CPSW Ethernet support in DRA7xx EVM.

Change-Id: I870a812e72995106dd5a6eb2566e2ebff814eea7
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Resolved merge conflicts and added change id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
7 years agoARM: DRA7xx: Add CPSW and MDIO pinmux support
Mugunthan V N [Mon, 8 Jul 2013 10:34:42 +0000 (16:04 +0530)]
ARM: DRA7xx: Add CPSW and MDIO pinmux support

Adding CPSW Slave 0 and MDIO pinmux support for DRA7xx EVM

Change-Id: I562fecee5194f9498d1e8387e1e3888e3ebb3fbd
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Resolved merge conflict and added change id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
7 years agoARM: DRA7xx: Add CPSW support to DRA7xx EVM
Mugunthan V N [Mon, 8 Jul 2013 10:34:41 +0000 (16:04 +0530)]
ARM: DRA7xx: Add CPSW support to DRA7xx EVM

Adding support for CPSW Ethernet support found in DRA7xx EVM

Change-Id: Id68e606967aeeecaaf991eb26ef94d2119dc7a83
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Resolved merge conflicts and added change id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
7 years agoARM: DRA7xx: Enable GMAC clock control
Mugunthan V N [Mon, 8 Jul 2013 10:34:40 +0000 (16:04 +0530)]
ARM: DRA7xx: Enable GMAC clock control

Enabling CPSW module by enabling GMAC clock control

Change-Id: I6b48ee2ba5dd400b3f9e1744933e7dbc09e4a13e
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Resolved merge conflicts and added change id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
7 years agoARM: DRA7xx: Lock DPLL_GMAC
Lokesh Vutla [Mon, 8 Jul 2013 10:34:39 +0000 (16:04 +0530)]
ARM: DRA7xx: Lock DPLL_GMAC

Locking DPLL_GMAC

[mugunthanvnm@ti.com:Configure only if CPSW is selected]

Change-Id: I5b3cffa699f83cf88ee98086ba2dc9a8586a1074
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Added change-id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
7 years agodrivers: net: cpsw: Enable statistics for all port
Mugunthan V N [Mon, 8 Jul 2013 10:34:38 +0000 (16:04 +0530)]
drivers: net: cpsw: Enable statistics for all port

Enable hardware statistics for all ports, enabling only to host port is useless

Change-Id: I0dd84448a5c002a8280275e6ed253fa61576e467
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Added change-id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
7 years agodrivers: net: cpsw: remove hard coding bd ram for cpsw
Mugunthan V N [Mon, 8 Jul 2013 10:34:37 +0000 (16:04 +0530)]
drivers: net: cpsw: remove hard coding bd ram for cpsw

BD ram address may vary in various SOC, so removing the hardcoding and
passing the same information through platform data

Change-Id: Ib36d34f66f741321abdf06575010c87c99d49085
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[Added change-id for gerrit]
Signed-off-by: Praveen Rao <prao@ti.com>
7 years agoHACK: ARM: DRA7xx: Add Ethernet crossbar setting
Somnath Mukherjee [Wed, 14 Aug 2013 11:16:23 +0000 (16:46 +0530)]
HACK: ARM: DRA7xx: Add Ethernet crossbar setting

Signed-off-by: Somnath Mukherjee <somnath@ti.com>
7 years agoMerge branch 'master' into early_boot
Somnath Mukherjee [Tue, 13 Aug 2013 13:06:10 +0000 (18:36 +0530)]
Merge branch 'master' into early_boot

Conflicts:
arch/arm/cpu/armv7/omap5/hw_data.c
boards.cfg

Following files are modified as a result of merge:
modified:   README
modified:   arch/arm/cpu/armv7/omap-common/hwinit-common.c
modified:   arch/arm/cpu/armv7/omap5/hw_data.c
modified:   arch/arm/include/asm/arch-omap5/spl.h
modified:   arch/arm/include/asm/arch-omap5/sys_proto.h
modified:   board/ti/dra7xx/evm.c
modified:   board/ti/dra7xx/mux_data.h
modified:   boards.cfg
renamed:    README.dra_qspi_test -> doc/README.ti_qspi_dra_test
renamed:    README.dra_qspi_flash -> doc/README.ti_qspi_flash
modified:   drivers/mtd/spi/spansion.c
modified:   drivers/mtd/spi/spi_flash.c
modified:   drivers/mtd/spi/spi_flash_internal.h
modified:   drivers/mtd/spi/stmicro.c
modified:   drivers/spi/ti_qspi.c
modified:   include/configs/dra7xx_evm.h
modified:   include/configs/omap5_common.h
modified:   include/spi.h
modified:   include/spi_flash.h

Signed-off-by: Somnath Mukherjee <somnath@ti.com>
7 years agodra7xx: Enabled UART-boot mode
Minal [Mon, 12 Aug 2013 12:13:18 +0000 (17:43 +0530)]
dra7xx: Enabled UART-boot mode

UART-boot is considered as a peripheral boot.
For dra7xx Peripheral boot UART3 is used as default console.
The ROM code transfers MLO over UART3 in this case.
For Memory boot UART1 is used as default console.
Which UART to be used is decided by parameter CONS_INDEX.
For peripheral boot this should be set to 3.

Changes common to memory boot and peripheral boot:
--------------------------------------------------
boards.cfg:
Moved definition of CONS_INDEX in boards.cfg to make it configurable between
memory boot and peripheral boot.

spl.h:
Added #define BOOT_DEVICE_UART for UART boot device code.

Changes specific to peripheral boot:
------------------------------------
boards.cfg:
Added a build variant "dra7xx_evm_uart3" for dra7xx that sets UART to UART3 and
enables YMODEM support.

MLO->u-boot needs YMODEM support enabled. By default it is disabled.

Changes needed in addition to the above:
----------------------------------------
1. When building u-boot ensure usage of dra7xx_evm_uart3_config instead of
dra7xx_evm_config.

2. Please note that apart from the above changes CONFIG_SPL_TEXT_BASE should point to
base of OCMC_RAM1 for proper execution.
In memory boot mode ROM code transfers MLO to location OCMC_RAM1 base+offset
(CONFIG_SPL_TEXT_BASE = 0x40300000+350).
In peripheral boot mode ROM code transfers MLO to location OCMC_RAM1 base
(0x40300000).
Hence is is a must to change CONFIG_SPL_TEXT_BASE in include/configs/omap5_common.h
from 0x40300350 to 0x40300000

Signed-off-by: Minal <minal.shah@ti.com>
7 years agoarm: omap5: dra7xx: Rework bootcmd to handle two MMC devs ti2013.04.02.prod.13.08.001
alaganraj [Tue, 6 Aug 2013 15:18:07 +0000 (20:48 +0530)]
arm: omap5: dra7xx: Rework bootcmd to handle two MMC devs

omap5_uevm and dra7xx_evm both can boot from either the MMC card
or eMMC chip on board. We should try both interfaces.

This modification also allows a graceful fallback if
a device exists but boot images are not present on it.

This is adopted from am335x_evm patch.

Signed-off-by: alaganraj <alaganraj.s@ti.com>
7 years agoHACK: ARM: DRA7xx: crossbar: Add support for crossbar
Amarinder Bindra [Wed, 7 Aug 2013 15:30:18 +0000 (21:00 +0530)]
HACK: ARM: DRA7xx: crossbar: Add support for crossbar

DRA7xx has a large number of interrupts/dma requests to service
the needs of its many peripherals and subsystems. All of the
requests lines from the subsystems are not needed at the same
time, so they have to be muxed to the controllers appropriately.
In such places a interrupt/dma controllers are preceded by an
IRQ/DMA CROSSBAR that provides flexibility in muxing the device
requests to the controller inputs.

This configures some of the MPU IRQs and SDMA DREQ at the u-boot
until this functionality is available at the kernel.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
7 years agoconfigs: DRA7: include Bank Address register support
Ravikumar Kattekola [Wed, 7 Aug 2013 12:38:35 +0000 (18:08 +0530)]
configs: DRA7: include Bank Address register support

CONFIG_SPI_FLASH_BAR            Ban/Extended Addr Reg

This option adds the Bank addr/Extended addr support
on SPI flashes which has size > 16Mbytes.

Signed-off-by: Ravikumar Kattekola <rk@ti.com>
7 years agoREADME: qspi usecase and testing documentation.
Sourav Poddar [Wed, 7 Aug 2013 12:38:34 +0000 (18:08 +0530)]
README: qspi usecase and testing documentation.

Contains documentation and testing details for qspi flash
interface.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agodriver: spi: Add memory mapped read support
Sourav Poddar [Wed, 7 Aug 2013 12:38:33 +0000 (18:08 +0530)]
driver: spi: Add memory mapped read support

Qspi controller has a memory mapped port which can be used for
data transfers. First controller need to be configured through
configuration port, then for data read switch the controller
to memory mapped and read from the predefined location.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agodrivers: mtd: qspi: Add quad read support
Ravikumar Kattekola [Wed, 7 Aug 2013 12:38:32 +0000 (18:08 +0530)]
drivers: mtd: qspi: Add quad read support

Add Quad read mode (6 pin interface) support to spi flash
and ti qspi driver.

Quad mode (0x6bh on spansion) uses two extra pins (D2 and D3) for
data transfer apart from the usual D0 and D1 pins thus transfering
4 bits per cycle.

Signed-off-by: Ravikumar Kattekola <rk@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agodra7xx_evm: add SPL API, QSPI, and serial flash support
Matt Porter [Wed, 7 Aug 2013 12:38:31 +0000 (18:08 +0530)]
dra7xx_evm: add SPL API, QSPI, and serial flash support

Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agospi: add TI QSPI driver
Matt Porter [Wed, 7 Aug 2013 12:38:30 +0000 (18:08 +0530)]
spi: add TI QSPI driver

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agoarmv7: hw_data: change clock divider setting.
Sourav Poddar [Wed, 7 Aug 2013 12:38:29 +0000 (18:08 +0530)]
armv7: hw_data: change clock divider setting.

Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,

f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)

fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agoomap5: add qspi support
Matt Porter [Wed, 7 Aug 2013 12:38:28 +0000 (18:08 +0530)]
omap5: add qspi support

Add QSPI definitions and clock configuration support.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agosf: Warn to use BAR for > 16MiB flashes
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:37:04 +0000 (18:07 +0530)]
sf: Warn to use BAR for > 16MiB flashes

Warning for > 16MiB flashes to #define CONFIG_SPI_FLASH_BAR

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
7 years agosf: Add debug messages on spi_flash_read_common
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:37:03 +0000 (18:07 +0530)]
sf: Add debug messages on spi_flash_read_common

- Added debug's on spi_flash_read_common()
- Added space

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
7 years agosf: Place the sf calls in proper order
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:37:02 +0000 (18:07 +0530)]
sf: Place the sf calls in proper order

Placed the sf calls in proper order - erase/write/read

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
7 years agosf: Unify spi_flash write code
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:37:01 +0000 (18:07 +0530)]
sf: Unify spi_flash write code

Move common flash write code into spi_flash_write_common().

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agosf: Add flag status register polling support
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:37:00 +0000 (18:07 +0530)]
sf: Add flag status register polling support

Flag status register polling is required for micron 512Mb flash
devices onwards, for performing erase/program operations.

Like polling for WIP(Write-In-Progress) bit in read status register,
spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control)
bit in flag status register.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agosf: Remove spi_flash_cmd_poll_bit()
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:36:59 +0000 (18:06 +0530)]
sf: Remove spi_flash_cmd_poll_bit()

There is no other call other than spi_flash_cmd_wait_ready(),
hence removed spi_flash_cmd_poll_bit and use the poll status code
spi_flash_cmd_wait_ready() itself.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agosf: spansion: Add support for S25FL512S_64K
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:36:58 +0000 (18:06 +0530)]
sf: spansion: Add support for S25FL512S_64K

Add support for Spansion S25FL512S_64K SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
7 years agosf: Use spi_flash_addr() in write call
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:36:57 +0000 (18:06 +0530)]
sf: Use spi_flash_addr() in write call

Use the existing spi_flash_addr() for 3-byte addressing
cmd filling in write call.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agosf: Add bank addr code in CONFIG_SPI_FLASH_BAR
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:36:56 +0000 (18:06 +0530)]
sf: Add bank addr code in CONFIG_SPI_FLASH_BAR

Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the
size for existing boards which has < 16Mbytes SPI flashes.

It's upto user which has provision to use the bank addr code for
flashes which has > 16Mbytes.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agosf: Update sf read to support all sizes of flashes
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:36:55 +0000 (18:06 +0530)]
sf: Update sf read to support all sizes of flashes

This patch updated the spi_flash read func to support all
sizes of flashes using bank reg addr facility.

The same support has been added in below patch for erase/write
spi_flash functions:
"sf: Support all sizes of flashes using bank addr reg facility"
(sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415)

With these new updates on sf framework, the flashes which has < 16MB
are not effected as per as performance is concern and but the
u-boot.bin size incrased ~460 bytes.

sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
  16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV
  16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K
  16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s

sf update(for first 16MBytes), Changes before:
U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256
  16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV
  16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K
  16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agosf: Update sf to support all sizes of flashes
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:36:54 +0000 (18:06 +0530)]
sf: Update sf to support all sizes of flashes

Updated the spi_flash framework to handle all sizes of flashes
using bank/extd addr reg facility

The current implementation in spi_flash supports 3-byte address mode
due to this up to 16Mbytes amount of flash is able to access for those
flashes which has an actual size of > 16MB.

As most of the flashes introduces a bank/extd address registers
for accessing the flashes in 16Mbytes of banks if the flash size
is > 16Mbytes, this new scheme will add the bank selection feature
for performing write/erase operations on all flashes.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agosf: Read flash bank addr register at probe time
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:36:53 +0000 (18:06 +0530)]
sf: Read flash bank addr register at probe time

Read the flash bank addr register to get the state of bank in
a perticular flash. and also bank write happens only when there is
a change in bank selection from user.

bank read only valid for flashes which has > 16Mbytes those are
opearted in 3-byte addr mode, each bank occupies 16Mytes.

Suppose if the flash has 64Mbytes size consists of 4 banks like
bank0, bank1, bank2 and bank3.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agosf: Discover the bank addr commands
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:36:52 +0000 (18:06 +0530)]
sf: Discover the bank addr commands

Bank/Extended addr commands are specific to particular
flash vendor so discover them based on the idocode0.

Assign the discovered bank commands to spi_flash members
so-that the bank read/write will use their specific operations.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
7 years agosf: Add bank address register writing support
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:36:51 +0000 (18:06 +0530)]
sf: Add bank address register writing support

This patch provides support to program a flash bank address
register.

extended/bank address register contains an information to access
the 4th byte addressing in 3-byte address mode.

reff' the spec for more details about bank addr register
in Page-63, Table 8.16
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agosf: spansion: Correct name of S25FL128S 64K Sector part
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 12:36:50 +0000 (18:06 +0530)]
sf: spansion: Correct name of S25FL128S 64K Sector part

Corrected the name of S25FL128S 64K sector part SPI flash,
S25FL128S supported has been added in below commit
"sf: spansion: Add support for S25FL128S"
(sha1: 1bfb9f156aa66cca6bb9c773867a1f02a84b14be)

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
7 years agoDRA7: Revert QSPI v1 patchset to apply v2 with code clean up
Ravikumar Kattekola [Wed, 7 Aug 2013 12:36:49 +0000 (18:06 +0530)]
DRA7: Revert QSPI v1 patchset to apply v2 with code clean up

This patch is a squash of 8 reverted patches as mentioned below.
This was required inorder to apply a later version of the
same patchset with code clean up and fixes.

Revert "arm: omap5: hw_data: Enable clock selectively."

Revert "board: dra7xxx: modfiy mux data."

Revert "Fix offset detail and add sysboot settings"

Revert "README: qspi usecase and testing documentation."

Revert "drivers: mtd: spi: Modify read/write command for sfl256s flash."

Revert "dra7xx_evm: add SPL API, QSPI, and serial flash support"

Revert "spi: add TI QSPI driver"

Revert "omap5: add qspi support"

7 years agoarm: omap5: hw_data: Enable clock selectively. ti2013.04.02.prod.13.07.001
Sourav Poddar [Mon, 24 Jun 2013 11:42:53 +0000 (17:12 +0530)]
arm: omap5: hw_data: Enable clock selectively.

Api to enable clock is common for both dra and omap5, hence
selectively enable qspi clock.

Without this, omap5 is not working properly at u-boot level.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reported-by: Amarinder Bindra <a-bindra@ti.com>
Signed-off-by: Somnath Mukherjee <somnath@ti.com>
7 years agoarm: omap5: hw_data: Enable clock selectively.
Sourav Poddar [Mon, 24 Jun 2013 11:42:53 +0000 (17:12 +0530)]
arm: omap5: hw_data: Enable clock selectively.

Api to enable clock is common for both dra and omap5, hence
selectively enable qspi clock.

Without this, omap5 is not working properly at u-boot level.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reported-by: Amarinder Bindra <a-bindra@ti.com>
Signed-off-by: Somnath Mukherjee <somnath@ti.com>
7 years agoSPL: Load the dtb file to jump directly to kernel from first stage u-boot on mmc.
Bindra, Amarinder [Wed, 26 Jun 2013 11:30:11 +0000 (17:00 +0530)]
SPL: Load the dtb file to jump directly to kernel from first stage u-boot on mmc.

The kernel image requires the dtb file to be loaded in the memory during the
boot. For this case, where the second stage of u-boot is skipped and kernel
image is loaded, add a custom call to load the dtb file from the mmc card to
the address specified by the macro CONFIG_SYS_SPL_ARGS_ADDR as defined in the
configuration file.

Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
Signed-off-by: Somnath Mukherjee <somnath@ti.com>
7 years agoARM: OMAP5: Add configuration for early boot.
Bindra, Amarinder [Wed, 26 Jun 2013 11:30:10 +0000 (17:00 +0530)]
ARM: OMAP5: Add configuration for early boot.

Adds a configuration file with the configs to skip the second stage of the
boot loader and jump directly to the kernel from the first stage of u-boot.

Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
Signed-off-by: Somnath Mukherjee <somnath@ti.com>
7 years agoboard: dra7xxx: modfiy mux data. ti2013.04.02
Sourav Poddar [Fri, 7 Jun 2013 11:46:15 +0000 (17:16 +0530)]
board: dra7xxx: modfiy mux data.

Modify qspi pin configuartions

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agoFix offset detail and add sysboot settings
Sourav Poddar [Fri, 7 Jun 2013 16:32:48 +0000 (22:02 +0530)]
Fix offset detail and add sysboot settings

Fix u-bot offset details and add qspi sysboot setings.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agoREADME: qspi usecase and testing documentation.
Sourav Poddar [Fri, 7 Jun 2013 16:32:48 +0000 (22:02 +0530)]
README: qspi usecase and testing documentation.

Contains documentation and testing details for qspi flash
interface.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agodrivers: mtd: spi: Modify read/write command for sfl256s flash.
Sourav Poddar [Fri, 7 Jun 2013 16:32:47 +0000 (22:02 +0530)]
drivers: mtd: spi: Modify read/write command for sfl256s flash.

Reading using the already supported read command is causing regression
even while reading 4k bytes, as a result doing a page by page read.

At the end of the write sequence, write enable latch should be disabled and
re enabled while doing the next page programming.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agodra7xx_evm: add SPL API, QSPI, and serial flash support
Matt Porter [Fri, 7 Jun 2013 16:32:46 +0000 (22:02 +0530)]
dra7xx_evm: add SPL API, QSPI, and serial flash support

Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.

Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agospi: add TI QSPI driver
Matt Porter [Fri, 7 Jun 2013 16:32:45 +0000 (22:02 +0530)]
spi: add TI QSPI driver

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agoomap5: add qspi support
Matt Porter [Fri, 7 Jun 2013 16:32:44 +0000 (22:02 +0530)]
omap5: add qspi support

Add QSPI definitions and clock configuration support.

Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agoARM: DRA7xx: EMIF: Change settings required for EVM board
Sricharan R [Tue, 28 May 2013 11:52:25 +0000 (17:22 +0530)]
ARM: DRA7xx: EMIF: Change settings required for EVM board

DRA7 EVM board has the below configuration. Adding the
settings for the same here.

   2Gb_1_35V_DDR3L part * 2 on EMIF1
   2Gb_1_35V_DDR3L part * 4 on EMIF2

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: DRA7xx: clocks: Update PLL values
Lokesh Vutla [Tue, 28 May 2013 04:28:11 +0000 (09:58 +0530)]
ARM: DRA7xx: clocks: Update PLL values

Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: DRA7xx: Update pinmux data
Lokesh Vutla [Wed, 22 May 2013 06:43:29 +0000 (12:13 +0530)]
ARM: DRA7xx: Update pinmux data

Updating pinmux data as specified in the latest DM

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
7 years agommc: omap_hsmmc: add mmc1 pbias, ldo1
Balaji T K [Fri, 3 May 2013 09:28:08 +0000 (14:58 +0530)]
mmc: omap_hsmmc: add mmc1 pbias, ldo1

add dra mmc pbias support and ldo1 power on

Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: DRA7xx: Correct SRAM END address
Sricharan R [Tue, 28 May 2013 05:28:25 +0000 (10:58 +0530)]
ARM: DRA7xx: Correct SRAM END address

NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: DRA7xx: Correct the SYS_CLK to 20MHZ
Sricharan R [Tue, 28 May 2013 05:02:23 +0000 (10:32 +0530)]
ARM: DRA7xx: Correct the SYS_CLK to 20MHZ

The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: DRA7xx: Change the Debug UART to UART1
Sricharan R [Tue, 28 May 2013 04:57:46 +0000 (10:27 +0530)]
ARM: DRA7xx: Change the Debug UART to UART1

Serial UART is connected to UART1. So add the change
for the same.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Lokesh Vutla [Tue, 28 May 2013 04:36:08 +0000 (10:06 +0530)]
ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's

Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP5: DRA7xx: support class 0 optimized voltages
Nishanth Menon [Thu, 4 Apr 2013 13:16:24 +0000 (18:46 +0530)]
ARM: OMAP5: DRA7xx: support class 0 optimized voltages

DRA752 now uses AVS Class 0 voltages which are voltages in efuse.

This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.

This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agoARM: DRA7xx: clocks: Fixing i2c_init for PMIC
Lokesh Vutla [Tue, 28 May 2013 04:40:56 +0000 (10:10 +0530)]
ARM: DRA7xx: clocks: Fixing i2c_init for PMIC

In DRA7xx Soc's voltage scaling is done using GPI2C.
So i2c_init should happen before scaling. I2C driver
uses __udelay which needs timer to be initialized.
So moving timer_init just before voltage scaling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: DRA7xx: power Add support for tps659038 PMIC
Lokesh Vutla [Tue, 2 Apr 2013 03:55:31 +0000 (09:25 +0530)]
ARM: DRA7xx: power Add support for tps659038 PMIC

TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: DRA7xx: Add control id code for DRA7xx
Lokesh Vutla [Thu, 21 Mar 2013 11:30:34 +0000 (17:00 +0530)]
ARM: DRA7xx: Add control id code for DRA7xx

The registers that are used for device identification
are changed from OMAP5 to DRA7xx.
Using the correct registers for DRA7xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP4+: pmic: Make generic bus init and write functions
Lokesh Vutla [Wed, 22 May 2013 06:05:04 +0000 (11:35 +0530)]
ARM: OMAP4+: pmic: Make generic bus init and write functions

Voltage scaling can be done in two ways:
-> Using SR I2C
-> Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP5: clocks: Do not enable sgx clocks
Sricharan R [Wed, 1 May 2013 13:58:54 +0000 (19:28 +0530)]
ARM: OMAP5: clocks: Do not enable sgx clocks

SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: OMAP4+: Cleanup header files
Lokesh Vutla [Wed, 22 May 2013 05:55:34 +0000 (11:25 +0530)]
ARM: OMAP4+: Cleanup header files

After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agoARM: OMAP: Add arch_cpu_init function
SRICHARAN R [Wed, 24 Apr 2013 00:41:25 +0000 (00:41 +0000)]
ARM: OMAP: Add arch_cpu_init function

The boot parameters passed from SPL to UBOOT
must be saved as a part of uboot's gd data
as early as possible, before we will inadvertently
overwrite it. So adding a arch_cpu_init for the required
Socs to save it.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
8 years agoARM: OMAP: Cleanup boot parameters usage
SRICHARAN R [Wed, 24 Apr 2013 00:41:24 +0000 (00:41 +0000)]
ARM: OMAP: Cleanup boot parameters usage

The boot parameters are read from individual variables
assigned for each of them. This been corrected and now
they are stored as a part of the global data 'gd'
structure. So read them from 'gd' instead.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
8 years agoARM: OMAP: Correct save_boot_params and replace with 'C' function
SRICHARAN R [Wed, 24 Apr 2013 00:41:23 +0000 (00:41 +0000)]
ARM: OMAP: Correct save_boot_params and replace with 'C' function

Currently save_boot_params saves the boot parameters passed
from romcode. But this is not stored in a writable location
consistently. So the current code would not work for a
'XIP' boot. Change this by saving the boot parameters in
'gd' which is always writable. Also add a 'C' function
instead of an assembly code that is more readable.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
8 years agoARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common
SRICHARAN R [Wed, 24 Apr 2013 00:41:22 +0000 (00:41 +0000)]
ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common

These defines are same across OMAP4/5. So move them to
omap_common.h. This is required for the patches that
follow.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
8 years agoARM: OMAP: Make omap_boot_parameters common across socs
SRICHARAN R [Wed, 24 Apr 2013 00:41:21 +0000 (00:41 +0000)]
ARM: OMAP: Make omap_boot_parameters common across socs

omap_boot_parameters is same and defined for each
soc. So move this to a common place to reuse it
across socs.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
8 years agoam33xx: Fix warning with CONFIG_DISPLAY_CPUINFO
Tom Rini [Thu, 25 Apr 2013 20:46:04 +0000 (16:46 -0400)]
am33xx: Fix warning with CONFIG_DISPLAY_CPUINFO

The arm_freq and ddr_freq variables are unused, so remove.  Fixup
whitespace slightly while in here.

Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Tom Rini <trini@ti.com>
8 years agodavinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASK
Eric Benard [Mon, 22 Apr 2013 05:55:00 +0000 (05:55 +0000)]
davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASK

these variables are curently defined in several config files but the
driver doesn't use them and defaults to hardcoded values in
nand_defs.h

It's interesting to be able to change this hardcoded valude when the
hardware is not using the default adress signals to drive ALE and CLE
and two configuration defines already exist for this purpose so use
them.

Signed-off-by: Eric Bénard <eric@eukrea.com>
8 years agoda850: provide davinci_enable_uart0
Eric Benard [Mon, 22 Apr 2013 05:54:59 +0000 (05:54 +0000)]
da850: provide davinci_enable_uart0

this is needed to bring UART0 out of reset but this function
currently only exists for dm644x/355/365/646x when da850 (at
least am1808 also need it).

Signed-off-by: Eric Bénard <eric@eukrea.com>
8 years agocm-t35: update config file
Igor Grinberg [Mon, 22 Apr 2013 01:06:55 +0000 (01:06 +0000)]
cm-t35: update config file

Several minor updates to the cm-t35 config file.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
8 years agoMAINTAINERS: fix the cm-t35 board name
Igor Grinberg [Mon, 22 Apr 2013 01:06:54 +0000 (01:06 +0000)]
MAINTAINERS: fix the cm-t35 board name

"cm-t35" in U-Boot source code is called "cm_t35".
Make the change "cm-t35" -> "cm_t35" for better greppability.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
8 years agocm-t35: move cm-t35 to live in compulab directory
Igor Grinberg [Mon, 22 Apr 2013 01:06:53 +0000 (01:06 +0000)]
cm-t35: move cm-t35 to live in compulab directory

Currently the cm-t35 support code lives under board/cm_t35 directory.
Some of the code can be shared with other/future CompuLab boards,
so move the cm-t35 to live under board/compulab/cm_t35 directory.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
8 years agoARM: Panda: Add flag to allow runtime enviroment varibale mods
Dan Murphy [Thu, 18 Apr 2013 06:29:54 +0000 (06:29 +0000)]
ARM: Panda: Add flag to allow runtime enviroment varibale mods

Add the flag to allow runtime enviroment variable modifications.
This is being added so that the board-name can be modified at runtime
to indicate either a panda(4430) or a panda-es(4460)

Signed-off-by: Dan Murphy <dmurphy@ti.com>
8 years agoARM:Panda:Fix device tree loading for the panda-es
Dan Murphy [Thu, 18 Apr 2013 06:29:53 +0000 (06:29 +0000)]
ARM:Panda:Fix device tree loading for the panda-es

Fix the device tree loading for panda(4430) and panda-es(4460)

Modify the board name if a 4460 panda or panda-es is detected
at run time.
In the findfdt add a check for the panda-es board name and load
the panda-es device tree blob.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
8 years agoARM: OMAP5: Fix warm reset with USB cable connected
Lokesh Vutla [Wed, 17 Apr 2013 20:49:40 +0000 (20:49 +0000)]
ARM: OMAP5: Fix warm reset with USB cable connected

Warm reset on OMAP5 freezes when USB cable is connected.
Fix requires PRM_RSTTIME.RSTTIME1 to be programmed
with the time for which reset should be held low for the
voltages and the oscillator to reach stable state.

There are 3 parameters to be considered for calculating
the time, which are mostly board and PMIC dependent.
-1- Time taken by the Oscillator to shut + restart
-2- PMIC OTP times
-3- Voltage rail ramp times, which inturn depends on the
PMIC slew rate and value of the voltage ramp needed.

In order to keep the code in u-boot simple, have a way
for boards to specify a pre computed time directly using
the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'
option. If boards fail to specify the time, use a default
as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead.
Using the default value translates into some ~22ms and should work in
all cases.
However in order to avoid this large delay hiding other bugs,
its recommended that all boards look at their respective data
sheets and specify a pre computed and optimal value using
'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'

In order to help future board additions to compute this
config option value, add a README at doc/README.omap-reset-time
which explains how to compute the value. Also update the toplevel
README with the additional option and pointers to
doc/README.omap-reset-time.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[rnayak@ti.com: Updated changelog and added the README]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
8 years agoRemove duplicate / unused #defines on AM335x boards
Mark Jackson [Wed, 17 Apr 2013 08:22:47 +0000 (08:22 +0000)]
Remove duplicate / unused #defines on AM335x boards

As part of a review of a recent patch to add a new AM335x board, Tom
found several duplicate and/or unused #defines.

This patch simply removes them.

The two affected configs have been recompiled to check nothing was
broken (from a compilation point of view !!)

Reported-by: Tom Rini <trini@ti.com>
Signed-off-by: Mark Jackson <mpfj-list@mimc.co.uk>
8 years agoomap5_common: Add optargs variable for kernel command line args
Tom Rini [Thu, 11 Apr 2013 05:22:10 +0000 (05:22 +0000)]
omap5_common: Add optargs variable for kernel command line args

Add 'optargs' variable to be set to additional kernel arguments, similar
to omap3*/am3* usage.

Cc: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
8 years agoOMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to work
Lubomir Popov [Thu, 11 Apr 2013 00:08:51 +0000 (00:08 +0000)]
OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to work

USB TLL clocks do not support 'explicit_en', only 'hw_auto'
control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be
moved to the clk_modules_hw_auto_essential[] array in order
to make the clock work.

This fix is needed (but not sufficient) for USB EHCI operation
in U-Boot.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
8 years agoARM: Add support for IGEP COM AQUILA/CYGNUS
Enric Balletbo i Serra [Thu, 4 Apr 2013 22:27:58 +0000 (22:27 +0000)]
ARM: Add support for IGEP COM AQUILA/CYGNUS

The IGEP COM AQUILA and CYGNUS are industrial processors modules with
following highlights:

  o AM3352/AM3354 Texas Instruments processor
  o Cortex-A8 ARM CPU
  o 3.3 volts Inputs / Outputs use industrial
  o 256 MB DDR3 SDRAM / 128 Megabytes FLASH
  o MicroSD card reader on-board
  o Ethernet controller on-board
  o JTAG debug connector available
  o Designed for industrial range purposes

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
8 years agoAdd DDR3 support for IGEP COM AQUILA/CYGNUS.
Enric Balletbo i Serra [Thu, 4 Apr 2013 22:27:57 +0000 (22:27 +0000)]
Add DDR3 support for IGEP COM AQUILA/CYGNUS.

These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
8 years agoarm: omap: emif: Fix DDR3 init after warm reset
Lokesh Vutla [Wed, 27 Mar 2013 20:24:42 +0000 (20:24 +0000)]
arm: omap: emif: Fix DDR3 init after warm reset

EMIF supports a global warm reset mode, during which the
EMIF keeps the SDRAM content. But if leveling is enabled
at the time of warm reset for DDR3, the following steps
needs to be done after warm reset:
1) Keep EMIF in self refresh mode.
2) Reset PHY to bring back the PHY to a known state.
3) Start Levelling procedure.
Doing the same.
And also enabling DLL lock and code output after warm reset.

Tested on OMAP5432 ES2.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
8 years agobeagleboard: Update comment in get_board_rev()
Tom Rini [Tue, 16 Apr 2013 20:31:20 +0000 (16:31 -0400)]
beagleboard: Update comment in get_board_rev()

We are able to tell the difference between xM Rev Ax/Bx and xM Rev Cx,
and have been for some time.  The comment above the function however did
not list this, so update.

Signed-off-by: Tom Rini <trini@ti.com>
8 years agoOMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5
Lubomir Popov [Mon, 8 Apr 2013 21:49:43 +0000 (21:49 +0000)]
OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
In order to be able to select one of these buses however, I2C_BUS_MAX
has to be set to 5; do this here.

Please note that for working bus selection, a fix to the i2c driver
is required as well (subject of a separate patch).

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
8 years agoOMAP5: I2C: Add I2C4 and I2C5 bases
Lubomir Popov [Mon, 8 Apr 2013 21:49:40 +0000 (21:49 +0000)]
OMAP5: I2C: Add I2C4 and I2C5 bases

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The I2C4 and I2C5 base addresses were however not defined; do this
here.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
8 years agoOMAP5: I2C: Enable i2c5 clocks
Lubomir Popov [Mon, 8 Apr 2013 21:49:37 +0000 (21:49 +0000)]
OMAP5: I2C: Enable i2c5 clocks

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The i2c5 clock was however not enabled; do this here.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
8 years agopalmas: add header guard
Nishanth Menon [Tue, 26 Mar 2013 05:20:58 +0000 (05:20 +0000)]
palmas: add header guard

Add an header guard to common header file to prevent multiple
includes messing things up.

Signed-off-by: Nishanth Menon <nm@ti.com>
8 years agopalmas: use palmas_i2c_[read|write]_u8
Nishanth Menon [Tue, 26 Mar 2013 05:20:57 +0000 (05:20 +0000)]
palmas: use palmas_i2c_[read|write]_u8

commit 21144298 (power: twl6035: add palmas PMIC support)
introduced twl6035_i2c_[read|write]_u8
Then, commit dd23e59d (omap5: pbias ldo9 turn on)
introduced palmas_[read|write]_u8 for precisely the same access
function. TWL6035 belongs to the palmas family, so instead of having
an twl6035 API, we could use an generic palmas API instead.

To stay consistent with the function naming of twl4030,6030 accessors,
we use palmas_i2c_[read|write]_u8

Cc: Balaji T K <balajitk@ti.com>
Cc: Sricharan R <r.sricharan@ti.com>
Reported-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
8 years agopalmas: rename twl6035_mmc1_poweron_ldo with an palmas generic function
Nishanth Menon [Tue, 26 Mar 2013 05:20:56 +0000 (05:20 +0000)]
palmas: rename twl6035_mmc1_poweron_ldo with an palmas generic function

Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_mmc1_poweron_ldo by a more generic palmas_mmc1_poweron_ldo
function.

Signed-off-by: Nishanth Menon <nm@ti.com>
8 years agopalmas: rename init_settings to an generic palmas init
Nishanth Menon [Tue, 26 Mar 2013 05:20:55 +0000 (05:20 +0000)]
palmas: rename init_settings to an generic palmas init

Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_init_settings with an more generic palmas_init_settings

Signed-off-by: Nishanth Menon <nm@ti.com>
8 years agotwl6035: rename to palmas
Nishanth Menon [Tue, 26 Mar 2013 05:20:54 +0000 (05:20 +0000)]
twl6035: rename to palmas

TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs
Rename twl6035 to palmas to allow reuse across multiple current and
future platforms

As part of this change, change the CONFIG_TWL6035_POWER to
CONFIG_PALMAS_POWER and update usage of header file accordingly.

Signed-off-by: Nishanth Menon <nm@ti.com>
8 years agotwl6030: add header guard
Nishanth Menon [Tue, 26 Mar 2013 05:20:53 +0000 (05:20 +0000)]
twl6030: add header guard

Add an header guard to common header file to prevent multiple includes
messing things up.

Signed-off-by: Nishanth Menon <nm@ti.com>
8 years agotwl6030: move twl6030 register access functions to common header file
Nishanth Menon [Tue, 26 Mar 2013 05:20:52 +0000 (05:20 +0000)]
twl6030: move twl6030 register access functions to common header file

twl6030_i2c_[read|write]_u8 can be used else where to access
multi-function device such as twl6030, so move the register access
functions to the common twl6030.h header file.

Signed-off-by: Nishanth Menon <nm@ti.com>
8 years agotwl6030: twl6030_i2c_[read|write]_u8 prototype consistent
Nishanth Menon [Tue, 26 Mar 2013 05:20:51 +0000 (05:20 +0000)]
twl6030: twl6030_i2c_[read|write]_u8 prototype consistent

u-boot standard i2c register access prototype is
i2c_read(addr, reg, 1, &buf, 1)
i2c_reg_write(u8 addr, u8 reg, u8 val)

twl6030_i2c_read_u8(u8 addr, u8 *val, u8 reg)
twl6030_i2c_write_u8(u8 addr, u8 val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl6030_i2c_read_u8(u8 addr, u8 reg, u8 *val)
twl6030_i2c_write_u8(u8 addr, u8 reg, u8 val)

Signed-off-by: Nishanth Menon <nm@ti.com>
8 years agotwl4030: make twl4030_i2c_read_u8 prototype consistent
Nishanth Menon [Tue, 26 Mar 2013 05:20:50 +0000 (05:20 +0000)]
twl4030: make twl4030_i2c_read_u8 prototype consistent

u-boot standard i2c read prototype is
i2c_read(addr, reg, 1, &buf, 1)

twl4030_i2c_read_u8(u8 addr, u8 *val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_read_u8(u8 addr, u8 reg, u8 *val)

Signed-off-by: Nishanth Menon <nm@ti.com>
8 years agotwl4030: make twl4030_i2c_write_u8 prototype consistent
Nishanth Menon [Tue, 26 Mar 2013 05:20:49 +0000 (05:20 +0000)]
twl4030: make twl4030_i2c_write_u8 prototype consistent

u-boot standard i2c register write prototype is
i2c_reg_write(u8 addr, u8 reg, u8 val)

twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val)

Signed-off-by: Nishanth Menon <nm@ti.com>
8 years agoti814x_evm: enable CPSW support
Matt Porter [Wed, 20 Mar 2013 05:38:14 +0000 (05:38 +0000)]
ti814x_evm: enable CPSW support

Adds CPSW support to the TI814X EVM configured with
an ET1011C PHY in GMII mode.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>