1 /* mmx.h
3 MultiMedia eXtensions GCC interface library for IA32.
5 To use this library, simply include this header file
6 and compile with GCC. You MUST have inlining enabled
7 in order for mmx_ok() to work; this can be done by
8 simply using -O on the GCC command line.
10 Compiling with -DMMX_TRACE will cause detailed trace
11 output to be sent to stderr for each mmx operation.
12 This adds lots of code, and obviously slows execution to
13 a crawl, but can be very useful for debugging.
15 THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
16 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
17 LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY
18 AND FITNESS FOR ANY PARTICULAR PURPOSE.
20 1997-98 by H. Dietz and R. Fisher
22 History:
23 97-98* R.Fisher Early versions
24 980501 R.Fisher Original Release
25 980611* H.Dietz Rewrite, correctly implementing inlines, and
26 R.Fisher including direct register accesses.
27 980616 R.Fisher Release of 980611 as 980616.
28 980714 R.Fisher Minor corrections to Makefile, etc.
29 980715 R.Fisher mmx_ok() now prevents optimizer from using
30 clobbered values.
31 mmx_ok() now checks if cpuid instruction is
32 available before trying to use it.
33 980726* R.Fisher mm_support() searches for AMD 3DNow, Cyrix
34 Extended MMX, and standard MMX. It returns a
35 value which is positive if any of these are
36 supported, and can be masked with constants to
37 see which. mmx_ok() is now a call to this
38 980726* R.Fisher Added i2r support for shift functions
39 980919 R.Fisher Fixed AMD extended feature recognition bug.
40 980921 R.Fisher Added definition/check for _MMX_H.
41 Added "float s[2]" to mmx_t for use with
42 3DNow and EMMX. So same mmx_t can be used.
43 981013 R.Fisher Fixed cpuid function 1 bug (looked at wrong reg)
44 Fixed psllq_i2r error in mmxtest.c
46 * Unreleased (internal or interim) versions
48 Notes:
49 It appears that the latest gas has the pand problem fixed, therefore
50 I'll undefine BROKEN_PAND by default.
51 String compares may be quicker than the multiple test/jumps in vendor
52 test sequence in mmx_ok(), but I'm not concerned with that right now.
54 Acknowledgments:
55 Jussi Laako for pointing out the errors ultimately found to be
56 connected to the failure to notify the optimizer of clobbered values.
57 Roger Hardiman for reminding us that CPUID isn't everywhere, and that
58 someone may actually try to use this on a machine without CPUID.
59 Also for suggesting code for checking this.
60 Robert Dale for pointing out the AMD recognition bug.
61 Jimmy Mayfield and Carl Witty for pointing out the Intel recognition
62 bug.
63 Carl Witty for pointing out the psllq_i2r test bug.
64 */
66 #ifndef _MMX_H
67 #define _MMX_H
69 /*#define MMX_TRACE */
71 /* Warning: at this writing, the version of GAS packaged
72 with most Linux distributions does not handle the
73 parallel AND operation mnemonic correctly. If the
74 symbol BROKEN_PAND is defined, a slower alternative
75 coding will be used. If execution of mmxtest results
76 in an illegal instruction fault, define this symbol.
77 */
78 #undef BROKEN_PAND
81 /* The type of an value that fits in an MMX register
82 (note that long long constant values MUST be suffixed
83 by LL and unsigned long long values by ULL, lest
84 they be truncated by the compiler)
85 */
86 typedef union
87 {
88 long long q; /* Quadword (64-bit) value */
89 unsigned long long uq; /* Unsigned Quadword */
90 int d[2]; /* 2 Doubleword (32-bit) values */
91 unsigned int ud[2]; /* 2 Unsigned Doubleword */
92 short w[4]; /* 4 Word (16-bit) values */
93 unsigned short uw[4]; /* 4 Unsigned Word */
94 char b[8]; /* 8 Byte (8-bit) values */
95 unsigned char ub[8]; /* 8 Unsigned Byte */
96 float s[2]; /* Single-precision (32-bit) value */
97 } mmx_t;
101 /* Function to test if multimedia instructions are supported...
102 */
103 inline extern int
104 mm_support (void)
105 {
106 /* Returns 1 if MMX instructions are supported,
107 3 if Cyrix MMX and Extended MMX instructions are supported
108 5 if AMD MMX and 3DNow! instructions are supported
109 0 if hardware does not support any of these
110 */
111 register int rval = 0;
113 __asm__ __volatile__ (
114 /* See if CPUID instruction is supported ... */
115 /* ... Get copies of EFLAGS into eax and ecx */
116 "pushf\n\t" "popl %%eax\n\t" "movl %%eax, %%ecx\n\t"
117 /* ... Toggle the ID bit in one copy and store */
118 /* to the EFLAGS reg */
119 "xorl $0x200000, %%eax\n\t" "push %%eax\n\t" "popf\n\t"
120 /* ... Get the (hopefully modified) EFLAGS */
121 "pushf\n\t" "popl %%eax\n\t"
122 /* ... Compare and test result */
123 "xorl %%eax, %%ecx\n\t" "testl $0x200000, %%ecx\n\t" "jz NotSupported1\n\t" /* Nothing supported */
124 /* Get standard CPUID information, and
125 go to a specific vendor section */
126 "movl $0, %%eax\n\t" "cpuid\n\t"
127 /* Check for Intel */
128 "cmpl $0x756e6547, %%ebx\n\t"
129 "jne TryAMD\n\t"
130 "cmpl $0x49656e69, %%edx\n\t"
131 "jne TryAMD\n\t"
132 "cmpl $0x6c65746e, %%ecx\n" "jne TryAMD\n\t" "jmp Intel\n\t"
133 /* Check for AMD */
134 "\nTryAMD:\n\t"
135 "cmpl $0x68747541, %%ebx\n\t"
136 "jne TryCyrix\n\t"
137 "cmpl $0x69746e65, %%edx\n\t"
138 "jne TryCyrix\n\t"
139 "cmpl $0x444d4163, %%ecx\n" "jne TryCyrix\n\t" "jmp AMD\n\t"
140 /* Check for Cyrix */
141 "\nTryCyrix:\n\t"
142 "cmpl $0x69727943, %%ebx\n\t"
143 "jne NotSupported2\n\t"
144 "cmpl $0x736e4978, %%edx\n\t"
145 "jne NotSupported3\n\t"
146 "cmpl $0x64616574, %%ecx\n\t" "jne NotSupported4\n\t"
147 /* Drop through to Cyrix... */
148 /* Cyrix Section */
149 /* See if extended CPUID is supported */
150 "movl $0x80000000, %%eax\n\t" "cpuid\n\t" "cmpl $0x80000000, %%eax\n\t" "jl MMXtest\n\t" /* Try standard CPUID instead */
151 /* Extended CPUID supported, so get extended features */
152 "movl $0x80000001, %%eax\n\t" "cpuid\n\t" "testl $0x00800000, %%eax\n\t" /* Test for MMX */
153 "jz NotSupported5\n\t" /* MMX not supported */
154 "testl $0x01000000, %%eax\n\t" /* Test for Ext'd MMX */
155 "jnz EMMXSupported\n\t" "movl $1, %0:\n\n\t" /* MMX Supported */
156 "jmp Return\n\n" "EMMXSupported:\n\t" "movl $3, %0:\n\n\t" /* EMMX and MMX Supported */
157 "jmp Return\n\t"
158 /* AMD Section */
159 "AMD:\n\t"
160 /* See if extended CPUID is supported */
161 "movl $0x80000000, %%eax\n\t" "cpuid\n\t" "cmpl $0x80000000, %%eax\n\t" "jl MMXtest\n\t" /* Try standard CPUID instead */
162 /* Extended CPUID supported, so get extended features */
163 "movl $0x80000001, %%eax\n\t" "cpuid\n\t" "testl $0x00800000, %%edx\n\t" /* Test for MMX */
164 "jz NotSupported6\n\t" /* MMX not supported */
165 "testl $0x80000000, %%edx\n\t" /* Test for 3DNow! */
166 "jnz ThreeDNowSupported\n\t" "movl $1, %0:\n\n\t" /* MMX Supported */
167 "jmp Return\n\n" "ThreeDNowSupported:\n\t" "movl $5, %0:\n\n\t" /* 3DNow! and MMX Supported */
168 "jmp Return\n\t"
169 /* Intel Section */
170 "Intel:\n\t"
171 /* Check for MMX */
172 "MMXtest:\n\t" "movl $1, %%eax\n\t" "cpuid\n\t" "testl $0x00800000, %%edx\n\t" /* Test for MMX */
173 "jz NotSupported7\n\t" /* MMX Not supported */
174 "movl $1, %0:\n\n\t" /* MMX Supported */
175 "jmp Return\n\t"
176 /* Nothing supported */
177 "\nNotSupported1:\n\t"
178 "#movl $101, %0:\n\n\t"
179 "\nNotSupported2:\n\t"
180 "#movl $102, %0:\n\n\t"
181 "\nNotSupported3:\n\t"
182 "#movl $103, %0:\n\n\t"
183 "\nNotSupported4:\n\t"
184 "#movl $104, %0:\n\n\t"
185 "\nNotSupported5:\n\t"
186 "#movl $105, %0:\n\n\t"
187 "\nNotSupported6:\n\t"
188 "#movl $106, %0:\n\n\t"
189 "\nNotSupported7:\n\t"
190 "#movl $107, %0:\n\n\t" "movl $0, %0:\n\n\t" "Return:\n\t":"=a" (rval)
191 : /* no input */
192 :"eax", "ebx", "ecx", "edx");
194 /* Return */
195 return (rval);
196 }
198 /* Function to test if mmx instructions are supported...
199 */
200 inline extern int
201 mmx_ok (void)
202 {
203 /* Returns 1 if MMX instructions are supported, 0 otherwise */
204 return (mm_support () & 0x1);
205 }
208 /* Helper functions for the instruction macros that follow...
209 (note that memory-to-register, m2r, instructions are nearly
210 as efficient as register-to-register, r2r, instructions;
211 however, memory-to-memory instructions are really simulated
212 as a convenience, and are only 1/3 as efficient)
213 */
214 #ifdef MMX_TRACE
216 /* Include the stuff for printing a trace to stderr...
217 */
219 #include <stdio.h>
221 #define mmx_i2r(op, imm, reg) \
222 { \
223 mmx_t mmx_trace; \
224 mmx_trace = (imm); \
225 fprintf(stderr, #op "_i2r(" #imm "=0x%016llx, ", mmx_trace.q); \
226 __asm__ __volatile__ ("movq %%" #reg ", %0" \
227 : "=X" (mmx_trace) \
228 : /* nothing */ ); \
229 fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
230 __asm__ __volatile__ (#op " %0, %%" #reg \
231 : /* nothing */ \
232 : "X" (imm)); \
233 __asm__ __volatile__ ("movq %%" #reg ", %0" \
234 : "=X" (mmx_trace) \
235 : /* nothing */ ); \
236 fprintf(stderr, #reg "=0x%016llx\n", mmx_trace.q); \
237 }
239 #define mmx_m2r(op, mem, reg) \
240 { \
241 mmx_t mmx_trace; \
242 mmx_trace = (mem); \
243 fprintf(stderr, #op "_m2r(" #mem "=0x%016llx, ", mmx_trace.q); \
244 __asm__ __volatile__ ("movq %%" #reg ", %0" \
245 : "=X" (mmx_trace) \
246 : /* nothing */ ); \
247 fprintf(stderr, #reg "=0x%016llx) => ", mmx_trace.q); \
248 __asm__ __volatile__ (#op " %0, %%" #reg \
249 : /* nothing */ \
250 : "X" (mem)); \
251 __asm__ __volatile__ ("movq %%" #reg ", %0" \
252 : "=X" (mmx_trace) \
253 : /* nothing */ ); \
254 fprintf(stderr, #reg "=0x%016llx\n", mmx_trace.q); \
255 }
257 #define mmx_r2m(op, reg, mem) \
258 { \
259 mmx_t mmx_trace; \
260 __asm__ __volatile__ ("movq %%" #reg ", %0" \
261 : "=X" (mmx_trace) \
262 : /* nothing */ ); \
263 fprintf(stderr, #op "_r2m(" #reg "=0x%016llx, ", mmx_trace.q); \
264 mmx_trace = (mem); \
265 fprintf(stderr, #mem "=0x%016llx) => ", mmx_trace.q); \
266 __asm__ __volatile__ (#op " %%" #reg ", %0" \
267 : "=X" (mem) \
268 : /* nothing */ ); \
269 mmx_trace = (mem); \
270 fprintf(stderr, #mem "=0x%016llx\n", mmx_trace.q); \
271 }
273 #define mmx_r2r(op, regs, regd) \
274 { \
275 mmx_t mmx_trace; \
276 __asm__ __volatile__ ("movq %%" #regs ", %0" \
277 : "=X" (mmx_trace) \
278 : /* nothing */ ); \
279 fprintf(stderr, #op "_r2r(" #regs "=0x%016llx, ", mmx_trace.q); \
280 __asm__ __volatile__ ("movq %%" #regd ", %0" \
281 : "=X" (mmx_trace) \
282 : /* nothing */ ); \
283 fprintf(stderr, #regd "=0x%016llx) => ", mmx_trace.q); \
284 __asm__ __volatile__ (#op " %" #regs ", %" #regd); \
285 __asm__ __volatile__ ("movq %%" #regd ", %0" \
286 : "=X" (mmx_trace) \
287 : /* nothing */ ); \
288 fprintf(stderr, #regd "=0x%016llx\n", mmx_trace.q); \
289 }
291 #define mmx_m2m(op, mems, memd) \
292 { \
293 mmx_t mmx_trace; \
294 mmx_trace = (mems); \
295 fprintf(stderr, #op "_m2m(" #mems "=0x%016llx, ", mmx_trace.q); \
296 mmx_trace = (memd); \
297 fprintf(stderr, #memd "=0x%016llx) => ", mmx_trace.q); \
298 __asm__ __volatile__ ("movq %0, %%mm0\n\t" \
299 #op " %1, %%mm0\n\t" \
300 "movq %%mm0, %0" \
301 : "=X" (memd) \
302 : "X" (mems)); \
303 mmx_trace = (memd); \
304 fprintf(stderr, #memd "=0x%016llx\n", mmx_trace.q); \
305 }
307 #else
309 /* These macros are a lot simpler without the tracing...
310 */
312 #define mmx_i2r(op, imm, reg) \
313 __asm__ __volatile__ (#op " $" #imm ", %%" #reg \
314 : /* nothing */ \
315 : /* nothing */);
317 #define mmx_m2r(op, mem, reg) \
318 __asm__ __volatile__ (#op " %0, %%" #reg \
319 : /* nothing */ \
320 : "m" (mem))
322 #define mmx_r2m(op, reg, mem) \
323 __asm__ __volatile__ (#op " %%" #reg ", %0" \
324 : "=m" (mem) \
325 : /* nothing */ )
327 #define mmx_r2r(op, regs, regd) \
328 __asm__ __volatile__ (#op " %" #regs ", %" #regd)
330 #define mmx_m2m(op, mems, memd) \
331 __asm__ __volatile__ ("movq %0, %%mm0\n\t" \
332 #op " %1, %%mm0\n\t" \
333 "movq %%mm0, %0" \
334 : "=m" (memd) \
335 : "m" (mems))
337 #endif
340 /* 1x64 MOVe Quadword
341 (this is both a load and a store...
342 in fact, it is the only way to store)
343 */
344 #define movq_m2r(var, reg) mmx_m2r(movq, var, reg)
345 #define movq_r2m(reg, var) mmx_r2m(movq, reg, var)
346 #define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd)
347 #define movq(vars, vard) \
348 __asm__ __volatile__ ("movq %1, %%mm0\n\t" \
349 "movq %%mm0, %0" \
350 : "=X" (vard) \
351 : "X" (vars))
354 /* 1x32 MOVe Doubleword
355 (like movq, this is both load and store...
356 but is most useful for moving things between
357 mmx registers and ordinary registers)
358 */
359 #define movd_m2r(var, reg) mmx_m2r(movd, var, reg)
360 #define movd_r2m(reg, var) mmx_r2m(movd, reg, var)
361 #define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd)
362 #define movd(vars, vard) \
363 __asm__ __volatile__ ("movd %1, %%mm0\n\t" \
364 "movd %%mm0, %0" \
365 : "=X" (vard) \
366 : "X" (vars))
369 /* 2x32, 4x16, and 8x8 Parallel ADDs
370 */
371 #define paddd_m2r(var, reg) mmx_m2r(paddd, var, reg)
372 #define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd)
373 #define paddd(vars, vard) mmx_m2m(paddd, vars, vard)
375 #define paddw_m2r(var, reg) mmx_m2r(paddw, var, reg)
376 #define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd)
377 #define paddw(vars, vard) mmx_m2m(paddw, vars, vard)
379 #define paddb_m2r(var, reg) mmx_m2r(paddb, var, reg)
380 #define paddb_r2r(regs, regd) mmx_r2r(paddb, regs, regd)
381 #define paddb(vars, vard) mmx_m2m(paddb, vars, vard)
384 /* 4x16 and 8x8 Parallel ADDs using Saturation arithmetic
385 */
386 #define paddsw_m2r(var, reg) mmx_m2r(paddsw, var, reg)
387 #define paddsw_r2r(regs, regd) mmx_r2r(paddsw, regs, regd)
388 #define paddsw(vars, vard) mmx_m2m(paddsw, vars, vard)
390 #define paddsb_m2r(var, reg) mmx_m2r(paddsb, var, reg)
391 #define paddsb_r2r(regs, regd) mmx_r2r(paddsb, regs, regd)
392 #define paddsb(vars, vard) mmx_m2m(paddsb, vars, vard)
395 /* 4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic
396 */
397 #define paddusw_m2r(var, reg) mmx_m2r(paddusw, var, reg)
398 #define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd)
399 #define paddusw(vars, vard) mmx_m2m(paddusw, vars, vard)
401 #define paddusb_m2r(var, reg) mmx_m2r(paddusb, var, reg)
402 #define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd)
403 #define paddusb(vars, vard) mmx_m2m(paddusb, vars, vard)
406 /* 2x32, 4x16, and 8x8 Parallel SUBs
407 */
408 #define psubd_m2r(var, reg) mmx_m2r(psubd, var, reg)
409 #define psubd_r2r(regs, regd) mmx_r2r(psubd, regs, regd)
410 #define psubd(vars, vard) mmx_m2m(psubd, vars, vard)
412 #define psubw_m2r(var, reg) mmx_m2r(psubw, var, reg)
413 #define psubw_r2r(regs, regd) mmx_r2r(psubw, regs, regd)
414 #define psubw(vars, vard) mmx_m2m(psubw, vars, vard)
416 #define psubb_m2r(var, reg) mmx_m2r(psubb, var, reg)
417 #define psubb_r2r(regs, regd) mmx_r2r(psubb, regs, regd)
418 #define psubb(vars, vard) mmx_m2m(psubb, vars, vard)
421 /* 4x16 and 8x8 Parallel SUBs using Saturation arithmetic
422 */
423 #define psubsw_m2r(var, reg) mmx_m2r(psubsw, var, reg)
424 #define psubsw_r2r(regs, regd) mmx_r2r(psubsw, regs, regd)
425 #define psubsw(vars, vard) mmx_m2m(psubsw, vars, vard)
427 #define psubsb_m2r(var, reg) mmx_m2r(psubsb, var, reg)
428 #define psubsb_r2r(regs, regd) mmx_r2r(psubsb, regs, regd)
429 #define psubsb(vars, vard) mmx_m2m(psubsb, vars, vard)
432 /* 4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic
433 */
434 #define psubusw_m2r(var, reg) mmx_m2r(psubusw, var, reg)
435 #define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd)
436 #define psubusw(vars, vard) mmx_m2m(psubusw, vars, vard)
438 #define psubusb_m2r(var, reg) mmx_m2r(psubusb, var, reg)
439 #define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd)
440 #define psubusb(vars, vard) mmx_m2m(psubusb, vars, vard)
443 /* 4x16 Parallel MULs giving Low 4x16 portions of results
444 */
445 #define pmullw_m2r(var, reg) mmx_m2r(pmullw, var, reg)
446 #define pmullw_r2r(regs, regd) mmx_r2r(pmullw, regs, regd)
447 #define pmullw(vars, vard) mmx_m2m(pmullw, vars, vard)
450 /* 4x16 Parallel MULs giving High 4x16 portions of results
451 */
452 #define pmulhw_m2r(var, reg) mmx_m2r(pmulhw, var, reg)
453 #define pmulhw_r2r(regs, regd) mmx_r2r(pmulhw, regs, regd)
454 #define pmulhw(vars, vard) mmx_m2m(pmulhw, vars, vard)
457 /* 4x16->2x32 Parallel Mul-ADD
458 (muls like pmullw, then adds adjacent 16-bit fields
459 in the multiply result to make the final 2x32 result)
460 */
461 #define pmaddwd_m2r(var, reg) mmx_m2r(pmaddwd, var, reg)
462 #define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd)
463 #define pmaddwd(vars, vard) mmx_m2m(pmaddwd, vars, vard)
466 /* 1x64 bitwise AND
467 */
468 #ifdef BROKEN_PAND
469 #define pand_m2r(var, reg) \
470 { \
471 mmx_m2r(pandn, (mmx_t) -1LL, reg); \
472 mmx_m2r(pandn, var, reg); \
473 }
474 #define pand_r2r(regs, regd) \
475 { \
476 mmx_m2r(pandn, (mmx_t) -1LL, regd); \
477 mmx_r2r(pandn, regs, regd); \
478 }
479 #define pand(vars, vard) \
480 { \
481 movq_m2r(vard, mm0); \
482 mmx_m2r(pandn, (mmx_t) -1LL, mm0); \
483 mmx_m2r(pandn, vars, mm0); \
484 movq_r2m(mm0, vard); \
485 }
486 #else
487 #define pand_m2r(var, reg) mmx_m2r(pand, var, reg)
488 #define pand_r2r(regs, regd) mmx_r2r(pand, regs, regd)
489 #define pand(vars, vard) mmx_m2m(pand, vars, vard)
490 #endif
493 /* 1x64 bitwise AND with Not the destination
494 */
495 #define pandn_m2r(var, reg) mmx_m2r(pandn, var, reg)
496 #define pandn_r2r(regs, regd) mmx_r2r(pandn, regs, regd)
497 #define pandn(vars, vard) mmx_m2m(pandn, vars, vard)
500 /* 1x64 bitwise OR
501 */
502 #define por_m2r(var, reg) mmx_m2r(por, var, reg)
503 #define por_r2r(regs, regd) mmx_r2r(por, regs, regd)
504 #define por(vars, vard) mmx_m2m(por, vars, vard)
507 /* 1x64 bitwise eXclusive OR
508 */
509 #define pxor_m2r(var, reg) mmx_m2r(pxor, var, reg)
510 #define pxor_r2r(regs, regd) mmx_r2r(pxor, regs, regd)
511 #define pxor(vars, vard) mmx_m2m(pxor, vars, vard)
514 /* 2x32, 4x16, and 8x8 Parallel CoMPare for EQuality
515 (resulting fields are either 0 or -1)
516 */
517 #define pcmpeqd_m2r(var, reg) mmx_m2r(pcmpeqd, var, reg)
518 #define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd)
519 #define pcmpeqd(vars, vard) mmx_m2m(pcmpeqd, vars, vard)
521 #define pcmpeqw_m2r(var, reg) mmx_m2r(pcmpeqw, var, reg)
522 #define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd)
523 #define pcmpeqw(vars, vard) mmx_m2m(pcmpeqw, vars, vard)
525 #define pcmpeqb_m2r(var, reg) mmx_m2r(pcmpeqb, var, reg)
526 #define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd)
527 #define pcmpeqb(vars, vard) mmx_m2m(pcmpeqb, vars, vard)
530 /* 2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than
531 (resulting fields are either 0 or -1)
532 */
533 #define pcmpgtd_m2r(var, reg) mmx_m2r(pcmpgtd, var, reg)
534 #define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd)
535 #define pcmpgtd(vars, vard) mmx_m2m(pcmpgtd, vars, vard)
537 #define pcmpgtw_m2r(var, reg) mmx_m2r(pcmpgtw, var, reg)
538 #define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd)
539 #define pcmpgtw(vars, vard) mmx_m2m(pcmpgtw, vars, vard)
541 #define pcmpgtb_m2r(var, reg) mmx_m2r(pcmpgtb, var, reg)
542 #define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd)
543 #define pcmpgtb(vars, vard) mmx_m2m(pcmpgtb, vars, vard)
546 /* 1x64, 2x32, and 4x16 Parallel Shift Left Logical
547 */
548 #define psllq_i2r(imm, reg) mmx_i2r(psllq, imm, reg)
549 #define psllq_m2r(var, reg) mmx_m2r(psllq, var, reg)
550 #define psllq_r2r(regs, regd) mmx_r2r(psllq, regs, regd)
551 #define psllq(vars, vard) mmx_m2m(psllq, vars, vard)
553 #define pslld_i2r(imm, reg) mmx_i2r(pslld, imm, reg)
554 #define pslld_m2r(var, reg) mmx_m2r(pslld, var, reg)
555 #define pslld_r2r(regs, regd) mmx_r2r(pslld, regs, regd)
556 #define pslld(vars, vard) mmx_m2m(pslld, vars, vard)
558 #define psllw_i2r(imm, reg) mmx_i2r(psllw, imm, reg)
559 #define psllw_m2r(var, reg) mmx_m2r(psllw, var, reg)
560 #define psllw_r2r(regs, regd) mmx_r2r(psllw, regs, regd)
561 #define psllw(vars, vard) mmx_m2m(psllw, vars, vard)
564 /* 1x64, 2x32, and 4x16 Parallel Shift Right Logical
565 */
566 #define psrlq_i2r(imm, reg) mmx_i2r(psrlq, imm, reg)
567 #define psrlq_m2r(var, reg) mmx_m2r(psrlq, var, reg)
568 #define psrlq_r2r(regs, regd) mmx_r2r(psrlq, regs, regd)
569 #define psrlq(vars, vard) mmx_m2m(psrlq, vars, vard)
571 #define psrld_i2r(imm, reg) mmx_i2r(psrld, imm, reg)
572 #define psrld_m2r(var, reg) mmx_m2r(psrld, var, reg)
573 #define psrld_r2r(regs, regd) mmx_r2r(psrld, regs, regd)
574 #define psrld(vars, vard) mmx_m2m(psrld, vars, vard)
576 #define psrlw_i2r(imm, reg) mmx_i2r(psrlw, imm, reg)
577 #define psrlw_m2r(var, reg) mmx_m2r(psrlw, var, reg)
578 #define psrlw_r2r(regs, regd) mmx_r2r(psrlw, regs, regd)
579 #define psrlw(vars, vard) mmx_m2m(psrlw, vars, vard)
582 /* 2x32 and 4x16 Parallel Shift Right Arithmetic
583 */
584 #define psrad_i2r(imm, reg) mmx_i2r(psrad, imm, reg)
585 #define psrad_m2r(var, reg) mmx_m2r(psrad, var, reg)
586 #define psrad_r2r(regs, regd) mmx_r2r(psrad, regs, regd)
587 #define psrad(vars, vard) mmx_m2m(psrad, vars, vard)
589 #define psraw_i2r(imm, reg) mmx_i2r(psraw, imm, reg)
590 #define psraw_m2r(var, reg) mmx_m2r(psraw, var, reg)
591 #define psraw_r2r(regs, regd) mmx_r2r(psraw, regs, regd)
592 #define psraw(vars, vard) mmx_m2m(psraw, vars, vard)
595 /* 2x32->4x16 and 4x16->8x8 PACK and Signed Saturate
596 (packs source and dest fields into dest in that order)
597 */
598 #define packssdw_m2r(var, reg) mmx_m2r(packssdw, var, reg)
599 #define packssdw_r2r(regs, regd) mmx_r2r(packssdw, regs, regd)
600 #define packssdw(vars, vard) mmx_m2m(packssdw, vars, vard)
602 #define packsswb_m2r(var, reg) mmx_m2r(packsswb, var, reg)
603 #define packsswb_r2r(regs, regd) mmx_r2r(packsswb, regs, regd)
604 #define packsswb(vars, vard) mmx_m2m(packsswb, vars, vard)
607 /* 4x16->8x8 PACK and Unsigned Saturate
608 (packs source and dest fields into dest in that order)
609 */
610 #define packuswb_m2r(var, reg) mmx_m2r(packuswb, var, reg)
611 #define packuswb_r2r(regs, regd) mmx_r2r(packuswb, regs, regd)
612 #define packuswb(vars, vard) mmx_m2m(packuswb, vars, vard)
615 /* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low
616 (interleaves low half of dest with low half of source
617 as padding in each result field)
618 */
619 #define punpckldq_m2r(var, reg) mmx_m2r(punpckldq, var, reg)
620 #define punpckldq_r2r(regs, regd) mmx_r2r(punpckldq, regs, regd)
621 #define punpckldq(vars, vard) mmx_m2m(punpckldq, vars, vard)
623 #define punpcklwd_m2r(var, reg) mmx_m2r(punpcklwd, var, reg)
624 #define punpcklwd_r2r(regs, regd) mmx_r2r(punpcklwd, regs, regd)
625 #define punpcklwd(vars, vard) mmx_m2m(punpcklwd, vars, vard)
627 #define punpcklbw_m2r(var, reg) mmx_m2r(punpcklbw, var, reg)
628 #define punpcklbw_r2r(regs, regd) mmx_r2r(punpcklbw, regs, regd)
629 #define punpcklbw(vars, vard) mmx_m2m(punpcklbw, vars, vard)
632 /* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High
633 (interleaves high half of dest with high half of source
634 as padding in each result field)
635 */
636 #define punpckhdq_m2r(var, reg) mmx_m2r(punpckhdq, var, reg)
637 #define punpckhdq_r2r(regs, regd) mmx_r2r(punpckhdq, regs, regd)
638 #define punpckhdq(vars, vard) mmx_m2m(punpckhdq, vars, vard)
640 #define punpckhwd_m2r(var, reg) mmx_m2r(punpckhwd, var, reg)
641 #define punpckhwd_r2r(regs, regd) mmx_r2r(punpckhwd, regs, regd)
642 #define punpckhwd(vars, vard) mmx_m2m(punpckhwd, vars, vard)
644 #define punpckhbw_m2r(var, reg) mmx_m2r(punpckhbw, var, reg)
645 #define punpckhbw_r2r(regs, regd) mmx_r2r(punpckhbw, regs, regd)
646 #define punpckhbw(vars, vard) mmx_m2m(punpckhbw, vars, vard)
649 /* Empty MMx State
650 (used to clean-up when going from mmx to float use
651 of the registers that are shared by both; note that
652 there is no float-to-mmx operation needed, because
653 only the float tag word info is corruptible)
654 */
655 #ifdef MMX_TRACE
657 #define emms() \
658 { \
659 fprintf(stderr, "emms()\n"); \
660 __asm__ __volatile__ ("emms"); \
661 }
663 #else
665 #define emms() __asm__ __volatile__ ("emms")
667 #endif
669 #endif