RM-autogen.py: Add support for am65x SoC
authorNikhil Devshatwar <nikhil.nd@ti.com>
Thu, 27 Feb 2020 13:30:26 +0000 (19:00 +0530)
committerNikhil Devshatwar <nikhil.nd@ti.com>
Thu, 27 Feb 2020 13:59:59 +0000 (19:29 +0530)
Add an argument to select the soc.
Based on the soc, import the required module which contains
all the macros required for sorting.

Also add the j721e and am65x modules.

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
.gitignore [new file with mode: 0644]
respart/RM-autogen.py
respart/am65x.py [new file with mode: 0644]
respart/j721e.py [new file with mode: 0644]

diff --git a/.gitignore b/.gitignore
new file mode 100644 (file)
index 0000000..5b2bb22
--- /dev/null
@@ -0,0 +1,2 @@
+.gitignore
+*.pyc
index 00b33347c9ac6a416e77ce6afe9bd5e0ccc1471e..dbe8fe01f47ed17e730f15f8761587087df4a207 100755 (executable)
@@ -102,15 +102,19 @@ def print_rmcfg(rmcfg):
 parser = argparse.ArgumentParser(prog='RM-autogen.py', formatter_class=argparse.RawTextHelpFormatter,
        description='RM-autogen.py - Auto generate the Resource Management data')
 
-parser.add_argument('-f', '--format', required=True, dest='format',
-       action='store', choices=["boardconfig", "rtos_rmcfg", "jailhouse_cell_config"],
-       help='format to select the output file')
+parser.add_argument('-s', '--soc', required=True, dest='soc',
+       action='store', choices=['j721e', 'am65x'],
+       help='Share resource with HOST_ID_A for HOST_ID_B')
 
 parser.add_argument('-o', '--output', required=True, dest='output',
        action='store',
        help='output file name')
 
-parser.add_argument('-s', '--share', dest='share', default=[],
+parser.add_argument('-f', '--format', required=True, dest='format',
+       action='store', choices=['boardconfig', 'jailhouse_cell_config'],
+       help='format to select the output file')
+
+parser.add_argument('--share', dest='share', default=[],
        action='append', nargs=2, metavar=('HOST_ID_A', 'HOST_ID_B'),
        help='Share resource with HOST_ID_A for HOST_ID_B')
 
@@ -119,8 +123,9 @@ parser.add_argument('workbook', help='Input excel sheet with assigned resources'
 args = parser.parse_args()
 print(args)
 
+soc = __import__(args.soc)
 workbook = xlrd.open_workbook(args.workbook)
-sheet = workbook.sheet_by_index(0)
+sheet = workbook.sheet_by_name(args.soc)
 
 #sheet.nrows = 9
 if (args.format == 'boardconfig'):
diff --git a/respart/am65x.py b/respart/am65x.py
new file mode 100644 (file)
index 0000000..17c7b12
--- /dev/null
@@ -0,0 +1,364 @@
+'''
+Generated from the SYSFW headers
+cat include/soc/am65x/devices.h | grep "#define AM6_DEV" | awk -F"[ ()]*" '{print "\""$2"\" : "$3","}'
+cat include/soc/am65x/resasg_types.h | grep "#define RESASG_SUBTYPE" | awk -F"[ ()]*" '{print "\""$2"\" : " substr($3, 1, length($3)-1)","}'
+cat include/soc/am65x/hosts.h | grep "#define HOST_ID" | awk -F"[ ()]*" '{print "\""$2"\" : " substr($3, 1, length($3)-1)","}'
+'''
+
+
+RESASG_TYPE_SHIFT = 6
+RESASG_SUBTYPE_SHIFT = 0
+
+const_values = {
+"AM6_DEV_DCC4" : 13,
+"AM6_DEV_DCC6" : 15,
+"AM6_DEV_DCC0" : 9,
+"AM6_DEV_MCU_DCC2" : 19,
+"AM6_DEV_DCC5" : 14,
+"AM6_DEV_MCU_DCC0" : 17,
+"AM6_DEV_MCU_DCC1" : 18,
+"AM6_DEV_DCC1" : 10,
+"AM6_DEV_DCC3" : 12,
+"AM6_DEV_DCC7" : 16,
+"AM6_DEV_DCC2" : 11,
+"AM6_DEV_MCU_I2C0" : 114,
+"AM6_DEV_I2C3" : 113,
+"AM6_DEV_I2C2" : 112,
+"AM6_DEV_WKUP_I2C0" : 115,
+"AM6_DEV_I2C0" : 110,
+"AM6_DEV_I2C1" : 111,
+"AM6_DEV_TIMER5" : 30,
+"AM6_DEV_TIMER6" : 31,
+"AM6_DEV_TIMER7" : 32,
+"AM6_DEV_MCU_TIMER0" : 35,
+"AM6_DEV_TIMER8" : 33,
+"AM6_DEV_TIMER2" : 27,
+"AM6_DEV_MCU_TIMER1" : 36,
+"AM6_DEV_MCU_TIMER2" : 37,
+"AM6_DEV_TIMER4" : 29,
+"AM6_DEV_TIMER3" : 28,
+"AM6_DEV_TIMER9" : 34,
+"AM6_DEV_TIMER11" : 26,
+"AM6_DEV_TIMER10" : 25,
+"AM6_DEV_TIMER0" : 23,
+"AM6_DEV_MCU_TIMER3" : 38,
+"AM6_DEV_TIMER1" : 24,
+"AM6_DEV_WKUP_PSC0" : 79,
+"AM6_DEV_CBASS0" : 82,
+"AM6_DEV_PLL_MMR0" : 101,
+"AM6_DEV_MCU_CPT2_AGGR0" : 7,
+"AM6_DEV_CPT2_AGGR0" : 6,
+"AM6_DEV_DEBUGSS0" : 68,
+"AM6_DEV_EHRPWM4" : 44,
+"AM6_DEV_EHRPWM1" : 41,
+"AM6_DEV_EHRPWM0" : 40,
+"AM6_DEV_EHRPWM3" : 43,
+"AM6_DEV_EHRPWM5" : 45,
+"AM6_DEV_EHRPWM2" : 42,
+"AM6_DEV_ELM0" : 46,
+"AM6_DEV_MCU_UART0" : 149,
+"AM6_DEV_WKUP_UART0" : 150,
+"AM6_DEV_UART1" : 147,
+"AM6_DEV_UART0" : 146,
+"AM6_DEV_UART2" : 148,
+"AM6_DEV_SA2_UL0" : 136,
+"AM6_DEV_CAL0" : 2,
+"AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMLO_4" : 206,
+"AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S1_3" : 207,
+"AM6_DEV_CPT2_PROBE_VBUSM_MCU_EXPORT_SLV_0" : 208,
+"AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVSRAMHI_3" : 209,
+"AM6_DEV_CPT2_PROBE_VBUSM_MCU_SRAM_SLV_1" : 210,
+"AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRHI_5" : 211,
+"AM6_DEV_CPT2_PROBE_VBUSM_MAIN_NAVDDRLO_6" : 212,
+"AM6_DEV_CPT2_PROBE_VBUSM_MAIN_CAL0_0" : 213,
+"AM6_DEV_CPT2_PROBE_VBUSM_MAIN_DSS_2" : 214,
+"AM6_DEV_CPT2_PROBE_VBUSM_MCU_FSS_S0_2" : 215,
+"AM6_DEV_PBIST0" : 73,
+"AM6_DEV_PBIST1" : 74,
+"AM6_DEV_MCU_PBIST0" : 75,
+"AM6_DEV_NAVSS0" : 118,
+"AM6_DEV_DSS0" : 67,
+"AM6_DEV_GPMC0" : 60,
+"AM6_DEV_MMCSD1" : 48,
+"AM6_DEV_WKUP_PLLCTRL0" : 77,
+"AM6_DEV_PLLCTRL0" : 76,
+"AM6_DEV_USB3SS1" : 152,
+"AM6_DEV_USB3SS0" : 151,
+"AM6_DEV_MCU_MCSPI0" : 142,
+"AM6_DEV_MCSPI2" : 139,
+"AM6_DEV_MCU_MCSPI2" : 144,
+"AM6_DEV_MCSPI0" : 137,
+"AM6_DEV_MCSPI1" : 138,
+"AM6_DEV_MCSPI4" : 141,
+"AM6_DEV_MCSPI3" : 140,
+"AM6_DEV_MCU_MCSPI1" : 143,
+"AM6_DEV_DEBUGSS_WRAP0" : 21,
+"AM6_DEV_CBASS_INFRA0" : 85,
+"AM6_DEV_STM0" : 8,
+"AM6_DEV_MCU_RTI1" : 135,
+"AM6_DEV_RTI0" : 130,
+"AM6_DEV_RTI3" : 133,
+"AM6_DEV_RTI1" : 131,
+"AM6_DEV_MCU_RTI0" : 134,
+"AM6_DEV_RTI2" : 132,
+"AM6_DEV_PSRAMECC0" : 128,
+"AM6_DEV_EFUSE0" : 69,
+"AM6_DEV_MCASP0" : 104,
+"AM6_DEV_MCASP1" : 105,
+"AM6_DEV_MCASP2" : 106,
+"AM6_DEV_MCU_ARMSS0" : 129,
+"AM6_DEV_MCU_ARMSS0_CPU0" : 159,
+"AM6_DEV_MCU_ARMSS0_CPU1" : 245,
+"AM6_DEV_CCDEBUGSS0" : 66,
+"AM6_DEV_WKUP_CTRL_MMR0" : 155,
+"AM6_DEV_MCU_CBASS_FW0" : 91,
+"AM6_DEV_MCU_CPSW0" : 5,
+"AM6_DEV_SERDES0" : 153,
+"AM6_DEV_SERDES1" : 154,
+"AM6_DEV_OLDI_TX_CORE_MAIN_0" : 216,
+"AM6_DEV_MCU_ADC1" : 1,
+"AM6_DEV_MCU_ADC0" : 0,
+"AM6_DEV_WKUP_DMSC0" : 22,
+"AM6_DEV_MCU_PLL_MMR0" : 108,
+"AM6_DEV_MCU_SEC_MMR0" : 109,
+"AM6_DEV_GIC0" : 56,
+"AM6_DEV_MCU_DEBUGSS0" : 71,
+"AM6_DEV_EQEP0" : 49,
+"AM6_DEV_EQEP2" : 51,
+"AM6_DEV_EQEP1" : 50,
+"AM6_DEV_WKUP_GPIO0" : 59,
+"AM6_DEV_GPIO0" : 57,
+"AM6_DEV_GPIO1" : 58,
+"AM6_DEV_COMPUTE_CLUSTER_MSMC0" : 196,
+"AM6_DEV_COMPUTE_CLUSTER_PBIST0" : 197,
+"AM6_DEV_COMPUTE_CLUSTER_CPAC0" : 198,
+"AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST0" : 199,
+"AM6_DEV_COMPUTE_CLUSTER_CPAC1" : 200,
+"AM6_DEV_COMPUTE_CLUSTER_CPAC_PBIST1" : 201,
+"AM6_DEV_COMPUTE_CLUSTER_A53_0" : 202,
+"AM6_DEV_COMPUTE_CLUSTER_A53_1" : 203,
+"AM6_DEV_COMPUTE_CLUSTER_A53_2" : 204,
+"AM6_DEV_COMPUTE_CLUSTER_A53_3" : 205,
+"AM6_DEV_WKUP_CBASS0" : 94,
+"AM6_DEV_MCU_ROM0" : 78,
+"AM6_DEV_K3_ARM_ATB_FUNNEL_3_32_MCU_0" : 217,
+"AM6_DEV_ESM0" : 52,
+"AM6_DEV_PRU_ICSSG2" : 64,
+"AM6_DEV_PRU_ICSSG0" : 62,
+"AM6_DEV_PRU_ICSSG1" : 63,
+"AM6_DEV_MCU_ESM0" : 53,
+"AM6_DEV_ECAP0" : 39,
+"AM6_DEV_WKUP_ESM0" : 54,
+"AM6_DEV_MCU_EFUSE0" : 72,
+"AM6_DEV_MCU_CTRL_MMR0" : 107,
+"AM6_DEV_PSC0" : 70,
+"AM6_DEV_CTRL_MMR0" : 99,
+"AM6_DEV_MCU_MCAN0" : 102,
+"AM6_DEV_MCU_MCAN1" : 103,
+"AM6_DEV_DDRSS0" : 20,
+"AM6_DEV_MCU_NAVSS0" : 119,
+"AM6_DEV_MCU_FSS0" : 55,
+"AM6_DEV_DFTSS0" : 117,
+"AM6_DEV_WKUP_GPIOMUX_INTRTR0" : 156,
+"AM6_DEV_GPIOMUX_INTRTR0" : 100,
+"AM6_DEV_MAIN2MCU_LVL_INTRTR0" : 97,
+"AM6_DEV_MAIN2MCU_PLS_INTRTR0" : 98,
+"AM6_DEV_ICEMELTER_WKUP_0" : 218,
+"AM6_DEV_GPU0" : 65,
+"AM6_DEV_PDMA_DEBUG0" : 122,
+"AM6_DEV_PDMA0" : 123,
+"AM6_DEV_PDMA1" : 124,
+"AM6_DEV_MCU_PDMA0" : 125,
+"AM6_DEV_MCU_PDMA1" : 126,
+"AM6_DEV_MCU_MSRAM0" : 116,
+"AM6_DEV_CMPEVENT_INTRTR0" : 3,
+"AM6_DEV_DEBUGSUSPENDRTR0" : 81,
+"AM6_DEV_TIMESYNC_INTRTR0" : 145,
+"AM6_DEV_CBASS_DEBUG0" : 83,
+"AM6_DEV_CBASS_FW0" : 84,
+"AM6_DEV_MCU_CBASS_DEBUG0" : 90,
+"AM6_DEV_WKUP_CBASS_FW0" : 96,
+"AM6_DEV_PCIE0" : 120,
+"AM6_DEV_PCIE1" : 121,
+"AM6_DEV_GTC0" : 61,
+"AM6_DEV_K3_LED_MAIN_0" : 219,
+"AM6_DEV_WKUP_VTM0" : 80,
+"AM6_DEV_MMCSD0" : 47,
+"AM6_DEV_MCU_ECC_AGGR0" : 92,
+"AM6_DEV_ECC_AGGR1" : 87,
+"AM6_DEV_ECC_AGGR2" : 88,
+"AM6_DEV_MCU_ECC_AGGR1" : 93,
+"AM6_DEV_WKUP_ECC_AGGR0" : 95,
+"AM6_DEV_VDC_DATA_VBUSM_32B_REF_WKUP2MCU" : 220,
+"AM6_DEV_VDC_DATA_VBUSM_32B_REF_MCU2WKUP" : 221,
+"AM6_DEV_VDC_DATA_VBUSM_64B_REF_MAIN2MCU" : 222,
+"AM6_DEV_VDC_DATA_VBUSM_64B_REF_MCU2MAIN" : 223,
+"AM6_DEV_VDC_DMSC_DBG_VBUSP_32B_REF_DBG2DMSC" : 224,
+"AM6_DEV_VDC_INFRA_VBUSP_32B_REF_WKUP2MAIN_INFRA" : 225,
+"AM6_DEV_VDC_INFRA_VBUSP_32B_REF_MCU2MAIN_INFRA" : 226,
+"AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWWKUP2MCU" : 227,
+"AM6_DEV_VDC_SOC_FW_VBUSP_32B_REF_FWMCU2MAIN" : 228,
+"AM6_DEV_VDC_MCU_DBG_VBUSP_32B_REF_DBGMAIN2MCU" : 229,
+"AM6_DEV_ECC_AGGR0" : 86,
+"AM6_DEV_VDC_NAV_PSIL_128B_REF_MAIN2MCU" : 230,
+"AM6_DEV_MCU_PSRAM0" : 127,
+"AM6_DEV_GS80PRG_SOC_WRAP_WKUP_0" : 231,
+"AM6_DEV_GS80PRG_MCU_WRAP_WKUP_0" : 232,
+"AM6_DEV_MCU_CBASS0" : 89,
+"AM6_DEV_MX_WAKEUP_RESET_SYNC_WKUP_0" : 233,
+"AM6_DEV_MX_EFUSE_MAIN_CHAIN_MAIN_0" : 234,
+"AM6_DEV_MX_EFUSE_MCU_CHAIN_MCU_0" : 235,
+"AM6_DEV_DUMMY_IP_LPSC_WKUP2MCU" : 236,
+"AM6_DEV_DUMMY_IP_LPSC_WKUP2MAIN_INFRA" : 237,
+"AM6_DEV_DUMMY_IP_LPSC_DEBUG2DMSC" : 238,
+"AM6_DEV_DUMMY_IP_LPSC_DMSC" : 239,
+"AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN_INFRA" : 240,
+"AM6_DEV_DUMMY_IP_LPSC_MCU2MAIN" : 241,
+"AM6_DEV_DUMMY_IP_LPSC_MCU2WKUP" : 242,
+"AM6_DEV_DUMMY_IP_LPSC_MAIN2MCU" : 243,
+"AM6_DEV_DUMMY_IP_LPSC_EMIF_DATA" : 244,
+"AM6_DEV_BOARD0" : 157,
+"AM6_DEV_WKUP_DMSC0_CORTEX_M3_0" : 161,
+"AM6_DEV_WKUP_DMSC0_INTR_AGGR_0" : 162,
+"AM6_DEV_NAVSS0_CPTS0" : 163,
+"AM6_DEV_NAVSS0_INTR_ROUTER_0" : 182,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0" : 164,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1" : 165,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2" : 166,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3" : 167,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4" : 168,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5" : 169,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6" : 170,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7" : 171,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8" : 172,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9" : 173,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10" : 174,
+"AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11" : 175,
+"AM6_DEV_NAVSS0_MCRC0" : 176,
+"AM6_DEV_NAVSS0_MODSS_INTA0" : 180,
+"AM6_DEV_NAVSS0_MODSS_INTA1" : 181,
+"AM6_DEV_NAVSS0_PROXY0" : 185,
+"AM6_DEV_NAVSS0_PVU0" : 177,
+"AM6_DEV_NAVSS0_PVU1" : 178,
+"AM6_DEV_NAVSS0_RINGACC0" : 187,
+"AM6_DEV_NAVSS0_SEC_PROXY0" : 186,
+"AM6_DEV_NAVSS0_TIMER_MGR0" : 183,
+"AM6_DEV_NAVSS0_TIMER_MGR1" : 184,
+"AM6_DEV_NAVSS0_UDMAP0" : 188,
+"AM6_DEV_NAVSS0_UDMASS_INTA0" : 179,
+"AM6_DEV_MCU_NAVSS0_INTR_AGGR_0" : 189,
+"AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0" : 190,
+"AM6_DEV_MCU_NAVSS0_MCRC0" : 193,
+"AM6_DEV_MCU_NAVSS0_PROXY0" : 191,
+"AM6_DEV_MCU_NAVSS0_RINGACC0" : 195,
+"AM6_DEV_MCU_NAVSS0_SEC_PROXY0" : 192,
+"AM6_DEV_MCU_NAVSS0_UDMAP0" : 194,
+
+"RESASG_SUBTYPE_SHIFT" : 0x0000,
+"RESASG_SUBTYPE_MASK" : 0x003F,
+"RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT" : 0x00,
+"RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI" : 0x01,
+"RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI" : 0x02,
+"RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI" : 0x03,
+"RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_CNT" : 0x04,
+"RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT" : 0x00,
+"RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI" : 0x01,
+"RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_CNT" : 0x02,
+"RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT" : 0x00,
+"RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI" : 0x01,
+"RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_CNT" : 0x02,
+"RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT" : 0x00,
+"RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI" : 0x01,
+"RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI" : 0x02,
+"RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI" : 0x03,
+"RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_CNT" : 0x04,
+"RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI" : 0x00,
+"RESASG_SUBTYPE_MAIN_NAV_MCRC_CNT" : 0x01,
+"RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI" : 0x00,
+"RESASG_SUBTYPE_MCU_NAV_MCRC_CNT" : 0x01,
+"RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER" : 0x00,
+"RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN" : 0x01,
+"RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN" : 0x02,
+"RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN" : 0x03,
+"RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN" : 0x04,
+"RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN" : 0x05,
+"RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON" : 0x06,
+"RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES" : 0x07,
+"RESASG_SUBTYPE_MAIN_NAV_UDMAP_GCFG" : 0x08,
+"RESASG_SUBTYPE_MAIN_NAV_UDMAP_CNT" : 0x09,
+"RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER" : 0x00,
+"RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN" : 0x01,
+"RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN" : 0x02,
+"RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN" : 0x03,
+"RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN" : 0x04,
+"RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON" : 0x05,
+"RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES" : 0x06,
+"RESASG_SUBTYPE_MCU_NAV_UDMAP_GCFG" : 0x07,
+"RESASG_SUBTYPE_MCU_NAV_UDMAP_CNT" : 0x08,
+"RESASG_SUBTYPE_MSMC_DRU" : 0x00,
+"RESASG_SUBTYPE_MSMC_CNT" : 0x01,
+"RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX" : 0x00,
+"RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX" : 0x01,
+"RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP" : 0x02,
+"RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES" : 0x03,
+"RESASG_SUBTYPE_MAIN_NAV_RA_VIRTID" : 0x04,
+"RESASG_SUBTYPE_MAIN_NAV_RA_MONITOR" : 0x05,
+"RESASG_SUBTYPE_MAIN_NAV_RA_CNT" : 0x06,
+"RESASG_SUBTYPE_MAIN_NAV_PROXY_PROXIES" : 0x00,
+"RESASG_SUBTYPE_MAIN_NAV_PROXY_CNT" : 0x01,
+"RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX" : 0x00,
+"RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX" : 0x01,
+"RESASG_SUBTYPE_MCU_NAV_RA_RING_GP" : 0x02,
+"RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES" : 0x03,
+"RESASG_SUBTYPE_MCU_NAV_RA_VIRTID" : 0x04,
+"RESASG_SUBTYPE_MCU_NAV_RA_MONITOR" : 0x05,
+"RESASG_SUBTYPE_MCU_NAV_RA_CNT" : 0x06,
+"RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0" : 0x00,
+"RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO" : 0x01,
+"RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1" : 0x02,
+"RESASG_SUBTYPE_GIC_IRQ_COMP_EVT" : 0x03,
+"RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO" : 0x04,
+"RESASG_SUBTYPE_GIC_IRQ_CNT" : 0x05,
+"RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV" : 0x00,
+"RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO" : 0x01,
+"RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL" : 0x02,
+"RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS" : 0x03,
+"RESASG_SUBTYPE_PULSAR_C0_IRQ_CNT" : 0x04,
+"RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV" : 0x00,
+"RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO" : 0x01,
+"RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL" : 0x02,
+"RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS" : 0x03,
+"RESASG_SUBTYPE_PULSAR_C1_IRQ_CNT" : 0x04,
+"RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV" : 0x00,
+"RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO" : 0x01,
+"RESASG_SUBTYPE_ICSSG0_IRQ_CNT" : 0x02,
+"RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV" : 0x00,
+"RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO" : 0x01,
+"RESASG_SUBTYPE_ICSSG1_IRQ_CNT" : 0x02,
+"RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV" : 0x00,
+"RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO" : 0x01,
+"RESASG_SUBTYPE_ICSSG2_IRQ_CNT" : 0x02,
+"RESASG_SUBTYPE_MCU_NAV_PROXY_PROXIES" : 0x00,
+"RESASG_SUBTYPE_MCU_NAV_PROXY_CNT" : 0x01,
+
+"HOST_ID_DMSC" : 0,
+"HOST_ID_R5_0" : 3,
+"HOST_ID_R5_1" : 4,
+"HOST_ID_R5_2" : 5,
+"HOST_ID_R5_3" : 6,
+"HOST_ID_A53_0" : 10,
+"HOST_ID_A53_1" : 11,
+"HOST_ID_A53_2" : 12,
+"HOST_ID_A53_3" : 13,
+"HOST_ID_A53_4" : 14,
+"HOST_ID_A53_5" : 15,
+"HOST_ID_A53_6" : 16,
+"HOST_ID_A53_7" : 17,
+"HOST_ID_GPU_0" : 30,
+"HOST_ID_GPU_1" : 31,
+"HOST_ID_ICSSG_0" : 50,
+"HOST_ID_ICSSG_1" : 51,
+"HOST_ID_ICSSG_2" : 52,
+"HOST_ID_ALL" : 128,
+"HOST_ID_CNT" : 19,
+}
diff --git a/respart/j721e.py b/respart/j721e.py
new file mode 100644 (file)
index 0000000..e8492b9
--- /dev/null
@@ -0,0 +1,465 @@
+'''
+Generated from the SYSFW headers
+cat include/soc/j721e/devices.h | grep "#define J721E_DEV" | awk -F"[ ()]*" '{print "\""$2"\" : "$3","}'
+cat include/soc/j721e/resasg_types.h | grep "#define RESASG_SUBTYPE" | awk -F"[ ()]*" '{print "\""$2"\" : " substr($3, 1, length($3)-1)","}'
+cat include/soc/j721e/hosts.h | grep "#define HOST_ID" | awk -F"[ ()]*" '{print "\""$2"\" : " substr($3, 1, length($3)-1)","}'
+'''
+
+
+RESASG_TYPE_SHIFT = 6
+RESASG_SUBTYPE_SHIFT = 0
+
+const_values = {
+"J721E_DEV_MCU_ADC0" : 0,
+"J721E_DEV_MCU_ADC1" : 1,
+"J721E_DEV_ATL0" : 2,
+"J721E_DEV_COMPUTE_CLUSTER_J7ES_TB_VDC_MAIN_0" : 3,
+"J721E_DEV_A72SS0" : 4,
+"J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP" : 5,
+"J721E_DEV_COMPUTE_CLUSTER0_CLEC" : 6,
+"J721E_DEV_COMPUTE_CLUSTER0_CORE_CORE" : 7,
+"J721E_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW" : 8,
+"J721E_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP" : 9,
+"J721E_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH0" : 10,
+"J721E_DEV_COMPUTE_CLUSTER0_DIVP_TFT0" : 11,
+"J721E_DEV_COMPUTE_CLUSTER0_DMSC_WRAP" : 12,
+"J721E_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN" : 13,
+"J721E_DEV_COMPUTE_CLUSTER0_GIC500SS" : 14,
+"J721E_DEV_C71SS0" : 15,
+"J721E_DEV_C71SS0_MMA" : 16,
+"J721E_DEV_COMPUTE_CLUSTER0_PBIST_WRAP" : 17,
+"J721E_DEV_MCU_CPSW0" : 18,
+"J721E_DEV_CPSW0" : 19,
+"J721E_DEV_CPT2_AGGR0" : 20,
+"J721E_DEV_CPT2_AGGR1" : 21,
+"J721E_DEV_DMSC_WKUP_0" : 22,
+"J721E_DEV_CPT2_AGGR2" : 23,
+"J721E_DEV_MCU_CPT2_AGGR0" : 24,
+"J721E_DEV_CSI_PSILSS0" : 25,
+"J721E_DEV_CSI_RX_IF0" : 26,
+"J721E_DEV_CSI_RX_IF1" : 27,
+"J721E_DEV_CSI_TX_IF0" : 28,
+"J721E_DEV_STM0" : 29,
+"J721E_DEV_DCC0" : 30,
+"J721E_DEV_DCC1" : 31,
+"J721E_DEV_DCC2" : 32,
+"J721E_DEV_DCC3" : 33,
+"J721E_DEV_DCC4" : 34,
+"J721E_DEV_MCU_TIMER0" : 35,
+"J721E_DEV_DCC5" : 36,
+"J721E_DEV_DCC6" : 37,
+"J721E_DEV_DCC7" : 38,
+"J721E_DEV_DCC8" : 39,
+"J721E_DEV_DCC9" : 40,
+"J721E_DEV_DCC10" : 41,
+"J721E_DEV_DCC11" : 42,
+"J721E_DEV_DCC12" : 43,
+"J721E_DEV_MCU_DCC0" : 44,
+"J721E_DEV_MCU_DCC1" : 45,
+"J721E_DEV_MCU_DCC2" : 46,
+"J721E_DEV_DDR0" : 47,
+"J721E_DEV_DMPAC_TOP_MAIN_0" : 48,
+"J721E_DEV_TIMER0" : 49,
+"J721E_DEV_TIMER1" : 50,
+"J721E_DEV_TIMER2" : 51,
+"J721E_DEV_TIMER3" : 52,
+"J721E_DEV_TIMER4" : 53,
+"J721E_DEV_TIMER5" : 54,
+"J721E_DEV_TIMER6" : 55,
+"J721E_DEV_TIMER7" : 57,
+"J721E_DEV_TIMER8" : 58,
+"J721E_DEV_TIMER9" : 59,
+"J721E_DEV_TIMER10" : 60,
+"J721E_DEV_GTC0" : 61,
+"J721E_DEV_TIMER11" : 62,
+"J721E_DEV_TIMER12" : 63,
+"J721E_DEV_TIMER13" : 64,
+"J721E_DEV_TIMER14" : 65,
+"J721E_DEV_TIMER15" : 66,
+"J721E_DEV_TIMER16" : 67,
+"J721E_DEV_TIMER17" : 68,
+"J721E_DEV_TIMER18" : 69,
+"J721E_DEV_TIMER19" : 70,
+"J721E_DEV_MCU_TIMER1" : 71,
+"J721E_DEV_MCU_TIMER2" : 72,
+"J721E_DEV_MCU_TIMER3" : 73,
+"J721E_DEV_MCU_TIMER4" : 74,
+"J721E_DEV_MCU_TIMER5" : 75,
+"J721E_DEV_MCU_TIMER6" : 76,
+"J721E_DEV_MCU_TIMER7" : 77,
+"J721E_DEV_MCU_TIMER8" : 78,
+"J721E_DEV_MCU_TIMER9" : 79,
+"J721E_DEV_ECAP0" : 80,
+"J721E_DEV_ECAP1" : 81,
+"J721E_DEV_ECAP2" : 82,
+"J721E_DEV_EHRPWM0" : 83,
+"J721E_DEV_EHRPWM1" : 84,
+"J721E_DEV_EHRPWM2" : 85,
+"J721E_DEV_EHRPWM3" : 86,
+"J721E_DEV_EHRPWM4" : 87,
+"J721E_DEV_EHRPWM5" : 88,
+"J721E_DEV_ELM0" : 89,
+"J721E_DEV_EMIF_DATA_0_VD" : 90,
+"J721E_DEV_MMCSD0" : 91,
+"J721E_DEV_MMCSD1" : 92,
+"J721E_DEV_MMCSD2" : 93,
+"J721E_DEV_EQEP0" : 94,
+"J721E_DEV_EQEP1" : 95,
+"J721E_DEV_EQEP2" : 96,
+"J721E_DEV_ESM0" : 97,
+"J721E_DEV_MCU_ESM0" : 98,
+"J721E_DEV_WKUP_ESM0" : 99,
+"J721E_DEV_FSS_MCU_0" : 100,
+"J721E_DEV_MCU_FSS0_FSAS_0" : 101,
+"J721E_DEV_MCU_FSS0_HYPERBUS1P0_0" : 102,
+"J721E_DEV_MCU_FSS0_OSPI_0" : 103,
+"J721E_DEV_MCU_FSS0_OSPI_1" : 104,
+"J721E_DEV_GPIO0" : 105,
+"J721E_DEV_GPIO1" : 106,
+"J721E_DEV_GPIO2" : 107,
+"J721E_DEV_GPIO3" : 108,
+"J721E_DEV_GPIO4" : 109,
+"J721E_DEV_GPIO5" : 110,
+"J721E_DEV_GPIO6" : 111,
+"J721E_DEV_GPIO7" : 112,
+"J721E_DEV_WKUP_GPIO0" : 113,
+"J721E_DEV_WKUP_GPIO1" : 114,
+"J721E_DEV_GPMC0" : 115,
+"J721E_DEV_I3C0" : 116,
+"J721E_DEV_MCU_I3C0" : 117,
+"J721E_DEV_MCU_I3C1" : 118,
+"J721E_DEV_PRU_ICSSG0" : 119,
+"J721E_DEV_PRU_ICSSG1" : 120,
+"J721E_DEV_C66SS0_INTROUTER0" : 121,
+"J721E_DEV_C66SS1_INTROUTER0" : 122,
+"J721E_DEV_CMPEVENT_INTRTR0" : 123,
+"J721E_DEV_J7_LASCAR_GPU_WRAP_MAIN_0" : 124,
+"J721E_DEV_GPU0_GPU_0" : 125,
+"J721E_DEV_GPU0_GPUCORE_0" : 126,
+"J721E_DEV_LED0" : 127,
+"J721E_DEV_MAIN2MCU_LVL_INTRTR0" : 128,
+"J721E_DEV_MAIN2MCU_PLS_INTRTR0" : 130,
+"J721E_DEV_GPIOMUX_INTRTR0" : 131,
+"J721E_DEV_WKUP_PORZ_SYNC0" : 132,
+"J721E_DEV_PSC0" : 133,
+"J721E_DEV_R5FSS0_INTROUTER0" : 134,
+"J721E_DEV_R5FSS1_INTROUTER0" : 135,
+"J721E_DEV_TIMESYNC_INTRTR0" : 136,
+"J721E_DEV_WKUP_GPIOMUX_INTRTR0" : 137,
+"J721E_DEV_WKUP_PSC0" : 138,
+"J721E_DEV_AASRC0" : 139,
+"J721E_DEV_K3_C66_COREPAC_MAIN_0" : 140,
+"J721E_DEV_K3_C66_COREPAC_MAIN_1" : 141,
+"J721E_DEV_C66SS0_CORE0" : 142,
+"J721E_DEV_C66SS1_CORE0" : 143,
+"J721E_DEV_DECODER0" : 144,
+"J721E_DEV_WKUP_DDPA0" : 145,
+"J721E_DEV_UART0" : 146,
+"J721E_DEV_DPHY_RX0" : 147,
+"J721E_DEV_DPHY_RX1" : 148,
+"J721E_DEV_MCU_UART0" : 149,
+"J721E_DEV_DSS_DSI0" : 150,
+"J721E_DEV_DSS_EDP0" : 151,
+"J721E_DEV_DSS0" : 152,
+"J721E_DEV_ENCODER0" : 153,
+"J721E_DEV_WKUP_VTM0" : 154,
+"J721E_DEV_MAIN2WKUPMCU_VD" : 155,
+"J721E_DEV_MCAN0" : 156,
+"J721E_DEV_BOARD0" : 157,
+"J721E_DEV_MCAN1" : 158,
+"J721E_DEV_MCAN2" : 160,
+"J721E_DEV_MCAN3" : 161,
+"J721E_DEV_MCAN4" : 162,
+"J721E_DEV_MCAN5" : 163,
+"J721E_DEV_MCAN6" : 164,
+"J721E_DEV_MCAN7" : 165,
+"J721E_DEV_MCAN8" : 166,
+"J721E_DEV_MCAN9" : 167,
+"J721E_DEV_MCAN10" : 168,
+"J721E_DEV_MCAN11" : 169,
+"J721E_DEV_MCAN12" : 170,
+"J721E_DEV_MCAN13" : 171,
+"J721E_DEV_MCU_MCAN0" : 172,
+"J721E_DEV_MCU_MCAN1" : 173,
+"J721E_DEV_MCASP0" : 174,
+"J721E_DEV_MCASP1" : 175,
+"J721E_DEV_MCASP2" : 176,
+"J721E_DEV_MCASP3" : 177,
+"J721E_DEV_MCASP4" : 178,
+"J721E_DEV_MCASP5" : 179,
+"J721E_DEV_MCASP6" : 180,
+"J721E_DEV_MCASP7" : 181,
+"J721E_DEV_MCASP8" : 182,
+"J721E_DEV_MCASP9" : 183,
+"J721E_DEV_MCASP10" : 184,
+"J721E_DEV_MCASP11" : 185,
+"J721E_DEV_MLB0" : 186,
+"J721E_DEV_I2C0" : 187,
+"J721E_DEV_I2C1" : 188,
+"J721E_DEV_I2C2" : 189,
+"J721E_DEV_I2C3" : 190,
+"J721E_DEV_I2C4" : 191,
+"J721E_DEV_I2C5" : 192,
+"J721E_DEV_I2C6" : 193,
+"J721E_DEV_MCU_I2C0" : 194,
+"J721E_DEV_MCU_I2C1" : 195,
+"J721E_DEV_WKUP_I2C0" : 197,
+"J721E_DEV_NAVSS512L_MAIN_0" : 199,
+"J721E_DEV_NAVSS0_CPTS_0" : 201,
+"J721E_DEV_A72SS0_CORE0" : 202,
+"J721E_DEV_A72SS0_CORE1" : 203,
+"J721E_DEV_NAVSS0_DTI_0" : 206,
+"J721E_DEV_NAVSS0_MODSS_INTAGGR_0" : 207,
+"J721E_DEV_NAVSS0_MODSS_INTAGGR_1" : 208,
+"J721E_DEV_NAVSS0_UDMASS_INTAGGR_0" : 209,
+"J721E_DEV_NAVSS0_PROXY_0" : 210,
+"J721E_DEV_NAVSS0_RINGACC_0" : 211,
+"J721E_DEV_NAVSS0_UDMAP_0" : 212,
+"J721E_DEV_NAVSS0_INTR_ROUTER_0" : 213,
+"J721E_DEV_NAVSS0_MAILBOX_0" : 214,
+"J721E_DEV_NAVSS0_MAILBOX_1" : 215,
+"J721E_DEV_NAVSS0_MAILBOX_2" : 216,
+"J721E_DEV_NAVSS0_MAILBOX_3" : 217,
+"J721E_DEV_NAVSS0_MAILBOX_4" : 218,
+"J721E_DEV_NAVSS0_MAILBOX_5" : 219,
+"J721E_DEV_NAVSS0_MAILBOX_6" : 220,
+"J721E_DEV_NAVSS0_MAILBOX_7" : 221,
+"J721E_DEV_NAVSS0_MAILBOX_8" : 222,
+"J721E_DEV_NAVSS0_MAILBOX_9" : 223,
+"J721E_DEV_NAVSS0_MAILBOX_10" : 224,
+"J721E_DEV_NAVSS0_MAILBOX_11" : 225,
+"J721E_DEV_NAVSS0_SPINLOCK_0" : 226,
+"J721E_DEV_NAVSS0_MCRC_0" : 227,
+"J721E_DEV_NAVSS0_TBU_0" : 228,
+"J721E_DEV_NAVSS0_TCU_0" : 229,
+"J721E_DEV_NAVSS0_TIMERMGR_0" : 230,
+"J721E_DEV_NAVSS0_TIMERMGR_1" : 231,
+"J721E_DEV_NAVSS_MCU_J7_MCU_0" : 232,
+"J721E_DEV_MCU_NAVSS0_INTAGGR_0" : 233,
+"J721E_DEV_MCU_NAVSS0_PROXY_0" : 234,
+"J721E_DEV_MCU_NAVSS0_RINGACC_0" : 235,
+"J721E_DEV_MCU_NAVSS0_UDMAP_0" : 236,
+"J721E_DEV_MCU_NAVSS0_INTR_ROUTER_0" : 237,
+"J721E_DEV_MCU_NAVSS0_MCRC_0" : 238,
+"J721E_DEV_PCIE0" : 239,
+"J721E_DEV_PCIE1" : 240,
+"J721E_DEV_PCIE2" : 241,
+"J721E_DEV_PCIE3" : 242,
+"J721E_DEV_PULSAR_SL_MAIN_0" : 243,
+"J721E_DEV_PULSAR_SL_MAIN_1" : 244,
+"J721E_DEV_R5FSS0_CORE0" : 245,
+"J721E_DEV_R5FSS0_CORE1" : 246,
+"J721E_DEV_R5FSS1_CORE0" : 247,
+"J721E_DEV_R5FSS1_CORE1" : 248,
+"J721E_DEV_PULSAR_SL_MCU_0" : 249,
+"J721E_DEV_MCU_R5FSS0_CORE0" : 250,
+"J721E_DEV_MCU_R5FSS0_CORE1" : 251,
+"J721E_DEV_RTI0" : 252,
+"J721E_DEV_RTI1" : 253,
+"J721E_DEV_RTI24" : 254,
+"J721E_DEV_RTI25" : 255,
+"J721E_DEV_RTI16" : 256,
+"J721E_DEV_RTI15" : 257,
+"J721E_DEV_RTI28" : 258,
+"J721E_DEV_RTI29" : 259,
+"J721E_DEV_RTI30" : 260,
+"J721E_DEV_RTI31" : 261,
+"J721E_DEV_MCU_RTI0" : 262,
+"J721E_DEV_MCU_RTI1" : 263,
+"J721E_DEV_SA2_UL0" : 264,
+"J721E_DEV_MCU_SA2_UL0" : 265,
+"J721E_DEV_MCSPI0" : 266,
+"J721E_DEV_MCSPI1" : 267,
+"J721E_DEV_MCSPI2" : 268,
+"J721E_DEV_MCSPI3" : 269,
+"J721E_DEV_MCSPI4" : 270,
+"J721E_DEV_MCSPI5" : 271,
+"J721E_DEV_MCSPI6" : 272,
+"J721E_DEV_MCSPI7" : 273,
+"J721E_DEV_MCU_MCSPI0" : 274,
+"J721E_DEV_MCU_MCSPI1" : 275,
+"J721E_DEV_MCU_MCSPI2" : 276,
+"J721E_DEV_UFS0" : 277,
+"J721E_DEV_UART1" : 278,
+"J721E_DEV_UART2" : 279,
+"J721E_DEV_UART3" : 280,
+"J721E_DEV_UART4" : 281,
+"J721E_DEV_UART5" : 282,
+"J721E_DEV_UART6" : 283,
+"J721E_DEV_UART7" : 284,
+"J721E_DEV_UART8" : 285,
+"J721E_DEV_UART9" : 286,
+"J721E_DEV_WKUP_UART0" : 287,
+"J721E_DEV_USB0" : 288,
+"J721E_DEV_USB1" : 289,
+"J721E_DEV_VPAC_TOP_MAIN_0" : 290,
+"J721E_DEV_VPFE0" : 291,
+"J721E_DEV_SERDES_16G0" : 292,
+"J721E_DEV_SERDES_16G1" : 293,
+"J721E_DEV_SERDES_16G2" : 294,
+"J721E_DEV_SERDES_16G3" : 295,
+"J721E_DEV_DPHY_TX0" : 296,
+"J721E_DEV_SERDES_10G0" : 297,
+"J721E_DEV_WKUPMCU2MAIN_VD" : 298,
+"J721E_DEV_NAVSS0_MODSS" : 299,
+"J721E_DEV_NAVSS0_UDMASS" : 300,
+"J721E_DEV_NAVSS0_VIRTSS" : 301,
+"J721E_DEV_MCU_NAVSS0_MODSS" : 302,
+"J721E_DEV_MCU_NAVSS0_UDMASS" : 303,
+"J721E_DEV_DEBUGSS_WRAP0" : 304,
+"J721E_DEV_DMPAC0_SDE_0" : 305,
+
+"RESASG_SUBTYPE_SHIFT" : 0x0000,
+"RESASG_SUBTYPE_MASK" : 0x003F,
+"RESASG_SUBTYPE_IA_VINT" : 0x000A,
+"RESASG_SUBTYPE_GLOBAL_EVENT_GEVT" : 0x000B,
+"RESASG_SUBTYPE_GLOBAL_EVENT_MEVT" : 0x000C,
+"RESASG_SUBTYPE_GLOBAL_EVENT_SEVT" : 0x000D,
+"RESASG_SUBTYPES_IA_CNT" : 0x0004,
+"RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP0_FROM_C66SS0_INTROUTER0" : 0x0000,
+"RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP1_FROM_C66SS0_INTROUTER0" : 0x0001,
+"RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP2_FROM_C66SS0_INTROUTER0" : 0x0002,
+"RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP3_FROM_C66SS0_INTROUTER0" : 0x0003,
+"RESASG_SUBTYPE_C66SS0_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP4_FROM_C66SS0_INTROUTER0" : 0x0004,
+"RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP0_FROM_C66SS1_INTROUTER0" : 0x0000,
+"RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP1_FROM_C66SS1_INTROUTER0" : 0x0001,
+"RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP2_FROM_C66SS1_INTROUTER0" : 0x0002,
+"RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP3_FROM_C66SS1_INTROUTER0" : 0x0003,
+"RESASG_SUBTYPE_C66SS1_CORE0_C66_EVENT_IN_SYNC_IRQ_GROUP4_FROM_C66SS1_INTROUTER0" : 0x0004,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0" : 0x0003,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0" : 0x0000,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0" : 0x0005,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0" : 0x0002,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_IRQ_GROUP2_FROM_NAVSS0_INTR_ROUTER_0" : 0x0004,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0" : 0x0003,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0" : 0x0000,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0" : 0x0005,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0" : 0x0002,
+"RESASG_SUBTYPE_COMPUTE_CLUSTER0_GIC500SS_SPI_IRQ_GROUP2_FROM_NAVSS0_INTR_ROUTER_0" : 0x0004,
+"RESASG_SUBTYPE_CPSW0_CPTS_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_CPSW0_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0002,
+"RESASG_SUBTYPE_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0003,
+"RESASG_SUBTYPE_CPSW0_CPTS_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0004,
+"RESASG_SUBTYPE_CPSW0_CPTS_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0005,
+"RESASG_SUBTYPE_CPSW0_CPTS_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0006,
+"RESASG_SUBTYPE_CPSW0_CPTS_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0007,
+"RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0002,
+"RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_MCU_NAVSS0_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0" : 0x0002,
+"RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0" : 0x0003,
+"RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0" : 0x0000,
+"RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0" : 0x0004,
+"RESASG_SUBTYPE_MCU_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0" : 0x0002,
+"RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0" : 0x0003,
+"RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0" : 0x0000,
+"RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0" : 0x0004,
+"RESASG_SUBTYPE_MCU_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_NAVSS0_UDMASS_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_NAVSS0_UDMASS_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0002,
+"RESASG_SUBTYPE_NAVSS0_UDMASS_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0002,
+"RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0003,
+"RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0004,
+"RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0005,
+"RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0006,
+"RESASG_SUBTYPE_NAVSS512L_MAIN_0_CPTS0_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0007,
+"RESASG_SUBTYPE_PCIE0_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_PCIE1_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_PCIE2_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_PCIE3_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0002,
+"RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0003,
+"RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0004,
+"RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0005,
+"RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0" : 0x0006,
+"RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0002,
+"RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0" : 0x0003,
+"RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0004,
+"RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0005,
+"RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0" : 0x0006,
+"RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0" : 0x0001,
+"RESASG_SUBTYPE_R5FSS0_CORE0_INTR_IRQ_GROUP0_FROM_R5FSS0_INTROUTER0" : 0x0002,
+"RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0" : 0x0001,
+"RESASG_SUBTYPE_R5FSS0_CORE1_INTR_IRQ_GROUP0_FROM_R5FSS0_INTROUTER0" : 0x0002,
+"RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0" : 0x0001,
+"RESASG_SUBTYPE_R5FSS1_CORE0_INTR_IRQ_GROUP0_FROM_R5FSS1_INTROUTER0" : 0x0002,
+"RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0" : 0x0001,
+"RESASG_SUBTYPE_R5FSS1_CORE1_INTR_IRQ_GROUP0_FROM_R5FSS1_INTROUTER0" : 0x0002,
+"RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0" : 0x0000,
+"RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0" : 0x0001,
+"RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0" : 0x0002,
+"RESASG_SUBTYPES_IRQ_CNT" : 0x005A,
+"RESASG_SUBTYPE_PROXY_PROXIES" : 0x0000,
+"RESASG_SUBTYPES_PROXY_CNT" : 0x0001,
+"RESASG_SUBTYPE_RA_ERROR_OES" : 0x0000,
+"RESASG_SUBTYPE_RA_GP" : 0x0001,
+"RESASG_SUBTYPE_RA_UDMAP_RX" : 0x0002,
+"RESASG_SUBTYPE_RA_UDMAP_TX" : 0x0003,
+"RESASG_SUBTYPE_RA_UDMAP_TX_EXT" : 0x0004,
+"RESASG_SUBTYPE_RA_UDMAP_RX_H" : 0x0005,
+"RESASG_SUBTYPE_RA_UDMAP_RX_UH" : 0x0006,
+"RESASG_SUBTYPE_RA_UDMAP_TX_H" : 0x0007,
+"RESASG_SUBTYPE_RA_UDMAP_TX_UH" : 0x0008,
+"RESASG_SUBTYPE_RA_VIRTID" : 0x000A,
+"RESASG_SUBTYPE_RA_MONITORS" : 0x000B,
+"RESASG_SUBTYPES_RA_CNT" : 0x000B,
+"RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON" : 0x0000,
+"RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES" : 0x0001,
+"RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER" : 0x0002,
+"RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG" : 0x0003,
+"RESASG_SUBTYPE_UDMAP_RX_CHAN" : 0x000A,
+"RESASG_SUBTYPE_UDMAP_RX_HCHAN" : 0x000B,
+"RESASG_SUBTYPE_UDMAP_RX_UHCHAN" : 0x000C,
+"RESASG_SUBTYPE_UDMAP_TX_CHAN" : 0x000D,
+"RESASG_SUBTYPE_UDMAP_TX_ECHAN" : 0x000E,
+"RESASG_SUBTYPE_UDMAP_TX_HCHAN" : 0x000F,
+"RESASG_SUBTYPE_UDMAP_TX_UHCHAN" : 0x0010,
+"RESASG_SUBTYPES_UDMAP_CNT" : 0x000B,
+
+"HOST_ID_DMSC" : 0,
+"HOST_ID_MCU_0_R5_0" : 3,
+"HOST_ID_MCU_0_R5_1" : 4,
+"HOST_ID_MCU_0_R5_2" : 5,
+"HOST_ID_MCU_0_R5_3" : 6,
+"HOST_ID_A72_0" : 10,
+"HOST_ID_A72_1" : 11,
+"HOST_ID_A72_2" : 12,
+"HOST_ID_A72_3" : 13,
+"HOST_ID_A72_4" : 14,
+"HOST_ID_C7X_0" : 20,
+"HOST_ID_C7X_1" : 21,
+"HOST_ID_C6X_0_0" : 25,
+"HOST_ID_C6X_0_1" : 26,
+"HOST_ID_C6X_1_0" : 27,
+"HOST_ID_C6X_1_1" : 28,
+"HOST_ID_GPU_0" : 30,
+"HOST_ID_MAIN_0_R5_0" : 35,
+"HOST_ID_MAIN_0_R5_1" : 36,
+"HOST_ID_MAIN_0_R5_2" : 37,
+"HOST_ID_MAIN_0_R5_3" : 38,
+"HOST_ID_MAIN_1_R5_0" : 40,
+"HOST_ID_MAIN_1_R5_1" : 41,
+"HOST_ID_MAIN_1_R5_2" : 42,
+"HOST_ID_MAIN_1_R5_3" : 43,
+"HOST_ID_ICSSG_0" : 50,
+"HOST_ID_ALL" : 128,
+"HOST_ID_CNT" : 26,
+}