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raw | patch | inline | side by side (parent: 1bfd675)
raw | patch | inline | side by side (parent: 1bfd675)
author | Nikhil Devshatwar <nikhil.nd@ti.com> | |
Wed, 23 Nov 2016 19:43:32 +0000 (01:13 +0530) | ||
committer | Praneeth Bajjuri <praneeth@ti.com> | |
Thu, 16 Feb 2017 18:08:17 +0000 (12:08 -0600) |
All values copied from the DRA72x PCT tool and iodelay tool
Add pinmux for i2c4 and mcASP on JAMR board
Change-Id: Iaddd31bd3055648c62dd360bd9b8c597c232f461
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Add pinmux for i2c4 and mcASP on JAMR board
Change-Id: Iaddd31bd3055648c62dd360bd9b8c597c232f461
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
board/ti/dra7xx/mux_data.h | patch | blob | history |
index 731c5521afe8860fcf0eead4720b9fb238e8d28f..931d76d8eba38362418b40fcf492000d251769a4 100644 (file)
{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)}, /* i2c2_scl.hdmi1_ddc_sda */
{WAKEUP0, (M15 | PULL_UP)}, /* Wakeup0.safe for dcan1_rx */
{WAKEUP3, (M1 | PULL_ENA | PULL_UP)}, /* Wakeup3.sys_nirq1 */
+#ifdef CONFIG_DRA7XX_JAMR3
+ {XREF_CLK1, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.atl_clk1 */
+ {XREF_CLK3, (M14 | PIN_INPUT)}, /* xref_clk3.gpio6_20 */
+ {MCASP1_AXR8, (M1 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL)}, /* mcasp1_axr8.mcasp6_axr0 */
+ {MCASP1_AXR9, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.mcasp6_axr1 */
+ {MCASP1_AXR10, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.mcasp6_aclkx */
+ {MCASP1_AXR11, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr11.mcasp6_fsx */
+ {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE9)}, /* mcasp2_aclkx.mcasp2_aclkx */
+ {MCASP2_FSX, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)}, /* mcasp2_fsx.mcasp2_fsx */
+ {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr0.mcasp2_axr0 */
+ {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr1.mcasp2_axr1 */
+ {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)}, /* mcasp2_axr2.mcasp2_axr2 */
+ {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE9)}, /* mcasp2_axr3.mcasp2_axr3 */
+ {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr4.mcasp2_axr4 */
+ {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr5.mcasp2_axr5 */
+ {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr6.mcasp2_axr6 */
+ {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN | VIRTUAL_MODE12)}, /* mcasp2_axr7.mcasp2_axr7 */
+ {MCASP4_ACLKX, (M4 | PIN_INPUT_PULLUP)},/* mcasp4_aclkx.i2c4_sda */
+ {MCASP4_FSX, (M4 | PIN_INPUT_PULLUP)}, /* mcasp4_fsx.i2c4_scl */
+#endif
};
const struct pad_conf_entry early_padconf[] = {