3b36b279495dbb74c49022805fd6218db4eadc0b
[glsdk/iodelay-config.git] / XMLFiles / DRA75x_DRA74x / CTRL_MODULE_CORE.xml
1 <module name="CTRL_MODULE_CORE" acronym="" XML_version="1.0" HW_revision="n/a" description="">\r
2   <register id="CTRL_CORE_STATUS" acronym="CTRL_CORE_STATUS" offset="0x134" width="32" description="Control Module Status Register">\r
3     <bitfield id="RESERVED" width="23" begin="31" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
4     <bitfield id="DEVICE_TYPE" width="3" begin="8" end="6" resetval="0x3" description="Device type captured at reset time. Read 0x3 = General Purpose (GP)" range="" rwaccess="R"/>\r
5     <bitfield id="RESERVED" width="6" begin="5" end="0" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
6   </register>\r
7   <register id="CTRL_CORE_SEC_ERR_STATUS_FUNC_1" acronym="CTRL_CORE_SEC_ERR_STATUS_FUNC_1" offset="0x148" width="32" description="Firewall Error Status functional Register 1">\r
8     <bitfield id="RESERVED" width="2" begin="31" end="30" resetval="0x0" description="" range="" rwaccess="R"/>\r
9     <bitfield id="EVE2_FW_ERROR" width="1" begin="29" end="29" resetval="0x0" description="EVE2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
10     <bitfield id="EVE1_FW_ERROR" width="1" begin="28" end="28" resetval="0x0" description="EVE1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
11     <bitfield id="RESERVED" width="4" begin="27" end="24" resetval="0x0" description="" range="" rwaccess="R"/>\r
12     <bitfield id="BB2D_FW_ERROR" width="1" begin="23" end="23" resetval="0x0" description="BB2D firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
13     <bitfield id="L4_WAKEUP_FW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="L4 wakeup firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
14     <bitfield id="RESERVED" width="3" begin="21" end="19" resetval="0x0" description="" range="" rwaccess="R"/>\r
15     <bitfield id="DEBUGSS_FW_ERROR" width="1" begin="18" end="18" resetval="0x0" description="DebugSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
16     <bitfield id="L4_CONFIG_FW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="L4 config firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
17     <bitfield id="L4_PERIPH1_FW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="L4 periph1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
18     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>\r
19     <bitfield id="DSS_FW_ERROR" width="1" begin="14" end="14" resetval="0x0" description="DSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
20     <bitfield id="GPU_FW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="GPU firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
21     <bitfield id="RESERVED" width="6" begin="12" end="7" resetval="0x0" description="" range="" rwaccess="R"/>\r
22     <bitfield id="IVAHD_SL2_FW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IVAHD SL2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
23     <bitfield id="IPU1_FW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="IPU1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
24     <bitfield id="IVAHD_FW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="IVAHD firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
25     <bitfield id="EMIF_FW_ERROR" width="1" begin="3" end="3" resetval="0x0" description="EMIF firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
26     <bitfield id="GPMC_FW_ERROR" width="1" begin="2" end="2" resetval="0x0" description="GPMC firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
27     <bitfield id="L3RAM1_FW_ERROR" width="1" begin="1" end="1" resetval="0x0" description="L3RAM1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
28     <bitfield id="RESERVED" width="1" begin="0" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
29   </register>\r
30   <register id="CTRL_CORE_SEC_ERR_STATUS_DEBUG_1" acronym="CTRL_CORE_SEC_ERR_STATUS_DEBUG_1" offset="0x150" width="32" description="Firewall Error Status Debug Register 1">\r
31     <bitfield id="RESERVED" width="2" begin="31" end="30" resetval="0x0" description="" range="" rwaccess="R"/>\r
32     <bitfield id="EVE2_DBGFW_ERROR" width="1" begin="29" end="29" resetval="0x0" description="EVE2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
33     <bitfield id="EVE1_DBGFW_ERROR" width="1" begin="28" end="28" resetval="0x0" description="EVE1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
34     <bitfield id="RESERVED" width="4" begin="27" end="24" resetval="0x0" description="" range="" rwaccess="R"/>\r
35     <bitfield id="BB2D_DBGFW_ERROR" width="1" begin="23" end="23" resetval="0x0" description="BB2D firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
36     <bitfield id="L4_WAKEUP_DBGFW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="L4 wakeup firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
37     <bitfield id="RESERVED" width="3" begin="21" end="19" resetval="0x0" description="" range="" rwaccess="R"/>\r
38     <bitfield id="DEBUGSS_DBGFW_ERROR" width="1" begin="18" end="18" resetval="0x0" description="DebugSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
39     <bitfield id="L4_CONFIG_DBGFW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="L4 config firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
40     <bitfield id="L4_PERIPH1_DBGFW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="L4 periph1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
41     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>\r
42     <bitfield id="DSS_DBGFW_ERROR" width="1" begin="14" end="14" resetval="0x0" description="DSS debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
43     <bitfield id="GPU_DBGFW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="GPU debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
44     <bitfield id="RESERVED" width="6" begin="12" end="7" resetval="0x0" description="" range="" rwaccess="R"/>\r
45     <bitfield id="IVAHD_SL2_DBGFW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IVAHD SL2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
46     <bitfield id="IPU1_DBGFW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="IPU1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
47     <bitfield id="IVAHD_DBGFW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="IVAHD debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
48     <bitfield id="EMIF_DBGFW_ERROR" width="1" begin="3" end="3" resetval="0x0" description="EMIF debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
49     <bitfield id="GPMC_DBGFW_ERROR" width="1" begin="2" end="2" resetval="0x0" description="GPMC debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
50     <bitfield id="L3RAM1_DBGFW_ERROR" width="1" begin="1" end="1" resetval="0x0" description="L3RAM1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
51     <bitfield id="RESERVED" width="1" begin="0" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
52   </register>\r
53   <register id="CTRL_CORE_MPU_FORCEWRNP" acronym="CTRL_CORE_MPU_FORCEWRNP" offset="0x15C" width="32" description="FORCE WRITE NON POSTED">\r
54     <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="" range="" rwaccess="R"/>\r
55     <bitfield id="MPU_FORCEWRNP" width="1" begin="0" end="0" resetval="0x0" description="Force mpu write non posted transactions 0x0 = disable force wrnp 0x1 = force wrnp" range="" rwaccess="RW"/>\r
56   </register>\r
57   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0" offset="0x194" width="32" description="Standard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
58     <bitfield id="STD_FUSE_OPP_VDD_GPU_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
59   </register>\r
60   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1" offset="0x198" width="32" description="Standard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
61     <bitfield id="STD_FUSE_OPP_VDD_GPU_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
62   </register>\r
63   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2" offset="0x19C" width="32" description="Standard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
64     <bitfield id="STD_FUSE_OPP_VDD_GPU_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
65   </register>\r
66   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3" offset="0x1A0" width="32" description="Standard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
67     <bitfield id="STD_FUSE_OPP_VDD_GPU_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
68   </register>\r
69   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4" offset="0x1A4" width="32" description="Standard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
70     <bitfield id="STD_FUSE_OPP_VDD_GPU_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
71   </register>\r
72   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5" offset="0x1A8" width="32" description="Standard Fuse OPP VDD_GPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
73     <bitfield id="STD_FUSE_OPP_VDD_GPU_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
74   </register>\r
75   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0" offset="0x1AC" width="32" description="Standard Fuse OPP VDD_MPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
76     <bitfield id="STD_FUSE_OPP_VDD_MPU_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
77   </register>\r
78   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1" offset="0x1B0" width="32" description="Standard Fuse OPP VDD_MPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
79     <bitfield id="STD_FUSE_OPP_VDD_MPU_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
80   </register>\r
81   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2" offset="0x1B4" width="32" description="Standard Fuse OPP VDD_MPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
82     <bitfield id="STD_FUSE_OPP_VDD_MPU_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
83   </register>\r
84   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3" offset="0x1B8" width="32" description="Standard Fuse OPP VDD_MPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
85     <bitfield id="STD_FUSE_OPP_VDD_MPU_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
86   </register>\r
87   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4" offset="0x1BC" width="32" description="Standard Fuse OPP VDD_MPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
88     <bitfield id="STD_FUSE_OPP_VDD_MPU_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
89   </register>\r
90   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5" offset="0x1C0" width="32" description="Standard Fuse OPP VDD_MPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
91     <bitfield id="STD_FUSE_OPP_VDD_MPU_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
92   </register>\r
93   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6" offset="0x1C4" width="32" description="Standard Fuse OPP VDD_MPU [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
94     <bitfield id="STD_FUSE_OPP_VDD_MPU_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
95   </register>\r
96   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7" offset="0x1C8" width="32" description="Standard Fuse OPP VDD_MPU [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
97     <bitfield id="STD_FUSE_OPP_VDD_MPU_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
98   </register>\r
99   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0" offset="0x1CC" width="32" description="Standard Fuse OPP VDD_CORE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
100     <bitfield id="STD_FUSE_OPP_VDD_CORE_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
101   </register>\r
102   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1" offset="0x1D0" width="32" description="Standard Fuse OPP VDD_CORE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
103     <bitfield id="STD_FUSE_OPP_VDD_CORE_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
104   </register>\r
105   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2" offset="0x1D4" width="32" description="Standard Fuse OPP VDD_CORE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
106     <bitfield id="STD_FUSE_OPP_VDD_CORE_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
107   </register>\r
108   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3" offset="0x1D8" width="32" description="Standard Fuse OPP VDD_CORE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
109     <bitfield id="STD_FUSE_OPP_VDD_CORE_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
110   </register>\r
111   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4" offset="0x1DC" width="32" description="Standard Fuse OPP VDD_CORE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
112     <bitfield id="STD_FUSE_OPP_VDD_CORE_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
113   </register>\r
114   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_GPU" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_GPU" offset="0x1E0" width="32" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">\r
115     <bitfield id="STD_FUSE_OPP_BGAP_GPU_0" width="8" begin="31" end="24" resetval="0x0" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
116     <bitfield id="STD_FUSE_OPP_BGAP_GPU_1" width="8" begin="23" end="16" resetval="0x0" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
117     <bitfield id="STD_FUSE_OPP_BGAP_GPU_2" width="8" begin="15" end="8" resetval="0x0" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
118     <bitfield id="STD_FUSE_OPP_BGAP_GPU_3" width="8" begin="7" end="0" resetval="0x0" description="Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
119   </register>\r
120   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU" offset="0x1E4" width="32" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">\r
121     <bitfield id="STD_FUSE_OPP_BGAP_MPU_0" width="8" begin="31" end="24" resetval="0x0" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
122     <bitfield id="STD_FUSE_OPP_BGAP_MPU_1" width="8" begin="23" end="16" resetval="0x0" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
123     <bitfield id="STD_FUSE_OPP_BGAP_MPU_2" width="8" begin="15" end="8" resetval="0x0" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
124     <bitfield id="STD_FUSE_OPP_BGAP_MPU_3" width="8" begin="7" end="0" resetval="0x0" description="Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
125   </register>\r
126   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_CORE" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_CORE" offset="0x1E8" width="32" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">\r
127     <bitfield id="STD_FUSE_OPP_BGAP_CORE_0" width="8" begin="31" end="24" resetval="0x0" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
128     <bitfield id="STD_FUSE_OPP_BGAP_CORE_1" width="8" begin="23" end="16" resetval="0x0" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
129     <bitfield id="STD_FUSE_OPP_BGAP_CORE_2" width="8" begin="15" end="8" resetval="0x0" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
130     <bitfield id="STD_FUSE_OPP_BGAP_CORE_3" width="8" begin="7" end="0" resetval="0x0" description="Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
131   </register>\r
132   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23" offset="0x1EC" width="32" description="Standard Fuse OPP BGAP. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
133     <bitfield id="STD_FUSE_OPP_BGAP_MPU3" width="16" begin="31" end="16" resetval="0x0" description="" range="" rwaccess="R"/>\r
134     <bitfield id="STD_FUSE_OPP_BGAP_MPU2" width="16" begin="15" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
135   </register>\r
136   <register id="CTRL_CORE_STD_FUSE_MPK_0" acronym="CTRL_CORE_STD_FUSE_MPK_0" offset="0x220" width="32" description="Standard Fuse keys. Root_public_key_hash [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
137     <bitfield id="STD_FUSE_MPK_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
138   </register>\r
139   <register id="CTRL_CORE_STD_FUSE_MPK_1" acronym="CTRL_CORE_STD_FUSE_MPK_1" offset="0x224" width="32" description="Standard Fuse keys. Root_public_key_hash [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
140     <bitfield id="STD_FUSE_MPK_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
141   </register>\r
142   <register id="CTRL_CORE_STD_FUSE_MPK_2" acronym="CTRL_CORE_STD_FUSE_MPK_2" offset="0x228" width="32" description="Standard Fuse keys. Root_public_key_hash [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
143     <bitfield id="STD_FUSE_MPK_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
144   </register>\r
145   <register id="CTRL_CORE_STD_FUSE_MPK_3" acronym="CTRL_CORE_STD_FUSE_MPK_3" offset="0x22C" width="32" description="Standard Fuse keys. Root_public_key_hash [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
146     <bitfield id="STD_FUSE_MPK_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
147   </register>\r
148   <register id="CTRL_CORE_STD_FUSE_MPK_4" acronym="CTRL_CORE_STD_FUSE_MPK_4" offset="0x230" width="32" description="Standard Fuse keys. Root_public_key_hash [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
149     <bitfield id="STD_FUSE_MPK_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
150   </register>\r
151   <register id="CTRL_CORE_STD_FUSE_MPK_5" acronym="CTRL_CORE_STD_FUSE_MPK_5" offset="0x234" width="32" description="Standard Fuse keys. Root_public_key_hash [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
152     <bitfield id="STD_FUSE_MPK_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
153   </register>\r
154   <register id="CTRL_CORE_STD_FUSE_MPK_6" acronym="CTRL_CORE_STD_FUSE_MPK_6" offset="0x238" width="32" description="Standard Fuse keys. Root_public_key_hash [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
155     <bitfield id="STD_FUSE_MPK_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
156   </register>\r
157   <register id="CTRL_CORE_STD_FUSE_MPK_7" acronym="CTRL_CORE_STD_FUSE_MPK_7" offset="0x23C" width="32" description="Standard Fuse keys. Root_public_key_hash [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
158     <bitfield id="STD_FUSE_MPK_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
159   </register>\r
160   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0" offset="0x240" width="32" description="Standard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
161     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
162   </register>\r
163   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1" offset="0x244" width="32" description="Standard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
164     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
165   </register>\r
166   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2" offset="0x248" width="32" description="Standard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
167     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
168   </register>\r
169   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3" offset="0x24C" width="32" description="Standard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
170     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
171   </register>\r
172   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4" offset="0x250" width="32" description="Standard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
173     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
174   </register>\r
175   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5" offset="0x254" width="32" description="Standard Fuse OPP VDD_GPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
176     <bitfield id="STD_FUSE_OPP_VDD_GPU_LVT_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
177   </register>\r
178   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0" offset="0x258" width="32" description="Standard Fuse OPP VDD_MPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
179     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
180   </register>\r
181   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1" offset="0x25C" width="32" description="Standard Fuse OPP VDD_MPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
182     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
183   </register>\r
184   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2" offset="0x260" width="32" description="Standard Fuse OPP VDD_MPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
185     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
186   </register>\r
187   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3" offset="0x264" width="32" description="Standard Fuse OPP VDD_MPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
188     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
189   </register>\r
190   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4" offset="0x268" width="32" description="Standard Fuse OPP VDD_MPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
191     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
192   </register>\r
193   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5" offset="0x26C" width="32" description="Standard Fuse OPP VDD_MPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
194     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
195   </register>\r
196   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6" offset="0x270" width="32" description="Standard Fuse OPP VDD_MPU [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
197     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
198   </register>\r
199   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7" offset="0x274" width="32" description="Standard Fuse OPP VDD_MPU [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
200     <bitfield id="STD_FUSE_OPP_VDD_MPU_LVT_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
201   </register>\r
202   <register id="CTRL_CORE_CUST_FUSE_SWRV_0" acronym="CTRL_CORE_CUST_FUSE_SWRV_0" offset="0x2BC" width="32" description="Customer Fuse keys. Software Version Control [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
203     <bitfield id="CUST_FUSE_SWRV_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
204   </register>\r
205   <register id="CTRL_CORE_CUST_FUSE_SWRV_1" acronym="CTRL_CORE_CUST_FUSE_SWRV_1" offset="0x2C0" width="32" description="Customer Fuse keys. Software Version Control [063:032] (16 bits upper Redundant field) [FIELD F]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
206     <bitfield id="CUST_FUSE_SWRV_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
207   </register>\r
208   <register id="CTRL_CORE_CUST_FUSE_SWRV_2" acronym="CTRL_CORE_CUST_FUSE_SWRV_2" offset="0x2C4" width="32" description="Customer Fuse keys. Software Version Control [095:064] (16 bits upper Redundant field) [FIELD E]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
209     <bitfield id="CUST_FUSE_SWRV_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
210   </register>\r
211   <register id="CTRL_CORE_CUST_FUSE_SWRV_3" acronym="CTRL_CORE_CUST_FUSE_SWRV_3" offset="0x2C8" width="32" description="Customer Fuse keys. Software Version Control [127:096] (16 bits upper Redundant field) [FIELD D]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
212     <bitfield id="CUST_FUSE_SWRV_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
213   </register>\r
214   <register id="CTRL_CORE_CUST_FUSE_SWRV_4" acronym="CTRL_CORE_CUST_FUSE_SWRV_4" offset="0x2CC" width="32" description="Customer Fuse keys. Software Version Control [159:127] (16 bits upper Redundant field) [FIELD C]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
215     <bitfield id="CUST_FUSE_SWRV_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
216   </register>\r
217   <register id="CTRL_CORE_CUST_FUSE_SWRV_5" acronym="CTRL_CORE_CUST_FUSE_SWRV_5" offset="0x2D0" width="32" description="Customer Fuse keys. Software Version Control [191:160] (16 bits upper Redundant field) [FIELD B]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
218     <bitfield id="CUST_FUSE_SWRV_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
219   </register>\r
220   <register id="CTRL_CORE_CUST_FUSE_SWRV_6" acronym="CTRL_CORE_CUST_FUSE_SWRV_6" offset="0x2D4" width="32" description="Customer Fuse keys. Software Version Control [223:192] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
221     <bitfield id="CUST_FUSE_SWRV_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
222   </register>\r
223   <register id="CTRL_CORE_BREG_SELECTION" acronym="CTRL_CORE_BREG_SELECTION" offset="0x2E0" width="32" description="DPLL selection">\r
224     <bitfield id="RESERVED" width="17" begin="31" end="15" resetval="0x0" description="" range="" rwaccess="R"/>\r
225     <bitfield id="SEL_DDR" width="1" begin="14" end="14" resetval="0x0" description="Selection ddr 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
226     <bitfield id="SEL_GPU" width="1" begin="13" end="13" resetval="0x0" description="Selection gpu 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
227     <bitfield id="SEL_GMAC" width="1" begin="12" end="12" resetval="0x0" description="Selection gmac 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
228     <bitfield id="SEL_DSP" width="1" begin="11" end="11" resetval="0x0" description="Selection dsp 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
229     <bitfield id="SEL_EVE" width="1" begin="10" end="10" resetval="0x0" description="Selection eve 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
230     <bitfield id="SEL_USB" width="1" begin="9" end="9" resetval="0x0" description="Selection usb 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
231     <bitfield id="SEL_IVA" width="1" begin="8" end="8" resetval="0x0" description="Selection iva 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
232     <bitfield id="SEL_PCIE" width="1" begin="7" end="7" resetval="0x0" description="Selection pcie 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
233     <bitfield id="SEL_SATA" width="1" begin="6" end="6" resetval="0x0" description="Selection sata 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
234     <bitfield id="SEL_PER" width="1" begin="5" end="5" resetval="0x0" description="Selection per 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
235     <bitfield id="SEL_HDMI" width="1" begin="4" end="4" resetval="0x0" description="Selection hdmi 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
236     <bitfield id="RESERVED" width="2" begin="3" end="2" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
237     <bitfield id="SEL_CORE" width="1" begin="1" end="1" resetval="0x0" description="Selection core 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
238     <bitfield id="SEL_IPU" width="1" begin="0" end="0" resetval="0x0" description="Selection ipu 0x0 = no dpll selected 0x1 = rdpll selected" range="" rwaccess="RW"/>\r
239   </register>\r
240   <register id="CTRL_CORE_DPLL_BCLK" acronym="CTRL_CORE_DPLL_BCLK" offset="0x2E4" width="32" description="DPPL obs">\r
241     <bitfield id="RESERVED" width="30" begin="31" end="2" resetval="0x0" description="" range="" rwaccess="R"/>\r
242     <bitfield id="BRW" width="1" begin="1" end="1" resetval="0x0" description="Reset 0x0 = no reset 0x1 = reset" range="" rwaccess="RW"/>\r
243     <bitfield id="BCLK" width="1" begin="0" end="0" resetval="0x0" description="clock" range="" rwaccess="RW"/>\r
244   </register>\r
245   <register id="CTRL_CORE_DPLL_BADDR_BDATAW" acronym="CTRL_CORE_DPLL_BADDR_BDATAW" offset="0x2E8" width="32" description="DPLL addr and dataw">\r
246     <bitfield id="RESERVED" width="12" begin="31" end="20" resetval="0x0" description="" range="" rwaccess="R"/>\r
247     <bitfield id="BADDR" width="4" begin="19" end="16" resetval="0x0" description="baddr" range="" rwaccess="RW"/>\r
248     <bitfield id="BDATAW" width="16" begin="15" end="0" resetval="0x0" description="bdataw" range="" rwaccess="RW"/>\r
249   </register>\r
250   <register id="CTRL_CORE_DPLL_BDATAR" acronym="CTRL_CORE_DPLL_BDATAR" offset="0x2EC" width="32" description="DPLL datar">\r
251     <bitfield id="RESERVED" width="16" begin="31" end="16" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
252     <bitfield id="BDATAR" width="16" begin="15" end="0" resetval="0x0" description="datar" range="" rwaccess="R"/>\r
253   </register>\r
254   <register id="CTRL_CORE_DEV_CONF" acronym="CTRL_CORE_DEV_CONF" offset="0x300" width="32" description="This register is used to power down the USB2_PHY1">\r
255     <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
256     <bitfield id="USBPHY_PD" width="1" begin="0" end="0" resetval="0x0" description="Power down the entire USB2_PHY1 (data, common module and UTMI). 0x0: Normal operation 0x1: Power down the USB2_PHY1" range="" rwaccess="RW"/>\r
257   </register>\r
258   <register id="CTRL_CORE_TEMP_SENSOR_MPU" acronym="CTRL_CORE_TEMP_SENSOR_MPU" offset="0x32C" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">\r
259     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
260     <bitfield id="BGAP_TMPSOFF_MPU" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>\r
261     <bitfield id="BGAP_EOCZ_MPU" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_MPU is valid." range="" rwaccess="R"/>\r
262     <bitfield id="BGAP_DTEMP_MPU" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>\r
263   </register>\r
264   <register id="CTRL_CORE_TEMP_SENSOR_GPU" acronym="CTRL_CORE_TEMP_SENSOR_GPU" offset="0x330" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">\r
265     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
266     <bitfield id="BGAP_TMPSOFF_GPU" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>\r
267     <bitfield id="BGAP_EOCZ_GPU" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_GPU is valid." range="" rwaccess="R"/>\r
268     <bitfield id="BGAP_DTEMP_GPU" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>\r
269   </register>\r
270   <register id="CTRL_CORE_TEMP_SENSOR_CORE" acronym="CTRL_CORE_TEMP_SENSOR_CORE" offset="0x334" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">\r
271     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
272     <bitfield id="BGAP_TMPSOFF_CORE" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>\r
273     <bitfield id="BGAP_EOCZ_CORE" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_CORE is valid." range="" rwaccess="R"/>\r
274     <bitfield id="BGAP_DTEMP_CORE" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>\r
275   </register>\r
276   <register id="CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR" acronym="CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR" offset="0x358" width="32" description="Cortex M4 register">\r
277     <bitfield id="RESERVED" width="12" begin="31" end="20" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
278     <bitfield id="CORTEX_M4_MMUADDRTRANSLTR" width="20" begin="19" end="0" resetval="0x0" description="Used to save the mmu address boot" range="" rwaccess="RW"/>\r
279   </register>\r
280   <register id="CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR" acronym="CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR" offset="0x35C" width="32" description="">\r
281     <bitfield id="RESERVED" width="12" begin="31" end="20" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
282     <bitfield id="CORTEX_M4_MMUADDRLOGICTR" width="20" begin="19" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>\r
283   </register>\r
284   <register id="CTRL_CORE_HWOBS_CONTROL" acronym="CTRL_CORE_HWOBS_CONTROL" offset="0x360" width="32" description="HW observability control. This register enables or disables HW observability outputs (to save power primarily)">\r
285     <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
286     <bitfield id="HWOBS_CLKDIV_SEL_2" width="5" begin="18" end="14" resetval="0x0" description="Clock divider selection on po_hwobs(2). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" range="" rwaccess="RW"/>\r
287     <bitfield id="HWOBS_CLKDIV_SEL_1" width="5" begin="13" end="9" resetval="0x0" description="Clock divider selection on po_hwobs(1). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" range="" rwaccess="RW"/>\r
288     <bitfield id="RESERVED" width="1" begin="8" end="8" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
289     <bitfield id="HWOBS_CLKDIV_SEL" width="5" begin="7" end="3" resetval="0x0" description="Clock divider selection on po_hwobs(0). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" range="" rwaccess="RW"/>\r
290     <bitfield id="HWOBS_ALL_ZERO_MODE" width="1" begin="2" end="2" resetval="0x0" description="Used to gate observable signals. When set all outputs are set to zero (can be used to check the path from HW observability to external pads). 0x0 = hw observability ports are not gated 0x1 = hw observability ports are all set to 0" range="" rwaccess="RW"/>\r
291     <bitfield id="HWOBS_ALL_ONE_MODE" width="1" begin="1" end="1" resetval="0x0" description="Used to gate observable signals. When set all outputs are set to one (can be used to check the path from HW observability to external pads). 0x0 = hw observability ports are not gated 0x1 = hw observability ports are all set to 1" range="" rwaccess="RW"/>\r
292     <bitfield id="HWOBS_MACRO_ENABLE" width="1" begin="0" end="0" resetval="0x0" description="Used to gate observable signals coming from macros using the 32:bit HWOBS bus definition. When deasserted all outputs of the HWOBS busdef are set to zero. 0x0 = hw observability ports from macros are gated and set to zero 0x1 = hw observability ports from macros are not gated" range="" rwaccess="RW"/>\r
293   </register>\r
294   <register id="CTRL_CORE_PCS1" acronym="CTRL_CORE_PCS1" offset="0x364" width="32" description="pcs1">\r
295     <bitfield id="USB_TEST_TXDATA" width="10" begin="31" end="22" resetval="0x0" description="" range="" rwaccess="RW"/>\r
296     <bitfield id="USB_ERR_USB_BIT_EN" width="10" begin="21" end="12" resetval="0x0" description="" range="" rwaccess="RW"/>\r
297     <bitfield id="USB_CFG_HOLDOFF" width="8" begin="11" end="4" resetval="0x0" description="" range="" rwaccess="RW"/>\r
298     <bitfield id="USB_DET_DELAY" width="4" begin="3" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>\r
299   </register>\r
300   <register id="CTRL_CORE_PCS2" acronym="CTRL_CORE_PCS2" offset="0x368" width="32" description="pcs2">\r
301     <bitfield id="USB_CFG_SYNC" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="RW"/>\r
302     <bitfield id="USB_CFG_EQ_FUNC" width="4" begin="26" end="23" resetval="0x0" description="" range="" rwaccess="RW"/>\r
303     <bitfield id="USB_CFG_EQ_HOLD" width="4" begin="22" end="19" resetval="0x0" description="" range="" rwaccess="RW"/>\r
304     <bitfield id="USB_CFG_EQ_INIT" width="4" begin="18" end="15" resetval="0x0" description="" range="" rwaccess="RW"/>\r
305     <bitfield id="USB_TEST_OSEL" width="3" begin="14" end="12" resetval="0x0" description="" range="" rwaccess="RW"/>\r
306     <bitfield id="USB_RC_DELAY" width="2" begin="11" end="10" resetval="0x0" description="" range="" rwaccess="RW"/>\r
307     <bitfield id="USB_TEST_LSEL" width="1" begin="9" end="9" resetval="0x0" description="" range="" rwaccess="RW"/>\r
308     <bitfield id="RESERVED" width="1" begin="8" end="8" resetval="0x0" description="" range="" rwaccess="R"/>\r
309     <bitfield id="USB_ERR_USB_MODE" width="2" begin="7" end="6" resetval="0x0" description="" range="" rwaccess="RW"/>\r
310     <bitfield id="USB_L1_SLEEP" width="1" begin="5" end="5" resetval="0x0" description="" range="" rwaccess="RW"/>\r
311     <bitfield id="USB_TEST_MODE" width="1" begin="4" end="4" resetval="0x0" description="" range="" rwaccess="RW"/>\r
312     <bitfield id="USB_ERR_USB_LN_EN" width="1" begin="3" end="3" resetval="0x0" description="" range="" rwaccess="RW"/>\r
313     <bitfield id="RESERVED" width="2" begin="2" end="1" resetval="0x0" description="" range="" rwaccess="R"/>\r
314     <bitfield id="USB_SHORT_TIMES" width="1" begin="0" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>\r
315   </register>\r
316   <register id="CTRL_CORE_PCS_REVISION" acronym="CTRL_CORE_PCS_REVISION" offset="0x36C" width="32" description="pcs_revision">\r
317     <bitfield id="USB_REVISION" width="3" begin="31" end="29" resetval="0x0" description="" range="" rwaccess="R"/>\r
318     <bitfield id="RESERVED" width="29" begin="28" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
319   </register>\r
320   <register id="CTRL_CORE_PHY_POWER_USB" acronym="CTRL_CORE_PHY_POWER_USB" offset="0x370" width="32" description="phy_power_usb">\r
321     <bitfield id="USB_PWRCTL_CLK_FREQ" width="10" begin="31" end="22" resetval="0x0" description="Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." range="" rwaccess="RW"/>\r
322     <bitfield id="USB_PWRCTL_CLK_CMD" width="8" begin="21" end="14" resetval="0x0" description="Powers up/down the USB3_PHY_TX and USB3_PHY_RX modules. This bit field is also used for partially power down these TX and RX modules. Each bit has the following meaning: Bit[14] - 0x1: Powers-up the USB3_PHY_RX Bit[15] - 0x1: Powers-up the USB3_PHY_TX Bit[16] - A don&#8217;t care bit. Not used. Bit[17] - A don&#8217;t care bit. Not used. Bit[18] - 0x1: Disables the synchronized power-up of USB3_PHY_TX with USB3_PHY_RX. The TX power-up is independent of the RX power-up. Bit[19] - 0x1: Disables the automatic power-cycling of USB3_PHY_RX in P3 power state when PLL_CLK stops and starts. Bit[20] - 0x1: Partially powers-down the USB3_PHY_RX when it is in P3 power state. DCC, Phase interpolator, Equalizer are disabled. Bit[21] - A don&#8217;t care bit. Not used." range="" rwaccess="RW"/>\r
323     <bitfield id="RESERVED" width="14" begin="13" end="0" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
324   </register>\r
325   <register id="CTRL_CORE_PHY_POWER_SATA" acronym="CTRL_CORE_PHY_POWER_SATA" offset="0x374" width="32" description="phy_power_sata">\r
326     <bitfield id="SATA_PWRCTL_CLK_FREQ" width="10" begin="31" end="22" resetval="0x0" description="Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." range="" rwaccess="RW"/>\r
327     <bitfield id="SATA_PWRCTL_CLK_CMD" width="8" begin="21" end="14" resetval="0x0" description="Powers up/down the SATA_PHY_TX and SATA_PHY_RX modules. 0x0: Powers down SATA_PHY_TX and SATA_PHY_RX 0x1: Powers up SATA_PHY_RX 0x2: Powers up SATA_PHY_TX 0x3: Powers up SATA_PHY_TX and SATA_PHY_RX0x4-0xFF: Reserved" range="" rwaccess="RW"/>\r
328     <bitfield id="RESERVED" width="14" begin="13" end="0" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
329   </register>\r
330   <register id="CTRL_CORE_BANDGAP_MASK_1" acronym="CTRL_CORE_BANDGAP_MASK_1" offset="0x380" width="32" description="bgap_mask">\r
331     <bitfield id="SIDLEMODE" width="2" begin="31" end="30" resetval="0x0" description="sidlemode for bandgap 0x0 = No Idle 0x1 = Force Idle 0x2 = Smart Idle 0x3 = Reserved" range="" rwaccess="RW"/>\r
332     <bitfield id="COUNTER_DELAY" width="3" begin="29" end="27" resetval="0x0" description="Counter delay 0x0 = Imediat 0x1 = Delay of 1ms 0x2 = Delay of 10ms 0x3 = Delay of 100ms 0x4 = Delay of 250ms 0x5 = Delay of 500ms" range="" rwaccess="RW"/>\r
333     <bitfield id="RESERVED" width="3" begin="26" end="24" resetval="0x0" description="" range="" rwaccess="R"/>\r
334     <bitfield id="FREEZE_CORE" width="1" begin="23" end="23" resetval="0x0" description="Freeze the FIFO CORE 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>\r
335     <bitfield id="FREEZE_GPU" width="1" begin="22" end="22" resetval="0x0" description="Freeze the FIFO GPU 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>\r
336     <bitfield id="FREEZE_MPU" width="1" begin="21" end="21" resetval="0x0" description="Freeze the FIFO MPU 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>\r
337     <bitfield id="CLEAR_CORE" width="1" begin="20" end="20" resetval="0x0" description="Reset the FIFO CORE 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>\r
338     <bitfield id="CLEAR_GPU" width="1" begin="19" end="19" resetval="0x0" description="Reset the FIFO GPU 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>\r
339     <bitfield id="CLEAR_MPU" width="1" begin="18" end="18" resetval="0x0" description="Reset the FIFO MPU 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>\r
340     <bitfield id="RESERVED" width="12" begin="17" end="6" resetval="0x0" description="" range="" rwaccess="R"/>\r
341     <bitfield id="MASK_HOT_CORE" width="1" begin="5" end="5" resetval="0x0" description="Mask for hot event CORE 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>\r
342     <bitfield id="MASK_COLD_CORE" width="1" begin="4" end="4" resetval="0x0" description="Mask for cold event CORE 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>\r
343     <bitfield id="MASK_HOT_GPU" width="1" begin="3" end="3" resetval="0x0" description="Mask for hot event GPU 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>\r
344     <bitfield id="MASK_COLD_GPU" width="1" begin="2" end="2" resetval="0x0" description="Mask for cold event GPU 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>\r
345     <bitfield id="MASK_HOT_MPU" width="1" begin="1" end="1" resetval="0x0" description="Mask for hot event MPU 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>\r
346     <bitfield id="MASK_COLD_MPU" width="1" begin="0" end="0" resetval="0x0" description="Mask for cold event MPU 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>\r
347   </register>\r
348   <register id="CTRL_CORE_BANDGAP_THRESHOLD_MPU" acronym="CTRL_CORE_BANDGAP_THRESHOLD_MPU" offset="0x384" width="32" description="BGAP THRESHOLD MPU">\r
349     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
350     <bitfield id="THOLD_HOT_MPU" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in" range="" rwaccess="RW"/>\r
351     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
352     <bitfield id="THOLD_COLD_MPU" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in" range="" rwaccess="RW"/>\r
353   </register>\r
354   <register id="CTRL_CORE_BANDGAP_THRESHOLD_GPU" acronym="CTRL_CORE_BANDGAP_THRESHOLD_GPU" offset="0x388" width="32" description="BGAP THRESHOLD MM">\r
355     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
356     <bitfield id="THOLD_HOT_GPU" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in" range="" rwaccess="RW"/>\r
357     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
358     <bitfield id="THOLD_COLD_GPU" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in" range="" rwaccess="RW"/>\r
359   </register>\r
360   <register id="CTRL_CORE_BANDGAP_THRESHOLD_CORE" acronym="CTRL_CORE_BANDGAP_THRESHOLD_CORE" offset="0x38C" width="32" description="BGAP THRESHOLD CORE">\r
361     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
362     <bitfield id="THOLD_HOT_CORE" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in" range="" rwaccess="RW"/>\r
363     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
364     <bitfield id="THOLD_COLD_CORE" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in" range="" rwaccess="RW"/>\r
365   </register>\r
366   <register id="CTRL_CORE_BANDGAP_TSHUT_MPU" acronym="CTRL_CORE_BANDGAP_TSHUT_MPU" offset="0x390" width="32" description="BGAP TSHUT THRESHOLD MPU">\r
367     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>\r
368     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
369     <bitfield id="TSHUT_HOT_MPU" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>\r
370     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
371     <bitfield id="TSHUT_COLD_MPU" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>\r
372   </register>\r
373   <register id="CTRL_CORE_BANDGAP_TSHUT_GPU" acronym="CTRL_CORE_BANDGAP_TSHUT_GPU" offset="0x394" width="32" description="BGAP TSHUT THRESHOLD GPU">\r
374     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>\r
375     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
376     <bitfield id="TSHUT_HOT_GPU" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>\r
377     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
378     <bitfield id="TSHUT_COLD_GPU" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>\r
379   </register>\r
380   <register id="CTRL_CORE_BANDGAP_TSHUT_CORE" acronym="CTRL_CORE_BANDGAP_TSHUT_CORE" offset="0x398" width="32" description="BGAP TSHUT THRESHOLD CORE">\r
381     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>\r
382     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
383     <bitfield id="TSHUT_HOT_CORE" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>\r
384     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
385     <bitfield id="TSHUT_COLD_CORE" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>\r
386   </register>\r
387   <register id="CTRL_CORE_BANDGAP_STATUS_1" acronym="CTRL_CORE_BANDGAP_STATUS_1" offset="0x3A8" width="32" description="BGAP STATUS">\r
388     <bitfield id="ALERT" width="1" begin="31" end="31" resetval="0x0" description="Alert temperature when '1'" range="" rwaccess="R"/>\r
389     <bitfield id="RESERVED" width="25" begin="30" end="6" resetval="0x0" description="" range="" rwaccess="R"/>\r
390     <bitfield id="HOT_CORE" width="1" begin="5" end="5" resetval="0x0" description="Event for hot temperature mpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>\r
391     <bitfield id="COLD_CORE" width="1" begin="4" end="4" resetval="0x0" description="Event for cold temperature mpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>\r
392     <bitfield id="HOT_GPU" width="1" begin="3" end="3" resetval="0x0" description="Event for hot temperature gpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>\r
393     <bitfield id="COLD_GPU" width="1" begin="2" end="2" resetval="0x0" description="Event for cold temperature gpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>\r
394     <bitfield id="HOT_MPU" width="1" begin="1" end="1" resetval="0x0" description="Event for hot temperature core bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>\r
395     <bitfield id="COLD_MPU" width="1" begin="0" end="0" resetval="0x0" description="Event for cold temperature core bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>\r
396   </register>\r
397   <register id="CTRL_CORE_SATA_EXT_MODE" acronym="CTRL_CORE_SATA_EXT_MODE" offset="0x3AC" width="32" description="SATA EXTENDED MODE">\r
398     <bitfield id="RESERVED" width="31" begin="31" end="1" resetval="0x0" description="" range="" rwaccess="R"/>\r
399     <bitfield id="SATA_EXTENDED_MODE" width="1" begin="0" end="0" resetval="0x0" description="sata extended mode 0x0 = no extended mode 0x1 = extended mode" range="" rwaccess="RW"/>\r
400   </register>\r
401   <register id="CTRL_CORE_DTEMP_MPU_0" acronym="CTRL_CORE_DTEMP_MPU_0" offset="0x3C0" width="32" description="TAGGED TEMPERATURE MPU DOMAIN. Most recent sample">\r
402     <bitfield id="DTEMP_TAG_MPU_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
403     <bitfield id="DTEMP_TEMPERATURE_MPU_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
404   </register>\r
405   <register id="CTRL_CORE_DTEMP_MPU_1" acronym="CTRL_CORE_DTEMP_MPU_1" offset="0x3C4" width="32" description="TAGGED TEMPERATURE MPU DOMAIN">\r
406     <bitfield id="DTEMP_TAG_MPU_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
407     <bitfield id="DTEMP_TEMPERATURE_MPU_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
408   </register>\r
409   <register id="CTRL_CORE_DTEMP_MPU_2" acronym="CTRL_CORE_DTEMP_MPU_2" offset="0x3C8" width="32" description="TAGGED TEMPERATURE MPU DOMAIN">\r
410     <bitfield id="DTEMP_TAG_MPU_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
411     <bitfield id="DTEMP_TEMPERATURE_MPU_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
412   </register>\r
413   <register id="CTRL_CORE_DTEMP_MPU_3" acronym="CTRL_CORE_DTEMP_MPU_3" offset="0x3CC" width="32" description="TAGGED TEMPERATURE MPU DOMAIN">\r
414     <bitfield id="DTEMP_TAG_MPU_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
415     <bitfield id="DTEMP_TEMPERATURE_MPU_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
416   </register>\r
417   <register id="CTRL_CORE_DTEMP_MPU_4" acronym="CTRL_CORE_DTEMP_MPU_4" offset="0x3D0" width="32" description="TAGGED TEMPERATURE MPU DOMAIN. Oldest sample">\r
418     <bitfield id="DTEMP_TAG_MPU_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
419     <bitfield id="DTEMP_TEMPERATURE_MPU_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
420   </register>\r
421   <register id="CTRL_CORE_DTEMP_GPU_0" acronym="CTRL_CORE_DTEMP_GPU_0" offset="0x3D4" width="32" description="TAGGED TEMPERATURE GPU DOMAIN. Most recent sample.">\r
422     <bitfield id="DTEMP_TAG_GPU_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
423     <bitfield id="DTEMP_TEMPERATURE_GPU_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
424   </register>\r
425   <register id="CTRL_CORE_DTEMP_GPU_1" acronym="CTRL_CORE_DTEMP_GPU_1" offset="0x3D8" width="32" description="TAGGED TEMPERATURE GPU DOMAIN.">\r
426     <bitfield id="DTEMP_TAG_GPU_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
427     <bitfield id="DTEMP_TEMPERATURE_GPU_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
428   </register>\r
429   <register id="CTRL_CORE_DTEMP_GPU_2" acronym="CTRL_CORE_DTEMP_GPU_2" offset="0x3DC" width="32" description="TAGGED TEMPERATURE GPU DOMAIN.">\r
430     <bitfield id="DTEMP_TAG_GPU_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
431     <bitfield id="DTEMP_TEMPERATURE_GPU_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
432   </register>\r
433   <register id="CTRL_CORE_DTEMP_GPU_3" acronym="CTRL_CORE_DTEMP_GPU_3" offset="0x3E0" width="32" description="TAGGED TEMPERATURE GPU DOMAIN.">\r
434     <bitfield id="DTEMP_TAG_GPU_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
435     <bitfield id="DTEMP_TEMPERATURE_GPU_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
436   </register>\r
437   <register id="CTRL_CORE_DTEMP_GPU_4" acronym="CTRL_CORE_DTEMP_GPU_4" offset="0x3E4" width="32" description="TAGGED TEMPERATURE GPU DOMAIN. Oldest sample.">\r
438     <bitfield id="DTEMP_TAG_GPU_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
439     <bitfield id="DTEMP_TEMPERATURE_GPU_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
440   </register>\r
441   <register id="CTRL_CORE_DTEMP_CORE_0" acronym="CTRL_CORE_DTEMP_CORE_0" offset="0x3E8" width="32" description="TAGGED TEMPERATURE CORE DOMAIN. Most recent sample.">\r
442     <bitfield id="DTEMP_TAG_CORE_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
443     <bitfield id="DTEMP_TEMPERATURE_CORE_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
444   </register>\r
445   <register id="CTRL_CORE_DTEMP_CORE_1" acronym="CTRL_CORE_DTEMP_CORE_1" offset="0x3EC" width="32" description="TAGGED TEMPERATURE CORE DOMAIN">\r
446     <bitfield id="DTEMP_TAG_CORE_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
447     <bitfield id="DTEMP_TEMPERATURE_CORE_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
448   </register>\r
449   <register id="CTRL_CORE_DTEMP_CORE_2" acronym="CTRL_CORE_DTEMP_CORE_2" offset="0x3F0" width="32" description="TAGGED TEMPERATURE CORE DOMAIN">\r
450     <bitfield id="DTEMP_TAG_CORE_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
451     <bitfield id="DTEMP_TEMPERATURE_CORE_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
452   </register>\r
453   <register id="CTRL_CORE_DTEMP_CORE_3" acronym="CTRL_CORE_DTEMP_CORE_3" offset="0x3F4" width="32" description="TAGGED TEMPERATURE CORE DOMAIN">\r
454     <bitfield id="DTEMP_TAG_CORE_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
455     <bitfield id="DTEMP_TEMPERATURE_CORE_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
456   </register>\r
457   <register id="CTRL_CORE_DTEMP_CORE_4" acronym="CTRL_CORE_DTEMP_CORE_4" offset="0x3F8" width="32" description="TAGGED TEMPERATURE CORE DOMAIN. Oldest sample.">\r
458     <bitfield id="DTEMP_TAG_CORE_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
459     <bitfield id="DTEMP_TEMPERATURE_CORE_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
460   </register>\r
461   <register id="CTRL_CORE_SMA_SW_0" acronym="CTRL_CORE_SMA_SW_0" offset="0x3FC" width="32" description="OCP Spare Register">\r
462     <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x0" description="" range="" rwaccess="R"/>\r
463     <bitfield id="SATA_PLL_SOFT_RESET" width="1" begin="18" end="18" resetval="0x0" description="Software reset control for SATA PLL" range="" rwaccess="RW"/>\r
464     <bitfield id="RESERVED" width="15" begin="17" end="3" resetval="0x0" description="" range="" rwaccess="R"/>\r
465     <bitfield id="ISOLATE" width="1" begin="2" end="2" resetval="0x0" description="This bit is used during the isolation/de-isolation sequence described in, ." range="" rwaccess="RW"/>\r
466     <bitfield id="EMIF2_CKE_GATING_CTRL" width="1" begin="1" end="1" resetval="0x0" description="Forces the EMIF2 CKE pad to tri-state. 0x0: The CKE pad is not in tri-state and can be controlled by EMIF2 0x1: The CKE pad is in tri-state" range="" rwaccess="RW"/>\r
467     <bitfield id="EMIF1_CKE_GATING_CTRL" width="1" begin="0" end="0" resetval="0x0" description="Forces the EMIF1 CKE pad to tri-state. 0x0: The CKE pad is not in tri-state and can be controlled by EMIF1 0x1: The CKE pad is in tri-state" range="" rwaccess="RW"/>\r
468   </register>\r
469   <register id="CTRL_CORE_SEC_ERR_STATUS_FUNC_2" acronym="CTRL_CORE_SEC_ERR_STATUS_FUNC_2" offset="0x414" width="32" description="Firewall Error Status functional Register 2">\r
470     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
471     <bitfield id="TC1_EDMA_FW_ERROR" width="1" begin="26" end="26" resetval="0x0" description="EDMA TC1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
472     <bitfield id="RESERVED" width="3" begin="25" end="23" resetval="0x0" description="" range="" rwaccess="R"/>\r
473     <bitfield id="QSPI_FW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="QSPI firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
474     <bitfield id="RESERVED" width="4" begin="21" end="18" resetval="0x0" description="" range="" rwaccess="R"/>\r
475     <bitfield id="TPCC_EDMA_FW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="EDMA TPCC firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
476     <bitfield id="TC0_EDMA_FW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="EDMA TC0 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
477     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
478     <bitfield id="MCASP3_FW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="McASP3 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
479     <bitfield id="MCASP2_FW_ERROR" width="1" begin="12" end="12" resetval="0x0" description="McASP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
480     <bitfield id="MCASP1_FW_ERROR" width="1" begin="11" end="11" resetval="0x0" description="McASP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
481     <bitfield id="VCP2_FW_ERROR" width="1" begin="10" end="10" resetval="0x0" description="VCP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
482     <bitfield id="VCP1_FW_ERROR" width="1" begin="9" end="9" resetval="0x0" description="VCP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
483     <bitfield id="PCIESS2_FW_ERROR" width="1" begin="8" end="8" resetval="0x0" description="PCIeSS2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
484     <bitfield id="PCIESS1_FW_ERROR" width="1" begin="7" end="7" resetval="0x0" description="PCIeSS1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
485     <bitfield id="IPU2_FW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IPU2 firewall. 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
486     <bitfield id="L4_PERIPH3_FW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="L4 periph3 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
487     <bitfield id="L4_PERIPH2_FW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="L4 periph2 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
488     <bitfield id="L3RAM3_FW_ERROR" width="1" begin="3" end="3" resetval="0x0" description="L3RAM3 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
489     <bitfield id="L3RAM2_FW_ERROR" width="1" begin="2" end="2" resetval="0x0" description="L3RAM2 target firewall. 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
490     <bitfield id="DSP2_FW_ERROR" width="1" begin="1" end="1" resetval="0x0" description="DSP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
491     <bitfield id="DSP1_FW_ERROR" width="1" begin="0" end="0" resetval="0x0" description="DSP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
492   </register>\r
493   <register id="CTRL_CORE_SEC_ERR_STATUS_DEBUG_2" acronym="CTRL_CORE_SEC_ERR_STATUS_DEBUG_2" offset="0x41C" width="32" description="Firewall Error Status debug Register 2">\r
494     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
495     <bitfield id="TC1_EDMA_DBGFW_ERROR" width="1" begin="26" end="26" resetval="0x0" description="EDMA TC1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
496     <bitfield id="RESERVED" width="3" begin="25" end="23" resetval="0x0" description="" range="" rwaccess="R"/>\r
497     <bitfield id="QSPI_DBGFW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="QSPI debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
498     <bitfield id="RESERVED" width="4" begin="21" end="18" resetval="0x0" description="" range="" rwaccess="R"/>\r
499     <bitfield id="TPCC_EDMA_DBGFW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="EDMA TPCC debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
500     <bitfield id="TC0_EDMA_DBGFW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="EDMA TC0 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
501     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
502     <bitfield id="MCASP3_DBGFW_ERROR" width="1" begin="13" end="13" resetval="0x0" description="McASP3 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
503     <bitfield id="MCASP2_DBGFW_ERROR" width="1" begin="12" end="12" resetval="0x0" description="McASP2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
504     <bitfield id="MCASP1_DBGFW_ERROR" width="1" begin="11" end="11" resetval="0x0" description="McASP1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
505     <bitfield id="VCP2_DBGFW_ERROR" width="1" begin="10" end="10" resetval="0x0" description="VCP2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
506     <bitfield id="VCP1_DBGFW_ERROR" width="1" begin="9" end="9" resetval="0x0" description="VCP1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
507     <bitfield id="PCIESS2_DBGFW_ERROR" width="1" begin="8" end="8" resetval="0x0" description="PCIeSS2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
508     <bitfield id="PCIESS1_DBGFW_ERROR" width="1" begin="7" end="7" resetval="0x0" description="PCIeSS1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
509     <bitfield id="IPU2_DBGFW_ERROR" width="1" begin="6" end="6" resetval="0x0" description="IPU2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
510     <bitfield id="L4_PERIPH3_DBGFW_ERROR" width="1" begin="5" end="5" resetval="0x0" description="L4 periph3 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
511     <bitfield id="L4_PERIPH2_DBGFW_ERROR" width="1" begin="4" end="4" resetval="0x0" description="L4 periph2 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
512     <bitfield id="L3RAM3_DBGFW_ERROR" width="1" begin="3" end="3" resetval="0x0" description="L3RAM3 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
513     <bitfield id="L3RAM2_DBGFW_ERROR" width="1" begin="2" end="2" resetval="0x0" description="L3RAM2 target debug firewall. 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
514     <bitfield id="DSP2_DBGFW_ERROR" width="1" begin="1" end="1" resetval="0x0" description="DSP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
515     <bitfield id="DSP1_DBGFW_ERROR" width="1" begin="0" end="0" resetval="0x0" description="DSP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
516   </register>\r
517   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_1" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_1" offset="0x420" width="32" description="Register for priority settings for EMIF arbitration">\r
518     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>\r
519     <bitfield id="MPU_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="MPU priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
520     <bitfield id="RESERVED" width="9" begin="27" end="19" resetval="0x88" description="" range="" rwaccess="R"/>\r
521     <bitfield id="DSP1_MDMA_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="DSP1 MDMA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
522     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>\r
523     <bitfield id="DSP1_CFG_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="DSP1 CFG priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
524     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
525     <bitfield id="DSP1_EDMA_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="DSP1 EDMA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
526     <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>\r
527     <bitfield id="DSP2_EDMA_EMIF_PRIORITY" width="3" begin="6" end="4" resetval="0x4" description="DSP2 EDMA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
528     <bitfield id="RESERVED" width="1" begin="3" end="3" resetval="0x0" description="" range="" rwaccess="R"/>\r
529     <bitfield id="DSP2_CFG_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="DSP2 CFG priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
530   </register>\r
531   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_2" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_2" offset="0x424" width="32" description="Register for priority settings for EMIF arbitration">\r
532     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>\r
533     <bitfield id="DSP2_MDMA_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="DSP2 MDMA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
534     <bitfield id="RESERVED" width="1" begin="27" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
535     <bitfield id="IVA_ICONT1_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="IVA ICONT1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
536     <bitfield id="RESERVED" width="5" begin="23" end="19" resetval="0x0" description="" range="" rwaccess="R"/>\r
537     <bitfield id="EVE1_TC0_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="EVE1 TC0 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
538     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>\r
539     <bitfield id="EVE2_TC0_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="EVE2 TC0 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
540     <bitfield id="RESERVED" width="12" begin="11" end="0" resetval="0x444" description="" range="" rwaccess="R"/>\r
541   </register>\r
542   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_3" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_3" offset="0x428" width="32" description="Register for priority settings for EMIF arbitration">\r
543     <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x888" description="" range="" rwaccess="R"/>\r
544     <bitfield id="IPU1_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="IPU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW"/>\r
545     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>\r
546     <bitfield id="IPU2_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="IPU2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
547     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
548     <bitfield id="DMA_SYSTEM_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="DMA SYSTEM priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
549     <bitfield id="RESERVED" width="5" begin="7" end="3" resetval="0x8" description="" range="" rwaccess="R"/>\r
550     <bitfield id="EDMA_TC0_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="EDMA TC0 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
551   </register>\r
552   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_4" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_4" offset="0x42C" width="32" description="Register for priority settings for EMIF arbitration">\r
553     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>\r
554     <bitfield id="EDMA_TC1_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="EDMA TC1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
555     <bitfield id="RESERVED" width="1" begin="27" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
556     <bitfield id="DSS_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="DSS priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
557     <bitfield id="RESERVED" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="R"/>\r
558     <bitfield id="MLB_MMU1_EMIF_PRIORITY" width="3" begin="22" end="20" resetval="0x4" description="MLB, MMU1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
559     <bitfield id="RESERVED" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="R"/>\r
560     <bitfield id="PCIESS1_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="PCIeSS1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
561     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>\r
562     <bitfield id="PCIESS2_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="PCIeSS2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
563     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
564     <bitfield id="VIP1_P1_P2_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="VIP1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
565     <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>\r
566     <bitfield id="VIP2_P1_P2_EMIF_PRIORITY" width="3" begin="6" end="4" resetval="0x4" description="VIP2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
567     <bitfield id="RESERVED" width="1" begin="3" end="3" resetval="0x0" description="" range="" rwaccess="R"/>\r
568     <bitfield id="VIP3_P1_P2_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="VIP3 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
569   </register>\r
570   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_5" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_5" offset="0x430" width="32" description="Register for priority settings for EMIF arbitration">\r
571     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>\r
572     <bitfield id="VPE_P1_P2_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="VPE priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
573     <bitfield id="RESERVED" width="1" begin="27" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
574     <bitfield id="MMC1_GPU_P1_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="MMC1, GPU P1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
575     <bitfield id="RESERVED" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="R"/>\r
576     <bitfield id="MMC2_GPU_P2_EMIF_PRIORITY" width="3" begin="22" end="20" resetval="0x4" description="MMC2, GPU P2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
577     <bitfield id="RESERVED" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="R"/>\r
578     <bitfield id="BB2D_P1_P2_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="BB2D priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
579     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>\r
580     <bitfield id="GMAC_SW_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="GMAC_SW priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
581     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
582     <bitfield id="USB1_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="USB1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
583     <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>\r
584     <bitfield id="USB2_EMIF_PRIORITY" width="3" begin="6" end="4" resetval="0x4" description="USB2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
585     <bitfield id="RESERVED" width="1" begin="3" end="3" resetval="0x0" description="" range="" rwaccess="R"/>\r
586     <bitfield id="USB3_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="USB3 priority setting 0x0 = highest priority 0x7 = lowest priorty" range="" rwaccess="RW"/>\r
587   </register>\r
588   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_6" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_6" offset="0x434" width="32" description="Register for priority settings for EMIF arbitration">\r
589     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>\r
590     <bitfield id="USB4_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="USB4 priority setting 0x0 = highest priority 0x7 = lowest prority" range="" rwaccess="RW"/>\r
591     <bitfield id="RESERVED" width="13" begin="27" end="15" resetval="0x888" description="" range="" rwaccess="R"/>\r
592     <bitfield id="SATA_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="SATA priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
593     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
594     <bitfield id="EVE1_TC1_EMIF_PRIORITY" width="3" begin="10" end="8" resetval="0x4" description="EVE1 TC1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
595     <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>\r
596     <bitfield id="EVE2_TC1_EMIF_PRIORITY" width="3" begin="6" end="4" resetval="0x4" description="EVE2 TC1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
597     <bitfield id="RESERVED" width="4" begin="3" end="0" resetval="0x4" description="" range="" rwaccess="R"/>\r
598   </register>\r
599   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_1" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_1" offset="0x43C" width="32" description="Register for pressure settings for L3 arbitration">\r
600     <bitfield id="RESERVED" width="4" begin="31" end="28" resetval="0x0" description="" range="" rwaccess="R"/>\r
601     <bitfield id="MPU_L3_PRESSURE" width="2" begin="27" end="26" resetval="0x0" description="MPU pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
602     <bitfield id="RESERVED" width="7" begin="25" end="19" resetval="0x0" description="" range="" rwaccess="R"/>\r
603     <bitfield id="DSP1_CFG_L3_PRESSURE" width="2" begin="18" end="17" resetval="0x0" description="DSP1 CFG pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
604     <bitfield id="RESERVED" width="6" begin="16" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
605     <bitfield id="DSP2_CFG_L3_PRESSURE" width="2" begin="10" end="9" resetval="0x0" description="DSP2 CFG pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
606     <bitfield id="RESERVED" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
607   </register>\r
608   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_2" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_2" offset="0x440" width="32" description="Register for pressure settings for L3 arbitration">\r
609     <bitfield id="RESERVED" width="18" begin="31" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
610     <bitfield id="IPU1_L3_PRESSURE" width="2" begin="13" end="12" resetval="0x0" description="IPU1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
611     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
612     <bitfield id="IPU2_L3_PRESSURE" width="2" begin="10" end="9" resetval="0x0" description="IPU2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
613     <bitfield id="RESERVED" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
614   </register>\r
615   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_4" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_4" offset="0x448" width="32" description="Register for pressure settings for L3 arbitration">\r
616     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
617     <bitfield id="GPU_P1_L3_PRESSURE" width="2" begin="24" end="23" resetval="0x0" description="GPU P1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
618     <bitfield id="RESERVED" width="1" begin="22" end="22" resetval="0x0" description="" range="" rwaccess="R"/>\r
619     <bitfield id="GPU_P2_L3_PRESSURE" width="2" begin="21" end="20" resetval="0x0" description="GPU P2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
620     <bitfield id="RESERVED" width="20" begin="19" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
621   </register>\r
622   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_5" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_5" offset="0x44C" width="32" description="Register for pressure settings for L3 arbitration">\r
623     <bitfield id="RESERVED" width="27" begin="31" end="5" resetval="0x0" description="" range="" rwaccess="R"/>\r
624     <bitfield id="SATA_L3_PRESSURE" width="2" begin="4" end="3" resetval="0x0" description="SATA pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
625     <bitfield id="RESERVED" width="1" begin="2" end="2" resetval="0x0" description="" range="" rwaccess="R"/>\r
626     <bitfield id="MMC1_L3_PRESSURE" width="2" begin="1" end="0" resetval="0x0" description="MMC1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
627   </register>\r
628   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_6" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_6" offset="0x450" width="32" description="Register for pressure settings for L3 arbitration">\r
629     <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x0" description="" range="" rwaccess="R"/>\r
630     <bitfield id="MMC2_L3_PRESSURE" width="2" begin="18" end="17" resetval="0x0" description="MMC2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
631     <bitfield id="USB1_L3_PRESSURE" width="2" begin="16" end="15" resetval="0x0" description="USB1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
632     <bitfield id="RESERVED" width="1" begin="14" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
633     <bitfield id="USB2_L3_PRESSURE" width="2" begin="13" end="12" resetval="0x0" description="USB2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
634     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
635     <bitfield id="USB3_L3_PRESSURE" width="2" begin="10" end="9" resetval="0x0" description="USB3 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
636     <bitfield id="RESERVED" width="1" begin="8" end="8" resetval="0x0" description="" range="" rwaccess="R"/>\r
637     <bitfield id="USB4_L3_PRESSURE" width="2" begin="7" end="6" resetval="0x0" description="USB4 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
638     <bitfield id="RESERVED" width="6" begin="5" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
639   </register>\r
640   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0" offset="0x458" width="32" description="Standard Fuse OPP VDD_iva [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
641     <bitfield id="STD_FUSE_OPP_VDD_IVA_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
642   </register>\r
643   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1" offset="0x45C" width="32" description="Standard Fuse OPP VDD_iva [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
644     <bitfield id="STD_FUSE_OPP_VDD_IVA_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
645   </register>\r
646   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2" offset="0x460" width="32" description="Standard Fuse OPP VDD_iva [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
647     <bitfield id="STD_FUSE_OPP_VDD_IVA_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
648   </register>\r
649   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3" offset="0x464" width="32" description="Standard Fuse OPP VDD_iva [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
650     <bitfield id="STD_FUSE_OPP_VDD_IVA_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
651   </register>\r
652   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4" offset="0x468" width="32" description="Standard Fuse OPP VDD_iva [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
653     <bitfield id="STD_FUSE_OPP_VDD_IVA_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
654   </register>\r
655   <register id="CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL" offset="0x46C" width="32" description="DSPEVE Voltage Body Bias LDO Control register">\r
656     <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
657     <bitfield id="LDOVBBDSPEVE_FBB_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Forward Body Bias voltage value 0x0 = efuse value is used 0x1 = override value is used" range="" rwaccess="RW"/>\r
658     <bitfield id="LDOVBBDSPEVE_FBB_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Forward Body Bias voltage value" range="" rwaccess="R"/>\r
659     <bitfield id="LDOVBBDSPEVE_FBB_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_x[24:20] VSETABB bit fields. This value applies if LDOVBBDSPEVE_FBB_MUX_CTRL is set to 0x1." range="" rwaccess="RW"/>\r
660   </register>\r
661   <register id="CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL" offset="0x470" width="32" description="IVA Voltage Body Bias LDO Control register">\r
662     <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
663     <bitfield id="LDOVBBIVA_FBB_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Forward Body Bias voltage value 0x0 = efuse value is used 0x1 = override value is used" range="" rwaccess="RW"/>\r
664     <bitfield id="LDOVBBIVA_FBB_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Forward Body Bias voltage value" range="" rwaccess="R"/>\r
665     <bitfield id="LDOVBBIVA_FBB_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_x[24:20] VSETABB bit fields. This value applies if LDOVBBIVA_FBB_MUX_CTRL is set to 0x1." range="" rwaccess="RW"/>\r
666   </register>\r
667   <register id="CTRL_CORE_CUST_FUSE_UID_0" acronym="CTRL_CORE_CUST_FUSE_UID_0" offset="0x4E8" width="32" description="Customer Fuse keys. UID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
668     <bitfield id="CUST_FUSE_UID_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
669   </register>\r
670   <register id="CTRL_CORE_CUST_FUSE_UID_1" acronym="CTRL_CORE_CUST_FUSE_UID_1" offset="0x4EC" width="32" description="Customer Fuse keys. UID [063:032] (16 bits upper Redundant field) [FIELD F]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
671     <bitfield id="CUST_FUSE_UID_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
672   </register>\r
673   <register id="CTRL_CORE_CUST_FUSE_UID_2" acronym="CTRL_CORE_CUST_FUSE_UID_2" offset="0x4F0" width="32" description="Customer Fuse keys. UID [095:064] (16 bits upper Redundant field) [FIELD E]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
674     <bitfield id="CUST_FUSE_UID_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
675   </register>\r
676   <register id="CTRL_CORE_CUST_FUSE_UID_3" acronym="CTRL_CORE_CUST_FUSE_UID_3" offset="0x4F4" width="32" description="Customer Fuse keys. UID [127:096] (16 bits upper Redundant field) [FIELD D]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
677     <bitfield id="CUST_FUSE_UID_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
678   </register>\r
679   <register id="CTRL_CORE_CUST_FUSE_UID_4" acronym="CTRL_CORE_CUST_FUSE_UID_4" offset="0x4F8" width="32" description="Customer Fuse keys. UID [159:127] (16 bits upper Redundant field) [FIELD C]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
680     <bitfield id="CUST_FUSE_UID_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
681   </register>\r
682   <register id="CTRL_CORE_CUST_FUSE_UID_5" acronym="CTRL_CORE_CUST_FUSE_UID_5" offset="0x4FC" width="32" description="Customer Fuse keys. UID [191:160] (16 bits upper Redundant field) [FIELD B]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
683     <bitfield id="CUST_FUSE_UID_5" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
684   </register>\r
685   <register id="CTRL_CORE_CUST_FUSE_UID_6" acronym="CTRL_CORE_CUST_FUSE_UID_6" offset="0x500" width="32" description="Customer Fuse keys. UID [223:192] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
686     <bitfield id="CUST_FUSE_UID_6" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
687   </register>\r
688   <register id="CTRL_CORE_CUST_FUSE_PCIE_ID_0" acronym="CTRL_CORE_CUST_FUSE_PCIE_ID_0" offset="0x508" width="32" description="Customer Fuse keys. PCIe ID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
689     <bitfield id="CUST_FUSE_PCIE_ID_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
690   </register>\r
691   <register id="CTRL_CORE_CUST_FUSE_USB_ID_0" acronym="CTRL_CORE_CUST_FUSE_USB_ID_0" offset="0x510" width="32" description="Customer Fuse keys. USB ID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
692     <bitfield id="CUST_FUSE_USB_ID_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
693   </register>\r
694   <register id="CTRL_CORE_MAC_ID_SW_0" acronym="CTRL_CORE_MAC_ID_SW_0" offset="0x514" width="32" description="Standard Fuse keys, MAC ID_1 [63:32].">\r
695     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
696     <bitfield id="STD_FUSE_MAC_ID_SW_0" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 0. Bits [23:16] contain the 4th octet of the MAC address. Bits [15:8] contain the 5th octet of the MAC address. Bits [7:0] contain the last (6th) octet of the MAC address." range="" rwaccess="R"/>\r
697   </register>\r
698   <register id="CTRL_CORE_MAC_ID_SW_1" acronym="CTRL_CORE_MAC_ID_SW_1" offset="0x518" width="32" description="Standard Fuse keys, MAC ID_1 [31:0].">\r
699     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
700     <bitfield id="STD_FUSE_MAC_ID_SW_1" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 0. Bits [23:16] contain the first octet of the MAC address. Bits [15:8] contain the second octet of the MAC address. Bits [7:0] contain the third octet of the MAC address." range="" rwaccess="R"/>\r
701   </register>\r
702   <register id="CTRL_CORE_MAC_ID_SW_2" acronym="CTRL_CORE_MAC_ID_SW_2" offset="0x51C" width="32" description="Standard Fuse keys, MAC ID_2 [63:32].">\r
703     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
704     <bitfield id="STD_FUSE_MAC_ID_SW_2" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 1. Bits [23:16] contain the 4th octet of the MAC address. Bits [15:8] contain the 5th octet of the MAC address. Bits [7:0] contain the last (6th) octet of the MAC address." range="" rwaccess="R"/>\r
705   </register>\r
706   <register id="CTRL_CORE_MAC_ID_SW_3" acronym="CTRL_CORE_MAC_ID_SW_3" offset="0x520" width="32" description="Standard Fuse keys, MAC ID_2 [31:0].">\r
707     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
708     <bitfield id="STD_FUSE_MAC_ID_SW_3" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 1. Bits [23:16] contain the first octet of the MAC address. Bits [15:8] contain the second octet of the MAC address. Bits [7:0] contain the third octet of the MAC address." range="" rwaccess="R"/>\r
709   </register>\r
710   <register id="CTRL_CORE_SMA_SW_1" acronym="CTRL_CORE_SMA_SW_1" offset="0x534" width="32" description="OCP Spare Register">\r
711     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
712     <bitfield id="DSS_CH2_ON_OFF" width="1" begin="24" end="24" resetval="0x0" description="DSS Channel 2 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH2_RF" range="" rwaccess="RW"/>\r
713     <bitfield id="DSS_CH1_ON_OFF" width="1" begin="23" end="23" resetval="0x0" description="DSS Channel 1 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH1_RF" range="" rwaccess="RW"/>\r
714     <bitfield id="DSS_CH0_ON_OFF" width="1" begin="22" end="22" resetval="0x0" description="DSS Channel 0 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH0_RF" range="" rwaccess="RW"/>\r
715     <bitfield id="DSS_CH2_IPC" width="1" begin="21" end="21" resetval="0x0" description="DSS Channel 2 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" range="" rwaccess="RW"/>\r
716     <bitfield id="DSS_CH1_IPC" width="1" begin="20" end="20" resetval="0x0" description="DSS Channel 1 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" range="" rwaccess="RW"/>\r
717     <bitfield id="DSS_CH0_IPC" width="1" begin="19" end="19" resetval="0x0" description="DSS Channel 0 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" range="" rwaccess="RW"/>\r
718     <bitfield id="DSS_CH2_RF" width="1" begin="18" end="18" resetval="0x0" description="DSS Channel 2 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH2_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH2_ON_OFF set to 1)" range="" rwaccess="RW"/>\r
719     <bitfield id="DSS_CH1_RF" width="1" begin="17" end="17" resetval="0x0" description="DSS Channel 1 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1)" range="" rwaccess="RW"/>\r
720     <bitfield id="DSS_CH0_RF" width="1" begin="16" end="16" resetval="0x0" description="DSS Channel 0 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1)" range="" rwaccess="RW"/>\r
721     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
722     <bitfield id="VIP3_CLK_INV_PORT_1A" width="1" begin="10" end="10" resetval="0x0" description="VIP3 Slice 1 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" range="" rwaccess="RW"/>\r
723     <bitfield id="VIP3_CLK_INV_PORT_2A" width="1" begin="9" end="9" resetval="0x0" description="VIP3 Slice 0 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" range="" rwaccess="RW"/>\r
724     <bitfield id="VPE_CLK_DIV_BY_2_EN" width="1" begin="8" end="8" resetval="0x0" description="Selects alternative clock source for VPE. 0x0: Default clock source from DPLL_CORE is selected 0x1: Alternative clock source from DPLL_VIDEO1 is selected" range="" rwaccess="RW"/>\r
725     <bitfield id="VIP2_CLK_INV_PORT_2B" width="1" begin="7" end="7" resetval="0x0" description="VIP2 Slice 1 Clock inversion for Port B enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" range="" rwaccess="RW"/>\r
726     <bitfield id="VIP2_CLK_INV_PORT_1B" width="1" begin="6" end="6" resetval="0x0" description="VIP2 Slice 0 Clock inversion for Port B enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" range="" rwaccess="RW"/>\r
727     <bitfield id="VIP2_CLK_INV_PORT_2A" width="1" begin="5" end="5" resetval="0x0" description="VIP2 Slice 1 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" range="" rwaccess="RW"/>\r
728     <bitfield id="VIP2_CLK_INV_PORT_1A" width="1" begin="4" end="4" resetval="0x0" description="VIP2 Slice 0 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" range="" rwaccess="RW"/>\r
729     <bitfield id="VIP1_CLK_INV_PORT_2B" width="1" begin="3" end="3" resetval="0x0" description="VIP1 Slice 1 Clock inversion for Port B enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" range="" rwaccess="RW"/>\r
730     <bitfield id="VIP1_CLK_INV_PORT_1B" width="1" begin="2" end="2" resetval="0x0" description="VIP1 Slice 0 Clock inversion for Port B enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" range="" rwaccess="RW"/>\r
731     <bitfield id="VIP1_CLK_INV_PORT_2A" width="1" begin="1" end="1" resetval="0x0" description="VIP1 Slice 1 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" range="" rwaccess="RW"/>\r
732     <bitfield id="VIP1_CLK_INV_PORT_1A" width="1" begin="0" end="0" resetval="0x0" description="VIP1 Slice 0 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" range="" rwaccess="RW"/>\r
733   </register>\r
734   <register id="CTRL_CORE_DSS_PLL_CONTROL" acronym="CTRL_CORE_DSS_PLL_CONTROL" offset="0x538" width="32" description="DSS PLLs Mux control register">\r
735     <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>\r
736     <bitfield id="SDVENC_CLK_SELECTION" width="2" begin="10" end="9" resetval="0x1" description="SDVENC_CLK mux configuration 0x0 = HDMI_CLK 0x1 = DPLL_VIDEO1_HSDIVIDER_clkout3" range="" rwaccess="RW"/>\r
737     <bitfield id="DSI1_C_CLK1_SELECTION" width="2" begin="8" end="7" resetval="0x1" description="DSI1_C_CLK1 mux configuration 0x0 = DPLL_VIDEO2 0x1 = DPLL_VIDEO1 0x2 = DPLL_HDMI" range="" rwaccess="RW"/>\r
738     <bitfield id="DSI1_B_CLK1_SELECTION" width="2" begin="6" end="5" resetval="0x1" description="DSI1_B_CLK1 mux configuration 0x0 = DPLL_VIDEO1 0x1 = DPLL_VIDEO2 0x2 = DPLL_HDMI 0x3 = DPLL_ABE" range="" rwaccess="RW"/>\r
739     <bitfield id="DSI1_A_CLK1_SELECTION" width="2" begin="4" end="3" resetval="0x1" description="DSI1_A_CLK1 mux configuration 0x0 = DPLL_VIDEO1 0x1 = DPLL_HDMI" range="" rwaccess="RW"/>\r
740     <bitfield id="PLL_HDMI_DSS_CONTROL_DISABLE" width="1" begin="2" end="2" resetval="0x1" description="HDMI PLL disable 0x0 = PLL enabled 0x1 = PLL disabled" range="" rwaccess="RW"/>\r
741     <bitfield id="PLL_VIDEO2_DSS_CONTROL_DISABLE" width="1" begin="1" end="1" resetval="0x1" description="VIDEO2 PLL disable 0x0 = PLL enabled 0x1 = PLL disabled" range="" rwaccess="RW"/>\r
742     <bitfield id="PLL_VIDEO1_DSS_CONTROL_DISABLE" width="1" begin="0" end="0" resetval="0x1" description="VIDEO1 PLL disable 0x0 = PLL enabled 0x1 = PLL disabled" range="" rwaccess="RW"/>\r
743   </register>\r
744   <register id="CTRL_CORE_MMR_LOCK_1" acronym="CTRL_CORE_MMR_LOCK_1" offset="0x540" width="32" description="Register to lock memory region starting at address offset 0x0000 0100 and ending at address offset 0x0000 079F">\r
745     <bitfield id="MMR_LOCK_1" width="32" begin="31" end="0" resetval="0x1A1C8144" description="Lock value for region 0x0000 0100 to 0x0000 079F 0x1A1C8144 = lock value 0x2FF1AC2B = unlock value" range="" rwaccess="RW"/>\r
746   </register>\r
747   <register id="CTRL_CORE_MMR_LOCK_2" acronym="CTRL_CORE_MMR_LOCK_2" offset="0x544" width="32" description="Register to lock memory region starting at address offset 0x0000 07A0 and ending at address offset 0x0000 0D9F">\r
748     <bitfield id="MMR_LOCK_2" width="32" begin="31" end="0" resetval="0xFDF45530" description="Lock value for region 0x0000 07A0 to 0x0000 0D9F 0xFDF45530 = lock value 0xF757FDC0 = unlock value" range="" rwaccess="RW"/>\r
749   </register>\r
750   <register id="CTRL_CORE_MMR_LOCK_3" acronym="CTRL_CORE_MMR_LOCK_3" offset="0x548" width="32" description="Register to lock memory region starting at address offset 0x0000 0DA0 and ending at address offset 0x0000 0FFF">\r
751     <bitfield id="MMR_LOCK_3" width="32" begin="31" end="0" resetval="0x1AE6E320" description="Lock value for region 0x0000 0DA0 to 0x0000 0FFF 0x1AE6E320 = lock value 0xE2BC3A6D = unlock value" range="" rwaccess="RW"/>\r
752   </register>\r
753   <register id="CTRL_CORE_MMR_LOCK_4" acronym="CTRL_CORE_MMR_LOCK_4" offset="0x54C" width="32" description="Register to lock memory region starting at address offset 0x0000 1000 and ending at address offset 0x0000 13FF">\r
754     <bitfield id="MMR_LOCK_4" width="32" begin="31" end="0" resetval="0x2FFA927C" description="Lock value for region 0x0000 1000 to 0x0000 13FF 0x2FFA927C = lock value 0x1EBF131D = unlock value" range="" rwaccess="RW"/>\r
755   </register>\r
756   <register id="CTRL_CORE_MMR_LOCK_5" acronym="CTRL_CORE_MMR_LOCK_5" offset="0x550" width="32" description="Register to lock memory region starting at address offset 0x0000 1400 and ending at address offset 0x0000 1FFF">\r
757     <bitfield id="MMR_LOCK_5" width="32" begin="31" end="0" resetval="0x143F832C" description="Lock value for region 0x0000 1400 to 0x0000 1FFF 0x143F832C = lock value 0x6F361E05 = unlock value" range="" rwaccess="RW"/>\r
758   </register>\r
759   <register id="CTRL_CORE_CONTROL_IO_1" acronym="CTRL_CORE_CONTROL_IO_1" offset="0x554" width="32" description="Register to configure some IP level signals">\r
760     <bitfield id="RESERVED" width="11" begin="31" end="21" resetval="0x0" description="" range="" rwaccess="R"/>\r
761     <bitfield id="MMU2_DISABLE" width="1" begin="20" end="20" resetval="0x0" description="MMU2 DISABLE setting" range="" rwaccess="RW"/>\r
762     <bitfield id="RESERVED" width="3" begin="19" end="17" resetval="0x0" description="" range="" rwaccess="R"/>\r
763     <bitfield id="MMU1_DISABLE" width="1" begin="16" end="16" resetval="0x0" description="MMU1 DISABLE setting" range="" rwaccess="RW"/>\r
764     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
765     <bitfield id="TC1_DEFAULT_BURST_SIZE" width="2" begin="13" end="12" resetval="0x3" description="EDMA TC1 DEFAULT BURST SIZE setting" range="" rwaccess="RW"/>\r
766     <bitfield id="RESERVED" width="2" begin="11" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
767     <bitfield id="TC0_DEFAULT_BURST_SIZE" width="2" begin="9" end="8" resetval="0x3" description="EDMA TC0 DEFAULT BURST SIZE setting" range="" rwaccess="RW"/>\r
768     <bitfield id="RESERVED" width="2" begin="7" end="6" resetval="0x0" description="" range="" rwaccess="R"/>\r
769     <bitfield id="GMII2_SEL" width="2" begin="5" end="4" resetval="0x0" description="GMII2 selection setting 0x0: GMII/MII 0x1: RMII 0x2: RGMII 0x3: Reserved" range="" rwaccess="RW"/>\r
770     <bitfield id="RESERVED" width="2" begin="3" end="2" resetval="0x0" description="" range="" rwaccess="R"/>\r
771     <bitfield id="GMII1_SEL" width="2" begin="1" end="0" resetval="0x0" description="GMII1 selection setting 0x0: GMII/MII 0x1: RMII 0x2: RGMII 0x3: Reserved" range="" rwaccess="RW"/>\r
772   </register>\r
773   <register id="CTRL_CORE_CONTROL_IO_2" acronym="CTRL_CORE_CONTROL_IO_2" offset="0x558" width="32" description="Register to configure some IP level signals">\r
774     <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="" range="" rwaccess="R"/>\r
775     <bitfield id="GMAC_RESET_ISOLATION_ENABLE" width="1" begin="23" end="23" resetval="0x0" description="Reset isolation enable setting 0x0 = Reset is not isolated 0x1 = Reset is isolated" range="" rwaccess="RW"/>\r
776     <bitfield id="PWMSS3_TBCLKEN" width="1" begin="22" end="22" resetval="0x0" description="PWMSS3 CLOCK ENABLE setting" range="" rwaccess="RW"/>\r
777     <bitfield id="PWMSS2_TBCLKEN" width="1" begin="21" end="21" resetval="0x0" description="PWMSS2 CLOCK ENABLE setting" range="" rwaccess="RW"/>\r
778     <bitfield id="PWMSS1_TBCLKEN" width="1" begin="20" end="20" resetval="0x0" description="PWMSS1 CLOCK ENABLE setting" range="" rwaccess="RW"/>\r
779     <bitfield id="RESERVED" width="6" begin="19" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
780     <bitfield id="PCIE_1LANE_2LANE_SELECTION" width="1" begin="13" end="13" resetval="0x0" description="PCIe one or two lane selection setting 0x0 = One PCIe lane is selected 0x1 = Two PCIe lanes are selected" range="" rwaccess="RW"/>\r
781     <bitfield id="RESERVED" width="2" begin="12" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
782     <bitfield id="QSPI_MEMMAPPED_CS" width="3" begin="10" end="8" resetval="0x0" description="QSPI CS MAPPING setting. 0x0: The QSPI configuration registers are accessed 0x1: An external device connected to CS0 is accessed 0x2: An external device connected to CS1 is accessed 0x3: An external device connected to CS2 is accessed 0x4-0x7: An external device connected to CS3 is accessed" range="" rwaccess="RW"/>\r
783     <bitfield id="RESERVED" width="2" begin="7" end="6" resetval="0x0" description="" range="" rwaccess="R"/>\r
784     <bitfield id="DCAN2_RAMINIT_START" width="1" begin="5" end="5" resetval="0x0" description="DCAN2 RAM INIT START setting To initialize DCAN2 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. : If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." range="" rwaccess="RW"/>\r
785     <bitfield id="DSS_DESHDCP_DISABLE" width="1" begin="4" end="4" resetval="0x0" description="DSS DESHDCP DISABLE setting" range="" rwaccess="RW"/>\r
786     <bitfield id="DCAN1_RAMINIT_START" width="1" begin="3" end="3" resetval="0x0" description="DCAN1 RAM INIT START setting To initialize DCAN1 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. : If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." range="" rwaccess="RW"/>\r
787     <bitfield id="DCAN2_RAMINIT_DONE" width="1" begin="2" end="2" resetval="0x0" description="DCAN2 RAM INIT DONE status" range="" rwaccess="RW"/>\r
788     <bitfield id="DCAN1_RAMINIT_DONE" width="1" begin="1" end="1" resetval="0x0" description="DCAN1 RAM INIT DONE status" range="" rwaccess="RW"/>\r
789     <bitfield id="DSS_DESHDCP_CLKEN" width="1" begin="0" end="0" resetval="0x0" description="DSS DESHDCP CLOCK ENABLE setting" range="" rwaccess="RW"/>\r
790   </register>\r
791   <register id="CTRL_CORE_CONTROL_DSP1_RST_VECT" acronym="CTRL_CORE_CONTROL_DSP1_RST_VECT" offset="0x55C" width="32" description="Register for storing DSP1 reset vector">\r
792     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>\r
793     <bitfield id="DSP1_NUM_MM" width="3" begin="26" end="24" resetval="0x0" description="Number of DSP instances in the SoC 0x1 = 1 0x2 = 2" range="" rwaccess="RW"/>\r
794     <bitfield id="RESERVED" width="2" begin="23" end="22" resetval="0x0" description="" range="" rwaccess="R"/>\r
795     <bitfield id="DSP1_RST_VECT" width="22" begin="21" end="0" resetval="0x0" description="DSP1 reset vector address" range="" rwaccess="RW"/>\r
796   </register>\r
797   <register id="CTRL_CORE_CONTROL_DSP2_RST_VECT" acronym="CTRL_CORE_CONTROL_DSP2_RST_VECT" offset="0x560" width="32" description="Register for storing DSP2 reset vector">\r
798     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>\r
799     <bitfield id="DSP2_NUM_MM" width="3" begin="26" end="24" resetval="0x0" description="Number of DSP instances in the SoC 0x1 = 1 0x2 = 2" range="" rwaccess="RW"/>\r
800     <bitfield id="RESERVED" width="2" begin="23" end="22" resetval="0x0" description="" range="" rwaccess="R"/>\r
801     <bitfield id="DSP2_RST_VECT" width="22" begin="21" end="0" resetval="0x0" description="DSP2 reset vector address" range="" rwaccess="RW"/>\r
802   </register>\r
803   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE" offset="0x564" width="32" description="Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use.">\r
804     <bitfield id="RESERVED" width="16" begin="31" end="16" resetval="0x0" description="" range="" rwaccess="R"/>\r
805     <bitfield id="STD_FUSE_OPP_BGAP_DSPEVE_0" width="8" begin="15" end="8" resetval="0x0" description="Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
806     <bitfield id="STD_FUSE_OPP_BGAP_DSPEVE_1" width="8" begin="7" end="0" resetval="0x0" description="Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
807   </register>\r
808   <register id="CTRL_CORE_STD_FUSE_OPP_BGAP_IVA" acronym="CTRL_CORE_STD_FUSE_OPP_BGAP_IVA" offset="0x568" width="32" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use.">\r
809     <bitfield id="STD_FUSE_OPP_BGAP_IVA_0" width="8" begin="31" end="24" resetval="0x0" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
810     <bitfield id="STD_FUSE_OPP_BGAP_IVA_1" width="8" begin="23" end="16" resetval="0x0" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
811     <bitfield id="STD_FUSE_OPP_BGAP_IVA_2" width="8" begin="15" end="8" resetval="0x0" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
812     <bitfield id="STD_FUSE_OPP_BGAP_IVA_3" width="8" begin="7" end="0" resetval="0x0" description="Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." range="" rwaccess="R"/>\r
813   </register>\r
814   <register id="CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL" offset="0x56C" width="32" description="DSPEVE SRAM LDO Control register">\r
815     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
816     <bitfield id="LDOSRAMDSPEVE_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">\r
817       <bitenum value="0" id="EFUSE" token="LDOSRAMDSPEVE_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>\r
818       <bitenum value="1" id="OCP" token="LDOSRAMDSPEVE_RETMODE_MUX_CTRL_1" description="Override value is used"/>\r
819     </bitfield>\r
820     <bitfield id="LDOSRAMDSPEVE_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>\r
821     <bitfield id="LDOSRAMDSPEVE_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>\r
822     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
823     <bitfield id="LDOSRAMDSPEVE_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">\r
824       <bitenum value="0" id="EFUSE" token="LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>\r
825       <bitenum value="1" id="OCP" token="LDOSRAMDSPEVE_ACTMODE_MUX_CTRL_1" description="Override value is used"/>\r
826     </bitfield>\r
827     <bitfield id="LDOSRAMDSPEVE_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>\r
828     <bitfield id="LDOSRAMDSPEVE_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>\r
829   </register>\r
830   <register id="CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL" offset="0x570" width="32" description="IVA SRAM LDO Control register">\r
831     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
832     <bitfield id="LDOSRAMIVA_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">\r
833       <bitenum value="0" id="EFUSE" token="LDOSRAMIVA_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>\r
834       <bitenum value="1" id="OCP" token="LDOSRAMIVA_RETMODE_MUX_CTRL_1" description="Override value is used"/>\r
835     </bitfield>\r
836     <bitfield id="LDOSRAMIVA_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>\r
837     <bitfield id="LDOSRAMIVA_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>\r
838     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
839     <bitfield id="LDOSRAMIVA_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">\r
840       <bitenum value="0" id="EFUSE" token="LDOSRAMIVA_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>\r
841       <bitenum value="1" id="OCP" token="LDOSRAMIVA_ACTMODE_MUX_CTRL_1" description="Override value is used"/>\r
842     </bitfield>\r
843     <bitfield id="LDOSRAMIVA_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>\r
844     <bitfield id="LDOSRAMIVA_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>\r
845   </register>\r
846   <register id="CTRL_CORE_TEMP_SENSOR_DSPEVE" acronym="CTRL_CORE_TEMP_SENSOR_DSPEVE" offset="0x574" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">\r
847     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>\r
848     <bitfield id="BGAP_TMPSOFF_DSPEVE" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>\r
849     <bitfield id="BGAP_EOCZ_DSPEVE" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_DSPEVE is valid." range="" rwaccess="R"/>\r
850     <bitfield id="BGAP_DTEMP_DSPEVE" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>\r
851   </register>\r
852   <register id="CTRL_CORE_TEMP_SENSOR_IVA" acronym="CTRL_CORE_TEMP_SENSOR_IVA" offset="0x578" width="32" description="Control VBGAPTS temperature sensor and thermal comparator shutdown register">\r
853     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="" range="" rwaccess="R"/>\r
854     <bitfield id="BGAP_TMPSOFF_IVA" width="1" begin="11" end="11" resetval="0x1" description="This bit indicates the temperature sensor state." range="" rwaccess="R"/>\r
855     <bitfield id="BGAP_EOCZ_IVA" width="1" begin="10" end="10" resetval="0x0" description="ADC End of Conversion. Active low, when BGAP_DTEMP_IVA is valid." range="" rwaccess="R"/>\r
856     <bitfield id="BGAP_DTEMP_IVA" width="10" begin="9" end="0" resetval="0x0" description="Temperature data from the ADC. Valid if EOCZ is low." range="" rwaccess="R"/>\r
857   </register>\r
858   <register id="CTRL_CORE_BANDGAP_MASK_2" acronym="CTRL_CORE_BANDGAP_MASK_2" offset="0x57C" width="32" description="bgap_mask">\r
859     <bitfield id="RESERVED" width="9" begin="31" end="23" resetval="0x0" description="" range="" rwaccess="R"/>\r
860     <bitfield id="FREEZE_IVA" width="1" begin="22" end="22" resetval="0x0" description="Freeze the FIFO IVA 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>\r
861     <bitfield id="FREEZE_DSPEVE" width="1" begin="21" end="21" resetval="0x0" description="Freeze the FIFO DSPEVE 0x0 = No operation 0x1 = Freeze the FIFO" range="" rwaccess="RW"/>\r
862     <bitfield id="RESERVED" width="1" begin="20" end="20" resetval="0x0" description="" range="" rwaccess="R"/>\r
863     <bitfield id="CLEAR_IVA" width="1" begin="19" end="19" resetval="0x0" description="Reset the FIFO IVA 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>\r
864     <bitfield id="CLEAR_DSPEVE" width="1" begin="18" end="18" resetval="0x0" description="Reset the FIFO DSPEVE 0x0 = No operation 0x1 = Reset the FIFO" range="" rwaccess="RW"/>\r
865     <bitfield id="RESERVED" width="14" begin="17" end="4" resetval="0x0" description="" range="" rwaccess="R"/>\r
866     <bitfield id="MASK_HOT_IVA" width="1" begin="3" end="3" resetval="0x0" description="Mask for hot event IVA 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>\r
867     <bitfield id="MASK_COLD_IVA" width="1" begin="2" end="2" resetval="0x0" description="Mask for cold event IVA 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>\r
868     <bitfield id="MASK_HOT_DSPEVE" width="1" begin="1" end="1" resetval="0x0" description="Mask for hot event DSPEVE 0x0 = hot event is masked 0x1 = hot event is not masked" range="" rwaccess="RW"/>\r
869     <bitfield id="MASK_COLD_DSPEVE" width="1" begin="0" end="0" resetval="0x0" description="Mask for cold event DSPEVE 0x0 = cold event is masked 0x1 = cold event is not masked" range="" rwaccess="RW"/>\r
870   </register>\r
871   <register id="CTRL_CORE_BANDGAP_THRESHOLD_DSPEVE" acronym="CTRL_CORE_BANDGAP_THRESHOLD_DSPEVE" offset="0x580" width="32" description="BGAP THRESHOLD DSPEVE">\r
872     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
873     <bitfield id="THOLD_HOT_DSPEVE" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in" range="" rwaccess="RW"/>\r
874     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
875     <bitfield id="THOLD_COLD_DSPEVE" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in" range="" rwaccess="RW"/>\r
876   </register>\r
877   <register id="CTRL_CORE_BANDGAP_THRESHOLD_IVA" acronym="CTRL_CORE_BANDGAP_THRESHOLD_IVA" offset="0x584" width="32" description="BGAP THRESHOLD IVA">\r
878     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
879     <bitfield id="THOLD_HOT_IVA" width="10" begin="25" end="16" resetval="0x0" description="Value for the high temperature threshold. The values for loading this bit field are listed in" range="" rwaccess="RW"/>\r
880     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
881     <bitfield id="THOLD_COLD_IVA" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in" range="" rwaccess="RW"/>\r
882   </register>\r
883   <register id="CTRL_CORE_BANDGAP_TSHUT_DSPEVE" acronym="CTRL_CORE_BANDGAP_TSHUT_DSPEVE" offset="0x588" width="32" description="BGAP TSHUT THRESHOLD IVA">\r
884     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>\r
885     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
886     <bitfield id="TSHUT_HOT_DSPEVE" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>\r
887     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
888     <bitfield id="TSHUT_COLD_DSPEVE" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>\r
889   </register>\r
890   <register id="CTRL_CORE_BANDGAP_TSHUT_IVA" acronym="CTRL_CORE_BANDGAP_TSHUT_IVA" offset="0x58C" width="32" description="BGAP TSHUT THRESHOLD IVA">\r
891     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>\r
892     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
893     <bitfield id="TSHUT_HOT_IVA" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>\r
894     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
895     <bitfield id="TSHUT_COLD_IVA" width="10" begin="9" end="0" resetval="0x0" description="tshut value cold Software should not modify this bit field." range="" rwaccess="RW"/>\r
896   </register>\r
897   <register id="CTRL_CORE_BANDGAP_STATUS_2" acronym="CTRL_CORE_BANDGAP_STATUS_2" offset="0x598" width="32" description="BGAP STATUS">\r
898     <bitfield id="RESERVED" width="28" begin="31" end="4" resetval="0x0" description="" range="" rwaccess="R"/>\r
899     <bitfield id="HOT_IVA" width="1" begin="3" end="3" resetval="0x0" description="Event for hot temperature iva bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>\r
900     <bitfield id="COLD_IVA" width="1" begin="2" end="2" resetval="0x0" description="Event for cold temperature iva bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>\r
901     <bitfield id="HOT_DSPEVE" width="1" begin="1" end="1" resetval="0x0" description="Event for hot temperature dspeve bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>\r
902     <bitfield id="COLD_DSPEVE" width="1" begin="0" end="0" resetval="0x0" description="Event for cold temperature dspeve bandgap when '1' 0x0 = event not detected 0x1 = event detected" range="" rwaccess="R"/>\r
903   </register>\r
904   <register id="CTRL_CORE_DTEMP_DSPEVE_0" acronym="CTRL_CORE_DTEMP_DSPEVE_0" offset="0x59C" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN. Most recent sample">\r
905     <bitfield id="DTEMP_TAG_DSPEVE_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
906     <bitfield id="DTEMP_TEMPERATURE_DSPEVE_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
907   </register>\r
908   <register id="CTRL_CORE_DTEMP_DSPEVE_1" acronym="CTRL_CORE_DTEMP_DSPEVE_1" offset="0x5A0" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN">\r
909     <bitfield id="DTEMP_TAG_DSPEVE_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
910     <bitfield id="DTEMP_TEMPERATURE_DSPEVE_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
911   </register>\r
912   <register id="CTRL_CORE_DTEMP_DSPEVE_2" acronym="CTRL_CORE_DTEMP_DSPEVE_2" offset="0x5A4" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN">\r
913     <bitfield id="DTEMP_TAG_DSPEVE_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
914     <bitfield id="DTEMP_TEMPERATURE_DSPEVE_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
915   </register>\r
916   <register id="CTRL_CORE_DTEMP_DSPEVE_3" acronym="CTRL_CORE_DTEMP_DSPEVE_3" offset="0x5A8" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN">\r
917     <bitfield id="DTEMP_TAG_DSPEVE_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
918     <bitfield id="DTEMP_TEMPERATURE_DSPEVE_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
919   </register>\r
920   <register id="CTRL_CORE_DTEMP_DSPEVE_4" acronym="CTRL_CORE_DTEMP_DSPEVE_4" offset="0x5AC" width="32" description="TAGGED TEMPERATURE DSPEVE DOMAIN. Oldest sample">\r
921     <bitfield id="DTEMP_TAG_DSPEVE_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
922     <bitfield id="DTEMP_TEMPERATURE_DSPEVE_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
923   </register>\r
924   <register id="CTRL_CORE_DTEMP_IVA_0" acronym="CTRL_CORE_DTEMP_IVA_0" offset="0x5B0" width="32" description="TAGGED TEMPERATURE IVA DOMAIN. Most recent sample">\r
925     <bitfield id="DTEMP_TAG_IVA_0" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
926     <bitfield id="DTEMP_TEMPERATURE_IVA_0" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
927   </register>\r
928   <register id="CTRL_CORE_DTEMP_IVA_1" acronym="CTRL_CORE_DTEMP_IVA_1" offset="0x5B4" width="32" description="TAGGED TEMPERATURE IVA DOMAIN">\r
929     <bitfield id="DTEMP_TAG_IVA_1" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
930     <bitfield id="DTEMP_TEMPERATURE_IVA_1" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
931   </register>\r
932   <register id="CTRL_CORE_DTEMP_IVA_2" acronym="CTRL_CORE_DTEMP_IVA_2" offset="0x5B8" width="32" description="TAGGED TEMPERATURE IVA DOMAIN">\r
933     <bitfield id="DTEMP_TAG_IVA_2" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
934     <bitfield id="DTEMP_TEMPERATURE_IVA_2" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
935   </register>\r
936   <register id="CTRL_CORE_DTEMP_IVA_3" acronym="CTRL_CORE_DTEMP_IVA_3" offset="0x5BC" width="32" description="TAGGED TEMPERATURE IVA DOMAIN">\r
937     <bitfield id="DTEMP_TAG_IVA_3" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
938     <bitfield id="DTEMP_TEMPERATURE_IVA_3" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
939   </register>\r
940   <register id="CTRL_CORE_DTEMP_IVA_4" acronym="CTRL_CORE_DTEMP_IVA_4" offset="0x5C0" width="32" description="TAGGED TEMPERATURE IVA DOMAIN. Oldest sample">\r
941     <bitfield id="DTEMP_TAG_IVA_4" width="22" begin="31" end="10" resetval="0x0" description="tag. Indicate number of times in the bgap state machine." range="" rwaccess="R"/>\r
942     <bitfield id="DTEMP_TEMPERATURE_IVA_4" width="10" begin="9" end="0" resetval="0x0" description="temperature" range="" rwaccess="R"/>\r
943   </register>\r
944   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2" offset="0x5CC" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM. This register also stores information about ABB configuration for that OPP.">\r
945     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
946     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">\r
947       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>\r
948       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>\r
949     </bitfield>\r
950     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x0" description="This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>\r
951     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
952     <bitfield id="STD_FUSE_OPP_VMIN_IVA_2" width="12" begin="11" end="0" resetval="0x0" description="AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>\r
953   </register>\r
954   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3" offset="0x5D0" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD. This register also stores information about ABB configuration for that OPP.">\r
955     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
956     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">\r
957       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>\r
958       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>\r
959     </bitfield>\r
960     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x0" description="This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>\r
961     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
962     <bitfield id="STD_FUSE_OPP_VMIN_IVA_3" width="12" begin="11" end="0" resetval="0x0" description="AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>\r
963   </register>\r
964   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4" offset="0x5D4" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH. This register also stores information about ABB configuration for that OPP.">\r
965     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
966     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">\r
967       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>\r
968       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>\r
969     </bitfield>\r
970     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x0" description="This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>\r
971     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
972     <bitfield id="STD_FUSE_OPP_VMIN_IVA_4" width="12" begin="11" end="0" resetval="0x0" description="AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>\r
973   </register>\r
974   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2" offset="0x5E0" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM. This register also stores information about ABB configuration for that OPP.">\r
975     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
976     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">\r
977       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>\r
978       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>\r
979     </bitfield>\r
980     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x0" description="This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>\r
981     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
982     <bitfield id="STD_FUSE_OPP_VMIN_DSPEVE_2" width="12" begin="11" end="0" resetval="0x0" description="AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>\r
983   </register>\r
984   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3" offset="0x5E4" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD. This register also stores information about ABB configuration for that OPP.">\r
985     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
986     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">\r
987       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>\r
988       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>\r
989     </bitfield>\r
990     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x0" description="This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>\r
991     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
992     <bitfield id="STD_FUSE_OPP_VMIN_DSPEVE_3" width="12" begin="11" end="0" resetval="0x0" description="AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>\r
993   </register>\r
994   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4" offset="0x5E8" width="32" description="This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH. This register also stores information about ABB configuration for that OPP.">\r
995     <bitfield id="RESERVED" width="6" begin="31" end="26" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
996     <bitfield id="ABBEN" width="1" begin="25" end="25" resetval="0x0" description="" range="" rwaccess="R">\r
997       <bitenum value="0" id="ABB_disabled" token="ABBEN_0" description="ABB is disabled"/>\r
998       <bitenum value="1" id="ABB_enabled" token="ABBEN_1" description="ABB is enabled"/>\r
999     </bitfield>\r
1000     <bitfield id="VSETABB" width="5" begin="24" end="20" resetval="0x0" description="This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." range="" rwaccess="R"/>\r
1001     <bitfield id="RESERVED" width="8" begin="19" end="12" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
1002     <bitfield id="STD_FUSE_OPP_VMIN_DSPEVE_4" width="12" begin="11" end="0" resetval="0x0" description="AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>\r
1003   </register>\r
1004   <register id="CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2" offset="0x5F4" width="32" description="This register contains the AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM.">\r
1005     <bitfield id="RESERVED" width="20" begin="31" end="12" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
1006     <bitfield id="STD_FUSE_OPP_VMIN_CORE_2" width="12" begin="11" end="0" resetval="0x0" description="AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." range="" rwaccess="R"/>\r
1007   </register>\r
1008   <register id="CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL" offset="0x680" width="32" description="CORE 2nd SRAM LDO Control register">\r
1009     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
1010     <bitfield id="LDOSRAMCORE_2_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">\r
1011       <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_2_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>\r
1012       <bitenum value="1" id="OCP" token="LDOSRAMCORE_2_RETMODE_MUX_CTRL_1" description="Override value is used"/>\r
1013     </bitfield>\r
1014     <bitfield id="LDOSRAMCORE_2_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>\r
1015     <bitfield id="LDOSRAMCORE_2_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>\r
1016     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
1017     <bitfield id="LDOSRAMCORE_2_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">\r
1018       <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_2_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>\r
1019       <bitenum value="1" id="OCP" token="LDOSRAMCORE_2_ACTMODE_MUX_CTRL_1" description="Override value is used"/>\r
1020     </bitfield>\r
1021     <bitfield id="LDOSRAMCORE_2_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>\r
1022     <bitfield id="LDOSRAMCORE_2_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>\r
1023   </register>\r
1024   <register id="CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL" acronym="CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL" offset="0x684" width="32" description="CORE 3rd SRAM LDO Control register">\r
1025     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
1026     <bitfield id="LDOSRAMCORE_3_RETMODE_MUX_CTRL" width="1" begin="26" end="26" resetval="0x0" description="Override control of EFUSE Retention Mode Voltage value" range="" rwaccess="RW">\r
1027       <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_3_RETMODE_MUX_CTRL_0" description="eFuse value is used"/>\r
1028       <bitenum value="1" id="OCP" token="LDOSRAMCORE_3_RETMODE_MUX_CTRL_1" description="Override value is used"/>\r
1029     </bitfield>\r
1030     <bitfield id="LDOSRAMCORE_3_RETMODE_VSET_IN" width="5" begin="25" end="21" resetval="0x0" description="EFUSE Retention Mode Voltage value (vset[9:5])" range="" rwaccess="R"/>\r
1031     <bitfield id="LDOSRAMCORE_3_RETMODE_VSET_OUT" width="5" begin="20" end="16" resetval="0x0" description="Override value for Retention Mode Voltage" range="" rwaccess="RW"/>\r
1032     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
1033     <bitfield id="LDOSRAMCORE_3_ACTMODE_MUX_CTRL" width="1" begin="10" end="10" resetval="0x0" description="Override control of EFUSE Active Mode Voltage value" range="" rwaccess="RW">\r
1034       <bitenum value="0" id="EFUSE" token="LDOSRAMCORE_3_ACTMODE_MUX_CTRL_0" description="eFuse value is used"/>\r
1035       <bitenum value="1" id="OCP" token="LDOSRAMCORE_3_ACTMODE_MUX_CTRL_1" description="Override value is used"/>\r
1036     </bitfield>\r
1037     <bitfield id="LDOSRAMCORE_3_ACTMODE_VSET_IN" width="5" begin="9" end="5" resetval="0x0" description="EFUSE Active Mode Voltage value (vset[4:0])" range="" rwaccess="R"/>\r
1038     <bitfield id="LDOSRAMCORE_3_ACTMODE_VSET_OUT" width="5" begin="4" end="0" resetval="0x0" description="Override value for Active Mode Voltage value" range="" rwaccess="RW"/>\r
1039   </register>\r
1040   <register id="CTRL_CORE_NMI_DESTINATION_1" acronym="CTRL_CORE_NMI_DESTINATION_1" offset="0x68C" width="32" description="Register for routing NMI interrupt to respective cores">\r
1041     <bitfield id="RESERVED" width="8" begin="31" end="24" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>\r
1042     <bitfield id="IPU2_C1" width="8" begin="23" end="16" resetval="0x0" description="Enable IPU2 CORE1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>\r
1043     <bitfield id="IPU2_C0" width="8" begin="15" end="8" resetval="0x0" description="Enable IPU2 CORE0 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>\r
1044     <bitfield id="IPU1_C1" width="8" begin="7" end="0" resetval="0x0" description="Enable IPU1 CORE1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>\r
1045   </register>\r
1046   <register id="CTRL_CORE_NMI_DESTINATION_2" acronym="CTRL_CORE_NMI_DESTINATION_2" offset="0x690" width="32" description="Register for routing NMI interrupt to respective cores">\r
1047     <bitfield id="IPU1_C0" width="8" begin="31" end="24" resetval="0x0" description="Enable IPU1 CORE0 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>\r
1048     <bitfield id="DSP2" width="8" begin="23" end="16" resetval="0x0" description="Enable DSP2 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>\r
1049     <bitfield id="DSP1" width="8" begin="15" end="8" resetval="0x0" description="Enable DSP1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>\r
1050     <bitfield id="MPU" width="8" begin="7" end="0" resetval="0x0" description="Comes from Efuse (MPU_EN) 0x0 = NMI disabled 0x1 = NMI enabled" range="" rwaccess="RW"/>\r
1051   </register>\r
1052   <register id="CTRL_CORE_IP_PRESSURE" acronym="CTRL_CORE_IP_PRESSURE" offset="0x698" width="32" description="Register to override the L3 pressure setting for the MLB module">\r
1053     <bitfield id="RESERVED" width="29" begin="31" end="3" resetval="0x0" description="" range="" rwaccess="R"/>\r
1054     <bitfield id="MLB_L3_PRESSURE_ENABLE" width="1" begin="2" end="2" resetval="0x0" description="Override enable for the MLB L3 pressure setting 0x0 = Overriding of the L3 pressure setting for the MLB module is disabled 0x1 = Overriding of the L3 pressure setting for the MLB module is enabled" range="" rwaccess="RW"/>\r
1055     <bitfield id="MLB_L3_PRESSURE" width="2" begin="1" end="0" resetval="0x0" description="MLB L3 pressure setting 0x0 = Lowest 0x3 = Highest" range="" rwaccess="RW"/>\r
1056   </register>\r
1057   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0" offset="0x6A0" width="32" description="Standard Fuse OPP VDD_DSPEVE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
1058     <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
1059   </register>\r
1060   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1" offset="0x6A4" width="32" description="Standard Fuse OPP VDD_DSPEVE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
1061     <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
1062   </register>\r
1063   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2" offset="0x6A8" width="32" description="Standard Fuse OPP VDD_DSPEVE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
1064     <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_2" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
1065   </register>\r
1066   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3" offset="0x6AC" width="32" description="Standard Fuse OPP VDD_DSPEVE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
1067     <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_3" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
1068   </register>\r
1069   <register id="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4" acronym="CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4" offset="0x6B0" width="32" description="Standard Fuse OPP VDD_DSPEVE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
1070     <bitfield id="STD_FUSE_OPP_VDD_DSPEVE_4" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
1071   </register>\r
1072   <register id="CTRL_CORE_CUST_FUSE_SWRV_7" acronym="CTRL_CORE_CUST_FUSE_SWRV_7" offset="0x6B4" width="32" description="Customer Fuse keys. SWRV [31:0] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
1073     <bitfield id="CUST_FUSE_SWRV_7" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
1074   </register>\r
1075   <register id="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0" acronym="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0" offset="0x6B8" width="32" description="Standard Fuse Calibration override value [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
1076     <bitfield id="STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
1077   </register>\r
1078   <register id="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1" acronym="CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1" offset="0x6BC" width="32" description="Standard Fuse Calibration override value [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain.">\r
1079     <bitfield id="STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1" width="32" begin="31" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
1080   </register>\r
1081   <register id="CTRL_CORE_PCIE_POWER_STATE" acronym="CTRL_CORE_PCIE_POWER_STATE" offset="0x6C0" width="32" description="Register to PCIe related controls">\r
1082     <bitfield id="BYPASS_EN_APLL_PCIE" width="1" begin="31" end="31" resetval="0x0" description="Bypass enable bit setting for APLL_PCIe" range="" rwaccess="RW"/>\r
1083     <bitfield id="CLKOOUTEN_APLL_PCIE" width="1" begin="30" end="30" resetval="0x0" description="Clock output enable bit setting for APLL_PCIe" range="" rwaccess="RW"/>\r
1084     <bitfield id="RESERVED" width="4" begin="29" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
1085     <bitfield id="EFUSE_TRIM_ACS_PCIE" width="10" begin="25" end="16" resetval="0x0" description="MMR override capability for ACS_PCIe efuse trim bits" range="" rwaccess="RW"/>\r
1086     <bitfield id="EFUSE_TRIM_PCIE_PLL" width="16" begin="15" end="0" resetval="0x0" description="MMR override capability for PCIe PLL efuse trim bits" range="" rwaccess="RW"/>\r
1087   </register>\r
1088   <register id="CTRL_CORE_BOOTSTRAP" acronym="CTRL_CORE_BOOTSTRAP" offset="0x6C4" width="32" description="Register to view all the sysboot settings">\r
1089     <bitfield id="RESERVED" width="16" begin="31" end="16" resetval="0x0" description="" range="" rwaccess="R"/>\r
1090     <bitfield id="DSP_CLOCK_DIVIDER" width="1" begin="15" end="15" resetval="0x0" description="Divide factor for DSP clock" range="" rwaccess="R"/>\r
1091     <bitfield id="RESERVED" width="1" begin="14" end="14" resetval="0x0" description="For proper device operation, a value of 0 is required on the sysboot14 pad." range="" rwaccess="R"/>\r
1092     <bitfield id="BOOTDEVICESIZE" width="1" begin="13" end="13" resetval="0x0" description="Select the size of the flash device on CS0. 0x0: 8-bit 0x1: 16-bit" range="" rwaccess="R"/>\r
1093     <bitfield id="MUXCS0DEVICE" width="2" begin="12" end="11" resetval="0x0" description="Select IC boot sequence to be executed from a multiplexed address and data device attached to CS0. 0x0: Non-muxed device attached 0x1: Addr-Data Mux device attached 0x2: Reserved 0x3: Reserved" range="" rwaccess="R"/>\r
1094     <bitfield id="BOOTWAITEN" width="1" begin="10" end="10" resetval="0x0" description="Enable the monitoring on CS0 of the wait pin at IC reset release time for read accesses. 0x0: Wait pin is not monitored for read accesses 0x1: Wait pin is monitored for read accesses" range="" rwaccess="R"/>\r
1095     <bitfield id="SPEEDSELECT" width="2" begin="9" end="8" resetval="0x0" description="Indicates the SYS_CLK1 frequency (from osc0). Note that the internal FUNC_32K_CLK is equal to SYS_CLK1/610, which is nominally 32.7869 kHz with 20 MHz clock. 0x0: Reserved 0x1: 20 MHz 0x2: 27 MHz 0x3: 19.2 MHz" range="" rwaccess="R"/>\r
1096     <bitfield id="RESERVED" width="2" begin="7" end="6" resetval="0x0" description="" range="" rwaccess="R"/>\r
1097     <bitfield id="BOOTMODE" width="6" begin="5" end="0" resetval="0x0" description="SYSBOOT mode" range="" rwaccess="R"/>\r
1098   </register>\r
1099   <register id="CTRL_CORE_MLB_SIG_IO_CTRL" acronym="CTRL_CORE_MLB_SIG_IO_CTRL" offset="0x6C8" width="32" description="Register to set the MLB's SIG IO characteristics">\r
1100     <bitfield id="RESERVED" width="10" begin="31" end="22" resetval="0x0" description="" range="" rwaccess="R"/>\r
1101     <bitfield id="SIG_NC_IN" width="6" begin="21" end="16" resetval="0x0" description="efuse trim for Nmos impedance" range="" rwaccess="RW"/>\r
1102     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
1103     <bitfield id="SIG_PC_IN" width="6" begin="13" end="8" resetval="0x0" description="efuse trim for Pmos impedance" range="" rwaccess="RW"/>\r
1104     <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>\r
1105     <bitfield id="SIG_REMOVE_SKEW" width="1" begin="6" end="6" resetval="0x0" description="Adjust for skew generated by the receiver due to asymmetric inputs. 0x0: skew compensation is disabled 0x1: skew compensation is enabled" range="" rwaccess="RW"/>\r
1106     <bitfield id="SIG_PWRDNRX" width="1" begin="5" end="5" resetval="0x1" description="powerdown receiver, active high 0x0 = Powered ON 0x1 = Powered OFF" range="" rwaccess="RW"/>\r
1107     <bitfield id="SIG_PWRDNTX" width="1" begin="4" end="4" resetval="0x1" description="powerdown transmitter, active high 0x0 = Powered ON 0x1 = Powered OFF" range="" rwaccess="RW"/>\r
1108     <bitfield id="SIG_EN_EXT_RES" width="1" begin="3" end="3" resetval="0x0" description="disables internal resistors 0x0 = Disabled 0x1 = Enabled" range="" rwaccess="RW"/>\r
1109     <bitfield id="RESERVED" width="3" begin="2" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
1110   </register>\r
1111   <register id="CTRL_CORE_MLB_DAT_IO_CTRL" acronym="CTRL_CORE_MLB_DAT_IO_CTRL" offset="0x6CC" width="32" description="Register to set the MLB's DAT IO characteristics">\r
1112     <bitfield id="RESERVED" width="10" begin="31" end="22" resetval="0x0" description="" range="" rwaccess="R"/>\r
1113     <bitfield id="DAT_NC_IN" width="6" begin="21" end="16" resetval="0x0" description="efuse trim for Nmos impedance" range="" rwaccess="RW"/>\r
1114     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
1115     <bitfield id="DAT_PC_IN" width="6" begin="13" end="8" resetval="0x0" description="efuse trim for Pmos impedance" range="" rwaccess="RW"/>\r
1116     <bitfield id="RESERVED" width="1" begin="7" end="7" resetval="0x0" description="" range="" rwaccess="R"/>\r
1117     <bitfield id="DAT_REMOVE_SKEW" width="1" begin="6" end="6" resetval="0x0" description="Adjust for skew generated by the receiver due to asymmetric inputs. 0x0: skew compensation is disabled 0x1: skew compensation is enabled" range="" rwaccess="RW"/>\r
1118     <bitfield id="DAT_PWRDNRX" width="1" begin="5" end="5" resetval="0x1" description="powerdown receiver, active high 0x0 = Powered ON 0x1 = Powered OFF" range="" rwaccess="RW"/>\r
1119     <bitfield id="DAT_PWRDNTX" width="1" begin="4" end="4" resetval="0x1" description="powerdown transmitter, active high 0x0 = Powered ON 0x1 = Powered OFF" range="" rwaccess="RW"/>\r
1120     <bitfield id="DAT_EN_EXT_RES" width="1" begin="3" end="3" resetval="0x0" description="Enable/disable internal resistors 0x0 = Disabled 0x1 = Enabled" range="" rwaccess="RW"/>\r
1121     <bitfield id="RESERVED" width="3" begin="2" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
1122   </register>\r
1123   <register id="CTRL_CORE_MLB_CLK_BG_CTRL" acronym="CTRL_CORE_MLB_CLK_BG_CTRL" offset="0x6D0" width="32" description="Register to set the MLB's clock receiver IO and bandgap characteristics">\r
1124     <bitfield id="RESERVED" width="15" begin="31" end="17" resetval="0x0" description="" range="" rwaccess="R"/>\r
1125     <bitfield id="T_HYSTERISIS_EN" width="1" begin="16" end="16" resetval="0x0" description="Hysterisis enable 0x0 = Disabled 0x1 = Enabled" range="" rwaccess="RW"/>\r
1126     <bitfield id="RESERVED" width="8" begin="15" end="8" resetval="0x0" description="" range="" rwaccess="R"/>\r
1127     <bitfield id="BG_TRIM" width="6" begin="7" end="2" resetval="0x0" description="Trim values for MLB bandgap" range="" rwaccess="RW"/>\r
1128     <bitfield id="BG_PWRDN" width="1" begin="1" end="1" resetval="0x0" description="MLB bandgap cell enable. 0x0 = The MLB bandgap cell is powered (enabled) 0x1 = The MLB bandgap cell is disabled" range="" rwaccess="RW"/>\r
1129     <bitfield id="CLK_PWRDN" width="1" begin="0" end="0" resetval="0x1" description="Enable the MLB differential clock receiver. 0x0 = MLB differential clock receiver is enabled 0x1 = MLB differential clock receiver is disabled" range="" rwaccess="RW"/>\r
1130   </register>\r
1131   <register id="CTRL_CORE_EVE1_IRQ_0_1" acronym="CTRL_CORE_EVE1_IRQ_0_1" offset="0x7A0" width="32" description="">\r
1132     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1133     <bitfield id="EVE1_IRQ_1" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>\r
1134     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1135     <bitfield id="EVE1_IRQ_0" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>\r
1136   </register>\r
1137   <register id="CTRL_CORE_EVE1_IRQ_2_3" acronym="CTRL_CORE_EVE1_IRQ_2_3" offset="0x7A4" width="32" description="">\r
1138     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1139     <bitfield id="EVE1_IRQ_3" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>\r
1140     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1141     <bitfield id="EVE1_IRQ_2" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>\r
1142   </register>\r
1143   <register id="CTRL_CORE_EVE1_IRQ_4_5" acronym="CTRL_CORE_EVE1_IRQ_4_5" offset="0x7A8" width="32" description="">\r
1144     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1145     <bitfield id="EVE1_IRQ_5" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>\r
1146     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1147     <bitfield id="EVE1_IRQ_4" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>\r
1148   </register>\r
1149   <register id="CTRL_CORE_EVE1_IRQ_6_7" acronym="CTRL_CORE_EVE1_IRQ_6_7" offset="0x7AC" width="32" description="">\r
1150     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1151     <bitfield id="EVE1_IRQ_7" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>\r
1152     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1153     <bitfield id="EVE1_IRQ_6" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>\r
1154   </register>\r
1155   <register id="CTRL_CORE_EVE2_IRQ_0_1" acronym="CTRL_CORE_EVE2_IRQ_0_1" offset="0x7B0" width="32" description="">\r
1156     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1157     <bitfield id="EVE2_IRQ_1" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>\r
1158     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1159     <bitfield id="EVE2_IRQ_0" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>\r
1160   </register>\r
1161   <register id="CTRL_CORE_EVE2_IRQ_2_3" acronym="CTRL_CORE_EVE2_IRQ_2_3" offset="0x7B4" width="32" description="">\r
1162     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1163     <bitfield id="EVE2_IRQ_3" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>\r
1164     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1165     <bitfield id="EVE2_IRQ_2" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>\r
1166   </register>\r
1167   <register id="CTRL_CORE_EVE2_IRQ_4_5" acronym="CTRL_CORE_EVE2_IRQ_4_5" offset="0x7B8" width="32" description="">\r
1168     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1169     <bitfield id="EVE2_IRQ_5" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>\r
1170     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1171     <bitfield id="EVE2_IRQ_4" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>\r
1172   </register>\r
1173   <register id="CTRL_CORE_EVE2_IRQ_6_7" acronym="CTRL_CORE_EVE2_IRQ_6_7" offset="0x7BC" width="32" description="">\r
1174     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1175     <bitfield id="EVE2_IRQ_7" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>\r
1176     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1177     <bitfield id="EVE2_IRQ_6" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>\r
1178   </register>\r
1179   <register id="CTRL_CORE_IPU1_IRQ_23_24" acronym="CTRL_CORE_IPU1_IRQ_23_24" offset="0x7E0" width="32" description="">\r
1180     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1181     <bitfield id="IPU1_IRQ_24" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>\r
1182     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1183     <bitfield id="IPU1_IRQ_23" width="9" begin="8" end="0" resetval="0x14" description="" range="" rwaccess="RW"/>\r
1184   </register>\r
1185   <register id="CTRL_CORE_IPU1_IRQ_25_26" acronym="CTRL_CORE_IPU1_IRQ_25_26" offset="0x7E4" width="32" description="">\r
1186     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1187     <bitfield id="IPU1_IRQ_26" width="9" begin="24" end="16" resetval="0x60" description="" range="" rwaccess="RW"/>\r
1188     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1189     <bitfield id="IPU1_IRQ_25" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>\r
1190   </register>\r
1191   <register id="CTRL_CORE_IPU1_IRQ_27_28" acronym="CTRL_CORE_IPU1_IRQ_27_28" offset="0x7E8" width="32" description="">\r
1192     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1193     <bitfield id="IPU1_IRQ_28" width="9" begin="24" end="16" resetval="0x7F" description="" range="" rwaccess="RW"/>\r
1194     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1195     <bitfield id="IPU1_IRQ_27" width="9" begin="8" end="0" resetval="0x7E" description="" range="" rwaccess="RW"/>\r
1196   </register>\r
1197   <register id="CTRL_CORE_IPU1_IRQ_29_30" acronym="CTRL_CORE_IPU1_IRQ_29_30" offset="0x7EC" width="32" description="">\r
1198     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1199     <bitfield id="IPU1_IRQ_30" width="9" begin="24" end="16" resetval="0x81" description="" range="" rwaccess="RW"/>\r
1200     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1201     <bitfield id="IPU1_IRQ_29" width="9" begin="8" end="0" resetval="0x80" description="" range="" rwaccess="RW"/>\r
1202   </register>\r
1203   <register id="CTRL_CORE_IPU1_IRQ_31_32" acronym="CTRL_CORE_IPU1_IRQ_31_32" offset="0x7F0" width="32" description="">\r
1204     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1205     <bitfield id="IPU1_IRQ_32" width="9" begin="24" end="16" resetval="0x13" description="" range="" rwaccess="RW"/>\r
1206     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1207     <bitfield id="IPU1_IRQ_31" width="9" begin="8" end="0" resetval="0x82" description="" range="" rwaccess="RW"/>\r
1208   </register>\r
1209   <register id="CTRL_CORE_IPU1_IRQ_33_34" acronym="CTRL_CORE_IPU1_IRQ_33_34" offset="0x7F4" width="32" description="">\r
1210     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1211     <bitfield id="IPU1_IRQ_34" width="9" begin="24" end="16" resetval="0x7" description="" range="" rwaccess="RW"/>\r
1212     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1213     <bitfield id="IPU1_IRQ_33" width="9" begin="8" end="0" resetval="0x83" description="" range="" rwaccess="RW"/>\r
1214   </register>\r
1215   <register id="CTRL_CORE_IPU1_IRQ_35_36" acronym="CTRL_CORE_IPU1_IRQ_35_36" offset="0x7F8" width="32" description="">\r
1216     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1217     <bitfield id="IPU1_IRQ_36" width="9" begin="24" end="16" resetval="0x9" description="" range="" rwaccess="RW"/>\r
1218     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1219     <bitfield id="IPU1_IRQ_35" width="9" begin="8" end="0" resetval="0x8" description="" range="" rwaccess="RW"/>\r
1220   </register>\r
1221   <register id="CTRL_CORE_IPU1_IRQ_37_38" acronym="CTRL_CORE_IPU1_IRQ_37_38" offset="0x7FC" width="32" description="">\r
1222     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1223     <bitfield id="IPU1_IRQ_38" width="9" begin="24" end="16" resetval="0x84" description="" range="" rwaccess="RW"/>\r
1224     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1225     <bitfield id="IPU1_IRQ_37" width="9" begin="8" end="0" resetval="0xA" description="" range="" rwaccess="RW"/>\r
1226   </register>\r
1227   <register id="CTRL_CORE_IPU1_IRQ_39_40" acronym="CTRL_CORE_IPU1_IRQ_39_40" offset="0x800" width="32" description="">\r
1228     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1229     <bitfield id="IPU1_IRQ_40" width="9" begin="24" end="16" resetval="0x63" description="" range="" rwaccess="RW"/>\r
1230     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1231     <bitfield id="IPU1_IRQ_39" width="9" begin="8" end="0" resetval="0x62" description="" range="" rwaccess="RW"/>\r
1232   </register>\r
1233   <register id="CTRL_CORE_IPU1_IRQ_41_42" acronym="CTRL_CORE_IPU1_IRQ_41_42" offset="0x804" width="32" description="">\r
1234     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1235     <bitfield id="IPU1_IRQ_42" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>\r
1236     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1237     <bitfield id="IPU1_IRQ_41" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>\r
1238   </register>\r
1239   <register id="CTRL_CORE_IPU1_IRQ_43_44" acronym="CTRL_CORE_IPU1_IRQ_43_44" offset="0x808" width="32" description="">\r
1240     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1241     <bitfield id="IPU1_IRQ_44" width="9" begin="24" end="16" resetval="0x39" description="" range="" rwaccess="RW"/>\r
1242     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1243     <bitfield id="IPU1_IRQ_43" width="9" begin="8" end="0" resetval="0x38" description="" range="" rwaccess="RW"/>\r
1244   </register>\r
1245   <register id="CTRL_CORE_IPU1_IRQ_45_46" acronym="CTRL_CORE_IPU1_IRQ_45_46" offset="0x80C" width="32" description="">\r
1246     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1247     <bitfield id="IPU1_IRQ_46" width="9" begin="24" end="16" resetval="0x5" description="" range="" rwaccess="RW"/>\r
1248     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1249     <bitfield id="IPU1_IRQ_45" width="9" begin="8" end="0" resetval="0x45" description="" range="" rwaccess="RW"/>\r
1250   </register>\r
1251   <register id="CTRL_CORE_IPU1_IRQ_47_48" acronym="CTRL_CORE_IPU1_IRQ_47_48" offset="0x810" width="32" description="">\r
1252     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1253     <bitfield id="IPU1_IRQ_48" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>\r
1254     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1255     <bitfield id="IPU1_IRQ_47" width="9" begin="8" end="0" resetval="0x85" description="" range="" rwaccess="RW"/>\r
1256   </register>\r
1257   <register id="CTRL_CORE_IPU1_IRQ_49_50" acronym="CTRL_CORE_IPU1_IRQ_49_50" offset="0x814" width="32" description="">\r
1258     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1259     <bitfield id="IPU1_IRQ_50" width="9" begin="24" end="16" resetval="0x86" description="" range="" rwaccess="RW"/>\r
1260     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1261     <bitfield id="IPU1_IRQ_49" width="9" begin="8" end="0" resetval="0x42" description="" range="" rwaccess="RW"/>\r
1262   </register>\r
1263   <register id="CTRL_CORE_IPU1_IRQ_51_52" acronym="CTRL_CORE_IPU1_IRQ_51_52" offset="0x818" width="32" description="">\r
1264     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1265     <bitfield id="IPU1_IRQ_52" width="9" begin="24" end="16" resetval="0x19" description="" range="" rwaccess="RW"/>\r
1266     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1267     <bitfield id="IPU1_IRQ_51" width="9" begin="8" end="0" resetval="0x18" description="" range="" rwaccess="RW"/>\r
1268   </register>\r
1269   <register id="CTRL_CORE_IPU1_IRQ_53_54" acronym="CTRL_CORE_IPU1_IRQ_53_54" offset="0x81C" width="32" description="">\r
1270     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1271     <bitfield id="IPU1_IRQ_54" width="9" begin="24" end="16" resetval="0x23" description="" range="" rwaccess="RW"/>\r
1272     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1273     <bitfield id="IPU1_IRQ_53" width="9" begin="8" end="0" resetval="0x22" description="" range="" rwaccess="RW"/>\r
1274   </register>\r
1275   <register id="CTRL_CORE_IPU1_IRQ_55_56" acronym="CTRL_CORE_IPU1_IRQ_55_56" offset="0x820" width="32" description="">\r
1276     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1277     <bitfield id="IPU1_IRQ_56" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>\r
1278     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1279     <bitfield id="IPU1_IRQ_55" width="9" begin="8" end="0" resetval="0x28" description="" range="" rwaccess="RW"/>\r
1280   </register>\r
1281   <register id="CTRL_CORE_IPU1_IRQ_57_58" acronym="CTRL_CORE_IPU1_IRQ_57_58" offset="0x824" width="32" description="">\r
1282     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1283     <bitfield id="IPU1_IRQ_58" width="9" begin="24" end="16" resetval="0x3D" description="" range="" rwaccess="RW"/>\r
1284     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1285     <bitfield id="IPU1_IRQ_57" width="9" begin="8" end="0" resetval="0x3C" description="" range="" rwaccess="RW"/>\r
1286   </register>\r
1287   <register id="CTRL_CORE_IPU1_IRQ_59_60" acronym="CTRL_CORE_IPU1_IRQ_59_60" offset="0x828" width="32" description="">\r
1288     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1289     <bitfield id="IPU1_IRQ_60" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>\r
1290     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1291     <bitfield id="IPU1_IRQ_59" width="9" begin="8" end="0" resetval="0x32" description="" range="" rwaccess="RW"/>\r
1292   </register>\r
1293   <register id="CTRL_CORE_IPU1_IRQ_61_62" acronym="CTRL_CORE_IPU1_IRQ_61_62" offset="0x82C" width="32" description="">\r
1294     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1295     <bitfield id="IPU1_IRQ_62" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>\r
1296     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1297     <bitfield id="IPU1_IRQ_61" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>\r
1298   </register>\r
1299   <register id="CTRL_CORE_IPU1_IRQ_63_64" acronym="CTRL_CORE_IPU1_IRQ_63_64" offset="0x830" width="32" description="">\r
1300     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1301     <bitfield id="IPU1_IRQ_64" width="9" begin="24" end="16" resetval="0x6C" description="" range="" rwaccess="RW"/>\r
1302     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1303     <bitfield id="IPU1_IRQ_63" width="9" begin="8" end="0" resetval="0x53" description="" range="" rwaccess="RW"/>\r
1304   </register>\r
1305   <register id="CTRL_CORE_IPU1_IRQ_65_66" acronym="CTRL_CORE_IPU1_IRQ_65_66" offset="0x834" width="32" description="">\r
1306     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1307     <bitfield id="IPU1_IRQ_66" width="9" begin="24" end="16" resetval="0x4E" description="" range="" rwaccess="RW"/>\r
1308     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1309     <bitfield id="IPU1_IRQ_65" width="9" begin="8" end="0" resetval="0x78" description="" range="" rwaccess="RW"/>\r
1310   </register>\r
1311   <register id="CTRL_CORE_IPU1_IRQ_67_68" acronym="CTRL_CORE_IPU1_IRQ_67_68" offset="0x838" width="32" description="">\r
1312     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1313     <bitfield id="IPU1_IRQ_68" width="9" begin="24" end="16" resetval="0x59" description="" range="" rwaccess="RW"/>\r
1314     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1315     <bitfield id="IPU1_IRQ_67" width="9" begin="8" end="0" resetval="0x51" description="" range="" rwaccess="RW"/>\r
1316   </register>\r
1317   <register id="CTRL_CORE_IPU1_IRQ_69_70" acronym="CTRL_CORE_IPU1_IRQ_69_70" offset="0x83C" width="32" description="">\r
1318     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1319     <bitfield id="IPU1_IRQ_70" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>\r
1320     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1321     <bitfield id="IPU1_IRQ_69" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>\r
1322   </register>\r
1323   <register id="CTRL_CORE_IPU1_IRQ_71_72" acronym="CTRL_CORE_IPU1_IRQ_71_72" offset="0x840" width="32" description="">\r
1324     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1325     <bitfield id="IPU1_IRQ_72" width="9" begin="24" end="16" resetval="0x76" description="" range="" rwaccess="RW"/>\r
1326     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1327     <bitfield id="IPU1_IRQ_71" width="9" begin="8" end="0" resetval="0x77" description="" range="" rwaccess="RW"/>\r
1328   </register>\r
1329   <register id="CTRL_CORE_IPU1_IRQ_73_74" acronym="CTRL_CORE_IPU1_IRQ_73_74" offset="0x844" width="32" description="">\r
1330     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1331     <bitfield id="IPU1_IRQ_74" width="9" begin="24" end="16" resetval="0x49" description="" range="" rwaccess="RW"/>\r
1332     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1333     <bitfield id="IPU1_IRQ_73" width="9" begin="8" end="0" resetval="0x48" description="" range="" rwaccess="RW"/>\r
1334   </register>\r
1335   <register id="CTRL_CORE_IPU1_IRQ_75_76" acronym="CTRL_CORE_IPU1_IRQ_75_76" offset="0x848" width="32" description="">\r
1336     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1337     <bitfield id="IPU1_IRQ_76" width="9" begin="24" end="16" resetval="0x57" description="" range="" rwaccess="RW"/>\r
1338     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1339     <bitfield id="IPU1_IRQ_75" width="9" begin="8" end="0" resetval="0x75" description="" range="" rwaccess="RW"/>\r
1340   </register>\r
1341   <register id="CTRL_CORE_IPU1_IRQ_77_78" acronym="CTRL_CORE_IPU1_IRQ_77_78" offset="0x84C" width="32" description="">\r
1342     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1343     <bitfield id="IPU1_IRQ_78" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>\r
1344     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1345     <bitfield id="IPU1_IRQ_77" width="9" begin="8" end="0" resetval="0x58" description="" range="" rwaccess="RW"/>\r
1346   </register>\r
1347   <register id="CTRL_CORE_IPU1_IRQ_79_80" acronym="CTRL_CORE_IPU1_IRQ_79_80" offset="0x850" width="32" description="">\r
1348     <bitfield id="RESERVED" width="23" begin="31" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1349     <bitfield id="IPU1_IRQ_79" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>\r
1350   </register>\r
1351   <register id="CTRL_CORE_IPU2_IRQ_23_24" acronym="CTRL_CORE_IPU2_IRQ_23_24" offset="0x854" width="32" description="">\r
1352     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1353     <bitfield id="IPU2_IRQ_24" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>\r
1354     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1355     <bitfield id="IPU2_IRQ_23" width="9" begin="8" end="0" resetval="0x14" description="" range="" rwaccess="RW"/>\r
1356   </register>\r
1357   <register id="CTRL_CORE_IPU2_IRQ_25_26" acronym="CTRL_CORE_IPU2_IRQ_25_26" offset="0x858" width="32" description="">\r
1358     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1359     <bitfield id="IPU2_IRQ_26" width="9" begin="24" end="16" resetval="0x60" description="" range="" rwaccess="RW"/>\r
1360     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1361     <bitfield id="IPU2_IRQ_25" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>\r
1362   </register>\r
1363   <register id="CTRL_CORE_IPU2_IRQ_27_28" acronym="CTRL_CORE_IPU2_IRQ_27_28" offset="0x85C" width="32" description="">\r
1364     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1365     <bitfield id="IPU2_IRQ_28" width="9" begin="24" end="16" resetval="0x7F" description="" range="" rwaccess="RW"/>\r
1366     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1367     <bitfield id="IPU2_IRQ_27" width="9" begin="8" end="0" resetval="0x7E" description="" range="" rwaccess="RW"/>\r
1368   </register>\r
1369   <register id="CTRL_CORE_IPU2_IRQ_29_30" acronym="CTRL_CORE_IPU2_IRQ_29_30" offset="0x860" width="32" description="">\r
1370     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1371     <bitfield id="IPU2_IRQ_30" width="9" begin="24" end="16" resetval="0x81" description="" range="" rwaccess="RW"/>\r
1372     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1373     <bitfield id="IPU2_IRQ_29" width="9" begin="8" end="0" resetval="0x80" description="" range="" rwaccess="RW"/>\r
1374   </register>\r
1375   <register id="CTRL_CORE_IPU2_IRQ_31_32" acronym="CTRL_CORE_IPU2_IRQ_31_32" offset="0x864" width="32" description="">\r
1376     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1377     <bitfield id="IPU2_IRQ_32" width="9" begin="24" end="16" resetval="0x13" description="" range="" rwaccess="RW"/>\r
1378     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1379     <bitfield id="IPU2_IRQ_31" width="9" begin="8" end="0" resetval="0x82" description="" range="" rwaccess="RW"/>\r
1380   </register>\r
1381   <register id="CTRL_CORE_IPU2_IRQ_33_34" acronym="CTRL_CORE_IPU2_IRQ_33_34" offset="0x868" width="32" description="">\r
1382     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1383     <bitfield id="IPU2_IRQ_34" width="9" begin="24" end="16" resetval="0x7" description="" range="" rwaccess="RW"/>\r
1384     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1385     <bitfield id="IPU2_IRQ_33" width="9" begin="8" end="0" resetval="0x83" description="" range="" rwaccess="RW"/>\r
1386   </register>\r
1387   <register id="CTRL_CORE_IPU2_IRQ_35_36" acronym="CTRL_CORE_IPU2_IRQ_35_36" offset="0x86C" width="32" description="">\r
1388     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1389     <bitfield id="IPU2_IRQ_36" width="9" begin="24" end="16" resetval="0x9" description="" range="" rwaccess="RW"/>\r
1390     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1391     <bitfield id="IPU2_IRQ_35" width="9" begin="8" end="0" resetval="0x8" description="" range="" rwaccess="RW"/>\r
1392   </register>\r
1393   <register id="CTRL_CORE_IPU2_IRQ_37_38" acronym="CTRL_CORE_IPU2_IRQ_37_38" offset="0x870" width="32" description="">\r
1394     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1395     <bitfield id="IPU2_IRQ_38" width="9" begin="24" end="16" resetval="0x84" description="" range="" rwaccess="RW"/>\r
1396     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1397     <bitfield id="IPU2_IRQ_37" width="9" begin="8" end="0" resetval="0xA" description="" range="" rwaccess="RW"/>\r
1398   </register>\r
1399   <register id="CTRL_CORE_IPU2_IRQ_39_40" acronym="CTRL_CORE_IPU2_IRQ_39_40" offset="0x874" width="32" description="">\r
1400     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1401     <bitfield id="IPU2_IRQ_40" width="9" begin="24" end="16" resetval="0x63" description="" range="" rwaccess="RW"/>\r
1402     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1403     <bitfield id="IPU2_IRQ_39" width="9" begin="8" end="0" resetval="0x62" description="" range="" rwaccess="RW"/>\r
1404   </register>\r
1405   <register id="CTRL_CORE_IPU2_IRQ_41_42" acronym="CTRL_CORE_IPU2_IRQ_41_42" offset="0x878" width="32" description="">\r
1406     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1407     <bitfield id="IPU2_IRQ_42" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>\r
1408     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1409     <bitfield id="IPU2_IRQ_41" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>\r
1410   </register>\r
1411   <register id="CTRL_CORE_IPU2_IRQ_43_44" acronym="CTRL_CORE_IPU2_IRQ_43_44" offset="0x87C" width="32" description="">\r
1412     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1413     <bitfield id="IPU2_IRQ_44" width="9" begin="24" end="16" resetval="0x39" description="" range="" rwaccess="RW"/>\r
1414     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1415     <bitfield id="IPU2_IRQ_43" width="9" begin="8" end="0" resetval="0x38" description="" range="" rwaccess="RW"/>\r
1416   </register>\r
1417   <register id="CTRL_CORE_IPU2_IRQ_45_46" acronym="CTRL_CORE_IPU2_IRQ_45_46" offset="0x880" width="32" description="">\r
1418     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1419     <bitfield id="IPU2_IRQ_46" width="9" begin="24" end="16" resetval="0x5" description="" range="" rwaccess="RW"/>\r
1420     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1421     <bitfield id="IPU2_IRQ_45" width="9" begin="8" end="0" resetval="0x45" description="" range="" rwaccess="RW"/>\r
1422   </register>\r
1423   <register id="CTRL_CORE_IPU2_IRQ_47_48" acronym="CTRL_CORE_IPU2_IRQ_47_48" offset="0x884" width="32" description="">\r
1424     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1425     <bitfield id="IPU2_IRQ_48" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>\r
1426     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1427     <bitfield id="IPU2_IRQ_47" width="9" begin="8" end="0" resetval="0x85" description="" range="" rwaccess="RW"/>\r
1428   </register>\r
1429   <register id="CTRL_CORE_IPU2_IRQ_49_50" acronym="CTRL_CORE_IPU2_IRQ_49_50" offset="0x888" width="32" description="">\r
1430     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1431     <bitfield id="IPU2_IRQ_50" width="9" begin="24" end="16" resetval="0x86" description="" range="" rwaccess="RW"/>\r
1432     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1433     <bitfield id="IPU2_IRQ_49" width="9" begin="8" end="0" resetval="0x42" description="" range="" rwaccess="RW"/>\r
1434   </register>\r
1435   <register id="CTRL_CORE_IPU2_IRQ_51_52" acronym="CTRL_CORE_IPU2_IRQ_51_52" offset="0x88C" width="32" description="">\r
1436     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1437     <bitfield id="IPU2_IRQ_52" width="9" begin="24" end="16" resetval="0x19" description="" range="" rwaccess="RW"/>\r
1438     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1439     <bitfield id="IPU2_IRQ_51" width="9" begin="8" end="0" resetval="0x18" description="" range="" rwaccess="RW"/>\r
1440   </register>\r
1441   <register id="CTRL_CORE_IPU2_IRQ_53_54" acronym="CTRL_CORE_IPU2_IRQ_53_54" offset="0x890" width="32" description="">\r
1442     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1443     <bitfield id="IPU2_IRQ_54" width="9" begin="24" end="16" resetval="0x23" description="" range="" rwaccess="RW"/>\r
1444     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1445     <bitfield id="IPU2_IRQ_53" width="9" begin="8" end="0" resetval="0x22" description="" range="" rwaccess="RW"/>\r
1446   </register>\r
1447   <register id="CTRL_CORE_IPU2_IRQ_55_56" acronym="CTRL_CORE_IPU2_IRQ_55_56" offset="0x894" width="32" description="">\r
1448     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1449     <bitfield id="IPU2_IRQ_56" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>\r
1450     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1451     <bitfield id="IPU2_IRQ_55" width="9" begin="8" end="0" resetval="0x28" description="" range="" rwaccess="RW"/>\r
1452   </register>\r
1453   <register id="CTRL_CORE_IPU2_IRQ_57_58" acronym="CTRL_CORE_IPU2_IRQ_57_58" offset="0x898" width="32" description="">\r
1454     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1455     <bitfield id="IPU2_IRQ_58" width="9" begin="24" end="16" resetval="0x3D" description="" range="" rwaccess="RW"/>\r
1456     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1457     <bitfield id="IPU2_IRQ_57" width="9" begin="8" end="0" resetval="0x3C" description="" range="" rwaccess="RW"/>\r
1458   </register>\r
1459   <register id="CTRL_CORE_IPU2_IRQ_59_60" acronym="CTRL_CORE_IPU2_IRQ_59_60" offset="0x89C" width="32" description="">\r
1460     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1461     <bitfield id="IPU2_IRQ_60" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>\r
1462     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1463     <bitfield id="IPU2_IRQ_59" width="9" begin="8" end="0" resetval="0x32" description="" range="" rwaccess="RW"/>\r
1464   </register>\r
1465   <register id="CTRL_CORE_IPU2_IRQ_61_62" acronym="CTRL_CORE_IPU2_IRQ_61_62" offset="0x8A0" width="32" description="">\r
1466     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1467     <bitfield id="IPU2_IRQ_62" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>\r
1468     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1469     <bitfield id="IPU2_IRQ_61" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>\r
1470   </register>\r
1471   <register id="CTRL_CORE_IPU2_IRQ_63_64" acronym="CTRL_CORE_IPU2_IRQ_63_64" offset="0x8A4" width="32" description="">\r
1472     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1473     <bitfield id="IPU2_IRQ_64" width="9" begin="24" end="16" resetval="0x6C" description="" range="" rwaccess="RW"/>\r
1474     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1475     <bitfield id="IPU2_IRQ_63" width="9" begin="8" end="0" resetval="0x53" description="" range="" rwaccess="RW"/>\r
1476   </register>\r
1477   <register id="CTRL_CORE_IPU2_IRQ_65_66" acronym="CTRL_CORE_IPU2_IRQ_65_66" offset="0x8A8" width="32" description="">\r
1478     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1479     <bitfield id="IPU2_IRQ_66" width="9" begin="24" end="16" resetval="0x4E" description="" range="" rwaccess="RW"/>\r
1480     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1481     <bitfield id="IPU2_IRQ_65" width="9" begin="8" end="0" resetval="0x78" description="" range="" rwaccess="RW"/>\r
1482   </register>\r
1483   <register id="CTRL_CORE_IPU2_IRQ_67_68" acronym="CTRL_CORE_IPU2_IRQ_67_68" offset="0x8AC" width="32" description="">\r
1484     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1485     <bitfield id="IPU2_IRQ_68" width="9" begin="24" end="16" resetval="0x59" description="" range="" rwaccess="RW"/>\r
1486     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1487     <bitfield id="IPU2_IRQ_67" width="9" begin="8" end="0" resetval="0x51" description="" range="" rwaccess="RW"/>\r
1488   </register>\r
1489   <register id="CTRL_CORE_IPU2_IRQ_69_70" acronym="CTRL_CORE_IPU2_IRQ_69_70" offset="0x8B0" width="32" description="">\r
1490     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1491     <bitfield id="IPU2_IRQ_70" width="9" begin="24" end="16" resetval="0x0" description="" range="" rwaccess="RW"/>\r
1492     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1493     <bitfield id="IPU2_IRQ_69" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>\r
1494   </register>\r
1495   <register id="CTRL_CORE_IPU2_IRQ_71_72" acronym="CTRL_CORE_IPU2_IRQ_71_72" offset="0x8B4" width="32" description="">\r
1496     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1497     <bitfield id="IPU2_IRQ_72" width="9" begin="24" end="16" resetval="0x76" description="" range="" rwaccess="RW"/>\r
1498     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1499     <bitfield id="IPU2_IRQ_71" width="9" begin="8" end="0" resetval="0x77" description="" range="" rwaccess="RW"/>\r
1500   </register>\r
1501   <register id="CTRL_CORE_IPU2_IRQ_73_74" acronym="CTRL_CORE_IPU2_IRQ_73_74" offset="0x8B8" width="32" description="">\r
1502     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1503     <bitfield id="IPU2_IRQ_74" width="9" begin="24" end="16" resetval="0x49" description="" range="" rwaccess="RW"/>\r
1504     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1505     <bitfield id="IPU2_IRQ_73" width="9" begin="8" end="0" resetval="0x48" description="" range="" rwaccess="RW"/>\r
1506   </register>\r
1507   <register id="CTRL_CORE_IPU2_IRQ_75_76" acronym="CTRL_CORE_IPU2_IRQ_75_76" offset="0x8BC" width="32" description="">\r
1508     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1509     <bitfield id="IPU2_IRQ_76" width="9" begin="24" end="16" resetval="0x57" description="" range="" rwaccess="RW"/>\r
1510     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1511     <bitfield id="IPU2_IRQ_75" width="9" begin="8" end="0" resetval="0x75" description="" range="" rwaccess="RW"/>\r
1512   </register>\r
1513   <register id="CTRL_CORE_IPU2_IRQ_77_78" acronym="CTRL_CORE_IPU2_IRQ_77_78" offset="0x8C0" width="32" description="">\r
1514     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1515     <bitfield id="IPU2_IRQ_78" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>\r
1516     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1517     <bitfield id="IPU2_IRQ_77" width="9" begin="8" end="0" resetval="0x58" description="" range="" rwaccess="RW"/>\r
1518   </register>\r
1519   <register id="CTRL_CORE_IPU2_IRQ_79_80" acronym="CTRL_CORE_IPU2_IRQ_79_80" offset="0x8C4" width="32" description="">\r
1520     <bitfield id="RESERVED" width="23" begin="31" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1521     <bitfield id="IPU2_IRQ_79" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>\r
1522   </register>\r
1523   <register id="CTRL_CORE_DSP1_IRQ_32_33" acronym="CTRL_CORE_DSP1_IRQ_32_33" offset="0x948" width="32" description="">\r
1524     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1525     <bitfield id="DSP1_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>\r
1526     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1527     <bitfield id="DSP1_IRQ_32" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>\r
1528   </register>\r
1529   <register id="CTRL_CORE_DSP1_IRQ_34_35" acronym="CTRL_CORE_DSP1_IRQ_34_35" offset="0x94C" width="32" description="">\r
1530     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1531     <bitfield id="DSP1_IRQ_35" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>\r
1532     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1533     <bitfield id="DSP1_IRQ_34" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>\r
1534   </register>\r
1535   <register id="CTRL_CORE_DSP1_IRQ_36_37" acronym="CTRL_CORE_DSP1_IRQ_36_37" offset="0x950" width="32" description="">\r
1536     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1537     <bitfield id="DSP1_IRQ_37" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>\r
1538     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1539     <bitfield id="DSP1_IRQ_36" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>\r
1540   </register>\r
1541   <register id="CTRL_CORE_DSP1_IRQ_38_39" acronym="CTRL_CORE_DSP1_IRQ_38_39" offset="0x954" width="32" description="">\r
1542     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1543     <bitfield id="DSP1_IRQ_39" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>\r
1544     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1545     <bitfield id="DSP1_IRQ_38" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>\r
1546   </register>\r
1547   <register id="CTRL_CORE_DSP1_IRQ_40_41" acronym="CTRL_CORE_DSP1_IRQ_40_41" offset="0x958" width="32" description="">\r
1548     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1549     <bitfield id="DSP1_IRQ_41" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>\r
1550     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1551     <bitfield id="DSP1_IRQ_40" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>\r
1552   </register>\r
1553   <register id="CTRL_CORE_DSP1_IRQ_42_43" acronym="CTRL_CORE_DSP1_IRQ_42_43" offset="0x95C" width="32" description="">\r
1554     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1555     <bitfield id="DSP1_IRQ_43" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>\r
1556     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1557     <bitfield id="DSP1_IRQ_42" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>\r
1558   </register>\r
1559   <register id="CTRL_CORE_DSP1_IRQ_44_45" acronym="CTRL_CORE_DSP1_IRQ_44_45" offset="0x960" width="32" description="">\r
1560     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1561     <bitfield id="DSP1_IRQ_45" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>\r
1562     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1563     <bitfield id="DSP1_IRQ_44" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>\r
1564   </register>\r
1565   <register id="CTRL_CORE_DSP1_IRQ_46_47" acronym="CTRL_CORE_DSP1_IRQ_46_47" offset="0x964" width="32" description="">\r
1566     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1567     <bitfield id="DSP1_IRQ_47" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>\r
1568     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1569     <bitfield id="DSP1_IRQ_46" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>\r
1570   </register>\r
1571   <register id="CTRL_CORE_DSP1_IRQ_48_49" acronym="CTRL_CORE_DSP1_IRQ_48_49" offset="0x968" width="32" description="">\r
1572     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1573     <bitfield id="DSP1_IRQ_49" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>\r
1574     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1575     <bitfield id="DSP1_IRQ_48" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>\r
1576   </register>\r
1577   <register id="CTRL_CORE_DSP1_IRQ_50_51" acronym="CTRL_CORE_DSP1_IRQ_50_51" offset="0x96C" width="32" description="">\r
1578     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1579     <bitfield id="DSP1_IRQ_51" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>\r
1580     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1581     <bitfield id="DSP1_IRQ_50" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>\r
1582   </register>\r
1583   <register id="CTRL_CORE_DSP1_IRQ_52_53" acronym="CTRL_CORE_DSP1_IRQ_52_53" offset="0x970" width="32" description="">\r
1584     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1585     <bitfield id="DSP1_IRQ_53" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>\r
1586     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1587     <bitfield id="DSP1_IRQ_52" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>\r
1588   </register>\r
1589   <register id="CTRL_CORE_DSP1_IRQ_54_55" acronym="CTRL_CORE_DSP1_IRQ_54_55" offset="0x974" width="32" description="">\r
1590     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1591     <bitfield id="DSP1_IRQ_55" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>\r
1592     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1593     <bitfield id="DSP1_IRQ_54" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>\r
1594   </register>\r
1595   <register id="CTRL_CORE_DSP1_IRQ_56_57" acronym="CTRL_CORE_DSP1_IRQ_56_57" offset="0x978" width="32" description="">\r
1596     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1597     <bitfield id="DSP1_IRQ_57" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>\r
1598     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1599     <bitfield id="DSP1_IRQ_56" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>\r
1600   </register>\r
1601   <register id="CTRL_CORE_DSP1_IRQ_58_59" acronym="CTRL_CORE_DSP1_IRQ_58_59" offset="0x97C" width="32" description="">\r
1602     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1603     <bitfield id="DSP1_IRQ_59" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>\r
1604     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1605     <bitfield id="DSP1_IRQ_58" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>\r
1606   </register>\r
1607   <register id="CTRL_CORE_DSP1_IRQ_60_61" acronym="CTRL_CORE_DSP1_IRQ_60_61" offset="0x980" width="32" description="">\r
1608     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1609     <bitfield id="DSP1_IRQ_61" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>\r
1610     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1611     <bitfield id="DSP1_IRQ_60" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>\r
1612   </register>\r
1613   <register id="CTRL_CORE_DSP1_IRQ_62_63" acronym="CTRL_CORE_DSP1_IRQ_62_63" offset="0x984" width="32" description="">\r
1614     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1615     <bitfield id="DSP1_IRQ_63" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>\r
1616     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1617     <bitfield id="DSP1_IRQ_62" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>\r
1618   </register>\r
1619   <register id="CTRL_CORE_DSP1_IRQ_64_65" acronym="CTRL_CORE_DSP1_IRQ_64_65" offset="0x988" width="32" description="">\r
1620     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1621     <bitfield id="DSP1_IRQ_65" width="9" begin="24" end="16" resetval="0x22" description="" range="" rwaccess="RW"/>\r
1622     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1623     <bitfield id="DSP1_IRQ_64" width="9" begin="8" end="0" resetval="0x21" description="" range="" rwaccess="RW"/>\r
1624   </register>\r
1625   <register id="CTRL_CORE_DSP1_IRQ_66_67" acronym="CTRL_CORE_DSP1_IRQ_66_67" offset="0x98C" width="32" description="">\r
1626     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1627     <bitfield id="DSP1_IRQ_67" width="9" begin="24" end="16" resetval="0x24" description="" range="" rwaccess="RW"/>\r
1628     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1629     <bitfield id="DSP1_IRQ_66" width="9" begin="8" end="0" resetval="0x23" description="" range="" rwaccess="RW"/>\r
1630   </register>\r
1631   <register id="CTRL_CORE_DSP1_IRQ_68_69" acronym="CTRL_CORE_DSP1_IRQ_68_69" offset="0x990" width="32" description="">\r
1632     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1633     <bitfield id="DSP1_IRQ_69" width="9" begin="24" end="16" resetval="0x26" description="" range="" rwaccess="RW"/>\r
1634     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1635     <bitfield id="DSP1_IRQ_68" width="9" begin="8" end="0" resetval="0x25" description="" range="" rwaccess="RW"/>\r
1636   </register>\r
1637   <register id="CTRL_CORE_DSP1_IRQ_70_71" acronym="CTRL_CORE_DSP1_IRQ_70_71" offset="0x994" width="32" description="">\r
1638     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1639     <bitfield id="DSP1_IRQ_71" width="9" begin="24" end="16" resetval="0x28" description="" range="" rwaccess="RW"/>\r
1640     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1641     <bitfield id="DSP1_IRQ_70" width="9" begin="8" end="0" resetval="0x27" description="" range="" rwaccess="RW"/>\r
1642   </register>\r
1643   <register id="CTRL_CORE_DSP1_IRQ_72_73" acronym="CTRL_CORE_DSP1_IRQ_72_73" offset="0x998" width="32" description="">\r
1644     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1645     <bitfield id="DSP1_IRQ_73" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>\r
1646     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1647     <bitfield id="DSP1_IRQ_72" width="9" begin="8" end="0" resetval="0x29" description="" range="" rwaccess="RW"/>\r
1648   </register>\r
1649   <register id="CTRL_CORE_DSP1_IRQ_74_75" acronym="CTRL_CORE_DSP1_IRQ_74_75" offset="0x99C" width="32" description="">\r
1650     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1651     <bitfield id="DSP1_IRQ_75" width="9" begin="24" end="16" resetval="0x2C" description="" range="" rwaccess="RW"/>\r
1652     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1653     <bitfield id="DSP1_IRQ_74" width="9" begin="8" end="0" resetval="0x2B" description="" range="" rwaccess="RW"/>\r
1654   </register>\r
1655   <register id="CTRL_CORE_DSP1_IRQ_76_77" acronym="CTRL_CORE_DSP1_IRQ_76_77" offset="0x9A0" width="32" description="">\r
1656     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1657     <bitfield id="DSP1_IRQ_77" width="9" begin="24" end="16" resetval="0x2E" description="" range="" rwaccess="RW"/>\r
1658     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1659     <bitfield id="DSP1_IRQ_76" width="9" begin="8" end="0" resetval="0x2D" description="" range="" rwaccess="RW"/>\r
1660   </register>\r
1661   <register id="CTRL_CORE_DSP1_IRQ_78_79" acronym="CTRL_CORE_DSP1_IRQ_78_79" offset="0x9A4" width="32" description="">\r
1662     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1663     <bitfield id="DSP1_IRQ_79" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>\r
1664     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1665     <bitfield id="DSP1_IRQ_78" width="9" begin="8" end="0" resetval="0x2F" description="" range="" rwaccess="RW"/>\r
1666   </register>\r
1667   <register id="CTRL_CORE_DSP1_IRQ_80_81" acronym="CTRL_CORE_DSP1_IRQ_80_81" offset="0x9A8" width="32" description="">\r
1668     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1669     <bitfield id="DSP1_IRQ_81" width="9" begin="24" end="16" resetval="0x32" description="" range="" rwaccess="RW"/>\r
1670     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1671     <bitfield id="DSP1_IRQ_80" width="9" begin="8" end="0" resetval="0x31" description="" range="" rwaccess="RW"/>\r
1672   </register>\r
1673   <register id="CTRL_CORE_DSP1_IRQ_82_83" acronym="CTRL_CORE_DSP1_IRQ_82_83" offset="0x9AC" width="32" description="">\r
1674     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1675     <bitfield id="DSP1_IRQ_83" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>\r
1676     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1677     <bitfield id="DSP1_IRQ_82" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>\r
1678   </register>\r
1679   <register id="CTRL_CORE_DSP1_IRQ_84_85" acronym="CTRL_CORE_DSP1_IRQ_84_85" offset="0x9B0" width="32" description="">\r
1680     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1681     <bitfield id="DSP1_IRQ_85" width="9" begin="24" end="16" resetval="0x36" description="" range="" rwaccess="RW"/>\r
1682     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1683     <bitfield id="DSP1_IRQ_84" width="9" begin="8" end="0" resetval="0x35" description="" range="" rwaccess="RW"/>\r
1684   </register>\r
1685   <register id="CTRL_CORE_DSP1_IRQ_86_87" acronym="CTRL_CORE_DSP1_IRQ_86_87" offset="0x9B4" width="32" description="">\r
1686     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1687     <bitfield id="DSP1_IRQ_87" width="9" begin="24" end="16" resetval="0x38" description="" range="" rwaccess="RW"/>\r
1688     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1689     <bitfield id="DSP1_IRQ_86" width="9" begin="8" end="0" resetval="0x37" description="" range="" rwaccess="RW"/>\r
1690   </register>\r
1691   <register id="CTRL_CORE_DSP1_IRQ_88_89" acronym="CTRL_CORE_DSP1_IRQ_88_89" offset="0x9B8" width="32" description="">\r
1692     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1693     <bitfield id="DSP1_IRQ_89" width="9" begin="24" end="16" resetval="0x3A" description="" range="" rwaccess="RW"/>\r
1694     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1695     <bitfield id="DSP1_IRQ_88" width="9" begin="8" end="0" resetval="0x39" description="" range="" rwaccess="RW"/>\r
1696   </register>\r
1697   <register id="CTRL_CORE_DSP1_IRQ_90_91" acronym="CTRL_CORE_DSP1_IRQ_90_91" offset="0x9BC" width="32" description="">\r
1698     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1699     <bitfield id="DSP1_IRQ_91" width="9" begin="24" end="16" resetval="0x3C" description="" range="" rwaccess="RW"/>\r
1700     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1701     <bitfield id="DSP1_IRQ_90" width="9" begin="8" end="0" resetval="0x3B" description="" range="" rwaccess="RW"/>\r
1702   </register>\r
1703   <register id="CTRL_CORE_DSP1_IRQ_92_93" acronym="CTRL_CORE_DSP1_IRQ_92_93" offset="0x9C0" width="32" description="">\r
1704     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1705     <bitfield id="DSP1_IRQ_93" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>\r
1706     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1707     <bitfield id="DSP1_IRQ_92" width="9" begin="8" end="0" resetval="0x3D" description="" range="" rwaccess="RW"/>\r
1708   </register>\r
1709   <register id="CTRL_CORE_DSP1_IRQ_94_95" acronym="CTRL_CORE_DSP1_IRQ_94_95" offset="0x9C4" width="32" description="">\r
1710     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1711     <bitfield id="DSP1_IRQ_95" width="9" begin="24" end="16" resetval="0x40" description="" range="" rwaccess="RW"/>\r
1712     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1713     <bitfield id="DSP1_IRQ_94" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>\r
1714   </register>\r
1715   <register id="CTRL_CORE_DSP2_IRQ_32_33" acronym="CTRL_CORE_DSP2_IRQ_32_33" offset="0x9C8" width="32" description="">\r
1716     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1717     <bitfield id="DSP2_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>\r
1718     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1719     <bitfield id="DSP2_IRQ_32" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>\r
1720   </register>\r
1721   <register id="CTRL_CORE_DSP2_IRQ_34_35" acronym="CTRL_CORE_DSP2_IRQ_34_35" offset="0x9CC" width="32" description="">\r
1722     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1723     <bitfield id="DSP2_IRQ_35" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>\r
1724     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1725     <bitfield id="DSP2_IRQ_34" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>\r
1726   </register>\r
1727   <register id="CTRL_CORE_DSP2_IRQ_36_37" acronym="CTRL_CORE_DSP2_IRQ_36_37" offset="0x9D0" width="32" description="">\r
1728     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1729     <bitfield id="DSP2_IRQ_37" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>\r
1730     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1731     <bitfield id="DSP2_IRQ_36" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>\r
1732   </register>\r
1733   <register id="CTRL_CORE_DSP2_IRQ_38_39" acronym="CTRL_CORE_DSP2_IRQ_38_39" offset="0x9D4" width="32" description="">\r
1734     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1735     <bitfield id="DSP2_IRQ_39" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>\r
1736     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1737     <bitfield id="DSP2_IRQ_38" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>\r
1738   </register>\r
1739   <register id="CTRL_CORE_DSP2_IRQ_40_41" acronym="CTRL_CORE_DSP2_IRQ_40_41" offset="0x9D8" width="32" description="">\r
1740     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1741     <bitfield id="DSP2_IRQ_41" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>\r
1742     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1743     <bitfield id="DSP2_IRQ_40" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>\r
1744   </register>\r
1745   <register id="CTRL_CORE_DSP2_IRQ_42_43" acronym="CTRL_CORE_DSP2_IRQ_42_43" offset="0x9DC" width="32" description="">\r
1746     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1747     <bitfield id="DSP2_IRQ_43" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>\r
1748     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1749     <bitfield id="DSP2_IRQ_42" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>\r
1750   </register>\r
1751   <register id="CTRL_CORE_DSP2_IRQ_44_45" acronym="CTRL_CORE_DSP2_IRQ_44_45" offset="0x9E0" width="32" description="">\r
1752     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1753     <bitfield id="DSP2_IRQ_45" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>\r
1754     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1755     <bitfield id="DSP2_IRQ_44" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>\r
1756   </register>\r
1757   <register id="CTRL_CORE_DSP2_IRQ_46_47" acronym="CTRL_CORE_DSP2_IRQ_46_47" offset="0x9E4" width="32" description="">\r
1758     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1759     <bitfield id="DSP2_IRQ_47" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>\r
1760     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1761     <bitfield id="DSP2_IRQ_46" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>\r
1762   </register>\r
1763   <register id="CTRL_CORE_DSP2_IRQ_48_49" acronym="CTRL_CORE_DSP2_IRQ_48_49" offset="0x9E8" width="32" description="">\r
1764     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1765     <bitfield id="DSP2_IRQ_49" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>\r
1766     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1767     <bitfield id="DSP2_IRQ_48" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>\r
1768   </register>\r
1769   <register id="CTRL_CORE_DSP2_IRQ_50_51" acronym="CTRL_CORE_DSP2_IRQ_50_51" offset="0x9EC" width="32" description="">\r
1770     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1771     <bitfield id="DSP2_IRQ_51" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>\r
1772     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1773     <bitfield id="DSP2_IRQ_50" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>\r
1774   </register>\r
1775   <register id="CTRL_CORE_DSP2_IRQ_52_53" acronym="CTRL_CORE_DSP2_IRQ_52_53" offset="0x9F0" width="32" description="">\r
1776     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1777     <bitfield id="DSP2_IRQ_53" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>\r
1778     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1779     <bitfield id="DSP2_IRQ_52" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>\r
1780   </register>\r
1781   <register id="CTRL_CORE_DSP2_IRQ_54_55" acronym="CTRL_CORE_DSP2_IRQ_54_55" offset="0x9F4" width="32" description="">\r
1782     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1783     <bitfield id="DSP2_IRQ_55" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>\r
1784     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1785     <bitfield id="DSP2_IRQ_54" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>\r
1786   </register>\r
1787   <register id="CTRL_CORE_DSP2_IRQ_56_57" acronym="CTRL_CORE_DSP2_IRQ_56_57" offset="0x9F8" width="32" description="">\r
1788     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1789     <bitfield id="DSP2_IRQ_57" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>\r
1790     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1791     <bitfield id="DSP2_IRQ_56" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>\r
1792   </register>\r
1793   <register id="CTRL_CORE_DSP2_IRQ_58_59" acronym="CTRL_CORE_DSP2_IRQ_58_59" offset="0x9FC" width="32" description="">\r
1794     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1795     <bitfield id="DSP2_IRQ_59" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>\r
1796     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1797     <bitfield id="DSP2_IRQ_58" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>\r
1798   </register>\r
1799   <register id="CTRL_CORE_DSP2_IRQ_60_61" acronym="CTRL_CORE_DSP2_IRQ_60_61" offset="0xA00" width="32" description="">\r
1800     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1801     <bitfield id="DSP2_IRQ_61" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>\r
1802     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1803     <bitfield id="DSP2_IRQ_60" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>\r
1804   </register>\r
1805   <register id="CTRL_CORE_DSP2_IRQ_62_63" acronym="CTRL_CORE_DSP2_IRQ_62_63" offset="0xA04" width="32" description="">\r
1806     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1807     <bitfield id="DSP2_IRQ_63" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>\r
1808     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1809     <bitfield id="DSP2_IRQ_62" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>\r
1810   </register>\r
1811   <register id="CTRL_CORE_DSP2_IRQ_64_65" acronym="CTRL_CORE_DSP2_IRQ_64_65" offset="0xA08" width="32" description="">\r
1812     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1813     <bitfield id="DSP2_IRQ_65" width="9" begin="24" end="16" resetval="0x22" description="" range="" rwaccess="RW"/>\r
1814     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1815     <bitfield id="DSP2_IRQ_64" width="9" begin="8" end="0" resetval="0x21" description="" range="" rwaccess="RW"/>\r
1816   </register>\r
1817   <register id="CTRL_CORE_DSP2_IRQ_66_67" acronym="CTRL_CORE_DSP2_IRQ_66_67" offset="0xA0C" width="32" description="">\r
1818     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1819     <bitfield id="DSP2_IRQ_67" width="9" begin="24" end="16" resetval="0x24" description="" range="" rwaccess="RW"/>\r
1820     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1821     <bitfield id="DSP2_IRQ_66" width="9" begin="8" end="0" resetval="0x23" description="" range="" rwaccess="RW"/>\r
1822   </register>\r
1823   <register id="CTRL_CORE_DSP2_IRQ_68_69" acronym="CTRL_CORE_DSP2_IRQ_68_69" offset="0xA10" width="32" description="">\r
1824     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1825     <bitfield id="DSP2_IRQ_69" width="9" begin="24" end="16" resetval="0x26" description="" range="" rwaccess="RW"/>\r
1826     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1827     <bitfield id="DSP2_IRQ_68" width="9" begin="8" end="0" resetval="0x25" description="" range="" rwaccess="RW"/>\r
1828   </register>\r
1829   <register id="CTRL_CORE_DSP2_IRQ_70_71" acronym="CTRL_CORE_DSP2_IRQ_70_71" offset="0xA14" width="32" description="">\r
1830     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1831     <bitfield id="DSP2_IRQ_71" width="9" begin="24" end="16" resetval="0x28" description="" range="" rwaccess="RW"/>\r
1832     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1833     <bitfield id="DSP2_IRQ_70" width="9" begin="8" end="0" resetval="0x27" description="" range="" rwaccess="RW"/>\r
1834   </register>\r
1835   <register id="CTRL_CORE_DSP2_IRQ_72_73" acronym="CTRL_CORE_DSP2_IRQ_72_73" offset="0xA18" width="32" description="">\r
1836     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1837     <bitfield id="DSP2_IRQ_73" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>\r
1838     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1839     <bitfield id="DSP2_IRQ_72" width="9" begin="8" end="0" resetval="0x29" description="" range="" rwaccess="RW"/>\r
1840   </register>\r
1841   <register id="CTRL_CORE_DSP2_IRQ_74_75" acronym="CTRL_CORE_DSP2_IRQ_74_75" offset="0xA1C" width="32" description="">\r
1842     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1843     <bitfield id="DSP2_IRQ_75" width="9" begin="24" end="16" resetval="0x2C" description="" range="" rwaccess="RW"/>\r
1844     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1845     <bitfield id="DSP2_IRQ_74" width="9" begin="8" end="0" resetval="0x2B" description="" range="" rwaccess="RW"/>\r
1846   </register>\r
1847   <register id="CTRL_CORE_DSP2_IRQ_76_77" acronym="CTRL_CORE_DSP2_IRQ_76_77" offset="0xA20" width="32" description="">\r
1848     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1849     <bitfield id="DSP2_IRQ_77" width="9" begin="24" end="16" resetval="0x2E" description="" range="" rwaccess="RW"/>\r
1850     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1851     <bitfield id="DSP2_IRQ_76" width="9" begin="8" end="0" resetval="0x2D" description="" range="" rwaccess="RW"/>\r
1852   </register>\r
1853   <register id="CTRL_CORE_DSP2_IRQ_78_79" acronym="CTRL_CORE_DSP2_IRQ_78_79" offset="0xA24" width="32" description="">\r
1854     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1855     <bitfield id="DSP2_IRQ_79" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>\r
1856     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1857     <bitfield id="DSP2_IRQ_78" width="9" begin="8" end="0" resetval="0x2F" description="" range="" rwaccess="RW"/>\r
1858   </register>\r
1859   <register id="CTRL_CORE_DSP2_IRQ_80_81" acronym="CTRL_CORE_DSP2_IRQ_80_81" offset="0xA28" width="32" description="">\r
1860     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1861     <bitfield id="DSP2_IRQ_81" width="9" begin="24" end="16" resetval="0x32" description="" range="" rwaccess="RW"/>\r
1862     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1863     <bitfield id="DSP2_IRQ_80" width="9" begin="8" end="0" resetval="0x31" description="" range="" rwaccess="RW"/>\r
1864   </register>\r
1865   <register id="CTRL_CORE_DSP2_IRQ_82_83" acronym="CTRL_CORE_DSP2_IRQ_82_83" offset="0xA2C" width="32" description="">\r
1866     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1867     <bitfield id="DSP2_IRQ_83" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>\r
1868     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1869     <bitfield id="DSP2_IRQ_82" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>\r
1870   </register>\r
1871   <register id="CTRL_CORE_DSP2_IRQ_84_85" acronym="CTRL_CORE_DSP2_IRQ_84_85" offset="0xA30" width="32" description="">\r
1872     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1873     <bitfield id="DSP2_IRQ_85" width="9" begin="24" end="16" resetval="0x36" description="" range="" rwaccess="RW"/>\r
1874     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1875     <bitfield id="DSP2_IRQ_84" width="9" begin="8" end="0" resetval="0x35" description="" range="" rwaccess="RW"/>\r
1876   </register>\r
1877   <register id="CTRL_CORE_DSP2_IRQ_86_87" acronym="CTRL_CORE_DSP2_IRQ_86_87" offset="0xA34" width="32" description="">\r
1878     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1879     <bitfield id="DSP2_IRQ_87" width="9" begin="24" end="16" resetval="0x38" description="" range="" rwaccess="RW"/>\r
1880     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1881     <bitfield id="DSP2_IRQ_86" width="9" begin="8" end="0" resetval="0x37" description="" range="" rwaccess="RW"/>\r
1882   </register>\r
1883   <register id="CTRL_CORE_DSP2_IRQ_88_89" acronym="CTRL_CORE_DSP2_IRQ_88_89" offset="0xA38" width="32" description="">\r
1884     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1885     <bitfield id="DSP2_IRQ_89" width="9" begin="24" end="16" resetval="0x3A" description="" range="" rwaccess="RW"/>\r
1886     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1887     <bitfield id="DSP2_IRQ_88" width="9" begin="8" end="0" resetval="0x39" description="" range="" rwaccess="RW"/>\r
1888   </register>\r
1889   <register id="CTRL_CORE_DSP2_IRQ_90_91" acronym="CTRL_CORE_DSP2_IRQ_90_91" offset="0xA3C" width="32" description="">\r
1890     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1891     <bitfield id="DSP2_IRQ_91" width="9" begin="24" end="16" resetval="0x3C" description="" range="" rwaccess="RW"/>\r
1892     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1893     <bitfield id="DSP2_IRQ_90" width="9" begin="8" end="0" resetval="0x3B" description="" range="" rwaccess="RW"/>\r
1894   </register>\r
1895   <register id="CTRL_CORE_DSP2_IRQ_92_93" acronym="CTRL_CORE_DSP2_IRQ_92_93" offset="0xA40" width="32" description="">\r
1896     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1897     <bitfield id="DSP2_IRQ_93" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>\r
1898     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1899     <bitfield id="DSP2_IRQ_92" width="9" begin="8" end="0" resetval="0x3D" description="" range="" rwaccess="RW"/>\r
1900   </register>\r
1901   <register id="CTRL_CORE_DSP2_IRQ_94_95" acronym="CTRL_CORE_DSP2_IRQ_94_95" offset="0xA44" width="32" description="">\r
1902     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1903     <bitfield id="DSP2_IRQ_95" width="9" begin="24" end="16" resetval="0x40" description="" range="" rwaccess="RW"/>\r
1904     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1905     <bitfield id="DSP2_IRQ_94" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>\r
1906   </register>\r
1907   <register id="CTRL_CORE_MPU_IRQ_4_7" acronym="CTRL_CORE_MPU_IRQ_4_7" offset="0xA48" width="32" description="">\r
1908     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1909     <bitfield id="MPU_IRQ_7" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>\r
1910     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1911     <bitfield id="MPU_IRQ_4" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>\r
1912   </register>\r
1913   <register id="CTRL_CORE_MPU_IRQ_8_9" acronym="CTRL_CORE_MPU_IRQ_8_9" offset="0xA4C" width="32" description="">\r
1914     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1915     <bitfield id="MPU_IRQ_9" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>\r
1916     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1917     <bitfield id="MPU_IRQ_8" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>\r
1918   </register>\r
1919   <register id="CTRL_CORE_MPU_IRQ_10_11" acronym="CTRL_CORE_MPU_IRQ_10_11" offset="0xA50" width="32" description="">\r
1920     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1921     <bitfield id="MPU_IRQ_11" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>\r
1922     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1923     <bitfield id="MPU_IRQ_10" width="9" begin="8" end="0" resetval="0x5" description="NOTE: This bit field is not functional" range="" rwaccess="RW"/>\r
1924   </register>\r
1925   <register id="CTRL_CORE_MPU_IRQ_12_13" acronym="CTRL_CORE_MPU_IRQ_12_13" offset="0xA54" width="32" description="">\r
1926     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1927     <bitfield id="MPU_IRQ_13" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>\r
1928     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1929     <bitfield id="MPU_IRQ_12" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>\r
1930   </register>\r
1931   <register id="CTRL_CORE_MPU_IRQ_14_15" acronym="CTRL_CORE_MPU_IRQ_14_15" offset="0xA58" width="32" description="">\r
1932     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1933     <bitfield id="MPU_IRQ_15" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>\r
1934     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1935     <bitfield id="MPU_IRQ_14" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>\r
1936   </register>\r
1937   <register id="CTRL_CORE_MPU_IRQ_16_17" acronym="CTRL_CORE_MPU_IRQ_16_17" offset="0xA5C" width="32" description="">\r
1938     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1939     <bitfield id="MPU_IRQ_17" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>\r
1940     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1941     <bitfield id="MPU_IRQ_16" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>\r
1942   </register>\r
1943   <register id="CTRL_CORE_MPU_IRQ_18_19" acronym="CTRL_CORE_MPU_IRQ_18_19" offset="0xA60" width="32" description="">\r
1944     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1945     <bitfield id="MPU_IRQ_19" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>\r
1946     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1947     <bitfield id="MPU_IRQ_18" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>\r
1948   </register>\r
1949   <register id="CTRL_CORE_MPU_IRQ_20_21" acronym="CTRL_CORE_MPU_IRQ_20_21" offset="0xA64" width="32" description="">\r
1950     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1951     <bitfield id="MPU_IRQ_21" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>\r
1952     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1953     <bitfield id="MPU_IRQ_20" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>\r
1954   </register>\r
1955   <register id="CTRL_CORE_MPU_IRQ_22_23" acronym="CTRL_CORE_MPU_IRQ_22_23" offset="0xA68" width="32" description="">\r
1956     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1957     <bitfield id="MPU_IRQ_23" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>\r
1958     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1959     <bitfield id="MPU_IRQ_22" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>\r
1960   </register>\r
1961   <register id="CTRL_CORE_MPU_IRQ_24_25" acronym="CTRL_CORE_MPU_IRQ_24_25" offset="0xA6C" width="32" description="">\r
1962     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1963     <bitfield id="MPU_IRQ_25" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>\r
1964     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1965     <bitfield id="MPU_IRQ_24" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>\r
1966   </register>\r
1967   <register id="CTRL_CORE_MPU_IRQ_26_27" acronym="CTRL_CORE_MPU_IRQ_26_27" offset="0xA70" width="32" description="">\r
1968     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1969     <bitfield id="MPU_IRQ_27" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>\r
1970     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1971     <bitfield id="MPU_IRQ_26" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>\r
1972   </register>\r
1973   <register id="CTRL_CORE_MPU_IRQ_28_29" acronym="CTRL_CORE_MPU_IRQ_28_29" offset="0xA74" width="32" description="">\r
1974     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1975     <bitfield id="MPU_IRQ_29" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>\r
1976     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1977     <bitfield id="MPU_IRQ_28" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>\r
1978   </register>\r
1979   <register id="CTRL_CORE_MPU_IRQ_30_31" acronym="CTRL_CORE_MPU_IRQ_30_31" offset="0xA78" width="32" description="">\r
1980     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1981     <bitfield id="MPU_IRQ_31" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>\r
1982     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1983     <bitfield id="MPU_IRQ_30" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>\r
1984   </register>\r
1985   <register id="CTRL_CORE_MPU_IRQ_32_33" acronym="CTRL_CORE_MPU_IRQ_32_33" offset="0xA7C" width="32" description="">\r
1986     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1987     <bitfield id="MPU_IRQ_33" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>\r
1988     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1989     <bitfield id="MPU_IRQ_32" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>\r
1990   </register>\r
1991   <register id="CTRL_CORE_MPU_IRQ_34_35" acronym="CTRL_CORE_MPU_IRQ_34_35" offset="0xA80" width="32" description="">\r
1992     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1993     <bitfield id="MPU_IRQ_35" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>\r
1994     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
1995     <bitfield id="MPU_IRQ_34" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>\r
1996   </register>\r
1997   <register id="CTRL_CORE_MPU_IRQ_36_37" acronym="CTRL_CORE_MPU_IRQ_36_37" offset="0xA84" width="32" description="">\r
1998     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
1999     <bitfield id="MPU_IRQ_37" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>\r
2000     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2001     <bitfield id="MPU_IRQ_36" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>\r
2002   </register>\r
2003   <register id="CTRL_CORE_MPU_IRQ_38_39" acronym="CTRL_CORE_MPU_IRQ_38_39" offset="0xA88" width="32" description="">\r
2004     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2005     <bitfield id="MPU_IRQ_39" width="9" begin="24" end="16" resetval="0x22" description="" range="" rwaccess="RW"/>\r
2006     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2007     <bitfield id="MPU_IRQ_38" width="9" begin="8" end="0" resetval="0x21" description="" range="" rwaccess="RW"/>\r
2008   </register>\r
2009   <register id="CTRL_CORE_MPU_IRQ_40_41" acronym="CTRL_CORE_MPU_IRQ_40_41" offset="0xA8C" width="32" description="">\r
2010     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2011     <bitfield id="MPU_IRQ_41" width="9" begin="24" end="16" resetval="0x24" description="" range="" rwaccess="RW"/>\r
2012     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2013     <bitfield id="MPU_IRQ_40" width="9" begin="8" end="0" resetval="0x23" description="" range="" rwaccess="RW"/>\r
2014   </register>\r
2015   <register id="CTRL_CORE_MPU_IRQ_42_43" acronym="CTRL_CORE_MPU_IRQ_42_43" offset="0xA90" width="32" description="">\r
2016     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2017     <bitfield id="MPU_IRQ_43" width="9" begin="24" end="16" resetval="0x26" description="" range="" rwaccess="RW"/>\r
2018     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2019     <bitfield id="MPU_IRQ_42" width="9" begin="8" end="0" resetval="0x25" description="" range="" rwaccess="RW"/>\r
2020   </register>\r
2021   <register id="CTRL_CORE_MPU_IRQ_44_45" acronym="CTRL_CORE_MPU_IRQ_44_45" offset="0xA94" width="32" description="">\r
2022     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2023     <bitfield id="MPU_IRQ_45" width="9" begin="24" end="16" resetval="0x28" description="" range="" rwaccess="RW"/>\r
2024     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2025     <bitfield id="MPU_IRQ_44" width="9" begin="8" end="0" resetval="0x27" description="" range="" rwaccess="RW"/>\r
2026   </register>\r
2027   <register id="CTRL_CORE_MPU_IRQ_46_47" acronym="CTRL_CORE_MPU_IRQ_46_47" offset="0xA98" width="32" description="">\r
2028     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2029     <bitfield id="MPU_IRQ_47" width="9" begin="24" end="16" resetval="0x2A" description="" range="" rwaccess="RW"/>\r
2030     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2031     <bitfield id="MPU_IRQ_46" width="9" begin="8" end="0" resetval="0x29" description="" range="" rwaccess="RW"/>\r
2032   </register>\r
2033   <register id="CTRL_CORE_MPU_IRQ_48_49" acronym="CTRL_CORE_MPU_IRQ_48_49" offset="0xA9C" width="32" description="">\r
2034     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2035     <bitfield id="MPU_IRQ_49" width="9" begin="24" end="16" resetval="0x2C" description="" range="" rwaccess="RW"/>\r
2036     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2037     <bitfield id="MPU_IRQ_48" width="9" begin="8" end="0" resetval="0x2B" description="" range="" rwaccess="RW"/>\r
2038   </register>\r
2039   <register id="CTRL_CORE_MPU_IRQ_50_51" acronym="CTRL_CORE_MPU_IRQ_50_51" offset="0xAA0" width="32" description="">\r
2040     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2041     <bitfield id="MPU_IRQ_51" width="9" begin="24" end="16" resetval="0x2E" description="" range="" rwaccess="RW"/>\r
2042     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2043     <bitfield id="MPU_IRQ_50" width="9" begin="8" end="0" resetval="0x2D" description="" range="" rwaccess="RW"/>\r
2044   </register>\r
2045   <register id="CTRL_CORE_MPU_IRQ_52_53" acronym="CTRL_CORE_MPU_IRQ_52_53" offset="0xAA4" width="32" description="">\r
2046     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2047     <bitfield id="MPU_IRQ_53" width="9" begin="24" end="16" resetval="0x30" description="" range="" rwaccess="RW"/>\r
2048     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2049     <bitfield id="MPU_IRQ_52" width="9" begin="8" end="0" resetval="0x2F" description="" range="" rwaccess="RW"/>\r
2050   </register>\r
2051   <register id="CTRL_CORE_MPU_IRQ_54_55" acronym="CTRL_CORE_MPU_IRQ_54_55" offset="0xAA8" width="32" description="">\r
2052     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2053     <bitfield id="MPU_IRQ_55" width="9" begin="24" end="16" resetval="0x32" description="" range="" rwaccess="RW"/>\r
2054     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2055     <bitfield id="MPU_IRQ_54" width="9" begin="8" end="0" resetval="0x31" description="" range="" rwaccess="RW"/>\r
2056   </register>\r
2057   <register id="CTRL_CORE_MPU_IRQ_56_57" acronym="CTRL_CORE_MPU_IRQ_56_57" offset="0xAAC" width="32" description="">\r
2058     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2059     <bitfield id="MPU_IRQ_57" width="9" begin="24" end="16" resetval="0x34" description="" range="" rwaccess="RW"/>\r
2060     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2061     <bitfield id="MPU_IRQ_56" width="9" begin="8" end="0" resetval="0x33" description="" range="" rwaccess="RW"/>\r
2062   </register>\r
2063   <register id="CTRL_CORE_MPU_IRQ_58_59" acronym="CTRL_CORE_MPU_IRQ_58_59" offset="0xAB0" width="32" description="">\r
2064     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2065     <bitfield id="MPU_IRQ_59" width="9" begin="24" end="16" resetval="0x36" description="" range="" rwaccess="RW"/>\r
2066     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2067     <bitfield id="MPU_IRQ_58" width="9" begin="8" end="0" resetval="0x35" description="" range="" rwaccess="RW"/>\r
2068   </register>\r
2069   <register id="CTRL_CORE_MPU_IRQ_60_61" acronym="CTRL_CORE_MPU_IRQ_60_61" offset="0xAB4" width="32" description="">\r
2070     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2071     <bitfield id="MPU_IRQ_61" width="9" begin="24" end="16" resetval="0x38" description="" range="" rwaccess="RW"/>\r
2072     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2073     <bitfield id="MPU_IRQ_60" width="9" begin="8" end="0" resetval="0x37" description="" range="" rwaccess="RW"/>\r
2074   </register>\r
2075   <register id="CTRL_CORE_MPU_IRQ_62_63" acronym="CTRL_CORE_MPU_IRQ_62_63" offset="0xAB8" width="32" description="">\r
2076     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2077     <bitfield id="MPU_IRQ_63" width="9" begin="24" end="16" resetval="0x3A" description="" range="" rwaccess="RW"/>\r
2078     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2079     <bitfield id="MPU_IRQ_62" width="9" begin="8" end="0" resetval="0x39" description="" range="" rwaccess="RW"/>\r
2080   </register>\r
2081   <register id="CTRL_CORE_MPU_IRQ_64_65" acronym="CTRL_CORE_MPU_IRQ_64_65" offset="0xABC" width="32" description="">\r
2082     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2083     <bitfield id="MPU_IRQ_65" width="9" begin="24" end="16" resetval="0x3C" description="" range="" rwaccess="RW"/>\r
2084     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2085     <bitfield id="MPU_IRQ_64" width="9" begin="8" end="0" resetval="0x3B" description="" range="" rwaccess="RW"/>\r
2086   </register>\r
2087   <register id="CTRL_CORE_MPU_IRQ_66_67" acronym="CTRL_CORE_MPU_IRQ_66_67" offset="0xAC0" width="32" description="">\r
2088     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2089     <bitfield id="MPU_IRQ_67" width="9" begin="24" end="16" resetval="0x3E" description="" range="" rwaccess="RW"/>\r
2090     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2091     <bitfield id="MPU_IRQ_66" width="9" begin="8" end="0" resetval="0x3D" description="" range="" rwaccess="RW"/>\r
2092   </register>\r
2093   <register id="CTRL_CORE_MPU_IRQ_68_69" acronym="CTRL_CORE_MPU_IRQ_68_69" offset="0xAC4" width="32" description="">\r
2094     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2095     <bitfield id="MPU_IRQ_69" width="9" begin="24" end="16" resetval="0x40" description="" range="" rwaccess="RW"/>\r
2096     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2097     <bitfield id="MPU_IRQ_68" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>\r
2098   </register>\r
2099   <register id="CTRL_CORE_MPU_IRQ_70_71" acronym="CTRL_CORE_MPU_IRQ_70_71" offset="0xAC8" width="32" description="">\r
2100     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2101     <bitfield id="MPU_IRQ_71" width="9" begin="24" end="16" resetval="0x42" description="" range="" rwaccess="RW"/>\r
2102     <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
2103     <bitfield id="MPU_IRQ_70" width="9" begin="8" end="0" resetval="0x41" description="" range="" rwaccess="RW"/>\r
2104   </register>\r
2105   <register id="CTRL_CORE_MPU_IRQ_72_73" acronym="CTRL_CORE_MPU_IRQ_72_73" offset="0xACC" width="32" description="">\r
2106     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
2107     <bitfield id="MPU_IRQ_73" width="9" begin="24" end="