XML: PCT: Migrate DRA72x to version 1.0.9
authorNikhil Devshatwar <nikhil.nd@ti.com>
Thu, 22 Dec 2016 09:27:11 +0000 (14:57 +0530)
committerNikhil Devshatwar <nikhil.nd@ti.com>
Thu, 22 Dec 2016 09:27:11 +0000 (14:57 +0530)
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
XMLFiles/DRA72x/CTRL_MODULE_CORE.xml
XMLFiles/DRA72x/model_DRA72x_SR1.0_v1.0.9.xml [moved from XMLFiles/DRA72x/model_DRA72x_SR1.0_v1.0.7.xml with 95% similarity]
XMLFiles/DRA72x/model_DRA72x_SR2.0_v1.0.9.xml [moved from XMLFiles/DRA72x/model_DRA72x_SR2.0_v1.0.7.xml with 96% similarity]
iodelay-autogen.py

index 2bf88450bc09129379c694db4feab59dff52f6ff..63b326681c216d50581d037ead892c91f15979fe 100644 (file)
     <bitfield id="TC1_EDMA_FW_ERROR" width="1" begin="26" end="26" resetval="0x0" description="EDMA TC1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
     <bitfield id="RESERVED" width="3" begin="25" end="23" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="QSPI_FW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="QSPI firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
-    <bitfield id="RESERVED" width="4" begin="21" end="18" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_FW_ERROR" width="1" begin="21" end="21" resetval="0x0" description="PRU-ICSS2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
+    <bitfield id="PRUSS1_FW_ERROR" width="1" begin="20" end="20" resetval="0x0" description="PRU-ICSS1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
+    <bitfield id="RESERVED" width="2" begin="19" end="18" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="TPCC_EDMA_FW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="EDMA TPCC firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
     <bitfield id="TC0_EDMA_FW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="EDMA TC0 firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="TC1_EDMA_DBGFW_ERROR" width="1" begin="26" end="26" resetval="0x0" description="EDMA TC1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
     <bitfield id="RESERVED" width="3" begin="25" end="23" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="QSPI_DBGFW_ERROR" width="1" begin="22" end="22" resetval="0x0" description="QSPI debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
-    <bitfield id="RESERVED" width="4" begin="21" end="18" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_DBGFW_ERROR" width="1" begin="21" end="21" resetval="0x0" description="PRU-ICSS2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
+    <bitfield id="PRUSS1_DBGFW_ERROR" width="1" begin="20" end="20" resetval="0x0" description="PRU-ICSS1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
+    <bitfield id="RESERVED" width="2" begin="19" end="18" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="TPCC_EDMA_DBGFW_ERROR" width="1" begin="17" end="17" resetval="0x0" description="EDMA TPCC debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
     <bitfield id="TC0_EDMA_DBGFW_ERROR" width="1" begin="16" end="16" resetval="0x0" description="EDMA TC0 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" range="" rwaccess="RW W1toClr"/>\r
     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_2" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_2" offset="0x424" width="32" description="Register for priority settings for EMIF arbitration">\r
     <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x4" description="" range="" rwaccess="R"/>\r
     <bitfield id="IVA_ICONT1_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="IVA ICONT1 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
-    <bitfield id="RESERVED" width="24" begin="23" end="0" resetval="0x44444" description="" range="" rwaccess="R"/>\r
+    <bitfield id="RESERVED" width="21" begin="23" end="3" resetval="0x8888" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_PRU0_EMIF_PRIORITY" width="3" begin="2" end="0" resetval="0x4" description="PRU-ICSS1 PRU0 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
   </register>\r
   <register id="CTRL_CORE_EMIF_INITIATOR_PRIORITY_3" acronym="CTRL_CORE_EMIF_INITIATOR_PRIORITY_3" offset="0x428" width="32" description="Register for priority settings for EMIF arbitration">\r
-    <bitfield id="RESERVED" width="13" begin="31" end="19" resetval="0x888" description="" range="" rwaccess="R"/>\r
+    <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_PRU1_EMIF_PRIORITY" width="3" begin="30" end="28" resetval="0x4" description="PRU-ICSS1 PRU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW" />\r
+    <bitfield id="RESERVED" width="1" begin="27" end="27" resetval="0x0" description="" range="" rwaccess="R" />\r
+    <bitfield id="PRUSS2_PRU0_EMIF_PRIORITY" width="3" begin="26" end="24" resetval="0x4" description="PRU-ICSS2 PRU0 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW" />\r
+    <bitfield id="RESERVED" width="1" begin="23" end="23" resetval="0x0" description="" range="" rwaccess="R" />\r
+    <bitfield id="PRUSS2_PRU1_EMIF_PRIORITY" width="3" begin="22" end="20" resetval="0x4" description="PRU-ICSS2 PRU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW" />\r
+    <bitfield id="RESERVED" width="1" begin="19" end="19" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="IPU1_EMIF_PRIORITY" width="3" begin="18" end="16" resetval="0x4" description="IPU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="1" begin="15" end="15" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="IPU2_EMIF_PRIORITY" width="3" begin="14" end="12" resetval="0x4" description="IPU2 priority setting 0x0 = highest priority 0x7 = lowest priority" range="" rwaccess="RW"/>\r
     <bitfield id="IPU1_L3_PRESSURE" width="2" begin="13" end="12" resetval="0x0" description="IPU1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="1" begin="11" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="IPU2_L3_PRESSURE" width="2" begin="10" end="9" resetval="0x0" description="IPU2 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
-    <bitfield id="RESERVED" width="9" begin="8" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="RESERVED" width="1" begin="8" end="8" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_PRU0_L3_PRESSURE" width="2" begin="7" end="6" resetval="0x0" description="PRU-ICSS1 PRU0 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="1" begin="5" end="5" resetval="0x0" description="" range="" rwaccess="R" />\r
+    <bitfield id="PRUSS1_PRU1_L3_PRESSURE" width="2" begin="4" end="3" resetval="0x0" description="PRU-ICSS1 PRU1 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="1" begin="2" end="2" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_PRU0_L3_PRESSURE" width="2" begin="1" end="0" resetval="0x0" description="PRU-ICSS2 PRU0 pressure setting 0x0 = lowest 0x3 = highest" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_3" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_3" offset="0x444" width="32" description="Register for pressure settings for L3 arbitration">\r
+    <bitfield id="RESERVED" width="4" begin="31" end="28" resetval="0x0" description="" range="" rwaccess="R" />\r
+    <bitfield id="PRUSS2_PRU1_L3_PRESSURE" width="2" begin="27" end="26" resetval="0x0" description="PRU-ICSS2 PRU1 pressure setting0x0 = lowest enum=LOWEST . 0x3 = highest enum=HIGHEST ." range="" rwaccess="RW" />\r
+    <bitfield id="RESERVED" width="26" begin="25" end="0" resetval="0x0" description="" range="" rwaccess="R"/>\r
   </register>\r
   <register id="CTRL_CORE_L3_INITIATOR_PRESSURE_4" acronym="CTRL_CORE_L3_INITIATOR_PRESSURE_4" offset="0x448" width="32" description="Register for pressure settings for L3 arbitration">\r
     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="Reserved" range="" rwaccess="R"/>\r
     <bitfield id="STD_FUSE_MAC_ID_SW_3" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 1. Bits [23:16] contain the first octet of the MAC address. Bits [15:8] contain the second octet of the MAC address. Bits [7:0] contain the third octet of the MAC address." range="" rwaccess="R"/>\r
   </register>\r
   <register id="CTRL_CORE_SMA_SW_1" acronym="CTRL_CORE_SMA_SW_1" offset="0x534" width="32" description="OCP Spare Register">\r
-    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="RGMII2_ID_MODE_N" width="1" begin="26" end="26" resetval="0x0" description="Ethernet RGMII port 2 internal delay on transmit(SR2.0) 0x0: Internal delay enabled 0x1: Internal delay disabled" range="" rwaccess="RW"/>\r
+    <bitfield id="RGMII1_ID_MODE_N" width="1" begin="25" end="25" resetval="0x0" description="Ethernet RGMII port 1 internal delay on transmit(SR2.0) 0x0: Internal delay enabled 0x1: Internal delay disabled" range="" rwaccess="RW"/>\r
     <bitfield id="DSS_CH2_ON_OFF" width="1" begin="24" end="24" resetval="0x0" description="DSS Channel 2 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH2_RF" range="" rwaccess="RW"/>\r
     <bitfield id="DSS_CH1_ON_OFF" width="1" begin="23" end="23" resetval="0x0" description="DSS Channel 1 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH1_RF" range="" rwaccess="RW"/>\r
     <bitfield id="DSS_CH0_ON_OFF" width="1" begin="22" end="22" resetval="0x0" description="DSS Channel 0 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH0_RF" range="" rwaccess="RW"/>\r
     <bitfield id="DSS_CH1_RF" width="1" begin="17" end="17" resetval="0x0" description="DSS Channel 1 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1)" range="" rwaccess="RW"/>\r
     <bitfield id="DSS_CH0_RF" width="1" begin="16" end="16" resetval="0x0" description="DSS Channel 0 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1)" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="5" begin="15" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
-    <bitfield id="VIP3_CLK_INV_PORT_1A" width="1" begin="10" end="10" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP5A. For more information, see, .0x0: Clock inversion is disabled0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
-    <bitfield id="VIP3_CLK_INV_PORT_2A" width="1" begin="9" end="9" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP6A. For more information, see, .0x0: Clock inversion is disabled0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
+    <bitfield id="VIP3_CLK_INV_PORT_1A" width="1" begin="10" end="10" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP5A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
+    <bitfield id="VIP3_CLK_INV_PORT_2A" width="1" begin="9" end="9" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP6A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
     <bitfield id="VPE_CLK_DIV_BY_2_EN" width="1" begin="8" end="8" resetval="0x0" description="Selects alternative clock source for VPE. 0x0: Default clock source from DPLL_CORE is selected 0x1: Alternative clock source from DPLL_VIDEO1 is selected" range="" rwaccess="RW"/>\r
-    <bitfield id="VIP2_CLK_INV_PORT_2B" width="1" begin="7" end="7" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP4B. For more information, see, .0x0: Clock inversion is disabled0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
-    <bitfield id="VIP2_CLK_INV_PORT_1B" width="1" begin="6" end="6" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP3B. For more information, see, .0x0: Clock inversion is disabled0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
-    <bitfield id="VIP2_CLK_INV_PORT_2A" width="1" begin="5" end="5" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP4A. For more information, see, .0x0: Clock inversion is disabled0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
-    <bitfield id="VIP2_CLK_INV_PORT_1A" width="1" begin="4" end="4" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP3A. For more information, see, .0x0: Clock inversion is disabled0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
+    <bitfield id="VIP2_CLK_INV_PORT_2B" width="1" begin="7" end="7" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP4B. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
+    <bitfield id="VIP2_CLK_INV_PORT_1B" width="1" begin="6" end="6" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP3B. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
+    <bitfield id="VIP2_CLK_INV_PORT_2A" width="1" begin="5" end="5" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP4A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
+    <bitfield id="VIP2_CLK_INV_PORT_1A" width="1" begin="4" end="4" resetval="0x0" description="Clock inversion enable for VIP1 clock signals when muxed on pads from GROUP3A. For more information, see, Additional Multiplexing of the VIP1 Signals. 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
     <bitfield id="VIP1_CLK_INV_PORT_2B" width="1" begin="3" end="3" resetval="0x0" description="VIP1 Slice 1 Clock inversion for Port B enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
     <bitfield id="VIP1_CLK_INV_PORT_1B" width="1" begin="2" end="2" resetval="0x0" description="VIP1 Slice 0 Clock inversion for Port B enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
     <bitfield id="VIP1_CLK_INV_PORT_2A" width="1" begin="1" end="1" resetval="0x0" description="VIP1 Slice 1 Clock inversion for Port A enable 0x0: Clock inversion is disabled 0x1: Clock inversion is enabled" range="" rwaccess="RW"/>\r
   <register id="CTRL_CORE_DSS_PLL_CONTROL" acronym="CTRL_CORE_DSS_PLL_CONTROL" offset="0x538" width="32" description="DSS PLLs Mux control register">\r
     <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>\r
     <bitfield id="SDVENC_CLK_SELECTION" width="2" begin="10" end="9" resetval="0x1" description="SDVENC_CLK mux configuration 0x0 = HDMI_CLK 0x1 = DPLL_VIDEO1_HSDIVIDER_clkout3" range="" rwaccess="RW"/>\r
-    <bitfield id="RESERVED" width="2" begin="8" end="7" resetval="0x1" description="" range="" rwaccess="R"/>\r
+    <bitfield id="DSI1_C_CLK1_SELECTION" width="2" begin="8" end="7" resetval="0x1" description="DSI1_C_CLK1 mux configuration 0x0 = Reserved 0x1 = DPLL_VIDEO1 0x2 = DPLL_HDMI" range="" rwaccess="RW"/>\r
     <bitfield id="DSI1_B_CLK1_SELECTION" width="2" begin="6" end="5" resetval="0x1" description="DSI1_B_CLK1 mux configuration 0x0 = DPLL_VIDEO1 0x1 = Reserved 0x2 = DPLL_HDMI 0x3 = DPLL_ABE" range="" rwaccess="RW"/>\r
     <bitfield id="DSI1_A_CLK1_SELECTION" width="2" begin="4" end="3" resetval="0x1" description="DSI1_A_CLK1 mux configuration 0x0 = DPLL_VIDEO1 0x1 = DPLL_HDMI" range="" rwaccess="RW"/>\r
     <bitfield id="PLL_HDMI_DSS_CONTROL_DISABLE" width="1" begin="2" end="2" resetval="0x1" description="HDMI PLL disable 0x0 = PLL enabled 0x1 = PLL disabled" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="3" begin="19" end="17" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="MMU1_DISABLE" width="1" begin="16" end="16" resetval="0x0" description="MMU1 DISABLE setting" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="2" begin="15" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
-    <bitfield id="TC1_DEFAULT_BURST_SIZE" width="2" begin="13" end="12" resetval="0x3" description="EDMA TC1 DEFAULT BURST SIZE setting" range="" rwaccess="RW"/>\r
+    <bitfield id="TC1_DEFAULT_BURST_SIZE" width="2" begin="13" end="12" resetval="0x3" description="EDMA TC1 Default Burst Size (DBS) setting0x0: 16 byte burst0x1: 32 byte burst0x2: 64 byte burst0x3: 128 byte burst" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="2" begin="11" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
-    <bitfield id="TC0_DEFAULT_BURST_SIZE" width="2" begin="9" end="8" resetval="0x3" description="EDMA TC0 DEFAULT BURST SIZE setting" range="" rwaccess="RW"/>\r
+    <bitfield id="TC0_DEFAULT_BURST_SIZE" width="2" begin="9" end="8" resetval="0x3" description="EDMA TC0 Default Burst Size (DBS) setting0x0: 16 byte burst0x1: 32 byte burst0x2: 64 byte burst0x3: 128 byte burst" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="2" begin="7" end="6" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="GMII2_SEL" width="2" begin="5" end="4" resetval="0x0" description="GMII2 selection setting 0x0: GMII/MII 0x1: RMII 0x2: RGMII 0x3: Reserved" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="2" begin="3" end="2" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="PWMSS2_TBCLKEN" width="1" begin="21" end="21" resetval="0x0" description="PWMSS2 CLOCK ENABLE setting" range="" rwaccess="RW"/>\r
     <bitfield id="PWMSS1_TBCLKEN" width="1" begin="20" end="20" resetval="0x0" description="PWMSS1 CLOCK ENABLE setting" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="6" begin="19" end="14" resetval="0x0" description="" range="" rwaccess="R"/>\r
-    <bitfield id="PCIE_1LANE_2LANE_SELECTION" width="1" begin="13" end="13" resetval="0x0" description="PCIe one or two lane selection setting 0x0 = One PCIe lane is selected 0x1 = Two PCIe lanes are selected" range="" rwaccess="RW"/>\r
+    <bitfield id="PCIE_1LANE_2LANE_SELECTION" width="1" begin="13" end="13" resetval="0x0" description="Reserved" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="2" begin="12" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="QSPI_MEMMAPPED_CS" width="3" begin="10" end="8" resetval="0x0" description="QSPI CS MAPPING setting. 0x0: The QSPI configuration registers are accessed 0x1: An external device connected to CS0 is accessed 0x2: An external device connected to CS1 is accessed 0x3: An external device connected to CS2 is accessed 0x4-0x7: An external device connected to CS3 is accessed" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="2" begin="7" end="6" resetval="0x0" description="" range="" rwaccess="R"/>\r
-    <bitfield id="DCAN2_RAMINIT_START" width="1" begin="5" end="5" resetval="0x0" description="DCAN2 RAM INIT START setting To initialize DCAN2 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. : If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." range="" rwaccess="RW"/>\r
+    <bitfield id="DCAN2_RAMINIT_START" width="1" begin="5" end="5" resetval="0x0" description="DCAN2 RAM INIT START setting To initialize DCAN2 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. Note: If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." range="" rwaccess="RW"/>\r
     <bitfield id="DSS_DESHDCP_DISABLE" width="1" begin="4" end="4" resetval="0x0" description="DSS DESHDCP DISABLE setting" range="" rwaccess="RW"/>\r
-    <bitfield id="DCAN1_RAMINIT_START" width="1" begin="3" end="3" resetval="0x0" description="DCAN1 RAM INIT START setting To initialize DCAN1 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. : If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." range="" rwaccess="RW"/>\r
+    <bitfield id="DCAN1_RAMINIT_START" width="1" begin="3" end="3" resetval="0x0" description="DCAN1 RAM INIT START setting To initialize DCAN1 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. Note: If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." range="" rwaccess="RW"/>\r
     <bitfield id="DCAN2_RAMINIT_DONE" width="1" begin="2" end="2" resetval="0x0" description="DCAN2 RAM INIT DONE status" range="" rwaccess="RW"/>\r
     <bitfield id="DCAN1_RAMINIT_DONE" width="1" begin="1" end="1" resetval="0x0" description="DCAN1 RAM INIT DONE status" range="" rwaccess="RW"/>\r
     <bitfield id="DSS_DESHDCP_CLKEN" width="1" begin="0" end="0" resetval="0x0" description="DSS DESHDCP CLOCK ENABLE setting" range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="6" begin="15" end="10" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="THOLD_COLD_IVA" width="10" begin="9" end="0" resetval="0x0" description="Value for the low temperature threshold. The values for loading this bit field are listed in." range="" rwaccess="RW"/>\r
   </register>\r
-  <register id="CTRL_CORE_BANDGAP_TSHUT_DSPEVE" acronym="CTRL_CORE_BANDGAP_TSHUT_DSPEVE" offset="0x588" width="32" description="BGAP TSHUT THRESHOLD IVA">\r
+  <register id="CTRL_CORE_BANDGAP_TSHUT_DSPEVE" acronym="CTRL_CORE_BANDGAP_TSHUT_DSPEVE" offset="0x588" width="32" description="BGAP TSHUT THRESHOLD DSPEVE">\r
     <bitfield id="RESERVED" width="1" begin="31" end="31" resetval="0x0" description="Software should not modify this bit." range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="5" begin="30" end="26" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="TSHUT_HOT_DSPEVE" width="10" begin="25" end="16" resetval="0x0" description="tshut value hot Software should not modify this bit field." range="" rwaccess="RW"/>\r
   </register>\r
   <register id="CTRL_CORE_MLB_DLL" acronym="CTRL_CORE_MLB_DLL" offset="0x798" width="32" description="">\r
     <bitfield id="RESERVED" width="21" begin="31" end="11" resetval="0x0" description="" range="" rwaccess="R"/>\r
-    <bitfield id="DLL_CLOCK_DISABLE" width="1" begin="10" end="10" resetval="0x0" description="0x0: MDLL reference clock is enabled 0x1: MDLL reference clock is disabled" range="" rwaccess="RW"/>\r
+    <bitfield id="DLL_CLOCK_DISABLE" width="1" begin="10" end="10" resetval="0x0" description="0x0: MDLL reference clock is enabled (on SR1.0) 0x0: MDLL reference clock is disabled 0x1: MDLL reference clock is disabled (on SR1.0) 0x1: MDLL reference clock is enabled" range="" rwaccess="RW"/>\r
     <bitfield id="DLL_LOCK" width="1" begin="9" end="9" resetval="0x0" description="Value of 0x1 indicates that the MDLL has locked to its reference clock. This bit remains high till MDLL reset occurs." range="" rwaccess="RW"/>\r
     <bitfield id="SDL_LOCK" width="1" begin="8" end="8" resetval="0x0" description="Value of 0x1 indicates that the SDL has been updated with a code. This bit remains high till the SDL reset occurs." range="" rwaccess="RW"/>\r
     <bitfield id="DLL_RATIO" width="8" begin="7" end="0" resetval="0x0" description="The value which has to be loaded in this bit field is calculated based on the equation DLL_RATIO = (2,5/MP)*256, where MP is the MDLL clock period measured in ns." range="" rwaccess="RW"/>\r
     <bitfield id="RESERVED" width="23" begin="31" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="IPU2_IRQ_79" width="9" begin="8" end="0" resetval="0x3F" description="" range="" rwaccess="RW"/>\r
   </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_32_33" acronym="CTRL_CORE_PRUSS1_IRQ_32_33" offset="0x8C8" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_32" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_34_35" acronym="CTRL_CORE_PRUSS1_IRQ_34_35" offset="0x8CC" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_35" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_34" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_36_37" acronym="CTRL_CORE_PRUSS1_IRQ_36_37" offset="0x8D0" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_37" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_36" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_38_39" acronym="CTRL_CORE_PRUSS1_IRQ_38_39" offset="0x8D4" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_39" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_38" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_40_41" acronym="CTRL_CORE_PRUSS1_IRQ_40_41" offset="0x8D8" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_41" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_40" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_42_43" acronym="CTRL_CORE_PRUSS1_IRQ_42_43" offset="0x8DC" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_43" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_42" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_44_45" acronym="CTRL_CORE_PRUSS1_IRQ_44_45" offset="0x8E0" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_45" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_44" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_46_47" acronym="CTRL_CORE_PRUSS1_IRQ_46_47" offset="0x8E4" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_47" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_46" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_48_49" acronym="CTRL_CORE_PRUSS1_IRQ_48_49" offset="0x8E8" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_49" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_48" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_50_51" acronym="CTRL_CORE_PRUSS1_IRQ_50_51" offset="0x8EC" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_51" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_50" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_52_53" acronym="CTRL_CORE_PRUSS1_IRQ_52_53" offset="0x8F0" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_53" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_52" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_54_55" acronym="CTRL_CORE_PRUSS1_IRQ_54_55" offset="0x8F4" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_55" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_54" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_56_57" acronym="CTRL_CORE_PRUSS1_IRQ_56_57" offset="0x8F8" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_57" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_56" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_58_59" acronym="CTRL_CORE_PRUSS1_IRQ_58_59" offset="0x8FC" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_59" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_58" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_60_61" acronym="CTRL_CORE_PRUSS1_IRQ_60_61" offset="0x900" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_61" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_60" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS1_IRQ_62_63" acronym="CTRL_CORE_PRUSS1_IRQ_62_63" offset="0x904" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_63" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS1_IRQ_62" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_32_33" acronym="CTRL_CORE_PRUSS2_IRQ_32_33" offset="0x908" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_32" width="9" begin="8" end="0" resetval="0x1" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_34_35" acronym="CTRL_CORE_PRUSS2_IRQ_34_35" offset="0x90C" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_35" width="9" begin="24" end="16" resetval="0x4" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_34" width="9" begin="8" end="0" resetval="0x3" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_36_37" acronym="CTRL_CORE_PRUSS2_IRQ_36_37" offset="0x910" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_37" width="9" begin="24" end="16" resetval="0x6" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_36" width="9" begin="8" end="0" resetval="0x5" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_38_39" acronym="CTRL_CORE_PRUSS2_IRQ_38_39" offset="0x914" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_39" width="9" begin="24" end="16" resetval="0x8" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_38" width="9" begin="8" end="0" resetval="0x7" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_40_41" acronym="CTRL_CORE_PRUSS2_IRQ_40_41" offset="0x918" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_41" width="9" begin="24" end="16" resetval="0xA" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_40" width="9" begin="8" end="0" resetval="0x9" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_42_43" acronym="CTRL_CORE_PRUSS2_IRQ_42_43" offset="0x91C" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_43" width="9" begin="24" end="16" resetval="0xC" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_42" width="9" begin="8" end="0" resetval="0xB" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_44_45" acronym="CTRL_CORE_PRUSS2_IRQ_44_45" offset="0x920" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_45" width="9" begin="24" end="16" resetval="0xE" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_44" width="9" begin="8" end="0" resetval="0xD" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_46_47" acronym="CTRL_CORE_PRUSS2_IRQ_46_47" offset="0x924" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_47" width="9" begin="24" end="16" resetval="0x10" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_46" width="9" begin="8" end="0" resetval="0xF" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_48_49" acronym="CTRL_CORE_PRUSS2_IRQ_48_49" offset="0x928" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_49" width="9" begin="24" end="16" resetval="0x12" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_48" width="9" begin="8" end="0" resetval="0x11" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_50_51" acronym="CTRL_CORE_PRUSS2_IRQ_50_51" offset="0x92C" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_51" width="9" begin="24" end="16" resetval="0x14" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_50" width="9" begin="8" end="0" resetval="0x13" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_52_53" acronym="CTRL_CORE_PRUSS2_IRQ_52_53" offset="0x930" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_53" width="9" begin="24" end="16" resetval="0x16" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_52" width="9" begin="8" end="0" resetval="0x15" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_54_55" acronym="CTRL_CORE_PRUSS2_IRQ_54_55" offset="0x934" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_55" width="9" begin="24" end="16" resetval="0x18" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_54" width="9" begin="8" end="0" resetval="0x17" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_56_57" acronym="CTRL_CORE_PRUSS2_IRQ_56_57" offset="0x938" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_57" width="9" begin="24" end="16" resetval="0x1A" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_56" width="9" begin="8" end="0" resetval="0x19" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_58_59" acronym="CTRL_CORE_PRUSS2_IRQ_58_59" offset="0x93C" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_59" width="9" begin="24" end="16" resetval="0x1C" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_58" width="9" begin="8" end="0" resetval="0x1B" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_60_61" acronym="CTRL_CORE_PRUSS2_IRQ_60_61" offset="0x940" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_61" width="9" begin="24" end="16" resetval="0x1E" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_60" width="9" begin="8" end="0" resetval="0x1D" description="" range="" rwaccess="RW"/>\r
+  </register>\r
+  <register id="CTRL_CORE_PRUSS2_IRQ_62_63" acronym="CTRL_CORE_PRUSS2_IRQ_62_63" offset="0x944" width="32" description="">\r
+    <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_63" width="9" begin="24" end="16" resetval="0x20" description="" range="" rwaccess="RW"/>\r
+    <bitfield id="RESERVED" width="7" begin="15" end="9" resetval="0x0" description="" range="" rwaccess="R"/>\r
+    <bitfield id="PRUSS2_IRQ_62" width="9" begin="8" end="0" resetval="0x1F" description="" range="" rwaccess="RW"/>\r
+  </register>\r
   <register id="CTRL_CORE_DSP1_IRQ_32_33" acronym="CTRL_CORE_DSP1_IRQ_32_33" offset="0x948" width="32" description="">\r
     <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
     <bitfield id="DSP1_IRQ_33" width="9" begin="24" end="16" resetval="0x2" description="" range="" rwaccess="RW"/>\r
       <bitenum value="0" id="GPMC_A24" token="GPMC_A24_MUXMODE_0" description="gpmc_a24"/>\r
       <bitenum value="1" id="MMC2_DAT0" token="GPMC_A24_MUXMODE_1" description="mmc2_dat0"/>\r
       <bitenum value="2" id="GPMC_A18" token="GPMC_A24_MUXMODE_2" description="gpmc_a18"/>\r
-      <bitenum value="4" id="VIN2A_D8 VIN1A_D8" token="GPMC_A24_MUXMODE_4" description="vin2a_d8 vin1a_d8"/>\r
+      <bitenum value="4" id="VIN2A_D8 VIN1A_D8" token="GPMC_A24_MUXMODE_4" description="vin1a_d8"/>\r
       <bitenum value="6" id="VIN2B_D5 VIN1B_D5" token="GPMC_A24_MUXMODE_6" description="vin2b_d5 vin1b_d5"/>\r
       <bitenum value="14" id="GPIO2_14" token="GPMC_A24_MUXMODE_14" description="gpio2_14"/>\r
       <bitenum value="15" id="DRIVER OFF" token="GPMC_A24_MUXMODE_15" description="Driver off"/>\r
       <bitenum value="0" id="GPMC_A25" token="GPMC_A25_MUXMODE_0" description="gpmc_a25"/>\r
       <bitenum value="1" id="MMC2_DAT1" token="GPMC_A25_MUXMODE_1" description="mmc2_dat1"/>\r
       <bitenum value="2" id="GPMC_A19" token="GPMC_A25_MUXMODE_2" description="gpmc_a19"/>\r
-      <bitenum value="4" id="VIN2A_D9 VIN1A_D9" token="GPMC_A25_MUXMODE_4" description="vin2a_d9 vin1a_d9"/>\r
+      <bitenum value="4" id="VIN2A_D9 VIN1A_D9" token="GPMC_A25_MUXMODE_4" description="vin1a_d9"/>\r
       <bitenum value="6" id="VIN2B_D6 VIN1B_D6" token="GPMC_A25_MUXMODE_6" description="vin2b_d6 vin1b_d6"/>\r
       <bitenum value="14" id="GPIO2_15" token="GPMC_A25_MUXMODE_14" description="gpio2_15"/>\r
       <bitenum value="15" id="DRIVER OFF" token="GPMC_A25_MUXMODE_15" description="Driver off"/>\r
       <bitenum value="0" id="GPMC_A26" token="GPMC_A26_MUXMODE_0" description="gpmc_a26"/>\r
       <bitenum value="1" id="MMC2_DAT2" token="GPMC_A26_MUXMODE_1" description="mmc2_dat2"/>\r
       <bitenum value="2" id="GPMC_A20" token="GPMC_A26_MUXMODE_2" description="gpmc_a20"/>\r
-      <bitenum value="4" id="VIN2A_D10 VIN1A_D10" token="GPMC_A26_MUXMODE_4" description="vin2a_d10 vin1a_d10"/>\r
+      <bitenum value="4" id="VIN2A_D10 VIN1A_D10" token="GPMC_A26_MUXMODE_4" description="vin1a_d10"/>\r
       <bitenum value="6" id="VIN2B_D7 VIN1B_D7" token="GPMC_A26_MUXMODE_6" description="vin2b_d7 vin1b_d7"/>\r
       <bitenum value="14" id="GPIO2_16" token="GPMC_A26_MUXMODE_14" description="gpio2_16"/>\r
       <bitenum value="15" id="DRIVER OFF" token="GPMC_A26_MUXMODE_15" description="Driver off"/>\r
       <bitenum value="0" id="GPMC_A27" token="GPMC_A27_MUXMODE_0" description="gpmc_a27"/>\r
       <bitenum value="1" id="MMC2_DAT3" token="GPMC_A27_MUXMODE_1" description="mmc2_dat3"/>\r
       <bitenum value="2" id="GPMC_A21" token="GPMC_A27_MUXMODE_2" description="gpmc_a21"/>\r
-      <bitenum value="4" id="VIN2A_D11 VIN1A_D11" token="GPMC_A27_MUXMODE_4" description="vin2a_d11 vin1a_d11"/>\r
+      <bitenum value="4" id="VIN2A_D11 VIN1A_D11" token="GPMC_A27_MUXMODE_4" description="vin1a_d11"/>\r
       <bitenum value="6" id="VIN2B_HSYNC1 VIN1B_HSYNC1" token="GPMC_A27_MUXMODE_6" description="vin2b_hsync1 vin1b_hsync1"/>\r
       <bitenum value="14" id="GPIO2_17" token="GPMC_A27_MUXMODE_14" description="gpio2_17"/>\r
       <bitenum value="15" id="DRIVER OFF" token="GPMC_A27_MUXMODE_15" description="Driver off"/>\r
similarity index 95%
rename from XMLFiles/DRA72x/model_DRA72x_SR1.0_v1.0.7.xml
rename to XMLFiles/DRA72x/model_DRA72x_SR1.0_v1.0.9.xml
index 3223e49cb0a3c8ca570c39802435aab84daa9789..1f05a7b23411809133a7ef9fc98c969979c58e49 100644 (file)
@@ -1,12 +1,11 @@
 <?xml version="1.0" encoding="US-ASCII"?>\r
 <SoC>\r
 <projectName>DRA72x_SR1.0</projectName>\r
-<versionNumber>1.0.7</versionNumber>\r
+<versionNumber>1.0.9</versionNumber>\r
 <padDB>\r
 \r
 <!-- START REGULAR PADCONF blocks -->\r
-
-
+\r
 <clockNode>\r
   <name>spi1_d0</name>\r
   <type>\r
         <mode>8</mode>\r
         <signal>vin2a_fld0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_GPIO6_16_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_vsync0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_GPIO6_15_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d18</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>13</value>\r
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           <AssociatedInfo>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
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+          <name>IOSET7</name>\r
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+            <signal>vin1b_clk1</signal>\r
+            <ball>N9</ball>\r
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         <signal>vin2a_d6</signal>\r
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           <AssociatedInfo>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
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+          <name>IOSET7</name>\r
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+            <ball>R4</ball>\r
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+            <ball>R6</ball>\r
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       <muxmode>\r
         <mode>7</mode>\r
         <mode>4</mode>\r
         <signal>vin2a_d0</signal>\r
         <color>0xbc8f8f</color>\r
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         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
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+          <name>IOSET7</name>\r
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+            <signal>vin1b_clk1</signal>\r
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+            <ball>R4</ball>\r
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+            <signal>vin1b_d3</signal>\r
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+            <ball>R9</ball>\r
+            <mode>6</mode>\r
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+            <ball>R5</ball>\r
+            <mode>6</mode>\r
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+            <signal>vin1b_d7</signal>\r
+            <ball>P5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
       </muxmode>\r
       <muxmode>\r
         <mode>7</mode>\r
         <mode>4</mode>\r
         <signal>vin2a_d11</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
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-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
         <mode>4</mode>\r
         <signal>vin2a_hsync0</signal>\r
         <color>0xbc8f8f</color>\r
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-            <value>12</value>\r
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         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
         <mode>4</mode>\r
         <signal>vin2a_d5</signal>\r
         <color>0xbc8f8f</color>\r
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-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
+        <ioset>\r
+          <name>IOSET7</name>\r
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+            <signal>vin1b_clk1</signal>\r
+            <ball>N9</ball>\r
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+          <AssociatedInfo>\r
+            <signal>vin1b_vsync1</signal>\r
+            <ball>R4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_fld1</signal>\r
+            <ball>P4</ball>\r
+            <mode>6</mode>\r
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+          <AssociatedInfo>\r
+            <signal>vin1b_de1</signal>\r
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+            <mode>6</mode>\r
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+          <AssociatedInfo>\r
+            <signal>vin1b_d6</signal>\r
+            <ball>R5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
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+            <signal>vin1b_d7</signal>\r
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+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
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       <muxmode>\r
         <mode>7</mode>\r
         <mode>8</mode>\r
         <signal>vin2a_d0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
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-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP1_ACLKR_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d14</signal>\r
         <color>0xbc8f8f</color>\r
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-          <mode>\r
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-            <value>9</value>\r
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         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP2_AXR6_IN</name>\r
       </muxmode>\r
       <muxmode>\r
         <mode>4</mode>\r
-        <signal>vin2a_d8</signal>\r
+        <signal>vin1a_d8</signal>\r
         <color>0xbc8f8f</color>\r
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-          <mode>\r
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       <muxmode>\r
         <mode>6</mode>\r
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             <name>VIP_VIRTUAL7</name>\r
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         <ioset>\r
           <name>IOSET2</name>\r
         <mode>4</mode>\r
         <signal>vin2a_d14</signal>\r
         <color>0xbc8f8f</color>\r
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-          <mode>\r
-            <value>-1</value>\r
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-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
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         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
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             <name>VIP_VIRTUAL7</name>\r
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         <ioset>\r
           <name>IOSET2</name>\r
       </muxmode>\r
       <muxmode>\r
         <mode>4</mode>\r
-        <signal>vin2a_d9</signal>\r
+        <signal>vin1a_d9</signal>\r
         <color>0xbc8f8f</color>\r
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-          <mode>\r
-            <value>-1</value>\r
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-            <value>12</value>\r
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       <muxmode>\r
         <mode>6</mode>\r
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             <name>VIP_VIRTUAL7</name>\r
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         </virtualmode>\r
         <ioset>\r
           <name>IOSET2</name>\r
         <mode>4</mode>\r
         <signal>vin2a_fld0</signal>\r
         <color>0xbc8f8f</color>\r
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-            <value>12</value>\r
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         <ioset>\r
           <name>IOSET9</name>\r
           <AssociatedInfo>\r
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             <name>VIP_VIRTUAL7</name>\r
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         <ioset>\r
           <name>IOSET2</name>\r
         <mode>3</mode>\r
         <signal>vin2a_d0</signal>\r
         <color>0xbc8f8f</color>\r
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-            <value>-1</value>\r
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         <ioset>\r
           <name>IOSET7</name>\r
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         <mode>3</mode>\r
         <signal>vin2a_d1</signal>\r
         <color>0xbc8f8f</color>\r
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         <ioset>\r
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         <mode>3</mode>\r
         <signal>vin2a_d6</signal>\r
         <color>0xbc8f8f</color>\r
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-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>8</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>8</mode>\r
         <signal>vin2a_d21</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>7</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP5_FSX_IN</name>\r
         <mode>4</mode>\r
         <signal>vin2a_d9</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
         <mode>4</mode>\r
         <signal>vin2a_d8</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <value>12</value>\r
             <name>VIP_VIRTUAL7</name>\r
           </mode>\r
-          <mode>\r
-            <value>13</value>\r
-            <name>VIP_VIRTUAL6</name>\r
-          </mode>\r
         </virtualmode>\r
         <ioset>\r
           <name>IOSET1</name>\r
         <mode>4</mode>\r
         <signal>vin2a_d13</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <value>9</value>\r
             <name>VIP_VIRTUAL7</name>\r
           </mode>\r
-          <mode>\r
-            <value>10</value>\r
-            <name>VIP_VIRTUAL6</name>\r
-          </mode>\r
         </virtualmode>\r
         <ioset>\r
           <name>IOSET2</name>\r
         <mode>3</mode>\r
         <signal>vin2a_d20</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d8</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d23</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>14</mode>\r
         <signal>gpio4_10</signal>\r
         <color>0x8fbc8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>GPMC_VIRTUAL1</name>\r
-          </mode>\r
-        </virtualmode>\r
       </muxmode>\r
       <muxmode>\r
         <mode>15</mode>\r
         <mode>14</mode>\r
         <signal>gpio3_28</signal>\r
         <color>0x8fbc8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>11</value>\r
-            <name>GPMC_VIRTUAL1</name>\r
-          </mode>\r
-        </virtualmode>\r
       </muxmode>\r
       <muxmode>\r
         <mode>15</mode>\r
         <mode>4</mode>\r
         <signal>vin2a_d10</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
         <mode>4</mode>\r
         <signal>vin2a_d4</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>11</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
+        <ioset>\r
+          <name>IOSET7</name>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_clk1</signal>\r
+            <ball>N9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_hsync1</signal>\r
+            <ball>N7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_vsync1</signal>\r
+            <ball>R4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_fld1</signal>\r
+            <ball>P4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_de1</signal>\r
+            <ball>P9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d0</signal>\r
+            <ball>R6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d1</signal>\r
+            <ball>T9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d2</signal>\r
+            <ball>T6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d3</signal>\r
+            <ball>T7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d5</signal>\r
+            <ball>R9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d6</signal>\r
+            <ball>R5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d7</signal>\r
+            <ball>P5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
       </muxmode>\r
       <muxmode>\r
         <mode>7</mode>\r
         <mode>4</mode>\r
         <signal>vin2a_hsync0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>14</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET9</name>\r
           <AssociatedInfo>\r
         <mode>5</mode>\r
         <signal>vin2a_de0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>14</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
         <mode>6</mode>\r
         <signal>vin2b_clk1</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>13</value>\r
-            <name>VIP_VIRTUAL6</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET1</name>\r
           <AssociatedInfo>\r
         <mode>4</mode>\r
         <signal>vin2a_clk0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>14</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
+        <ioset>\r
+          <name>IOSET7</name>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_clk1</signal>\r
+            <ball>N9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_hsync1</signal>\r
+            <ball>N7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_vsync1</signal>\r
+            <ball>R4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_de1</signal>\r
+            <ball>P9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d0</signal>\r
+            <ball>R6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d1</signal>\r
+            <ball>T9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d2</signal>\r
+            <ball>T6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d3</signal>\r
+            <ball>T7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d4</signal>\r
+            <ball>P6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d5</signal>\r
+            <ball>R9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d6</signal>\r
+            <ball>R5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d7</signal>\r
+            <ball>P5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
       </muxmode>\r
       <muxmode>\r
         <mode>7</mode>\r
         <mode>4</mode>\r
         <signal>vin2a_d7</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>13</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
+        <ioset>\r
+          <name>IOSET7</name>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_clk1</signal>\r
+            <ball>N9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_hsync1</signal>\r
+            <ball>N7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_vsync1</signal>\r
+            <ball>R4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_fld1</signal>\r
+            <ball>P4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_de1</signal>\r
+            <ball>P9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d0</signal>\r
+            <ball>R6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d1</signal>\r
+            <ball>T9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d2</signal>\r
+            <ball>T6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d3</signal>\r
+            <ball>T7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d4</signal>\r
+            <ball>P6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d5</signal>\r
+            <ball>R9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d6</signal>\r
+            <ball>R5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
       </muxmode>\r
       <muxmode>\r
         <mode>7</mode>\r
         <mode>4</mode>\r
         <signal>vin2a_fld0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>13</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
+        <ioset>\r
+          <name>IOSET7</name>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_clk1</signal>\r
+            <ball>N9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_hsync1</signal>\r
+            <ball>N7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_vsync1</signal>\r
+            <ball>R4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_fld1</signal>\r
+            <ball>P4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d0</signal>\r
+            <ball>R6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d1</signal>\r
+            <ball>T9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d2</signal>\r
+            <ball>T6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d3</signal>\r
+            <ball>T7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d4</signal>\r
+            <ball>P6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d5</signal>\r
+            <ball>R9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d6</signal>\r
+            <ball>R5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d7</signal>\r
+            <ball>P5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
       </muxmode>\r
       <muxmode>\r
         <mode>7</mode>\r
         <mode>8</mode>\r
         <signal>vin2a_d5</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>11</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP1_AXR5_IN</name>\r
         <mode>3</mode>\r
         <signal>vin2a_d18</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d16</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>4</mode>\r
         <signal>vin2a_de0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET9</name>\r
           <AssociatedInfo>\r
             <value>9</value>\r
             <name>VIP_VIRTUAL7</name>\r
           </mode>\r
-          <mode>\r
-            <value>10</value>\r
-            <name>VIP_VIRTUAL6</name>\r
-          </mode>\r
         </virtualmode>\r
         <ioset>\r
           <name>IOSET2</name>\r
         <mode>14</mode>\r
         <signal>gpio3_30</signal>\r
         <color>0x8fbc8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>11</value>\r
-            <name>GPMC_VIRTUAL1</name>\r
-          </mode>\r
-        </virtualmode>\r
       </muxmode>\r
       <muxmode>\r
         <mode>15</mode>\r
       </muxmode>\r
       <muxmode>\r
         <mode>4</mode>\r
-        <signal>vin2a_d10</signal>\r
+        <signal>vin1a_d10</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
       </muxmode>\r
       <muxmode>\r
         <mode>6</mode>\r
             <value>9</value>\r
             <name>VIP_VIRTUAL7</name>\r
           </mode>\r
-          <mode>\r
-            <value>10</value>\r
-            <name>VIP_VIRTUAL6</name>\r
-          </mode>\r
         </virtualmode>\r
         <ioset>\r
           <name>IOSET2</name>\r
       </muxmode>\r
       <muxmode>\r
         <mode>4</mode>\r
-        <signal>vin2a_d11</signal>\r
+        <signal>vin1a_d11</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
       </muxmode>\r
       <muxmode>\r
         <mode>6</mode>\r
             <value>9</value>\r
             <name>VIP_VIRTUAL7</name>\r
           </mode>\r
-          <mode>\r
-            <value>10</value>\r
-            <name>VIP_VIRTUAL6</name>\r
-          </mode>\r
         </virtualmode>\r
         <ioset>\r
           <name>IOSET2</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d12</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP2_AXR4_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d19</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>7</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP4_AXR1_IN</name>\r
         <mode>3</mode>\r
         <signal>vin2a_fld0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>14</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>8</mode>\r
         <signal>vin2a_d7</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>11</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP1_AXR7_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d13</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP2_AXR5_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_clk0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>7</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_XREF_CLK2_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d10</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>10</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP2_AXR0_IN</name>\r
         <mode>4</mode>\r
         <signal>vin2a_d12</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <value>9</value>\r
             <name>VIP_VIRTUAL7</name>\r
           </mode>\r
-          <mode>\r
-            <value>10</value>\r
-            <name>VIP_VIRTUAL6</name>\r
-          </mode>\r
         </virtualmode>\r
         <ioset>\r
           <name>IOSET2</name>\r
         <mode>4</mode>\r
         <signal>vin2a_d15</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <value>9</value>\r
             <name>VIP_VIRTUAL7</name>\r
           </mode>\r
-          <mode>\r
-            <value>10</value>\r
-            <name>VIP_VIRTUAL6</name>\r
-          </mode>\r
         </virtualmode>\r
         <ioset>\r
           <name>IOSET2</name>\r
         <mode>3</mode>\r
         <signal>vin2a_de0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>14</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_clk0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>14</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d4</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>8</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d14</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         </ioset>\r
       </muxmode>\r
       <muxmode>\r
-        <mode>8</mode>\r
-        <signal>mii1_rxd1</signal>\r
-        <color>0x2e8b57</color>\r
-        <ioset>\r
-          <name>IOSET5</name>\r
-          <AssociatedInfo>\r
-            <signal>mii1_txd3</signal>\r
-            <ball>C5</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_txd2</signal>\r
-            <ball>D6</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_txd1</signal>\r
-            <ball>B2</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_txd0</signal>\r
-            <ball>C4</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_rxd3</signal>\r
-            <ball>F5</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_rxd2</signal>\r
-            <ball>E4</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_rxd0</signal>\r
-            <ball>E6</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_col</signal>\r
-            <ball>B4</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_rxer</signal>\r
-            <ball>B3</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_txer</signal>\r
-            <ball>A3</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_txen</signal>\r
-            <ball>A4</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_crs</signal>\r
-            <ball>B5</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_rxclk</signal>\r
-            <ball>D5</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_txclk</signal>\r
-            <ball>C3</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>mii1_rxdv</signal>\r
-            <ball>C2</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-        </ioset>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>9</mode>\r
-        <signal>kbd_col3</signal>\r
-        <color>0xeedd82</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>10</mode>\r
-        <signal>eQEP2B_in</signal>\r
-        <color>0x4169e1</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>14</mode>\r
-        <signal>gpio4_7</signal>\r
-        <color>0x8fbc8f</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>15</mode>\r
-        <signal>Driveroff</signal>\r
-        <color>0xf0fff0</color>\r
-      </muxmode>\r
-      <confregisters>\r
-        <regbit>\r
-          <register>CTRL_CORE_PAD_VIN2A_D6</register>\r
-        </regbit>\r
-      </confregisters>\r
-    </pad>\r
-  </type>\r
-</clockNode>\r
-<clockNode>\r
-  <name>vout1_d15</name>\r
-  <type>\r
-    <pad>\r
-      <ballname>C7</ballname>\r
-      <dir>IO</dir>\r
-      <numberOfMuxmodes>16</numberOfMuxmodes>\r
-      <muxmode>\r
-        <mode>0</mode>\r
-        <signal>vout1_d15</signal>\r
-        <color>0xe9967a</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>15</value>\r
-            <name>DSS_VIRTUAL1</name>\r
-          </mode>\r
-        </virtualmode>\r
-        <manualmode>\r
-          <cfgreg>\r
-            <name>CFG_VOUT1_D15_OUT</name>\r
-            <mode>\r
-              <adelay>-1</adelay>\r
-              <gdelay>-1</gdelay>\r
-              <name>NA</name>\r
-            </mode>\r
-            <mode>\r
-              <adelay>2832</adelay>\r
-              <gdelay>23</gdelay>\r
-              <name>VOUT1_MANUAL1</name>\r
-            </mode>\r
-          </cfgreg>\r
-        </manualmode>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>2</mode>\r
-        <signal>emu14</signal>\r
-        <color>0x778899</color>\r
-        <ioset>\r
-          <name>IOSET2</name>\r
-          <AssociatedInfo>\r
-            <signal>emu19</signal>\r
-            <ball>A10</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu18</signal>\r
-            <ball>B9</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu17</signal>\r
-            <ball>A9</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu16</signal>\r
-            <ball>C9</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu15</signal>\r
-            <ball>A8</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu13</signal>\r
-            <ball>C8</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu12</signal>\r
-            <ball>C6</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu11</signal>\r
-            <ball>A5</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu10</signal>\r
-            <ball>D8</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu9</signal>\r
-            <ball>E7</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu8</signal>\r
-            <ball>F8</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu7</signal>\r
-            <ball>F9</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu6</signal>\r
-            <ball>E9</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu5</signal>\r
-            <ball>G11</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu4</signal>\r
-            <ball>A7</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu3</signal>\r
-            <ball>D7</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu2</signal>\r
-            <ball>F10</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu1</signal>\r
-            <ball>D24</ball>\r
-            <mode>0</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu0</signal>\r
-            <ball>G21</ball>\r
-            <mode>0</mode>\r
-          </AssociatedInfo>\r
-        </ioset>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>3</mode>\r
-        <signal>vin2a_d15</signal>\r
-        <color>0xbc8f8f</color>\r
+        <mode>8</mode>\r
+        <signal>mii1_rxd1</signal>\r
+        <color>0x2e8b57</color>\r
+        <ioset>\r
+          <name>IOSET5</name>\r
+          <AssociatedInfo>\r
+            <signal>mii1_txd3</signal>\r
+            <ball>C5</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_txd2</signal>\r
+            <ball>D6</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_txd1</signal>\r
+            <ball>B2</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_txd0</signal>\r
+            <ball>C4</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_rxd3</signal>\r
+            <ball>F5</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_rxd2</signal>\r
+            <ball>E4</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_rxd0</signal>\r
+            <ball>E6</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_col</signal>\r
+            <ball>B4</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_rxer</signal>\r
+            <ball>B3</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_txer</signal>\r
+            <ball>A3</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_txen</signal>\r
+            <ball>A4</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_crs</signal>\r
+            <ball>B5</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_rxclk</signal>\r
+            <ball>D5</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_txclk</signal>\r
+            <ball>C3</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>mii1_rxdv</signal>\r
+            <ball>C2</ball>\r
+            <mode>8</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
+      </muxmode>\r
+      <muxmode>\r
+        <mode>9</mode>\r
+        <signal>kbd_col3</signal>\r
+        <color>0xeedd82</color>\r
+      </muxmode>\r
+      <muxmode>\r
+        <mode>10</mode>\r
+        <signal>eQEP2B_in</signal>\r
+        <color>0x4169e1</color>\r
+      </muxmode>\r
+      <muxmode>\r
+        <mode>14</mode>\r
+        <signal>gpio4_7</signal>\r
+        <color>0x8fbc8f</color>\r
+      </muxmode>\r
+      <muxmode>\r
+        <mode>15</mode>\r
+        <signal>Driveroff</signal>\r
+        <color>0xf0fff0</color>\r
+      </muxmode>\r
+      <confregisters>\r
+        <regbit>\r
+          <register>CTRL_CORE_PAD_VIN2A_D6</register>\r
+        </regbit>\r
+      </confregisters>\r
+    </pad>\r
+  </type>\r
+</clockNode>\r
+<clockNode>\r
+  <name>vout1_d15</name>\r
+  <type>\r
+    <pad>\r
+      <ballname>C7</ballname>\r
+      <dir>IO</dir>\r
+      <numberOfMuxmodes>16</numberOfMuxmodes>\r
+      <muxmode>\r
+        <mode>0</mode>\r
+        <signal>vout1_d15</signal>\r
+        <color>0xe9967a</color>\r
         <virtualmode>\r
           <mode>\r
             <value>-1</value>\r
             <name>NA</name>\r
           </mode>\r
           <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
+            <value>15</value>\r
+            <name>DSS_VIRTUAL1</name>\r
           </mode>\r
         </virtualmode>\r
+        <manualmode>\r
+          <cfgreg>\r
+            <name>CFG_VOUT1_D15_OUT</name>\r
+            <mode>\r
+              <adelay>-1</adelay>\r
+              <gdelay>-1</gdelay>\r
+              <name>NA</name>\r
+            </mode>\r
+            <mode>\r
+              <adelay>2832</adelay>\r
+              <gdelay>23</gdelay>\r
+              <name>VOUT1_MANUAL1</name>\r
+            </mode>\r
+          </cfgreg>\r
+        </manualmode>\r
+      </muxmode>\r
+      <muxmode>\r
+        <mode>2</mode>\r
+        <signal>emu14</signal>\r
+        <color>0x778899</color>\r
+        <ioset>\r
+          <name>IOSET2</name>\r
+          <AssociatedInfo>\r
+            <signal>emu19</signal>\r
+            <ball>A10</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu18</signal>\r
+            <ball>B9</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu17</signal>\r
+            <ball>A9</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu16</signal>\r
+            <ball>C9</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu15</signal>\r
+            <ball>A8</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu13</signal>\r
+            <ball>C8</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu12</signal>\r
+            <ball>C6</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu11</signal>\r
+            <ball>A5</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu10</signal>\r
+            <ball>D8</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu9</signal>\r
+            <ball>E7</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu8</signal>\r
+            <ball>F8</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu7</signal>\r
+            <ball>F9</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu6</signal>\r
+            <ball>E9</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu5</signal>\r
+            <ball>G11</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu4</signal>\r
+            <ball>A7</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu3</signal>\r
+            <ball>D7</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu2</signal>\r
+            <ball>F10</ball>\r
+            <mode>2</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu1</signal>\r
+            <ball>D24</ball>\r
+            <mode>0</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>emu0</signal>\r
+            <ball>G21</ball>\r
+            <mode>0</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
+      </muxmode>\r
+      <muxmode>\r
+        <mode>3</mode>\r
+        <signal>vin2a_d15</signal>\r
+        <color>0xbc8f8f</color>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d13</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>8</mode>\r
         <signal>vin2a_hsync0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_GPIO6_14_IN</name>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
+        <ioset>\r
+          <name>IOSET7</name>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_hsync1</signal>\r
+            <ball>N7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_vsync1</signal>\r
+            <ball>R4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_fld1</signal>\r
+            <ball>P4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_de1</signal>\r
+            <ball>P9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d0</signal>\r
+            <ball>R6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d1</signal>\r
+            <ball>T9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d2</signal>\r
+            <ball>T6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d3</signal>\r
+            <ball>T7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d4</signal>\r
+            <ball>P6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d5</signal>\r
+            <ball>R9</ball>\r
+            <mode>6</mode>\r
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+          <AssociatedInfo>\r
+            <signal>vin1b_d6</signal>\r
+            <ball>R5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d7</signal>\r
+            <ball>P5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
       </muxmode>\r
       <muxmode>\r
         <mode>7</mode>\r
         <mode>4</mode>\r
         <signal>vin2a_vsync0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>14</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET9</name>\r
           <AssociatedInfo>\r
         <mode>8</mode>\r
         <signal>vin2a_d2</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>11</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP1_AXR2_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d1</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP1_FSR_IN</name>\r
             <value>12</value>\r
             <name>VIP_VIRTUAL7</name>\r
           </mode>\r
-          <mode>\r
-            <value>13</value>\r
-            <name>VIP_VIRTUAL6</name>\r
-          </mode>\r
         </virtualmode>\r
         <ioset>\r
           <name>IOSET2</name>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
+        <ioset>\r
+          <name>IOSET7</name>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_clk1</signal>\r
+            <ball>N9</ball>\r
+            <mode>6</mode>\r
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+          <AssociatedInfo>\r
+            <signal>vin1b_vsync1</signal>\r
+            <ball>R4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_fld1</signal>\r
+            <ball>P4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_de1</signal>\r
+            <ball>P9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d0</signal>\r
+            <ball>R6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d1</signal>\r
+            <ball>T9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d2</signal>\r
+            <ball>T6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d3</signal>\r
+            <ball>T7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d4</signal>\r
+            <ball>P6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d5</signal>\r
+            <ball>R9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d6</signal>\r
+            <ball>R5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d7</signal>\r
+            <ball>P5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
       </muxmode>\r
       <muxmode>\r
         <mode>7</mode>\r
         <mode>8</mode>\r
         <signal>vin2a_d9</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>11</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP2_FSR_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d17</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>13</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP4_FSX_IN</name>\r
         <mode>14</mode>\r
         <signal>gpio4_9</signal>\r
         <color>0x8fbc8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>GPMC_VIRTUAL1</name>\r
-          </mode>\r
-        </virtualmode>\r
       </muxmode>\r
       <muxmode>\r
         <mode>15</mode>\r
         <mode>14</mode>\r
         <signal>gpio4_12</signal>\r
         <color>0x8fbc8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>9</value>\r
-            <name>GPMC_VIRTUAL1</name>\r
-          </mode>\r
-        </virtualmode>\r
       </muxmode>\r
       <muxmode>\r
         <mode>15</mode>\r
         <mode>3</mode>\r
         <signal>vin2a_d22</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d21</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>8</mode>\r
         <signal>vin2a_d3</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>11</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
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         <mode>8</mode>\r
         <signal>vin2a_de0</signal>\r
         <color>0xbc8f8f</color>\r
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-          </mode>\r
-        </virtualmode>\r
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         <mode>3</mode>\r
         <signal>vin2a_vsync0</signal>\r
         <color>0xbc8f8f</color>\r
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-          <mode>\r
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-          <mode>\r
-            <value>10</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
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         <signal>vin2a_d4</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>11</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
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         <mode>8</mode>\r
         <signal>vin2a_d8</signal>\r
         <color>0xbc8f8f</color>\r
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-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>11</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP2_ACLKR_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d16</signal>\r
         <color>0xbc8f8f</color>\r
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-          <mode>\r
-            <value>-1</value>\r
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-          </mode>\r
-          <mode>\r
-            <value>13</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP4_ACLKX_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d6</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>11</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
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         <mode>3</mode>\r
         <signal>vin2a_hsync0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>14</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
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         <mode>8</mode>\r
         <signal>vin2a_d11</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>10</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
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         <mode>3</mode>\r
         <signal>vin2a_d7</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-            <value>7</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d12</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d2</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
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-          <mode>\r
-            <value>8</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d5</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>8</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d3</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>8</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>8</mode>\r
         <signal>vin2a_d20</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-            <value>7</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP5_ACLKX_IN</name>\r
         <mode>4</mode>\r
         <signal>vin2a_d1</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-            <value>13</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
+        <ioset>\r
+          <name>IOSET7</name>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_clk1</signal>\r
+            <ball>N9</ball>\r
+            <mode>6</mode>\r
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+          <AssociatedInfo>\r
+            <signal>vin1b_hsync1</signal>\r
+            <ball>N7</ball>\r
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+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_vsync1</signal>\r
+            <ball>R4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_fld1</signal>\r
+            <ball>P4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_de1</signal>\r
+            <ball>P9</ball>\r
+            <mode>6</mode>\r
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+          <AssociatedInfo>\r
+            <signal>vin1b_d0</signal>\r
+            <ball>R6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d2</signal>\r
+            <ball>T6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d3</signal>\r
+            <ball>T7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d4</signal>\r
+            <ball>P6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d5</signal>\r
+            <ball>R9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d6</signal>\r
+            <ball>R5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d7</signal>\r
+            <ball>P5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
       </muxmode>\r
       <muxmode>\r
         <mode>7</mode>\r
         <mode>4</mode>\r
         <signal>vin2a_d2</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>13</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
           </AssociatedInfo>\r
         </ioset>\r
         <ioset>\r
-          <name>IOSET9</name>\r
+          <name>IOSET9</name>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_clk0</signal>\r
+            <ball>P4</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_hsync0</signal>\r
+            <ball>P7</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_vsync0</signal>\r
+            <ball>N1</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_fld0</signal>\r
+            <ball>J7</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_de0</signal>\r
+            <ball>H6</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d0</signal>\r
+            <ball>R6</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d1</signal>\r
+            <ball>T9</ball>\r
+            <mode>4</mode>\r
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+          <AssociatedInfo>\r
+            <signal>vin2a_d3</signal>\r
+            <ball>T7</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d4</signal>\r
+            <ball>P6</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d5</signal>\r
+            <ball>R9</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d6</signal>\r
+            <ball>R5</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d7</signal>\r
+            <ball>P5</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d8</signal>\r
+            <ball>U2</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d9</signal>\r
+            <ball>U1</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d10</signal>\r
+            <ball>P3</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d11</signal>\r
+            <ball>R2</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d12</signal>\r
+            <ball>K7</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d13</signal>\r
+            <ball>M7</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d14</signal>\r
+            <ball>J5</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin2a_d15</signal>\r
+            <ball>K6</ball>\r
+            <mode>4</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
+      </muxmode>\r
+      <muxmode>\r
+        <mode>6</mode>\r
+        <signal>vin1b_d2</signal>\r
+        <color>0xbc8f8f</color>\r
+        <virtualmode>\r
+          <mode>\r
+            <value>-1</value>\r
+            <name>NA</name>\r
+          </mode>\r
+          <mode>\r
+            <value>13</value>\r
+            <name>VIP_VIRTUAL4</name>\r
+          </mode>\r
+        </virtualmode>\r
+        <ioset>\r
+          <name>IOSET7</name>\r
           <AssociatedInfo>\r
-            <signal>vin2a_clk0</signal>\r
-            <ball>P4</ball>\r
-            <mode>4</mode>\r
+            <signal>vin1b_clk1</signal>\r
+            <ball>N9</ball>\r
+            <mode>6</mode>\r
           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_hsync0</signal>\r
-            <ball>P7</ball>\r
-            <mode>4</mode>\r
+            <signal>vin1b_hsync1</signal>\r
+            <ball>N7</ball>\r
+            <mode>6</mode>\r
           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_vsync0</signal>\r
-            <ball>N1</ball>\r
-            <mode>4</mode>\r
+            <signal>vin1b_vsync1</signal>\r
+            <ball>R4</ball>\r
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           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_fld0</signal>\r
-            <ball>J7</ball>\r
-            <mode>4</mode>\r
+            <signal>vin1b_fld1</signal>\r
+            <ball>P4</ball>\r
+            <mode>6</mode>\r
           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_de0</signal>\r
-            <ball>H6</ball>\r
-            <mode>4</mode>\r
+            <signal>vin1b_de1</signal>\r
+            <ball>P9</ball>\r
+            <mode>6</mode>\r
           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_d0</signal>\r
+            <signal>vin1b_d0</signal>\r
             <ball>R6</ball>\r
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+            <mode>6</mode>\r
           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_d1</signal>\r
+            <signal>vin1b_d1</signal>\r
             <ball>T9</ball>\r
-            <mode>4</mode>\r
+            <mode>6</mode>\r
           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_d3</signal>\r
+            <signal>vin1b_d3</signal>\r
             <ball>T7</ball>\r
-            <mode>4</mode>\r
+            <mode>6</mode>\r
           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_d4</signal>\r
+            <signal>vin1b_d4</signal>\r
             <ball>P6</ball>\r
-            <mode>4</mode>\r
+            <mode>6</mode>\r
           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_d5</signal>\r
+            <signal>vin1b_d5</signal>\r
             <ball>R9</ball>\r
-            <mode>4</mode>\r
+            <mode>6</mode>\r
           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_d6</signal>\r
+            <signal>vin1b_d6</signal>\r
             <ball>R5</ball>\r
-            <mode>4</mode>\r
+            <mode>6</mode>\r
           </AssociatedInfo>\r
           <AssociatedInfo>\r
-            <signal>vin2a_d7</signal>\r
+            <signal>vin1b_d7</signal>\r
             <ball>P5</ball>\r
-            <mode>4</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vin2a_d8</signal>\r
-            <ball>U2</ball>\r
-            <mode>4</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vin2a_d9</signal>\r
-            <ball>U1</ball>\r
-            <mode>4</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vin2a_d10</signal>\r
-            <ball>P3</ball>\r
-            <mode>4</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vin2a_d11</signal>\r
-            <ball>R2</ball>\r
-            <mode>4</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vin2a_d12</signal>\r
-            <ball>K7</ball>\r
-            <mode>4</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vin2a_d13</signal>\r
-            <ball>M7</ball>\r
-            <mode>4</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vin2a_d14</signal>\r
-            <ball>J5</ball>\r
-            <mode>4</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vin2a_d15</signal>\r
-            <ball>K6</ball>\r
-            <mode>4</mode>\r
+            <mode>6</mode>\r
           </AssociatedInfo>\r
         </ioset>\r
       </muxmode>\r
-      <muxmode>\r
-        <mode>6</mode>\r
-        <signal>vin1b_d2</signal>\r
-        <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
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-          <mode>\r
-            <value>13</value>\r
-            <name>VIP_VIRTUAL4</name>\r
-          </mode>\r
-        </virtualmode>\r
-      </muxmode>\r
       <muxmode>\r
         <mode>7</mode>\r
         <signal>uart7_rxd</signal>\r
         <mode>4</mode>\r
         <signal>vin2a_d3</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>11</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
             <name>VIP_VIRTUAL4</name>\r
           </mode>\r
         </virtualmode>\r
+        <ioset>\r
+          <name>IOSET7</name>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_clk1</signal>\r
+            <ball>N9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_hsync1</signal>\r
+            <ball>N7</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_vsync1</signal>\r
+            <ball>R4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_fld1</signal>\r
+            <ball>P4</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_de1</signal>\r
+            <ball>P9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d0</signal>\r
+            <ball>R6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d1</signal>\r
+            <ball>T9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d2</signal>\r
+            <ball>T6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d4</signal>\r
+            <ball>P6</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d5</signal>\r
+            <ball>R9</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d6</signal>\r
+            <ball>R5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+          <AssociatedInfo>\r
+            <signal>vin1b_d7</signal>\r
+            <ball>P5</ball>\r
+            <mode>6</mode>\r
+          </AssociatedInfo>\r
+        </ioset>\r
       </muxmode>\r
       <muxmode>\r
         <mode>7</mode>\r
         <mode>4</mode>\r
         <signal>vin2a_vsync0</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>12</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET8</name>\r
           <AssociatedInfo>\r
         <mode>8</mode>\r
         <signal>vin2a_d15</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP2_AXR7_IN</name>\r
         <mode>8</mode>\r
         <signal>vin2a_d23</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>4</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <manualmode>\r
           <cfgreg>\r
             <name>CFG_MCASP5_AXR1_IN</name>\r
         <mode>3</mode>\r
         <signal>vin2a_d11</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d9</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>3</mode>\r
         <signal>vin2a_d10</signal>\r
         <color>0xbc8f8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>VIP_VIRTUAL3</name>\r
-          </mode>\r
-        </virtualmode>\r
         <ioset>\r
           <name>IOSET7</name>\r
           <AssociatedInfo>\r
         <mode>14</mode>\r
         <signal>gpio4_11</signal>\r
         <color>0x8fbc8f</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
-            <name>NA</name>\r
-          </mode>\r
-          <mode>\r
-            <value>9</value>\r
-            <name>GPMC_VIRTUAL1</name>\r
-          </mode>\r
-        </virtualmode>\r
       </muxmode>\r
       <muxmode>\r
         <mode>15</mode>\r
     </pad>\r
   </type>\r
 </clockNode>\r
-
 \r
 <!-- END REGULAR PADCONF blocks -->\r
 \r
similarity index 96%
rename from XMLFiles/DRA72x/model_DRA72x_SR2.0_v1.0.7.xml
rename to XMLFiles/DRA72x/model_DRA72x_SR2.0_v1.0.9.xml
index 6f284ed196a53dfb23f5e0ff0bd2f2331517251b..1bc40251c410d12ffd23f6f697c5c6baca2081f5 100644 (file)
 <?xml version="1.0" encoding="US-ASCII"?>\r
 <SoC>\r
 <projectName>DRA72x_SR2.0</projectName>\r
-<versionNumber>1.0.7</versionNumber>\r
+<versionNumber>1.0.9</versionNumber>\r
 <padDB>\r
 \r
 <!-- START REGULAR PADCONF blocks -->\r
 \r
-
-<clockNode>\r
-  <name>spi1_d0</name>\r
-  <type>\r
-    <pad>\r
-      <ballname>B25</ballname>\r
-      <dir>IO</dir>\r
-      <numberOfMuxmodes>16</numberOfMuxmodes>\r
-      <muxmode>\r
-        <mode>0</mode>\r
-        <signal>spi1_d0</signal>\r
-        <color>0x3cb371</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>14</mode>\r
-        <signal>gpio7_9</signal>\r
-        <color>0x8fbc8f</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>15</mode>\r
-        <signal>Driveroff</signal>\r
-        <color>0xf0fff0</color>\r
-      </muxmode>\r
-      <confregisters>\r
-        <regbit>\r
-          <register>CTRL_CORE_PAD_SPI1_D0</register>\r
-        </regbit>\r
-      </confregisters>\r
-    </pad>\r
-  </type>\r
-</clockNode>\r
-<clockNode>\r
-  <name>dcan1_tx</name>\r
-  <type>\r
-    <pad>\r
-      <ballname>G20</ballname>\r
-      <dir>IO</dir>\r
-      <numberOfMuxmodes>16</numberOfMuxmodes>\r
-      <muxmode>\r
-        <mode>0</mode>\r
-        <signal>dcan1_tx</signal>\r
-        <color>0xff0000</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>2</mode>\r
-        <signal>uart8_rxd</signal>\r
-        <color>0xffa500</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>3</mode>\r
-        <signal>mmc2_sdcd</signal>\r
-        <color>0xff6347</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>6</mode>\r
-        <signal>hdmi1_hpd</signal>\r
-        <color>0xa52a2a</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>14</mode>\r
-        <signal>gpio1_14</signal>\r
-        <color>0x8fbc8f</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>15</mode>\r
-        <signal>Driveroff</signal>\r
-        <color>0xf0fff0</color>\r
-      </muxmode>\r
-      <confregisters>\r
-        <regbit>\r
-          <register>CTRL_CORE_PAD_DCAN1_TX</register>\r
-        </regbit>\r
-      </confregisters>\r
-    </pad>\r
-  </type>\r
-</clockNode>\r
-<clockNode>\r
-  <name>emu0</name>\r
-  <type>\r
-    <pad>\r
-      <ballname>G21</ballname>\r
-      <dir>IO</dir>\r
-      <numberOfMuxmodes>16</numberOfMuxmodes>\r
-      <muxmode>\r
-        <mode>0</mode>\r
-        <signal>emu0</signal>\r
-        <color>0x778899</color>\r
-        <ioset>\r
-          <name>IOSET2</name>\r
-          <AssociatedInfo>\r
-            <signal>emu19</signal>\r
-            <ball>A10</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu18</signal>\r
-            <ball>B9</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu17</signal>\r
-            <ball>A9</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu16</signal>\r
-            <ball>C9</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu15</signal>\r
-            <ball>A8</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu14</signal>\r
-            <ball>C7</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu13</signal>\r
-            <ball>C8</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu12</signal>\r
-            <ball>C6</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu11</signal>\r
-            <ball>A5</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu10</signal>\r
-            <ball>D8</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu9</signal>\r
-            <ball>E7</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu8</signal>\r
-            <ball>F8</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu7</signal>\r
-            <ball>F9</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu6</signal>\r
-            <ball>E9</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu5</signal>\r
-            <ball>G11</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu4</signal>\r
-            <ball>A7</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu3</signal>\r
-            <ball>D7</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu2</signal>\r
-            <ball>F10</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu1</signal>\r
-            <ball>D24</ball>\r
-            <mode>0</mode>\r
-          </AssociatedInfo>\r
-        </ioset>\r
-        <ioset>\r
-          <name>IOSET1</name>\r
-          <AssociatedInfo>\r
-            <signal>emu19</signal>\r
-            <ball>E6</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu18</signal>\r
-            <ball>F5</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu17</signal>\r
-            <ball>E4</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu16</signal>\r
-            <ball>C1</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu15</signal>\r
-            <ball>F4</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu14</signal>\r
-            <ball>D2</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu13</signal>\r
-            <ball>E2</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu12</signal>\r
-            <ball>D1</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu11</signal>\r
-            <ball>F3</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu10</signal>\r
-            <ball>F2</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu9</signal>\r
-            <ball>G6</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu8</signal>\r
-            <ball>G1</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu7</signal>\r
-            <ball>H7</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu6</signal>\r
-            <ball>G2</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu5</signal>\r
-            <ball>E1</ball>\r
-            <mode>5</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu4</signal>\r
-            <ball>A7</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu3</signal>\r
-            <ball>D7</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu2</signal>\r
-            <ball>F10</ball>\r
-            <mode>2</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>emu1</signal>\r
-            <ball>D24</ball>\r
-            <mode>0</mode>\r
-          </AssociatedInfo>\r
-        </ioset>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>14</mode>\r
-        <signal>gpio8_30</signal>\r
-        <color>0x8fbc8f</color>\r
-      </muxmode>\r
-      <confregisters>\r
-        <regbit>\r
-          <register>CTRL_CORE_PAD_EMU0</register>\r
-        </regbit>\r
-      </confregisters>\r
-    </pad>\r
-  </type>\r
-</clockNode>\r
-<clockNode>\r
-  <name>mmc3_dat7</name>\r
-  <type>\r
-    <pad>\r
-      <ballname>AB5</ballname>\r
-      <dir>IO</dir>\r
-      <numberOfMuxmodes>16</numberOfMuxmodes>\r
-      <muxmode>\r
-        <mode>0</mode>\r
-        <signal>mmc3_dat7</signal>\r
-        <color>0xff6347</color>\r
-        <manualmode>\r
-          <cfgreg>\r
-            <name>CFG_MMC3_DAT7_IN</name>\r
-            <mode>\r
-              <adelay>-1</adelay>\r
-              <gdelay>-1</gdelay>\r
-              <name>NA</name>\r
-            </mode>\r
-            <mode>\r
-              <adelay>0</adelay>\r
-              <gdelay>0</gdelay>\r
-              <name>MMC3_MANUAL1</name>\r
-            </mode>\r
-          </cfgreg>\r
-        </manualmode>\r
-        <manualmode>\r
-          <cfgreg>\r
-            <name>CFG_MMC3_DAT7_OEN</name>\r
-            <mode>\r
-              <adelay>-1</adelay>\r
-              <gdelay>-1</gdelay>\r
-              <name>NA</name>\r
-            </mode>\r
-            <mode>\r
-              <adelay>344</adelay>\r
-              <gdelay>0</gdelay>\r
-              <name>MMC3_MANUAL1</name>\r
-            </mode>\r
-          </cfgreg>\r
-        </manualmode>\r
-        <manualmode>\r
-          <cfgreg>\r
-            <name>CFG_MMC3_DAT7_OUT</name>\r
-            <mode>\r
-              <adelay>-1</adelay>\r
-              <gdelay>-1</gdelay>\r
-              <name>NA</name>\r
-            </mode>\r
-            <mode>\r
-              <adelay>0</adelay>\r
-              <gdelay>0</gdelay>\r
-              <name>MMC3_MANUAL1</name>\r
-            </mode>\r
-          </cfgreg>\r
-        </manualmode>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>1</mode>\r
-        <signal>spi4_cs0</signal>\r
-        <color>0x3cb371</color>\r
-        <ioset>\r
-          <name>IOSET5</name>\r
-          <AssociatedInfo>\r
-            <signal>spi4_cs1</signal>\r
-            <ball>Y1</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>spi4_cs2</signal>\r
-            <ball>W9</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>spi4_cs3</signal>\r
-            <ball>V9</ball>\r
-            <mode>8</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
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-            <ball>A17</ball>\r
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-            <ball>C18</ball>\r
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-            <ball>G16</ball>\r
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-          <AssociatedInfo>\r
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-            <ball>D17</ball>\r
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-            <ball>AA3</ball>\r
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-            <ball>AB9</ball>\r
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-          <AssociatedInfo>\r
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-            <ball>AB3</ball>\r
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-          <AssociatedInfo>\r
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-            <ball>AA4</ball>\r
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-      </muxmode>\r
-      <muxmode>\r
-        <mode>10</mode>\r
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-        <color>0xffd700</color>\r
-      </muxmode>\r
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-        <mode>14</mode>\r
-        <signal>gpio6_16</signal>\r
-        <color>0x8fbc8f</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>15</mode>\r
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-        <color>0xf0fff0</color>\r
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-        <regbit>\r
-          <register>CTRL_CORE_PAD_GPIO6_16</register>\r
-        </regbit>\r
-      </confregisters>\r
-    </pad>\r
-  </type>\r
-</clockNode>\r
-<clockNode>\r
-  <name>gpio6_15</name>\r
-  <type>\r
-    <pad>\r
-      <ballname>F20</ballname>\r
-      <dir>IO</dir>\r
-      <numberOfMuxmodes>16</numberOfMuxmodes>\r
-      <muxmode>\r
-        <mode>0</mode>\r
-        <signal>gpio6_15</signal>\r
-        <color>0x8fbc8f</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>1</mode>\r
-        <signal>mcasp1_axr9</signal>\r
-        <color>0xcd5c5c</color>\r
-        <virtualmode>\r
-          <mode>\r
-            <value>-1</value>\r
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-            <value>14</value>\r
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-          <mode>\r
-            <value>13</value>\r
-            <name>MCASP1_VIRTUAL2_ASYNC_RX</name>\r
-          </mode>\r
-        </virtualmode>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>2</mode>\r
-        <signal>dcan2_rx</signal>\r
-        <color>0xff0000</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>3</mode>\r
-        <signal>uart10_txd</signal>\r
-        <color>0xffa500</color>\r
-      </muxmode>\r
-      <muxmode>\r
-        <mode>6</mode>\r
-        <signal>vout2_vsync</signal>\r
-        <color>0xe9967a</color>\r
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-            <name>CFG_GPIO6_15_OUT</name>\r
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-              <adelay>-1</adelay>\r
-              <gdelay>-1</gdelay>\r
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-            <mode>\r
-              <adelay>1659</adelay>\r
-              <gdelay>0</gdelay>\r
-              <name>VOUT2_IOSET2_MANUAL1</name>\r
-            </mode>\r
-            <mode>\r
-              <adelay>158</adelay>\r
-              <gdelay>0</gdelay>\r
-              <name>VOUT2_IOSET2_MANUAL2</name>\r
-            </mode>\r
-            <mode>\r
-              <adelay>148</adelay>\r
-              <gdelay>0</gdelay>\r
-              <name>VOUT2_IOSET2_MANUAL3</name>\r
-            </mode>\r
-          </cfgreg>\r
-        </manualmode>\r
-        <ioset>\r
-          <name>IOSET2</name>\r
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-            <signal>vout2_d23</signal>\r
-            <ball>AA4</ball>\r
-            <mode>6</mode>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d22</signal>\r
-            <ball>AB3</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d21</signal>\r
-            <ball>AB9</ball>\r
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-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vout2_d20</signal>\r
-            <ball>AA3</ball>\r
-            <mode>6</mode>\r
-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vout2_d19</signal>\r
-            <ball>D17</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d18</signal>\r
-            <ball>G16</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d17</signal>\r
-            <ball>A21</ball>\r
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-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vout2_d16</signal>\r
-            <ball>C18</ball>\r
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-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vout2_d15</signal>\r
-            <ball>A17</ball>\r
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-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vout2_d14</signal>\r
-            <ball>B17</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d13</signal>\r
-            <ball>B16</ball>\r
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-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vout2_d12</signal>\r
-            <ball>D15</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d11</signal>\r
-            <ball>A15</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d10</signal>\r
-            <ball>B15</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d9</signal>\r
-            <ball>A20</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d8</signal>\r
-            <ball>E15</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d7</signal>\r
-            <ball>D12</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d6</signal>\r
-            <ball>C12</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d5</signal>\r
-            <ball>F13</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d4</signal>\r
-            <ball>E12</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d3</signal>\r
-            <ball>J11</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d2</signal>\r
-            <ball>G13</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d1</signal>\r
-            <ball>J14</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_d0</signal>\r
-            <ball>B14</ball>\r
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-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vout2_hsync</signal>\r
-            <ball>E21</ball>\r
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-          </AssociatedInfo>\r
-          <AssociatedInfo>\r
-            <signal>vout2_clk</signal>\r
-            <ball>B26</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_fld</signal>\r
-            <ball>F21</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vout2_de</signal>\r
-            <ball>C23</ball>\r
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-        </ioset>\r
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-            <name>CFG_GPIO6_15_IN</name>\r
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-              <adelay>-1</adelay>\r
-              <gdelay>-1</gdelay>\r
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-              <adelay>1170</adelay>\r
-              <gdelay>240</gdelay>\r
-              <name>VIP_MANUAL1</name>\r
-            </mode>\r
-            <mode>\r
-              <adelay>1522</adelay>\r
-              <gdelay>0</gdelay>\r
-              <name>VIP_MANUAL2</name>\r
-            </mode>\r
-          </cfgreg>\r
-        </manualmode>\r
-        <ioset>\r
-          <name>IOSET10</name>\r
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-            <signal>vin2a_clk0</signal>\r
-            <ball>B26</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vin2a_hsync0</signal>\r
-            <ball>E21</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vin2a_fld0</signal>\r
-            <ball>F21</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vin2a_de0</signal>\r
-            <ball>C23</ball>\r
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-          <AssociatedInfo>\r
-            <signal>vin2a_d0</signal>\r
-            <ball>B14</ball>\r
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-            <signal>vin2a_d1</signal>\r
-            <ball>J14</ball>\r
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-            <ball>J11</ball>\r
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-          <AssociatedInfo>\r
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-            <ball>E12</ball>\r
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-            <signal>vin2a_d5</signal>\r
-            <ball>F13</ball>\r
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-            <ball>C12</ball>\r
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-          <AssociatedInfo>\r
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-          <register>CTRL_CORE_PAD_GPIO6_15</register>\r
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-      </confregisters>\r
-    </pad>\r
-  </type>\r
-</clockNode>\r
-<clockNode>\r
-  <name>mcasp4_axr0</name>\r
-  <type>\r
-    <pad>\r
-      <ballname>G16</ballname>\r
-      <dir>IO</dir>\r
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-          <mode>\r
-            <value>-1</value>\r
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-            <value>14</value>\r
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-        </virtualmode>\r
-      </muxmode>\r
-      <muxmode>\r
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-        <color>0x3cb371</color>\r
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-          <name>IOSET4</name>\r
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-            <ball>D17</ball>\r
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-            <signal>spi3_cs1</signal>\r
-            <ball>B11</ball>\r
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-            <signal>spi3_cs2</signal>\r
-            <ball>F11</ball>\r
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-            <signal>spi3_cs3</signal>\r
-            <ball>A10</ball>\r
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-          <AssociatedInfo>\r
-            <signal>spi3_d1</signal>\r
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