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author | Nikhil Devshatwar <nikhil.nd@ti.com> | |
Wed, 10 Feb 2016 11:32:08 +0000 (17:02 +0530) | ||
committer | Nikhil Devshatwar <nikhil.nd@ti.com> | |
Wed, 10 Feb 2016 11:35:54 +0000 (17:05 +0530) |
This has the fixes for the RGMII additional modes
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
XMLFiles/DRA75x_DRA74x/CTRL_MODULE_CORE.xml | patch | blob | history | |
XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR1.1_v1.0.10.xml | [moved from XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR1.1_v1.0.9.xml with 99% similarity] | patch | blob | history |
XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR2.0_v1.0.10.xml | [moved from XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR2.0_v1.0.9.xml with 99% similarity] | patch | blob | history |
iodelay-autogen.py | patch | blob | history |
diff --git a/XMLFiles/DRA75x_DRA74x/CTRL_MODULE_CORE.xml b/XMLFiles/DRA75x_DRA74x/CTRL_MODULE_CORE.xml
index 3b36b279495dbb74c49022805fd6218db4eadc0b..0f51d70b7b3302ae3f702769043e2a5aab492bb1 100755 (executable)
<bitfield id="STD_FUSE_MAC_ID_SW_3" width="25" begin="24" end="0" resetval="0x0" description="This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 1. Bits [23:16] contain the first octet of the MAC address. Bits [15:8] contain the second octet of the MAC address. Bits [7:0] contain the third octet of the MAC address." range="" rwaccess="R"/>\r
</register>\r
<register id="CTRL_CORE_SMA_SW_1" acronym="CTRL_CORE_SMA_SW_1" offset="0x534" width="32" description="OCP Spare Register">\r
- <bitfield id="RESERVED" width="7" begin="31" end="25" resetval="0x0" description="" range="" rwaccess="R"/>\r
+ <bitfield id="RESERVED" width="5" begin="31" end="27" resetval="0x0" description="" range="" rwaccess="R"/>\r
+ <bitfield id="RGMII2_ID_MODE_N" width="1" begin="26" end="26" resetval="0x0" description="Ethernet RGMII port 2 internal delay on transmit (SR2.0) 0x0: Internal delay enabled 0x1: Internal delay disabled" range="" rwaccess="RW"/>\r
+ <bitfield id="RGMII1_ID_MODE_N" width="1" begin="25" end="25" resetval="0x0" description="Ethernet RGMII port 1 internal delay on transmit (SR2.0) 0x0: Internal delay enabled 0x1: Internal delay disabled" range="" rwaccess="RW"/>\r
<bitfield id="DSS_CH2_ON_OFF" width="1" begin="24" end="24" resetval="0x0" description="DSS Channel 2 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH2_RF" range="" rwaccess="RW"/>\r
<bitfield id="DSS_CH1_ON_OFF" width="1" begin="23" end="23" resetval="0x0" description="DSS Channel 1 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH1_RF" range="" rwaccess="RW"/>\r
<bitfield id="DSS_CH0_ON_OFF" width="1" begin="22" end="22" resetval="0x0" description="DSS Channel 0 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH0_RF" range="" rwaccess="RW"/>\r
</register>\r
<register id="CTRL_CORE_PCIE_CONTROL" acronym="CTRL_CORE_PCIE_CONTROL" offset="0x1C3C" width="32" description="serdes control selection PCIE C0 (0 default) vs PCIE B1 (1)">\r
<bitfield id="RESERVED" width="29" begin="31" end="3" resetval="0x0" description="" range="" rwaccess="R"/>\r
- <bitfield id="PCIE_B1C0_MODE_SEL" width="1" begin="2" end="2" resetval="0x0" description="" range="" rwaccess="RW"/>\r
+ <bitfield id="PCIE_B1C0_MODE_SEL" width="1" begin="2" end="2" resetval="0x0" description="0x0: PCIESS1 x1 Mode and/or PCIESS2 x1 Mode0x1: PCIESS1 x2 Mode, PCIESS2 Unused" range="" rwaccess="RW"/>\r
<bitfield id="RESERVED" width="1" begin="1" end="1" resetval="0x0" description="" range="" rwaccess="R"/>\r
- <bitfield id="PCIE_B0_B1_TSYNCEN" width="1" begin="0" end="0" resetval="0x0" description="" range="" rwaccess="RW"/>\r
+ <bitfield id="PCIE_B0_B1_TSYNCEN" width="1" begin="0" end="0" resetval="0x0" description="0x0: PCIESS1 x1 Mode and/or PCIESS2 x1 Mode0x1: PCIESS1 x2 Mode, PCIESS2 Unused" range="" rwaccess="RW"/>\r
</register>\r
<register id="CTRL_CORE_PHY_POWER_PCIESS1" acronym="CTRL_CORE_PHY_POWER_PCIESS1" offset="0x1C40" width="32" description="">\r
<bitfield id="PCIESS1_PWRCTL_CLKFREQ" width="10" begin="31" end="22" resetval="0x0" description="Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." range="" rwaccess="RW"/>\r
diff --git a/XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR1.1_v1.0.9.xml b/XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR1.1_v1.0.10.xml
similarity index 99%
rename from XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR1.1_v1.0.9.xml
rename to XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR1.1_v1.0.10.xml
index 74298ed168c7a5d1fc1f24f740c23b66f95a2475..c0244a24e1abdc068105118c95cb36ce902efe7a 100644 (file)
rename from XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR1.1_v1.0.9.xml
rename to XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR1.1_v1.0.10.xml
index 74298ed168c7a5d1fc1f24f740c23b66f95a2475..c0244a24e1abdc068105118c95cb36ce902efe7a 100644 (file)
<?xml version="1.0" encoding="US-ASCII"?>\r
<SoC>\r
<projectName>DRA75x_DRA74x_SR1.1</projectName>\r
-<versionNumber>1.0.9</versionNumber>\r
+<versionNumber>1.0.10</versionNumber>\r
<padDB>\r
\r
<!-- START REGULAR PADCONF blocks -->\r
+
<clockNode>
<name>spi1_d0</name>
<type>
<gdelay>180</gdelay>
<name>GMAC_RMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>7000</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<mode>1</mode>
<signal>rmii0_txd0</signal>
<color>0x2e8b57</color>
- <manualmode>
- <cfgreg>
- <name>CFG_RGMII0_RXD0_OUT</name>
- <mode>
- <adelay>-1</adelay>
- <gdelay>-1</gdelay>
- <name>NA</name>
- </mode>
- <mode>
- <adelay>5400</adelay>
- <gdelay>4000</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
- </cfgreg>
- </manualmode>
<ioset>
<name>IOSET2</name>
<AssociatedInfo>
<gdelay>0</gdelay>
<name>GMAC_RMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>7000</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>0</gdelay>
<name>GMAC_RMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>7000</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>0</gdelay>
<name>GMAC_RMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>0</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
<mode>
<adelay>0</adelay>
<gdelay>0</gdelay>
</mode>
</cfgreg>
</manualmode>
- <manualmode>
- <cfgreg>
- <name>CFG_RMII_MHZ_50_CLK_OUT</name>
- <mode>
- <adelay>-1</adelay>
- <gdelay>-1</gdelay>
- <name>NA</name>
- </mode>
- <mode>
- <adelay>2900</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
- </cfgreg>
- </manualmode>
<ioset>
<name>IOSET1</name>
<AssociatedInfo>
<mode>1</mode>
<signal>rmii0_txen</signal>
<color>0x2e8b57</color>
- <manualmode>
- <cfgreg>
- <name>CFG_RGMII0_RXD2_OUT</name>
- <mode>
- <adelay>-1</adelay>
- <gdelay>-1</gdelay>
- <name>NA</name>
- </mode>
- <mode>
- <adelay>5400</adelay>
- <gdelay>4000</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
- </cfgreg>
- </manualmode>
<ioset>
<name>IOSET2</name>
<AssociatedInfo>
<gdelay>0</gdelay>
<name>GMAC_RMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>7000</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<mode>1</mode>
<signal>rmii0_txd1</signal>
<color>0x2e8b57</color>
- <manualmode>
- <cfgreg>
- <name>CFG_RGMII0_RXD1_OUT</name>
- <mode>
- <adelay>-1</adelay>
- <gdelay>-1</gdelay>
- <name>NA</name>
- </mode>
- <mode>
- <adelay>5400</adelay>
- <gdelay>4000</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
- </cfgreg>
- </manualmode>
<ioset>
<name>IOSET2</name>
<AssociatedInfo>
diff --git a/XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR2.0_v1.0.9.xml b/XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR2.0_v1.0.10.xml
similarity index 99%
rename from XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR2.0_v1.0.9.xml
rename to XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR2.0_v1.0.10.xml
index 16d95b59939773276d1524cb9a8cf3dcb71c1e1f..9647808e994ce4806cda6563c3aa619b747f7e52 100644 (file)
rename from XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR2.0_v1.0.9.xml
rename to XMLFiles/DRA75x_DRA74x/model_DRA75x_DRA74x_SR2.0_v1.0.10.xml
index 16d95b59939773276d1524cb9a8cf3dcb71c1e1f..9647808e994ce4806cda6563c3aa619b747f7e52 100644 (file)
<?xml version="1.0" encoding="US-ASCII"?>\r
<SoC>\r
<projectName>DRA75x_DRA74x_SR2.0</projectName>\r
-<versionNumber>1.0.9</versionNumber>\r
+<versionNumber>1.0.10</versionNumber>\r
<padDB>\r
\r
<!-- START REGULAR PADCONF blocks -->\r
+
<clockNode>
<name>spi1_d0</name>
<type>
<gdelay>70</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>0</adelay>
- <gdelay>70</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>1000</gdelay>
<name>GMAC_RMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>7000</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>1919</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>4</adelay>
- <gdelay>1601</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>70</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>35</adelay>
- <gdelay>70</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>1450</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>138</adelay>
- <gdelay>1078</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>1269</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>153</adelay>
- <gdelay>896</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>1688</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>63</adelay>
- <gdelay>1329</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<mode>1</mode>
<signal>rmii0_txd0</signal>
<color>0x2e8b57</color>
- <manualmode>
- <cfgreg>
- <name>CFG_RGMII0_RXD0_OUT</name>
- <mode>
- <adelay>-1</adelay>
- <gdelay>-1</gdelay>
- <name>NA</name>
- </mode>
- <mode>
- <adelay>5400</adelay>
- <gdelay>4000</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
- </cfgreg>
- </manualmode>
<ioset>
<name>IOSET2</name>
<AssociatedInfo>
<gdelay>70</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>0</adelay>
- <gdelay>70</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>70</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>70</adelay>
- <gdelay>70</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>0</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>2131</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>0</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>0</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>840</gdelay>
<name>GMAC_RMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>7000</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>70</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>100</adelay>
- <gdelay>130</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>500</gdelay>
<name>GMAC_RMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>7000</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>0</gdelay>
<name>GMAC_RMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>0</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
<mode>
<adelay>0</adelay>
<gdelay>0</gdelay>
</mode>
</cfgreg>
</manualmode>
- <manualmode>
- <cfgreg>
- <name>CFG_RMII_MHZ_50_CLK_OUT</name>
- <mode>
- <adelay>-1</adelay>
- <gdelay>-1</gdelay>
- <name>NA</name>
- </mode>
- <mode>
- <adelay>2900</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
- </cfgreg>
- </manualmode>
<ioset>
<name>IOSET1</name>
<AssociatedInfo>
<gdelay>70</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>0</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>70</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>90</adelay>
- <gdelay>70</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>0</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>2199</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>70</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>0</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>1804</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>75</adelay>
- <gdelay>1395</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>927</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>2</adelay>
- <gdelay>571</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>1703</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>0</adelay>
- <gdelay>1298</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<mode>1</mode>
<signal>rmii0_txen</signal>
<color>0x2e8b57</color>
- <manualmode>
- <cfgreg>
- <name>CFG_RGMII0_RXD2_OUT</name>
- <mode>
- <adelay>-1</adelay>
- <gdelay>-1</gdelay>
- <name>NA</name>
- </mode>
- <mode>
- <adelay>5400</adelay>
- <gdelay>4000</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
- </cfgreg>
- </manualmode>
<ioset>
<name>IOSET2</name>
<AssociatedInfo>
<gdelay>1330</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>0</adelay>
- <gdelay>967</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>70</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>100</adelay>
- <gdelay>130</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>1000</gdelay>
<name>GMAC_RMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>7000</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>1697</gdelay>
<name>GMAC_RGMII0_MANUAL1</name>
</mode>
- <mode>
- <adelay>90</adelay>
- <gdelay>1320</gdelay>
- <name>GMAC_RGMII0_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<mode>1</mode>
<signal>rmii0_txd1</signal>
<color>0x2e8b57</color>
- <manualmode>
- <cfgreg>
- <name>CFG_RGMII0_RXD1_OUT</name>
- <mode>
- <adelay>-1</adelay>
- <gdelay>-1</gdelay>
- <name>NA</name>
- </mode>
- <mode>
- <adelay>5400</adelay>
- <gdelay>4000</gdelay>
- <name>GMAC_RMII0_MANUAL2</name>
- </mode>
- </cfgreg>
- </manualmode>
<ioset>
<name>IOSET2</name>
<AssociatedInfo>
<gdelay>1340</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>145</adelay>
- <gdelay>968</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>0</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>0</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
<gdelay>70</gdelay>
<name>GMAC_RGMII1_MANUAL1</name>
</mode>
- <mode>
- <adelay>140</adelay>
- <gdelay>0</gdelay>
- <name>GMAC_RGMII1_MANUAL2</name>
- </mode>
</cfgreg>
</manualmode>
<ioset>
</type>
</clockNode>
+
<!-- END REGULAR PADCONF blocks -->
diff --git a/iodelay-autogen.py b/iodelay-autogen.py
index 1f48e6ad3659eda3a05bac12557027b1af7bbc5d..29f6f6ae1f8bde2ce4a61b887b6acbf08fdfdaf2 100755 (executable)
--- a/iodelay-autogen.py
+++ b/iodelay-autogen.py
if (args.part == "dra74x" or args.part == "dra75x"):
XML_PATH = "XMLFiles/DRA75x_DRA74x"
PART = "DRA75x_DRA74x"
- PCT_VERSION = "v1.0.9"
+ PCT_VERSION = "v1.0.10"
elif (args.part == "dra72x"):
XML_PATH = "XMLFiles/DRA72x"
PART = "DRA72x"