summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 3bc571a)
raw | patch | inline | side by side (parent: 3bc571a)
author | Nikhil Devshatwar <nikhil.nd@ti.com> | |
Fri, 6 Nov 2015 09:51:53 +0000 (15:21 +0530) | ||
committer | Nikhil Devshatwar <nikhil.nd@ti.com> | |
Fri, 6 Nov 2015 10:03:07 +0000 (15:33 +0530) |
Different parts may have virtual/manual modes with the same name.
It's better to use a different guideline so as to avoid conflicts.
Also, fix an RE regarding the parsing to handle extra columns.
Add the guidelines.txt for the DRA72 part.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
It's better to use a different guideline so as to avoid conflicts.
Also, fix an RE regarding the parsing to handle extra columns.
Add the guidelines.txt for the DRA72 part.
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
XMLFiles/DRA72x/guidelines.txt | [new file with mode: 0644] | patch | blob |
XMLFiles/DRA75x_DRA74x/guidelines.txt | [moved from guidelines.txt with 100% similarity] | patch | blob | history |
iodelay-autogen.py | patch | blob | history | |
selected-modes.txt | patch | blob | history |
diff --git a/XMLFiles/DRA72x/guidelines.txt b/XMLFiles/DRA72x/guidelines.txt
--- /dev/null
@@ -0,0 +1,92 @@
+========================== Guildelines for selecting mode ==========================
+Following are the guidelines for selecting a specific virtual/manual mode
+DO NOT CHANGE ANYTHING HERE. USE ONLY THE CORRECT MODE NAME IN THE ABOVE LIST
+
+========================== DPI Video Output ==========================
+No Virtual or Manual IO Timing DPI1/2/3 Video Output Default Timings - Rising-edge Clock Reference
+DSS_VIRTUAL1 DPI1/2/3 Video Output Default Timings - Falling-edge Clock Reference
+VOUT1_MANUAL1 DPI1 Video Output Alternate Timings VOUT1_SAME_EDGE
+VOUT2_IOSET1_MANUAL1 DPI2 Video Output IOSET1 Alternate Timings VOUT2a_SAME_EDGE
+VOUT2_IOSET2_MANUAL1 DPI2 Video Output IOSET2 Alternate Timings VOUT2b_SAME_EDGE
+VOUT3_MANUAL1 DPI3 Video Output Alternate Timings VOUT3_SAME_EDGE
+========================== GPMC ==========================
+No Virtual or Manual IO Timing GPMC Asyncronous Mode Timings and Synchronous Mode - 1 Load Timings
+GPMC_VIRTUAL1 GPMC Synchronous Mode - 5 Load Timings
+========================== McASP ==========================
+No Virtual or Manual IO Timing McASP1 Asynchronous and Synchronous Transmit Timings
+MCASP1_VIRTUAL2_SYNC_RX McASP1 Synchronous Receive Timings
+MCASP1_VIRTUAL3_ASYNC_RX McASP1 Asynchronous Receive Timings
+No Virtual or Manual IO Timing McASP2 Asynchronous and Synchronous Transmit Timings
+MCASP2_VIRTUAL1_ASYNC_RX_80M McASP2 Asynchronous Receive Timings when ACLKx, AFSX, and AXR are all inputs
+MCASP2_VIRTUAL2_ASYNC_RX McASP2 Asynchronous Receive Timings
+MCASP2_VIRTUAL4_SYNC_RX McASP2 Synchronous Receive Timings
+MCASP2_VIRTUAL5_SYNC_RX_80M McASP2 Synchronous Receive Timings when ACLKx, AFSX, and AXR are all inputs
+No Virtual or Manual IO Timing McASP3 Synchronous Transmit Timings
+MCASP3_VIRTUAL2_SYNC_RX McASP3 Synchronous Receive Timings
+No Virtual or Manual IO Timing McASP4 Synchronous Transmit Timings
+MCASP4_VIRTUAL1_SYNC_RX McASP4 Synchronous Receive Timings
+No Virtual or Manual IO Timing McASP5 Synchronous Transmit Timings
+MCASP5_VIRTUAL1_SYNC_RX McASP5 Synchronous Receive Timings
+No Virtual or Manual IO Timing McASP6 Synchronous Transmit Timings
+MCASP6_VIRTUAL1_SYNC_RX McASP6 Synchronous Receive Timings
+No Virtual or Manual IO Timing McASP7 Synchronous Transmit Timings
+MCASP7_VIRTUAL2_SYNC_RX McASP7 Synchronous Receive Timings
+No Virtual or Manual IO Timing McASP8 Synchronous Transmit Timings
+MCASP8_VIRTUAL1_SYNC_RX McASP8 Synchronous Receive Timings
+========================== eMMC/SD/SDIO ==========================
+No Virtual or Manual IO Timing MMC1 DS (Pad Loopback), HS (Internal Loopback and Pad Loopback), SDR12 (Internal Loopback and Pad Loopback), and SDR25 Timings (Internal Loopback and Pad Loopback) Timings
+MMC1_VIRTUAL1 MMC1 SDR50 (Pad Loopback) Timings
+MMC1_VIRTUAL4 MMC1 DS (Internal Loopback) Timings
+MMC1_VIRTUAL5 MMC1 SDR50 (Internal Loopback) Timings
+MMC1_VIRTUAL6 MMC1 DDR50 (Internal Loopback) Timings
+MMC1_MANUAL1 MMC1 DDR50 (Pad Loopback) Timings MMC1_DDR_in, MMC1_DDR_out
+MMC1_MANUAL2 MMC1 SDR104 Timings MMC1_SDR104
+No Virtual or Manual IO Timing MMC2 Standard (Pad Loopback), High Speed (Pad Loopback) Timings
+MMC2_VIRTUAL2 MMC2 Standard (Internal Loopback), High Speed (Internal Loopback)
+MMC2_MANUAL1 MMC2 DDR (Pad Loopback) Timings MMC2_DDR_in, MMC2_DDR_out
+MMC2_MANUAL2 MMC2 DDR (Internal Loopback) Timings MMC2_DDR_LB_in, MMC2_DDR_LB_out
+MMC2_MANUAL3 MMC2 HS200 Timings MMC2_HS200
+No Virtual or Manual IO Timing MMC3 DS, SDR12, HS, SDR25 Timings
+MMC3_MANUAL1 MMC3 SDR50 Timings MMC3_SDR50
+No Virtual or Manual IO Timing MMC4 DS, SDR12, HS, SDR25 Timings
+========================== QSPI ==========================
+No Virtual or Manual IO Timing QSPI Mode 3 Default Timing Mode
+QSPI1_VIRTUAL1 QSPI Mode 3 Alternate Timing Mode 1
+QSPI1_VIRTUAL2 QSPI Mode 3 Alternate Timing Mode 2
+QSPI1_MANUAL1 QSPI Mode 0 Timing Mode QSPI_DEFAULT
+========================== GMAC ==========================
+No Virtual or Manual IO Timing GMAC MII0/1 and RMII0/RMII1 Timings
+GMAC_RGMII0_MANUAL1 GMAC RGMII0 with Transmit Clock Internal Delay Enabled EMAC_RGMII1_in, EMAC_RGMII1_out
+GMAC_RGMII1_MANUAL1 GMAC RGMII1 with Transmit Clock Internal Delay Enabled EMAC_RGMII2_in, EMAC_RGMII2_out
+GMAC_RGMII0_MANUAL2 GMAC RGMII0 with Transmit Clock Internal Delay Disabled EMAC_RGMII1_in, EMAC_RGMII1_2_out
+GMAC_RGMII1_MANUAL2 GMAC RGMII1 with Transmit Clock Internal Delay Disabled EMAC_RGMII2_in, EMAC_RGMII2_2_out
+GMAC_RMII0_MANUAL1 GMAC RMII0 Timings EMAC_RMII1_in
+GMAC_RMII1_MANUAL1 GMAC RMII1 Timings EMAC_RMII2_in
+========================== VIP ==========================
+No Virtual or Manual IO Timing All VIP Modes not covered below
+VIP_VIRTUAL1 VIN2B (IOSET7, IOSET8, IOSET9) Fall-Edge Capture Mode Timings
+VIP_VIRTUAL2 VIN2A (IOSET4, IOSET5, IOSET6) Fall-Edge Capture Mode Timings
+VIP_VIRTUAL3 VIN1A (IOSET5, IOSET6, IOSET7) Fall-Edge Capture Mode Timings
+VIP_VIRTUAL4 VIN1B (IOSET6) Fall-Edge Capture Mode Timings
+VIP_VIRTUAL5 VIN1B (IOSET5) and VIN2B (IOSET2) Rise-Edge Capture Mode Timings
+VIP_VIRTUAL6 VIN1A (IOSET2, IOSET3, IOSET4) and VIN1B (IOSET4) Fall-Edge Capture Mode Timings
+VIP_VIRTUAL7 VIN1B (IOSET5) and VIN2B (IOSET2) Fall-Edge Capture Mode Timings
+VIP_VIRTUAL8 VIN1A (IOSET8, IOSET9) Fall-Edge Capture Mode Timings
+========================== PRU-ICSS (only include in AM Data Manual) ==========================
+No Virtual or Manual IO Timing All PRU_ICSS Modes not covered below
+PRU_ICSS1_IN_VIRTUAL1 PRU-ICSS1 Direct Input Mode Timings
+PRU_ICSS1_OUT_VIRTUAL1 PRU-ICSS1 Direct Output Mode Timings
+PRU_ICSS2_IN_VIRTUAL1 PRU-ICSS2 Direct Input Mode Timings
+PRU_ICSS2_OUT_VIRTUAL1 PRU-ICSS2 Direct Output Mode Timings
+PR1_PRU1_DIR_IN_MANUAL PRU-ICSS1 PRU1 Direct Input Mode Timings PR1_PRU1_DIR_IN
+PR1_PRU1_DIR_OUT_MANUAL PRU-ICSS1 PRU1 Direct Output Mode Timings PR1_PRU1_DIR_OUT
+PR2_PRU0_DIR_IN_MANUAL1 PRU-ICSS2 PRU0 IOSET1 Direct Input Mode Timings PR2_PRU0_DIR_IN-IOSET1
+PR2_PRU0_DIR_IN_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Direct Input Mode Timings PR2_PRU0_DIR_IN-IOSET2
+PR2_PRU0_DIR_OUT_MANUAL1 PRU-ICSS2 PRU0 IOSET1 Direct Output Mode Timings PR2_PRU0_DIR_OUT-IOSET1
+PR2_PRU0_DIR_OUT_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Direct Output Mode Timings PR2_PRU0_DIR_OUT-IOSET2
+PR2_PRU1_DIR_IN_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Direct Input Mode Timings PR2_PRU1_DIR_IN-IOSET1
+PR2_PRU1_DIR_IN_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Direct Input Mode Timings PR2_PRU1_DIR_IN-IOSET2
+PR2_PRU1_DIR_OUT_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Direct Output Mode Timings PR2_PRU1_DIR_OUT-IOSET1
+PR2_PRU1_DIR_OUT_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Direct Output Mode Timings PR2_PRU1_DIR_OUT-IOSET2
+========================== HDMI, EMIF, Timers, I2C, HDQ/1-Wire, UART, McSPI, USB, SATA, PCIe, DCAN, GPIO, KBD, PWM, ATL, JTAG, TPIU, RTC, SDMA, INTC, MLB ==========================
+No Virtual or Manual IO Timing All Modes
diff --git a/iodelay-autogen.py b/iodelay-autogen.py
index a79dfd5694d1e1ae839f447203fa6996aa00d708..7f50fed8f5e69d074474b7a7d011d6e11cf102fa 100755 (executable)
--- a/iodelay-autogen.py
+++ b/iodelay-autogen.py
pad_data_xml = XML_PATH + "/CTRL_MODULE_CORE.xml"
iod_data_xml = XML_PATH + "/IODELAYCONFIG.xml"
model_data_xml = XML_PATH + "/model_" + PART + "_SR" + args.revision + "_" + PCT_VERSION + ".xml"
+modehelp_file = XML_PATH + "/guidelines.txt"
-modehelp_file = "guidelines.txt"
pad_file = "ctrl-core.dump"
sel_file = "selected-modes.txt"
print "iodelay-autogen.py - Python script to generate the IOdelay data."
print "v" + VERSION + " using PCT version " + PCT_VERSION
+print "Parsing PCT data from " + model_data_xml + "..."
print ""
# Read the XML file database for pad and delay registers
-if (args.debug >= 1):
- print ("Parsing PCT data from " + model_data_xml)
pad_xml = ET.parse(pad_data_xml).getroot()
iod_xml = ET.parse(iod_data_xml).getroot()
model_xml = ET.parse(model_data_xml).getroot()
# Functions to parse the input files and build data structures
def read_guidelines(fname):
modehelp = {}
- pattern = re.compile('(.+\w)\t+(.+)')
+ pattern = re.compile('([^\t.]+\w)\t+(.+)')
f = open(fname)
for line in f.readlines():
list = re.match(pattern, line)
diff --git a/selected-modes.txt b/selected-modes.txt
index 4cf7eaad12a52afb213523df1138edf218047676..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/selected-modes.txt
+++ b/selected-modes.txt
-VIN1A, VIP1_MANUAL1