1 /**
2 * \file drm.h
3 * Header for the Direct Rendering Manager
4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 *
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
9 */
11 /*
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
15 *
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
22 *
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
25 * Software.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
34 */
36 #ifndef _DRM_H_
37 #define _DRM_H_
39 #if defined(__linux__)
41 #include <linux/types.h>
42 #include <asm/ioctl.h>
43 typedef unsigned int drm_handle_t;
45 #else /* One of the BSDs */
47 #include <sys/ioccom.h>
48 #include <sys/types.h>
49 typedef int8_t __s8;
50 typedef uint8_t __u8;
51 typedef int16_t __s16;
52 typedef uint16_t __u16;
53 typedef int32_t __s32;
54 typedef uint32_t __u32;
55 typedef int64_t __s64;
56 typedef uint64_t __u64;
57 typedef unsigned long drm_handle_t;
59 #endif
61 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
62 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
63 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
64 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
66 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
67 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
68 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
69 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
70 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
72 typedef unsigned int drm_context_t;
73 typedef unsigned int drm_drawable_t;
74 typedef unsigned int drm_magic_t;
76 /**
77 * Cliprect.
78 *
79 * \warning: If you change this structure, make sure you change
80 * XF86DRIClipRectRec in the server as well
81 *
82 * \note KW: Actually it's illegal to change either for
83 * backwards-compatibility reasons.
84 */
85 struct drm_clip_rect {
86 unsigned short x1;
87 unsigned short y1;
88 unsigned short x2;
89 unsigned short y2;
90 };
92 /**
93 * Drawable information.
94 */
95 struct drm_drawable_info {
96 unsigned int num_rects;
97 struct drm_clip_rect *rects;
98 };
100 /**
101 * Texture region,
102 */
103 struct drm_tex_region {
104 unsigned char next;
105 unsigned char prev;
106 unsigned char in_use;
107 unsigned char padding;
108 unsigned int age;
109 };
111 /**
112 * Hardware lock.
113 *
114 * The lock structure is a simple cache-line aligned integer. To avoid
115 * processor bus contention on a multiprocessor system, there should not be any
116 * other data stored in the same cache line.
117 */
118 struct drm_hw_lock {
119 __volatile__ unsigned int lock; /**< lock variable */
120 char padding[60]; /**< Pad to cache line */
121 };
123 /**
124 * DRM_IOCTL_VERSION ioctl argument type.
125 *
126 * \sa drmGetVersion().
127 */
128 struct drm_version {
129 int version_major; /**< Major version */
130 int version_minor; /**< Minor version */
131 int version_patchlevel; /**< Patch level */
132 size_t name_len; /**< Length of name buffer */
133 char *name; /**< Name of driver */
134 size_t date_len; /**< Length of date buffer */
135 char *date; /**< User-space buffer to hold date */
136 size_t desc_len; /**< Length of desc buffer */
137 char *desc; /**< User-space buffer to hold desc */
138 };
140 /**
141 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
142 *
143 * \sa drmGetBusid() and drmSetBusId().
144 */
145 struct drm_unique {
146 size_t unique_len; /**< Length of unique */
147 char *unique; /**< Unique name for driver instantiation */
148 };
150 struct drm_list {
151 int count; /**< Length of user-space structures */
152 struct drm_version *version;
153 };
155 struct drm_block {
156 int unused;
157 };
159 /**
160 * DRM_IOCTL_CONTROL ioctl argument type.
161 *
162 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
163 */
164 struct drm_control {
165 enum {
166 DRM_ADD_COMMAND,
167 DRM_RM_COMMAND,
168 DRM_INST_HANDLER,
169 DRM_UNINST_HANDLER
170 } func;
171 int irq;
172 };
174 /**
175 * Type of memory to map.
176 */
177 enum drm_map_type {
178 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
179 _DRM_REGISTERS = 1, /**< no caching, no core dump */
180 _DRM_SHM = 2, /**< shared, cached */
181 _DRM_AGP = 3, /**< AGP/GART */
182 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
183 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
184 _DRM_GEM = 6, /**< GEM object */
185 };
187 /**
188 * Memory mapping flags.
189 */
190 enum drm_map_flags {
191 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
192 _DRM_READ_ONLY = 0x02,
193 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
194 _DRM_KERNEL = 0x08, /**< kernel requires access */
195 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
196 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
197 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
198 _DRM_DRIVER = 0x80 /**< Managed by driver */
199 };
201 struct drm_ctx_priv_map {
202 unsigned int ctx_id; /**< Context requesting private mapping */
203 void *handle; /**< Handle of map */
204 };
206 /**
207 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
208 * argument type.
209 *
210 * \sa drmAddMap().
211 */
212 struct drm_map {
213 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
214 unsigned long size; /**< Requested physical size (bytes) */
215 enum drm_map_type type; /**< Type of memory to map */
216 enum drm_map_flags flags; /**< Flags */
217 void *handle; /**< User-space: "Handle" to pass to mmap() */
218 /**< Kernel-space: kernel-virtual address */
219 int mtrr; /**< MTRR slot used */
220 /* Private data */
221 };
223 /**
224 * DRM_IOCTL_GET_CLIENT ioctl argument type.
225 */
226 struct drm_client {
227 int idx; /**< Which client desired? */
228 int auth; /**< Is client authenticated? */
229 unsigned long pid; /**< Process ID */
230 unsigned long uid; /**< User ID */
231 unsigned long magic; /**< Magic */
232 unsigned long iocs; /**< Ioctl count */
233 };
235 enum drm_stat_type {
236 _DRM_STAT_LOCK,
237 _DRM_STAT_OPENS,
238 _DRM_STAT_CLOSES,
239 _DRM_STAT_IOCTLS,
240 _DRM_STAT_LOCKS,
241 _DRM_STAT_UNLOCKS,
242 _DRM_STAT_VALUE, /**< Generic value */
243 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
244 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
246 _DRM_STAT_IRQ, /**< IRQ */
247 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
248 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
249 _DRM_STAT_DMA, /**< DMA */
250 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
251 _DRM_STAT_MISSED /**< Missed DMA opportunity */
252 /* Add to the *END* of the list */
253 };
255 /**
256 * DRM_IOCTL_GET_STATS ioctl argument type.
257 */
258 struct drm_stats {
259 unsigned long count;
260 struct {
261 unsigned long value;
262 enum drm_stat_type type;
263 } data[15];
264 };
266 /**
267 * Hardware locking flags.
268 */
269 enum drm_lock_flags {
270 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
271 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
272 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
273 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
274 /* These *HALT* flags aren't supported yet
275 -- they will be used to support the
276 full-screen DGA-like mode. */
277 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
278 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
279 };
281 /**
282 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
283 *
284 * \sa drmGetLock() and drmUnlock().
285 */
286 struct drm_lock {
287 int context;
288 enum drm_lock_flags flags;
289 };
291 /**
292 * DMA flags
293 *
294 * \warning
295 * These values \e must match xf86drm.h.
296 *
297 * \sa drm_dma.
298 */
299 enum drm_dma_flags {
300 /* Flags for DMA buffer dispatch */
301 _DRM_DMA_BLOCK = 0x01, /**<
302 * Block until buffer dispatched.
303 *
304 * \note The buffer may not yet have
305 * been processed by the hardware --
306 * getting a hardware lock with the
307 * hardware quiescent will ensure
308 * that the buffer has been
309 * processed.
310 */
311 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
312 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
314 /* Flags for DMA buffer request */
315 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
316 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
317 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
318 };
320 /**
321 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
322 *
323 * \sa drmAddBufs().
324 */
325 struct drm_buf_desc {
326 int count; /**< Number of buffers of this size */
327 int size; /**< Size in bytes */
328 int low_mark; /**< Low water mark */
329 int high_mark; /**< High water mark */
330 enum {
331 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
332 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
333 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
334 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
335 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
336 } flags;
337 unsigned long agp_start; /**<
338 * Start address of where the AGP buffers are
339 * in the AGP aperture
340 */
341 };
343 /**
344 * DRM_IOCTL_INFO_BUFS ioctl argument type.
345 */
346 struct drm_buf_info {
347 int count; /**< Entries in list */
348 struct drm_buf_desc *list;
349 };
351 /**
352 * DRM_IOCTL_FREE_BUFS ioctl argument type.
353 */
354 struct drm_buf_free {
355 int count;
356 int *list;
357 };
359 /**
360 * Buffer information
361 *
362 * \sa drm_buf_map.
363 */
364 struct drm_buf_pub {
365 int idx; /**< Index into the master buffer list */
366 int total; /**< Buffer size */
367 int used; /**< Amount of buffer in use (for DMA) */
368 void *address; /**< Address of buffer */
369 };
371 /**
372 * DRM_IOCTL_MAP_BUFS ioctl argument type.
373 */
374 struct drm_buf_map {
375 int count; /**< Length of the buffer list */
376 #ifdef __cplusplus
377 void *virt;
378 #else
379 void *virtual; /**< Mmap'd area in user-virtual */
380 #endif
381 struct drm_buf_pub *list; /**< Buffer information */
382 };
384 /**
385 * DRM_IOCTL_DMA ioctl argument type.
386 *
387 * Indices here refer to the offset into the buffer list in drm_buf_get.
388 *
389 * \sa drmDMA().
390 */
391 struct drm_dma {
392 int context; /**< Context handle */
393 int send_count; /**< Number of buffers to send */
394 int *send_indices; /**< List of handles to buffers */
395 int *send_sizes; /**< Lengths of data to send */
396 enum drm_dma_flags flags; /**< Flags */
397 int request_count; /**< Number of buffers requested */
398 int request_size; /**< Desired size for buffers */
399 int *request_indices; /**< Buffer information */
400 int *request_sizes;
401 int granted_count; /**< Number of buffers granted */
402 };
404 enum drm_ctx_flags {
405 _DRM_CONTEXT_PRESERVED = 0x01,
406 _DRM_CONTEXT_2DONLY = 0x02
407 };
409 /**
410 * DRM_IOCTL_ADD_CTX ioctl argument type.
411 *
412 * \sa drmCreateContext() and drmDestroyContext().
413 */
414 struct drm_ctx {
415 drm_context_t handle;
416 enum drm_ctx_flags flags;
417 };
419 /**
420 * DRM_IOCTL_RES_CTX ioctl argument type.
421 */
422 struct drm_ctx_res {
423 int count;
424 struct drm_ctx *contexts;
425 };
427 /**
428 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
429 */
430 struct drm_draw {
431 drm_drawable_t handle;
432 };
434 /**
435 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
436 */
437 typedef enum {
438 DRM_DRAWABLE_CLIPRECTS,
439 } drm_drawable_info_type_t;
441 struct drm_update_draw {
442 drm_drawable_t handle;
443 unsigned int type;
444 unsigned int num;
445 unsigned long long data;
446 };
448 /**
449 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
450 */
451 struct drm_auth {
452 drm_magic_t magic;
453 };
455 /**
456 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
457 *
458 * \sa drmGetInterruptFromBusID().
459 */
460 struct drm_irq_busid {
461 int irq; /**< IRQ number */
462 int busnum; /**< bus number */
463 int devnum; /**< device number */
464 int funcnum; /**< function number */
465 };
467 enum drm_vblank_seq_type {
468 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
469 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
470 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
471 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
472 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
473 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
474 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
475 };
477 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
478 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
479 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
481 struct drm_wait_vblank_request {
482 enum drm_vblank_seq_type type;
483 unsigned int sequence;
484 unsigned long signal;
485 };
487 struct drm_wait_vblank_reply {
488 enum drm_vblank_seq_type type;
489 unsigned int sequence;
490 long tval_sec;
491 long tval_usec;
492 };
494 /**
495 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
496 *
497 * \sa drmWaitVBlank().
498 */
499 union drm_wait_vblank {
500 struct drm_wait_vblank_request request;
501 struct drm_wait_vblank_reply reply;
502 };
504 #define _DRM_PRE_MODESET 1
505 #define _DRM_POST_MODESET 2
507 /**
508 * DRM_IOCTL_MODESET_CTL ioctl argument type
509 *
510 * \sa drmModesetCtl().
511 */
512 struct drm_modeset_ctl {
513 __u32 crtc;
514 __u32 cmd;
515 };
517 /**
518 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
519 *
520 * \sa drmAgpEnable().
521 */
522 struct drm_agp_mode {
523 unsigned long mode; /**< AGP mode */
524 };
526 /**
527 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
528 *
529 * \sa drmAgpAlloc() and drmAgpFree().
530 */
531 struct drm_agp_buffer {
532 unsigned long size; /**< In bytes -- will round to page boundary */
533 unsigned long handle; /**< Used for binding / unbinding */
534 unsigned long type; /**< Type of memory to allocate */
535 unsigned long physical; /**< Physical used by i810 */
536 };
538 /**
539 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
540 *
541 * \sa drmAgpBind() and drmAgpUnbind().
542 */
543 struct drm_agp_binding {
544 unsigned long handle; /**< From drm_agp_buffer */
545 unsigned long offset; /**< In bytes -- will round to page boundary */
546 };
548 /**
549 * DRM_IOCTL_AGP_INFO ioctl argument type.
550 *
551 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
552 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
553 * drmAgpVendorId() and drmAgpDeviceId().
554 */
555 struct drm_agp_info {
556 int agp_version_major;
557 int agp_version_minor;
558 unsigned long mode;
559 unsigned long aperture_base; /* physical address */
560 unsigned long aperture_size; /* bytes */
561 unsigned long memory_allowed; /* bytes */
562 unsigned long memory_used;
564 /* PCI information */
565 unsigned short id_vendor;
566 unsigned short id_device;
567 };
569 /**
570 * DRM_IOCTL_SG_ALLOC ioctl argument type.
571 */
572 struct drm_scatter_gather {
573 unsigned long size; /**< In bytes -- will round to page boundary */
574 unsigned long handle; /**< Used for mapping / unmapping */
575 };
577 /**
578 * DRM_IOCTL_SET_VERSION ioctl argument type.
579 */
580 struct drm_set_version {
581 int drm_di_major;
582 int drm_di_minor;
583 int drm_dd_major;
584 int drm_dd_minor;
585 };
587 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */
588 struct drm_gem_close {
589 /** Handle of the object to be closed. */
590 __u32 handle;
591 __u32 pad;
592 };
594 /** DRM_IOCTL_GEM_FLINK ioctl argument type */
595 struct drm_gem_flink {
596 /** Handle for the object being named */
597 __u32 handle;
599 /** Returned global name */
600 __u32 name;
601 };
603 /** DRM_IOCTL_GEM_OPEN ioctl argument type */
604 struct drm_gem_open {
605 /** Name of object being opened */
606 __u32 name;
608 /** Returned handle for the object */
609 __u32 handle;
611 /** Returned size of the object */
612 __u64 size;
613 };
615 /** DRM_IOCTL_GET_CAP ioctl argument type */
616 struct drm_get_cap {
617 __u64 capability;
618 __u64 value;
619 };
621 #define DRM_CLOEXEC O_CLOEXEC
622 struct drm_prime_handle {
623 __u32 handle;
625 /** Flags.. only applicable for handle->fd */
626 __u32 flags;
628 /** Returned dmabuf file descriptor */
629 __s32 fd;
630 };
632 #include "drm_mode.h"
634 #define DRM_IOCTL_BASE 'd'
635 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
636 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
637 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
638 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
640 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
641 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
642 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
643 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
644 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
645 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
646 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
647 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
648 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
649 #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
650 #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
651 #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
652 #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
654 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
655 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
656 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
657 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
658 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
659 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
660 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
661 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
662 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
663 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
664 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
666 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
668 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
669 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
671 #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
672 #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
674 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
675 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
676 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
677 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
678 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
679 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
680 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
681 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
682 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
683 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
684 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
685 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
686 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
688 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
689 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
690 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
691 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
692 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
693 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
694 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
695 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
697 #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
698 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
700 #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
701 #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
703 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
705 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
707 #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
708 #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
709 #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
710 #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
711 #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
712 #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
713 #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
714 #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
715 #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
716 #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
718 #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
719 #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
720 #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
721 #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
722 #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
723 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
724 #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
725 #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
727 #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
728 #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
729 #define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
730 #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
731 #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
732 #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
733 #define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
734 #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
735 #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
737 /**
738 * Device specific ioctls should only be in their respective headers
739 * The device specific ioctl range is from 0x40 to 0x99.
740 * Generic IOCTLS restart at 0xA0.
741 *
742 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
743 * drmCommandReadWrite().
744 */
745 #define DRM_COMMAND_BASE 0x40
746 #define DRM_COMMAND_END 0xA0
748 /**
749 * Header for events written back to userspace on the drm fd. The
750 * type defines the type of event, the length specifies the total
751 * length of the event (including the header), and user_data is
752 * typically a 64 bit value passed with the ioctl that triggered the
753 * event. A read on the drm fd will always only return complete
754 * events, that is, if for example the read buffer is 100 bytes, and
755 * there are two 64 byte events pending, only one will be returned.
756 *
757 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
758 * up are chipset specific.
759 */
760 struct drm_event {
761 __u32 type;
762 __u32 length;
763 };
765 #define DRM_EVENT_VBLANK 0x01
766 #define DRM_EVENT_FLIP_COMPLETE 0x02
768 struct drm_event_vblank {
769 struct drm_event base;
770 __u64 user_data;
771 __u32 tv_sec;
772 __u32 tv_usec;
773 __u32 sequence;
774 __u32 reserved;
775 };
777 #define DRM_CAP_DUMB_BUFFER 0x1
778 #define DRM_CAP_VBLANK_HIGH_CRTC 0x2
779 #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
780 #define DRM_CAP_DUMB_PREFER_SHADOW 0x4
782 /* typedef area */
783 typedef struct drm_clip_rect drm_clip_rect_t;
784 typedef struct drm_drawable_info drm_drawable_info_t;
785 typedef struct drm_tex_region drm_tex_region_t;
786 typedef struct drm_hw_lock drm_hw_lock_t;
787 typedef struct drm_version drm_version_t;
788 typedef struct drm_unique drm_unique_t;
789 typedef struct drm_list drm_list_t;
790 typedef struct drm_block drm_block_t;
791 typedef struct drm_control drm_control_t;
792 typedef enum drm_map_type drm_map_type_t;
793 typedef enum drm_map_flags drm_map_flags_t;
794 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
795 typedef struct drm_map drm_map_t;
796 typedef struct drm_client drm_client_t;
797 typedef enum drm_stat_type drm_stat_type_t;
798 typedef struct drm_stats drm_stats_t;
799 typedef enum drm_lock_flags drm_lock_flags_t;
800 typedef struct drm_lock drm_lock_t;
801 typedef enum drm_dma_flags drm_dma_flags_t;
802 typedef struct drm_buf_desc drm_buf_desc_t;
803 typedef struct drm_buf_info drm_buf_info_t;
804 typedef struct drm_buf_free drm_buf_free_t;
805 typedef struct drm_buf_pub drm_buf_pub_t;
806 typedef struct drm_buf_map drm_buf_map_t;
807 typedef struct drm_dma drm_dma_t;
808 typedef union drm_wait_vblank drm_wait_vblank_t;
809 typedef struct drm_agp_mode drm_agp_mode_t;
810 typedef enum drm_ctx_flags drm_ctx_flags_t;
811 typedef struct drm_ctx drm_ctx_t;
812 typedef struct drm_ctx_res drm_ctx_res_t;
813 typedef struct drm_draw drm_draw_t;
814 typedef struct drm_update_draw drm_update_draw_t;
815 typedef struct drm_auth drm_auth_t;
816 typedef struct drm_irq_busid drm_irq_busid_t;
817 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
819 typedef struct drm_agp_buffer drm_agp_buffer_t;
820 typedef struct drm_agp_binding drm_agp_binding_t;
821 typedef struct drm_agp_info drm_agp_info_t;
822 typedef struct drm_scatter_gather drm_scatter_gather_t;
823 typedef struct drm_set_version drm_set_version_t;
825 #endif