1 /*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
27 #ifndef _I915_DRM_H_
28 #define _I915_DRM_H_
30 #include "drm.h"
32 /* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
34 */
36 /* Each region is a minimum of 16k, and there are at most 255 of them.
37 */
38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
42 typedef struct _drm_i915_init {
43 enum {
44 I915_INIT_DMA = 0x01,
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
47 } func;
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
56 unsigned int w;
57 unsigned int h;
58 unsigned int pitch;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
62 unsigned int cpp;
63 unsigned int chipset;
64 } drm_i915_init_t;
66 typedef struct _drm_i915_sarea {
67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
68 int last_upload; /* last time texture was uploaded */
69 int last_enqueue; /* last time a buffer was enqueued */
70 int last_dispatch; /* age of the most recently dispatched buffer */
71 int ctxOwner; /* last context to upload state */
72 int texAge;
73 int pf_enabled; /* is pageflipping allowed? */
74 int pf_active;
75 int pf_current_page; /* which buffer is being displayed? */
76 int perf_boxes; /* performance boxes to be displayed */
77 int width, height; /* screen size in pixels */
79 drm_handle_t front_handle;
80 int front_offset;
81 int front_size;
83 drm_handle_t back_handle;
84 int back_offset;
85 int back_size;
87 drm_handle_t depth_handle;
88 int depth_offset;
89 int depth_size;
91 drm_handle_t tex_handle;
92 int tex_offset;
93 int tex_size;
94 int log_tex_granularity;
95 int pitch;
96 int rotation; /* 0, 90, 180 or 270 */
97 int rotated_offset;
98 int rotated_size;
99 int rotated_pitch;
100 int virtualX, virtualY;
102 unsigned int front_tiled;
103 unsigned int back_tiled;
104 unsigned int depth_tiled;
105 unsigned int rotated_tiled;
106 unsigned int rotated2_tiled;
108 int pipeA_x;
109 int pipeA_y;
110 int pipeA_w;
111 int pipeA_h;
112 int pipeB_x;
113 int pipeB_y;
114 int pipeB_w;
115 int pipeB_h;
117 /* fill out some space for old userspace triple buffer */
118 drm_handle_t unused_handle;
119 __u32 unused1, unused2, unused3;
121 /* buffer object handles for static buffers. May change
122 * over the lifetime of the client.
123 */
124 __u32 front_bo_handle;
125 __u32 back_bo_handle;
126 __u32 unused_bo_handle;
127 __u32 depth_bo_handle;
129 } drm_i915_sarea_t;
131 /* due to userspace building against these headers we need some compat here */
132 #define planeA_x pipeA_x
133 #define planeA_y pipeA_y
134 #define planeA_w pipeA_w
135 #define planeA_h pipeA_h
136 #define planeB_x pipeB_x
137 #define planeB_y pipeB_y
138 #define planeB_w pipeB_w
139 #define planeB_h pipeB_h
141 /* Flags for perf_boxes
142 */
143 #define I915_BOX_RING_EMPTY 0x1
144 #define I915_BOX_FLIP 0x2
145 #define I915_BOX_WAIT 0x4
146 #define I915_BOX_TEXTURE_LOAD 0x8
147 #define I915_BOX_LOST_CONTEXT 0x10
149 /* I915 specific ioctls
150 * The device specific ioctl range is 0x40 to 0x79.
151 */
152 #define DRM_I915_INIT 0x00
153 #define DRM_I915_FLUSH 0x01
154 #define DRM_I915_FLIP 0x02
155 #define DRM_I915_BATCHBUFFER 0x03
156 #define DRM_I915_IRQ_EMIT 0x04
157 #define DRM_I915_IRQ_WAIT 0x05
158 #define DRM_I915_GETPARAM 0x06
159 #define DRM_I915_SETPARAM 0x07
160 #define DRM_I915_ALLOC 0x08
161 #define DRM_I915_FREE 0x09
162 #define DRM_I915_INIT_HEAP 0x0a
163 #define DRM_I915_CMDBUFFER 0x0b
164 #define DRM_I915_DESTROY_HEAP 0x0c
165 #define DRM_I915_SET_VBLANK_PIPE 0x0d
166 #define DRM_I915_GET_VBLANK_PIPE 0x0e
167 #define DRM_I915_VBLANK_SWAP 0x0f
168 #define DRM_I915_HWS_ADDR 0x11
169 #define DRM_I915_GEM_INIT 0x13
170 #define DRM_I915_GEM_EXECBUFFER 0x14
171 #define DRM_I915_GEM_PIN 0x15
172 #define DRM_I915_GEM_UNPIN 0x16
173 #define DRM_I915_GEM_BUSY 0x17
174 #define DRM_I915_GEM_THROTTLE 0x18
175 #define DRM_I915_GEM_ENTERVT 0x19
176 #define DRM_I915_GEM_LEAVEVT 0x1a
177 #define DRM_I915_GEM_CREATE 0x1b
178 #define DRM_I915_GEM_PREAD 0x1c
179 #define DRM_I915_GEM_PWRITE 0x1d
180 #define DRM_I915_GEM_MMAP 0x1e
181 #define DRM_I915_GEM_SET_DOMAIN 0x1f
182 #define DRM_I915_GEM_SW_FINISH 0x20
183 #define DRM_I915_GEM_SET_TILING 0x21
184 #define DRM_I915_GEM_GET_TILING 0x22
185 #define DRM_I915_GEM_GET_APERTURE 0x23
186 #define DRM_I915_GEM_MMAP_GTT 0x24
187 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
188 #define DRM_I915_GEM_MADVISE 0x26
189 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
190 #define DRM_I915_OVERLAY_ATTRS 0x28
191 #define DRM_I915_GEM_EXECBUFFER2 0x29
192 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
193 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
195 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
196 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
197 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
198 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
199 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
200 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
201 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
202 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
203 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
204 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
205 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
206 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
207 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
208 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
209 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
210 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
211 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
212 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
213 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
214 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
215 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
216 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
217 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
218 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
219 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
220 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
221 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
222 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
223 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
224 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
225 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
226 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
227 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
228 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
229 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
230 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
231 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
232 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
233 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
234 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
235 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
236 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
238 /* Allow drivers to submit batchbuffers directly to hardware, relying
239 * on the security mechanisms provided by hardware.
240 */
241 typedef struct drm_i915_batchbuffer {
242 int start; /* agp offset */
243 int used; /* nr bytes in use */
244 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
245 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
246 int num_cliprects; /* mulitpass with multiple cliprects? */
247 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
248 } drm_i915_batchbuffer_t;
250 /* As above, but pass a pointer to userspace buffer which can be
251 * validated by the kernel prior to sending to hardware.
252 */
253 typedef struct _drm_i915_cmdbuffer {
254 char *buf; /* pointer to userspace command buffer */
255 int sz; /* nr bytes in buf */
256 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
257 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
258 int num_cliprects; /* mulitpass with multiple cliprects? */
259 struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
260 } drm_i915_cmdbuffer_t;
262 /* Userspace can request & wait on irq's:
263 */
264 typedef struct drm_i915_irq_emit {
265 int *irq_seq;
266 } drm_i915_irq_emit_t;
268 typedef struct drm_i915_irq_wait {
269 int irq_seq;
270 } drm_i915_irq_wait_t;
272 /* Ioctl to query kernel params:
273 */
274 #define I915_PARAM_IRQ_ACTIVE 1
275 #define I915_PARAM_ALLOW_BATCHBUFFER 2
276 #define I915_PARAM_LAST_DISPATCH 3
277 #define I915_PARAM_CHIPSET_ID 4
278 #define I915_PARAM_HAS_GEM 5
279 #define I915_PARAM_NUM_FENCES_AVAIL 6
280 #define I915_PARAM_HAS_OVERLAY 7
281 #define I915_PARAM_HAS_PAGEFLIPPING 8
282 #define I915_PARAM_HAS_EXECBUF2 9
283 #define I915_PARAM_HAS_BSD 10
284 #define I915_PARAM_HAS_BLT 11
285 #define I915_PARAM_HAS_RELAXED_FENCING 12
286 #define I915_PARAM_HAS_COHERENT_RINGS 13
287 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
288 #define I915_PARAM_HAS_RELAXED_DELTA 15
289 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
290 #define I915_PARAM_HAS_LLC 17
292 typedef struct drm_i915_getparam {
293 int param;
294 int *value;
295 } drm_i915_getparam_t;
297 /* Ioctl to set kernel params:
298 */
299 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
300 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
301 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
302 #define I915_SETPARAM_NUM_USED_FENCES 4
304 typedef struct drm_i915_setparam {
305 int param;
306 int value;
307 } drm_i915_setparam_t;
309 /* A memory manager for regions of shared memory:
310 */
311 #define I915_MEM_REGION_AGP 1
313 typedef struct drm_i915_mem_alloc {
314 int region;
315 int alignment;
316 int size;
317 int *region_offset; /* offset from start of fb or agp */
318 } drm_i915_mem_alloc_t;
320 typedef struct drm_i915_mem_free {
321 int region;
322 int region_offset;
323 } drm_i915_mem_free_t;
325 typedef struct drm_i915_mem_init_heap {
326 int region;
327 int size;
328 int start;
329 } drm_i915_mem_init_heap_t;
331 /* Allow memory manager to be torn down and re-initialized (eg on
332 * rotate):
333 */
334 typedef struct drm_i915_mem_destroy_heap {
335 int region;
336 } drm_i915_mem_destroy_heap_t;
338 /* Allow X server to configure which pipes to monitor for vblank signals
339 */
340 #define DRM_I915_VBLANK_PIPE_A 1
341 #define DRM_I915_VBLANK_PIPE_B 2
343 typedef struct drm_i915_vblank_pipe {
344 int pipe;
345 } drm_i915_vblank_pipe_t;
347 /* Schedule buffer swap at given vertical blank:
348 */
349 typedef struct drm_i915_vblank_swap {
350 drm_drawable_t drawable;
351 enum drm_vblank_seq_type seqtype;
352 unsigned int sequence;
353 } drm_i915_vblank_swap_t;
355 typedef struct drm_i915_hws_addr {
356 __u64 addr;
357 } drm_i915_hws_addr_t;
359 struct drm_i915_gem_init {
360 /**
361 * Beginning offset in the GTT to be managed by the DRM memory
362 * manager.
363 */
364 __u64 gtt_start;
365 /**
366 * Ending offset in the GTT to be managed by the DRM memory
367 * manager.
368 */
369 __u64 gtt_end;
370 };
372 struct drm_i915_gem_create {
373 /**
374 * Requested size for the object.
375 *
376 * The (page-aligned) allocated size for the object will be returned.
377 */
378 __u64 size;
379 /**
380 * Returned handle for the object.
381 *
382 * Object handles are nonzero.
383 */
384 __u32 handle;
385 __u32 pad;
386 };
388 struct drm_i915_gem_pread {
389 /** Handle for the object being read. */
390 __u32 handle;
391 __u32 pad;
392 /** Offset into the object to read from */
393 __u64 offset;
394 /** Length of data to read */
395 __u64 size;
396 /**
397 * Pointer to write the data into.
398 *
399 * This is a fixed-size type for 32/64 compatibility.
400 */
401 __u64 data_ptr;
402 };
404 struct drm_i915_gem_pwrite {
405 /** Handle for the object being written to. */
406 __u32 handle;
407 __u32 pad;
408 /** Offset into the object to write to */
409 __u64 offset;
410 /** Length of data to write */
411 __u64 size;
412 /**
413 * Pointer to read the data from.
414 *
415 * This is a fixed-size type for 32/64 compatibility.
416 */
417 __u64 data_ptr;
418 };
420 struct drm_i915_gem_mmap {
421 /** Handle for the object being mapped. */
422 __u32 handle;
423 __u32 pad;
424 /** Offset in the object to map. */
425 __u64 offset;
426 /**
427 * Length of data to map.
428 *
429 * The value will be page-aligned.
430 */
431 __u64 size;
432 /**
433 * Returned pointer the data was mapped at.
434 *
435 * This is a fixed-size type for 32/64 compatibility.
436 */
437 __u64 addr_ptr;
438 };
440 struct drm_i915_gem_mmap_gtt {
441 /** Handle for the object being mapped. */
442 __u32 handle;
443 __u32 pad;
444 /**
445 * Fake offset to use for subsequent mmap call
446 *
447 * This is a fixed-size type for 32/64 compatibility.
448 */
449 __u64 offset;
450 };
452 struct drm_i915_gem_set_domain {
453 /** Handle for the object */
454 __u32 handle;
456 /** New read domains */
457 __u32 read_domains;
459 /** New write domain */
460 __u32 write_domain;
461 };
463 struct drm_i915_gem_sw_finish {
464 /** Handle for the object */
465 __u32 handle;
466 };
468 struct drm_i915_gem_relocation_entry {
469 /**
470 * Handle of the buffer being pointed to by this relocation entry.
471 *
472 * It's appealing to make this be an index into the mm_validate_entry
473 * list to refer to the buffer, but this allows the driver to create
474 * a relocation list for state buffers and not re-write it per
475 * exec using the buffer.
476 */
477 __u32 target_handle;
479 /**
480 * Value to be added to the offset of the target buffer to make up
481 * the relocation entry.
482 */
483 __u32 delta;
485 /** Offset in the buffer the relocation entry will be written into */
486 __u64 offset;
488 /**
489 * Offset value of the target buffer that the relocation entry was last
490 * written as.
491 *
492 * If the buffer has the same offset as last time, we can skip syncing
493 * and writing the relocation. This value is written back out by
494 * the execbuffer ioctl when the relocation is written.
495 */
496 __u64 presumed_offset;
498 /**
499 * Target memory domains read by this operation.
500 */
501 __u32 read_domains;
503 /**
504 * Target memory domains written by this operation.
505 *
506 * Note that only one domain may be written by the whole
507 * execbuffer operation, so that where there are conflicts,
508 * the application will get -EINVAL back.
509 */
510 __u32 write_domain;
511 };
513 /** @{
514 * Intel memory domains
515 *
516 * Most of these just align with the various caches in
517 * the system and are used to flush and invalidate as
518 * objects end up cached in different domains.
519 */
520 /** CPU cache */
521 #define I915_GEM_DOMAIN_CPU 0x00000001
522 /** Render cache, used by 2D and 3D drawing */
523 #define I915_GEM_DOMAIN_RENDER 0x00000002
524 /** Sampler cache, used by texture engine */
525 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
526 /** Command queue, used to load batch buffers */
527 #define I915_GEM_DOMAIN_COMMAND 0x00000008
528 /** Instruction cache, used by shader programs */
529 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
530 /** Vertex address cache */
531 #define I915_GEM_DOMAIN_VERTEX 0x00000020
532 /** GTT domain - aperture and scanout */
533 #define I915_GEM_DOMAIN_GTT 0x00000040
534 /** @} */
536 struct drm_i915_gem_exec_object {
537 /**
538 * User's handle for a buffer to be bound into the GTT for this
539 * operation.
540 */
541 __u32 handle;
543 /** Number of relocations to be performed on this buffer */
544 __u32 relocation_count;
545 /**
546 * Pointer to array of struct drm_i915_gem_relocation_entry containing
547 * the relocations to be performed in this buffer.
548 */
549 __u64 relocs_ptr;
551 /** Required alignment in graphics aperture */
552 __u64 alignment;
554 /**
555 * Returned value of the updated offset of the object, for future
556 * presumed_offset writes.
557 */
558 __u64 offset;
559 };
561 struct drm_i915_gem_execbuffer {
562 /**
563 * List of buffers to be validated with their relocations to be
564 * performend on them.
565 *
566 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
567 *
568 * These buffers must be listed in an order such that all relocations
569 * a buffer is performing refer to buffers that have already appeared
570 * in the validate list.
571 */
572 __u64 buffers_ptr;
573 __u32 buffer_count;
575 /** Offset in the batchbuffer to start execution from. */
576 __u32 batch_start_offset;
577 /** Bytes used in batchbuffer from batch_start_offset */
578 __u32 batch_len;
579 __u32 DR1;
580 __u32 DR4;
581 __u32 num_cliprects;
582 /** This is a struct drm_clip_rect *cliprects */
583 __u64 cliprects_ptr;
584 };
586 struct drm_i915_gem_exec_object2 {
587 /**
588 * User's handle for a buffer to be bound into the GTT for this
589 * operation.
590 */
591 __u32 handle;
593 /** Number of relocations to be performed on this buffer */
594 __u32 relocation_count;
595 /**
596 * Pointer to array of struct drm_i915_gem_relocation_entry containing
597 * the relocations to be performed in this buffer.
598 */
599 __u64 relocs_ptr;
601 /** Required alignment in graphics aperture */
602 __u64 alignment;
604 /**
605 * Returned value of the updated offset of the object, for future
606 * presumed_offset writes.
607 */
608 __u64 offset;
610 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
611 __u64 flags;
612 __u64 rsvd1;
613 __u64 rsvd2;
614 };
616 struct drm_i915_gem_execbuffer2 {
617 /**
618 * List of gem_exec_object2 structs
619 */
620 __u64 buffers_ptr;
621 __u32 buffer_count;
623 /** Offset in the batchbuffer to start execution from. */
624 __u32 batch_start_offset;
625 /** Bytes used in batchbuffer from batch_start_offset */
626 __u32 batch_len;
627 __u32 DR1;
628 __u32 DR4;
629 __u32 num_cliprects;
630 /** This is a struct drm_clip_rect *cliprects */
631 __u64 cliprects_ptr;
632 #define I915_EXEC_RING_MASK (7<<0)
633 #define I915_EXEC_DEFAULT (0<<0)
634 #define I915_EXEC_RENDER (1<<0)
635 #define I915_EXEC_BSD (2<<0)
636 #define I915_EXEC_BLT (3<<0)
638 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
639 * Gen6+ only supports relative addressing to dynamic state (default) and
640 * absolute addressing.
641 *
642 * These flags are ignored for the BSD and BLT rings.
643 */
644 #define I915_EXEC_CONSTANTS_MASK (3<<6)
645 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
646 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
647 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
648 __u64 flags;
649 __u64 rsvd1;
650 __u64 rsvd2;
651 };
653 /** Resets the SO write offset registers for transform feedback on gen7. */
654 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
656 struct drm_i915_gem_pin {
657 /** Handle of the buffer to be pinned. */
658 __u32 handle;
659 __u32 pad;
661 /** alignment required within the aperture */
662 __u64 alignment;
664 /** Returned GTT offset of the buffer. */
665 __u64 offset;
666 };
668 struct drm_i915_gem_unpin {
669 /** Handle of the buffer to be unpinned. */
670 __u32 handle;
671 __u32 pad;
672 };
674 struct drm_i915_gem_busy {
675 /** Handle of the buffer to check for busy */
676 __u32 handle;
678 /** Return busy status (1 if busy, 0 if idle) */
679 __u32 busy;
680 };
682 #define I915_TILING_NONE 0
683 #define I915_TILING_X 1
684 #define I915_TILING_Y 2
686 #define I915_BIT_6_SWIZZLE_NONE 0
687 #define I915_BIT_6_SWIZZLE_9 1
688 #define I915_BIT_6_SWIZZLE_9_10 2
689 #define I915_BIT_6_SWIZZLE_9_11 3
690 #define I915_BIT_6_SWIZZLE_9_10_11 4
691 /* Not seen by userland */
692 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
693 /* Seen by userland. */
694 #define I915_BIT_6_SWIZZLE_9_17 6
695 #define I915_BIT_6_SWIZZLE_9_10_17 7
697 struct drm_i915_gem_set_tiling {
698 /** Handle of the buffer to have its tiling state updated */
699 __u32 handle;
701 /**
702 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
703 * I915_TILING_Y).
704 *
705 * This value is to be set on request, and will be updated by the
706 * kernel on successful return with the actual chosen tiling layout.
707 *
708 * The tiling mode may be demoted to I915_TILING_NONE when the system
709 * has bit 6 swizzling that can't be managed correctly by GEM.
710 *
711 * Buffer contents become undefined when changing tiling_mode.
712 */
713 __u32 tiling_mode;
715 /**
716 * Stride in bytes for the object when in I915_TILING_X or
717 * I915_TILING_Y.
718 */
719 __u32 stride;
721 /**
722 * Returned address bit 6 swizzling required for CPU access through
723 * mmap mapping.
724 */
725 __u32 swizzle_mode;
726 };
728 struct drm_i915_gem_get_tiling {
729 /** Handle of the buffer to get tiling state for. */
730 __u32 handle;
732 /**
733 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
734 * I915_TILING_Y).
735 */
736 __u32 tiling_mode;
738 /**
739 * Returned address bit 6 swizzling required for CPU access through
740 * mmap mapping.
741 */
742 __u32 swizzle_mode;
743 };
745 struct drm_i915_gem_get_aperture {
746 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
747 __u64 aper_size;
749 /**
750 * Available space in the aperture used by i915_gem_execbuffer, in
751 * bytes
752 */
753 __u64 aper_available_size;
754 };
756 struct drm_i915_get_pipe_from_crtc_id {
757 /** ID of CRTC being requested **/
758 __u32 crtc_id;
760 /** pipe of requested CRTC **/
761 __u32 pipe;
762 };
764 #define I915_MADV_WILLNEED 0
765 #define I915_MADV_DONTNEED 1
766 #define __I915_MADV_PURGED 2 /* internal state */
768 struct drm_i915_gem_madvise {
769 /** Handle of the buffer to change the backing store advice */
770 __u32 handle;
772 /* Advice: either the buffer will be needed again in the near future,
773 * or wont be and could be discarded under memory pressure.
774 */
775 __u32 madv;
777 /** Whether the backing store still exists. */
778 __u32 retained;
779 };
781 /* flags */
782 #define I915_OVERLAY_TYPE_MASK 0xff
783 #define I915_OVERLAY_YUV_PLANAR 0x01
784 #define I915_OVERLAY_YUV_PACKED 0x02
785 #define I915_OVERLAY_RGB 0x03
787 #define I915_OVERLAY_DEPTH_MASK 0xff00
788 #define I915_OVERLAY_RGB24 0x1000
789 #define I915_OVERLAY_RGB16 0x2000
790 #define I915_OVERLAY_RGB15 0x3000
791 #define I915_OVERLAY_YUV422 0x0100
792 #define I915_OVERLAY_YUV411 0x0200
793 #define I915_OVERLAY_YUV420 0x0300
794 #define I915_OVERLAY_YUV410 0x0400
796 #define I915_OVERLAY_SWAP_MASK 0xff0000
797 #define I915_OVERLAY_NO_SWAP 0x000000
798 #define I915_OVERLAY_UV_SWAP 0x010000
799 #define I915_OVERLAY_Y_SWAP 0x020000
800 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
802 #define I915_OVERLAY_FLAGS_MASK 0xff000000
803 #define I915_OVERLAY_ENABLE 0x01000000
805 struct drm_intel_overlay_put_image {
806 /* various flags and src format description */
807 __u32 flags;
808 /* source picture description */
809 __u32 bo_handle;
810 /* stride values and offsets are in bytes, buffer relative */
811 __u16 stride_Y; /* stride for packed formats */
812 __u16 stride_UV;
813 __u32 offset_Y; /* offset for packet formats */
814 __u32 offset_U;
815 __u32 offset_V;
816 /* in pixels */
817 __u16 src_width;
818 __u16 src_height;
819 /* to compensate the scaling factors for partially covered surfaces */
820 __u16 src_scan_width;
821 __u16 src_scan_height;
822 /* output crtc description */
823 __u32 crtc_id;
824 __u16 dst_x;
825 __u16 dst_y;
826 __u16 dst_width;
827 __u16 dst_height;
828 };
830 /* flags */
831 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
832 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
833 struct drm_intel_overlay_attrs {
834 __u32 flags;
835 __u32 color_key;
836 __s32 brightness;
837 __u32 contrast;
838 __u32 saturation;
839 __u32 gamma0;
840 __u32 gamma1;
841 __u32 gamma2;
842 __u32 gamma3;
843 __u32 gamma4;
844 __u32 gamma5;
845 };
847 /*
848 * Intel sprite handling
849 *
850 * Color keying works with a min/mask/max tuple. Both source and destination
851 * color keying is allowed.
852 *
853 * Source keying:
854 * Sprite pixels within the min & max values, masked against the color channels
855 * specified in the mask field, will be transparent. All other pixels will
856 * be displayed on top of the primary plane. For RGB surfaces, only the min
857 * and mask fields will be used; ranged compares are not allowed.
858 *
859 * Destination keying:
860 * Primary plane pixels that match the min value, masked against the color
861 * channels specified in the mask field, will be replaced by corresponding
862 * pixels from the sprite plane.
863 *
864 * Note that source & destination keying are exclusive; only one can be
865 * active on a given plane.
866 */
868 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
869 #define I915_SET_COLORKEY_DESTINATION (1<<1)
870 #define I915_SET_COLORKEY_SOURCE (1<<2)
871 struct drm_intel_sprite_colorkey {
872 __u32 plane_id;
873 __u32 min_value;
874 __u32 channel_mask;
875 __u32 max_value;
876 __u32 flags;
877 };
879 #endif /* _I915_DRM_H_ */