1 /**************************************************************************
2 *
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
26 * of the Software.
27 *
28 *
29 **************************************************************************/
30 /*
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
35 */
37 #ifdef HAVE_CONFIG_H
38 #include "config.h"
39 #endif
41 #include <xf86drm.h>
42 #include <xf86atomic.h>
43 #include <fcntl.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <string.h>
47 #include <unistd.h>
48 #include <assert.h>
49 #include <pthread.h>
50 #include <sys/ioctl.h>
51 #include <sys/mman.h>
52 #include <sys/stat.h>
53 #include <sys/types.h>
55 #include "errno.h"
56 #include "libdrm_lists.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
60 #include "string.h"
62 #include "i915_drm.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
67 } while (0)
69 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
71 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
73 struct drm_intel_gem_bo_bucket {
74 drmMMListHead head;
75 unsigned long size;
76 };
78 typedef struct _drm_intel_bufmgr_gem {
79 drm_intel_bufmgr bufmgr;
81 int fd;
83 int max_relocs;
85 pthread_mutex_t lock;
87 struct drm_i915_gem_exec_object *exec_objects;
88 struct drm_i915_gem_exec_object2 *exec2_objects;
89 drm_intel_bo **exec_bos;
90 int exec_size;
91 int exec_count;
93 /** Array of lists of cached gem objects of power-of-two sizes */
94 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
95 int num_buckets;
96 time_t time;
98 uint64_t gtt_size;
99 int available_fences;
100 int pci_device;
101 int gen;
102 unsigned int has_bsd : 1;
103 unsigned int has_blt : 1;
104 unsigned int has_relaxed_fencing : 1;
105 unsigned int bo_reuse : 1;
106 char fenced_relocs;
107 } drm_intel_bufmgr_gem;
109 #define DRM_INTEL_RELOC_FENCE (1<<0)
111 typedef struct _drm_intel_reloc_target_info {
112 drm_intel_bo *bo;
113 int flags;
114 } drm_intel_reloc_target;
116 struct _drm_intel_bo_gem {
117 drm_intel_bo bo;
119 atomic_t refcount;
120 uint32_t gem_handle;
121 const char *name;
123 /**
124 * Kenel-assigned global name for this object
125 */
126 unsigned int global_name;
128 /**
129 * Index of the buffer within the validation list while preparing a
130 * batchbuffer execution.
131 */
132 int validate_index;
134 /**
135 * Current tiling mode
136 */
137 uint32_t tiling_mode;
138 uint32_t swizzle_mode;
139 unsigned long stride;
141 time_t free_time;
143 /** Array passed to the DRM containing relocation information. */
144 struct drm_i915_gem_relocation_entry *relocs;
145 /**
146 * Array of info structs corresponding to relocs[i].target_handle etc
147 */
148 drm_intel_reloc_target *reloc_target_info;
149 /** Number of entries in relocs */
150 int reloc_count;
151 /** Mapped address for the buffer, saved across map/unmap cycles */
152 void *mem_virtual;
153 /** GTT virtual address for the buffer, saved across map/unmap cycles */
154 void *gtt_virtual;
156 /** BO cache list */
157 drmMMListHead head;
159 /**
160 * Boolean of whether this BO and its children have been included in
161 * the current drm_intel_bufmgr_check_aperture_space() total.
162 */
163 char included_in_check_aperture;
165 /**
166 * Boolean of whether this buffer has been used as a relocation
167 * target and had its size accounted for, and thus can't have any
168 * further relocations added to it.
169 */
170 char used_as_reloc_target;
172 /**
173 * Boolean of whether we have encountered an error whilst building the relocation tree.
174 */
175 char has_error;
177 /**
178 * Boolean of whether this buffer can be re-used
179 */
180 char reusable;
182 /**
183 * Size in bytes of this buffer and its relocation descendents.
184 *
185 * Used to avoid costly tree walking in
186 * drm_intel_bufmgr_check_aperture in the common case.
187 */
188 int reloc_tree_size;
190 /**
191 * Number of potential fence registers required by this buffer and its
192 * relocations.
193 */
194 int reloc_tree_fences;
195 };
197 static unsigned int
198 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
200 static unsigned int
201 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
203 static int
204 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
205 uint32_t * swizzle_mode);
207 static int
208 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
209 uint32_t tiling_mode,
210 uint32_t stride);
212 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
213 time_t time);
215 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
217 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
219 static unsigned long
220 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
221 uint32_t *tiling_mode)
222 {
223 unsigned long min_size, max_size;
224 unsigned long i;
226 if (*tiling_mode == I915_TILING_NONE)
227 return size;
229 /* 965+ just need multiples of page size for tiling */
230 if (bufmgr_gem->gen >= 4)
231 return ROUND_UP_TO(size, 4096);
233 /* Older chips need powers of two, of at least 512k or 1M */
234 if (bufmgr_gem->gen == 3) {
235 min_size = 1024*1024;
236 max_size = 128*1024*1024;
237 } else {
238 min_size = 512*1024;
239 max_size = 64*1024*1024;
240 }
242 if (size > max_size) {
243 *tiling_mode = I915_TILING_NONE;
244 return size;
245 }
247 /* Do we need to allocate every page for the fence? */
248 if (bufmgr_gem->has_relaxed_fencing)
249 return ROUND_UP_TO(size, 4096);
251 for (i = min_size; i < size; i <<= 1)
252 ;
254 return i;
255 }
257 /*
258 * Round a given pitch up to the minimum required for X tiling on a
259 * given chip. We use 512 as the minimum to allow for a later tiling
260 * change.
261 */
262 static unsigned long
263 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
264 unsigned long pitch, uint32_t *tiling_mode)
265 {
266 unsigned long tile_width;
267 unsigned long i;
269 /* If untiled, then just align it so that we can do rendering
270 * to it with the 3D engine.
271 */
272 if (*tiling_mode == I915_TILING_NONE)
273 return ALIGN(pitch, 64);
275 if (*tiling_mode == I915_TILING_X)
276 tile_width = 512;
277 else
278 tile_width = 128;
280 /* 965 is flexible */
281 if (bufmgr_gem->gen >= 4)
282 return ROUND_UP_TO(pitch, tile_width);
284 /* The older hardware has a maximum pitch of 8192 with tiled
285 * surfaces, so fallback to untiled if it's too large.
286 */
287 if (pitch > 8192) {
288 *tiling_mode = I915_TILING_NONE;
289 return ALIGN(pitch, 64);
290 }
292 /* Pre-965 needs power of two tile width */
293 for (i = tile_width; i < pitch; i <<= 1)
294 ;
296 return i;
297 }
299 static struct drm_intel_gem_bo_bucket *
300 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
301 unsigned long size)
302 {
303 int i;
305 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
306 struct drm_intel_gem_bo_bucket *bucket =
307 &bufmgr_gem->cache_bucket[i];
308 if (bucket->size >= size) {
309 return bucket;
310 }
311 }
313 return NULL;
314 }
316 static void
317 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
318 {
319 int i, j;
321 for (i = 0; i < bufmgr_gem->exec_count; i++) {
322 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
323 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
325 if (bo_gem->relocs == NULL) {
326 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
327 bo_gem->name);
328 continue;
329 }
331 for (j = 0; j < bo_gem->reloc_count; j++) {
332 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
333 drm_intel_bo_gem *target_gem =
334 (drm_intel_bo_gem *) target_bo;
336 DBG("%2d: %d (%s)@0x%08llx -> "
337 "%d (%s)@0x%08lx + 0x%08x\n",
338 i,
339 bo_gem->gem_handle, bo_gem->name,
340 (unsigned long long)bo_gem->relocs[j].offset,
341 target_gem->gem_handle,
342 target_gem->name,
343 target_bo->offset,
344 bo_gem->relocs[j].delta);
345 }
346 }
347 }
349 static inline void
350 drm_intel_gem_bo_reference(drm_intel_bo *bo)
351 {
352 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
354 atomic_inc(&bo_gem->refcount);
355 }
357 /**
358 * Adds the given buffer to the list of buffers to be validated (moved into the
359 * appropriate memory type) with the next batch submission.
360 *
361 * If a buffer is validated multiple times in a batch submission, it ends up
362 * with the intersection of the memory type flags and the union of the
363 * access flags.
364 */
365 static void
366 drm_intel_add_validate_buffer(drm_intel_bo *bo)
367 {
368 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
369 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
370 int index;
372 if (bo_gem->validate_index != -1)
373 return;
375 /* Extend the array of validation entries as necessary. */
376 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
377 int new_size = bufmgr_gem->exec_size * 2;
379 if (new_size == 0)
380 new_size = 5;
382 bufmgr_gem->exec_objects =
383 realloc(bufmgr_gem->exec_objects,
384 sizeof(*bufmgr_gem->exec_objects) * new_size);
385 bufmgr_gem->exec_bos =
386 realloc(bufmgr_gem->exec_bos,
387 sizeof(*bufmgr_gem->exec_bos) * new_size);
388 bufmgr_gem->exec_size = new_size;
389 }
391 index = bufmgr_gem->exec_count;
392 bo_gem->validate_index = index;
393 /* Fill in array entry */
394 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
395 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
396 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
397 bufmgr_gem->exec_objects[index].alignment = 0;
398 bufmgr_gem->exec_objects[index].offset = 0;
399 bufmgr_gem->exec_bos[index] = bo;
400 bufmgr_gem->exec_count++;
401 }
403 static void
404 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
405 {
406 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
407 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
408 int index;
410 if (bo_gem->validate_index != -1) {
411 if (need_fence)
412 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
413 EXEC_OBJECT_NEEDS_FENCE;
414 return;
415 }
417 /* Extend the array of validation entries as necessary. */
418 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
419 int new_size = bufmgr_gem->exec_size * 2;
421 if (new_size == 0)
422 new_size = 5;
424 bufmgr_gem->exec2_objects =
425 realloc(bufmgr_gem->exec2_objects,
426 sizeof(*bufmgr_gem->exec2_objects) * new_size);
427 bufmgr_gem->exec_bos =
428 realloc(bufmgr_gem->exec_bos,
429 sizeof(*bufmgr_gem->exec_bos) * new_size);
430 bufmgr_gem->exec_size = new_size;
431 }
433 index = bufmgr_gem->exec_count;
434 bo_gem->validate_index = index;
435 /* Fill in array entry */
436 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
437 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
438 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
439 bufmgr_gem->exec2_objects[index].alignment = 0;
440 bufmgr_gem->exec2_objects[index].offset = 0;
441 bufmgr_gem->exec_bos[index] = bo;
442 bufmgr_gem->exec2_objects[index].flags = 0;
443 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
444 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
445 if (need_fence) {
446 bufmgr_gem->exec2_objects[index].flags |=
447 EXEC_OBJECT_NEEDS_FENCE;
448 }
449 bufmgr_gem->exec_count++;
450 }
452 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
453 sizeof(uint32_t))
455 static void
456 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
457 drm_intel_bo_gem *bo_gem)
458 {
459 int size;
461 assert(!bo_gem->used_as_reloc_target);
463 /* The older chipsets are far-less flexible in terms of tiling,
464 * and require tiled buffer to be size aligned in the aperture.
465 * This means that in the worst possible case we will need a hole
466 * twice as large as the object in order for it to fit into the
467 * aperture. Optimal packing is for wimps.
468 */
469 size = bo_gem->bo.size;
470 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
471 int min_size;
473 if (bufmgr_gem->has_relaxed_fencing) {
474 if (bufmgr_gem->gen == 3)
475 min_size = 1024*1024;
476 else
477 min_size = 512*1024;
479 while (min_size < size)
480 min_size *= 2;
481 } else
482 min_size = size;
484 /* Account for worst-case alignment. */
485 size = 2 * min_size;
486 }
488 bo_gem->reloc_tree_size = size;
489 }
491 static int
492 drm_intel_setup_reloc_list(drm_intel_bo *bo)
493 {
494 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
495 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
496 unsigned int max_relocs = bufmgr_gem->max_relocs;
498 if (bo->size / 4 < max_relocs)
499 max_relocs = bo->size / 4;
501 bo_gem->relocs = malloc(max_relocs *
502 sizeof(struct drm_i915_gem_relocation_entry));
503 bo_gem->reloc_target_info = malloc(max_relocs *
504 sizeof(drm_intel_reloc_target));
505 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
506 bo_gem->has_error = 1;
508 free (bo_gem->relocs);
509 bo_gem->relocs = NULL;
511 free (bo_gem->reloc_target_info);
512 bo_gem->reloc_target_info = NULL;
514 return 1;
515 }
517 return 0;
518 }
520 static int
521 drm_intel_gem_bo_busy(drm_intel_bo *bo)
522 {
523 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
524 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
525 struct drm_i915_gem_busy busy;
526 int ret;
528 memset(&busy, 0, sizeof(busy));
529 busy.handle = bo_gem->gem_handle;
531 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
533 return (ret == 0 && busy.busy);
534 }
536 static int
537 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
538 drm_intel_bo_gem *bo_gem, int state)
539 {
540 struct drm_i915_gem_madvise madv;
542 madv.handle = bo_gem->gem_handle;
543 madv.madv = state;
544 madv.retained = 1;
545 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
547 return madv.retained;
548 }
550 static int
551 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
552 {
553 return drm_intel_gem_bo_madvise_internal
554 ((drm_intel_bufmgr_gem *) bo->bufmgr,
555 (drm_intel_bo_gem *) bo,
556 madv);
557 }
559 /* drop the oldest entries that have been purged by the kernel */
560 static void
561 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
562 struct drm_intel_gem_bo_bucket *bucket)
563 {
564 while (!DRMLISTEMPTY(&bucket->head)) {
565 drm_intel_bo_gem *bo_gem;
567 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
568 bucket->head.next, head);
569 if (drm_intel_gem_bo_madvise_internal
570 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
571 break;
573 DRMLISTDEL(&bo_gem->head);
574 drm_intel_gem_bo_free(&bo_gem->bo);
575 }
576 }
578 static drm_intel_bo *
579 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
580 const char *name,
581 unsigned long size,
582 unsigned long flags,
583 uint32_t tiling_mode,
584 unsigned long stride)
585 {
586 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
587 drm_intel_bo_gem *bo_gem;
588 unsigned int page_size = getpagesize();
589 int ret;
590 struct drm_intel_gem_bo_bucket *bucket;
591 int alloc_from_cache;
592 unsigned long bo_size;
593 int for_render = 0;
595 if (flags & BO_ALLOC_FOR_RENDER)
596 for_render = 1;
598 /* Round the allocated size up to a power of two number of pages. */
599 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
601 /* If we don't have caching at this size, don't actually round the
602 * allocation up.
603 */
604 if (bucket == NULL) {
605 bo_size = size;
606 if (bo_size < page_size)
607 bo_size = page_size;
608 } else {
609 bo_size = bucket->size;
610 }
612 pthread_mutex_lock(&bufmgr_gem->lock);
613 /* Get a buffer out of the cache if available */
614 retry:
615 alloc_from_cache = 0;
616 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
617 if (for_render) {
618 /* Allocate new render-target BOs from the tail (MRU)
619 * of the list, as it will likely be hot in the GPU
620 * cache and in the aperture for us.
621 */
622 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
623 bucket->head.prev, head);
624 DRMLISTDEL(&bo_gem->head);
625 alloc_from_cache = 1;
626 } else {
627 /* For non-render-target BOs (where we're probably
628 * going to map it first thing in order to fill it
629 * with data), check if the last BO in the cache is
630 * unbusy, and only reuse in that case. Otherwise,
631 * allocating a new buffer is probably faster than
632 * waiting for the GPU to finish.
633 */
634 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
635 bucket->head.next, head);
636 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
637 alloc_from_cache = 1;
638 DRMLISTDEL(&bo_gem->head);
639 }
640 }
642 if (alloc_from_cache) {
643 if (!drm_intel_gem_bo_madvise_internal
644 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
645 drm_intel_gem_bo_free(&bo_gem->bo);
646 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
647 bucket);
648 goto retry;
649 }
651 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
652 tiling_mode,
653 stride)) {
654 drm_intel_gem_bo_free(&bo_gem->bo);
655 goto retry;
656 }
657 }
658 }
659 pthread_mutex_unlock(&bufmgr_gem->lock);
661 if (!alloc_from_cache) {
662 struct drm_i915_gem_create create;
664 bo_gem = calloc(1, sizeof(*bo_gem));
665 if (!bo_gem)
666 return NULL;
668 bo_gem->bo.size = bo_size;
669 memset(&create, 0, sizeof(create));
670 create.size = bo_size;
672 ret = drmIoctl(bufmgr_gem->fd,
673 DRM_IOCTL_I915_GEM_CREATE,
674 &create);
675 bo_gem->gem_handle = create.handle;
676 bo_gem->bo.handle = bo_gem->gem_handle;
677 if (ret != 0) {
678 free(bo_gem);
679 return NULL;
680 }
681 bo_gem->bo.bufmgr = bufmgr;
683 bo_gem->tiling_mode = I915_TILING_NONE;
684 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
685 bo_gem->stride = 0;
687 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
688 tiling_mode,
689 stride)) {
690 drm_intel_gem_bo_free(&bo_gem->bo);
691 return NULL;
692 }
693 }
695 bo_gem->name = name;
696 atomic_set(&bo_gem->refcount, 1);
697 bo_gem->validate_index = -1;
698 bo_gem->reloc_tree_fences = 0;
699 bo_gem->used_as_reloc_target = 0;
700 bo_gem->has_error = 0;
701 bo_gem->reusable = 1;
703 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
705 DBG("bo_create: buf %d (%s) %ldb\n",
706 bo_gem->gem_handle, bo_gem->name, size);
708 return &bo_gem->bo;
709 }
711 static drm_intel_bo *
712 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
713 const char *name,
714 unsigned long size,
715 unsigned int alignment)
716 {
717 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
718 BO_ALLOC_FOR_RENDER,
719 I915_TILING_NONE, 0);
720 }
722 static drm_intel_bo *
723 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
724 const char *name,
725 unsigned long size,
726 unsigned int alignment)
727 {
728 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
729 I915_TILING_NONE, 0);
730 }
732 static drm_intel_bo *
733 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
734 int x, int y, int cpp, uint32_t *tiling_mode,
735 unsigned long *pitch, unsigned long flags)
736 {
737 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
738 unsigned long size, stride;
739 uint32_t tiling;
741 do {
742 unsigned long aligned_y;
744 tiling = *tiling_mode;
746 /* If we're tiled, our allocations are in 8 or 32-row blocks,
747 * so failure to align our height means that we won't allocate
748 * enough pages.
749 *
750 * If we're untiled, we still have to align to 2 rows high
751 * because the data port accesses 2x2 blocks even if the
752 * bottom row isn't to be rendered, so failure to align means
753 * we could walk off the end of the GTT and fault. This is
754 * documented on 965, and may be the case on older chipsets
755 * too so we try to be careful.
756 */
757 aligned_y = y;
758 if (tiling == I915_TILING_NONE)
759 aligned_y = ALIGN(y, 2);
760 else if (tiling == I915_TILING_X)
761 aligned_y = ALIGN(y, 8);
762 else if (tiling == I915_TILING_Y)
763 aligned_y = ALIGN(y, 32);
765 stride = x * cpp;
766 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
767 size = stride * aligned_y;
768 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
769 } while (*tiling_mode != tiling);
770 *pitch = stride;
772 if (tiling == I915_TILING_NONE)
773 stride = 0;
775 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
776 tiling, stride);
777 }
779 /**
780 * Returns a drm_intel_bo wrapping the given buffer object handle.
781 *
782 * This can be used when one application needs to pass a buffer object
783 * to another.
784 */
785 drm_intel_bo *
786 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
787 const char *name,
788 unsigned int handle)
789 {
790 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
791 drm_intel_bo_gem *bo_gem;
792 int ret;
793 struct drm_gem_open open_arg;
794 struct drm_i915_gem_get_tiling get_tiling;
796 bo_gem = calloc(1, sizeof(*bo_gem));
797 if (!bo_gem)
798 return NULL;
800 memset(&open_arg, 0, sizeof(open_arg));
801 open_arg.name = handle;
802 ret = drmIoctl(bufmgr_gem->fd,
803 DRM_IOCTL_GEM_OPEN,
804 &open_arg);
805 if (ret != 0) {
806 DBG("Couldn't reference %s handle 0x%08x: %s\n",
807 name, handle, strerror(errno));
808 free(bo_gem);
809 return NULL;
810 }
811 bo_gem->bo.size = open_arg.size;
812 bo_gem->bo.offset = 0;
813 bo_gem->bo.virtual = NULL;
814 bo_gem->bo.bufmgr = bufmgr;
815 bo_gem->name = name;
816 atomic_set(&bo_gem->refcount, 1);
817 bo_gem->validate_index = -1;
818 bo_gem->gem_handle = open_arg.handle;
819 bo_gem->global_name = handle;
820 bo_gem->reusable = 0;
822 memset(&get_tiling, 0, sizeof(get_tiling));
823 get_tiling.handle = bo_gem->gem_handle;
824 ret = drmIoctl(bufmgr_gem->fd,
825 DRM_IOCTL_I915_GEM_GET_TILING,
826 &get_tiling);
827 if (ret != 0) {
828 drm_intel_gem_bo_unreference(&bo_gem->bo);
829 return NULL;
830 }
831 bo_gem->tiling_mode = get_tiling.tiling_mode;
832 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
833 /* XXX stride is unknown */
834 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
836 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
838 return &bo_gem->bo;
839 }
841 static void
842 drm_intel_gem_bo_free(drm_intel_bo *bo)
843 {
844 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
845 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
846 struct drm_gem_close close;
847 int ret;
849 if (bo_gem->mem_virtual)
850 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
851 if (bo_gem->gtt_virtual)
852 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
854 /* Close this object */
855 memset(&close, 0, sizeof(close));
856 close.handle = bo_gem->gem_handle;
857 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
858 if (ret != 0) {
859 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
860 bo_gem->gem_handle, bo_gem->name, strerror(errno));
861 }
862 free(bo);
863 }
865 /** Frees all cached buffers significantly older than @time. */
866 static void
867 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
868 {
869 int i;
871 if (bufmgr_gem->time == time)
872 return;
874 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
875 struct drm_intel_gem_bo_bucket *bucket =
876 &bufmgr_gem->cache_bucket[i];
878 while (!DRMLISTEMPTY(&bucket->head)) {
879 drm_intel_bo_gem *bo_gem;
881 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
882 bucket->head.next, head);
883 if (time - bo_gem->free_time <= 1)
884 break;
886 DRMLISTDEL(&bo_gem->head);
888 drm_intel_gem_bo_free(&bo_gem->bo);
889 }
890 }
892 bufmgr_gem->time = time;
893 }
895 static void
896 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
897 {
898 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
899 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
900 struct drm_intel_gem_bo_bucket *bucket;
901 int i;
903 /* Unreference all the target buffers */
904 for (i = 0; i < bo_gem->reloc_count; i++) {
905 if (bo_gem->reloc_target_info[i].bo != bo) {
906 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
907 reloc_target_info[i].bo,
908 time);
909 }
910 }
911 bo_gem->reloc_count = 0;
912 bo_gem->used_as_reloc_target = 0;
914 DBG("bo_unreference final: %d (%s)\n",
915 bo_gem->gem_handle, bo_gem->name);
917 /* release memory associated with this object */
918 if (bo_gem->reloc_target_info) {
919 free(bo_gem->reloc_target_info);
920 bo_gem->reloc_target_info = NULL;
921 }
922 if (bo_gem->relocs) {
923 free(bo_gem->relocs);
924 bo_gem->relocs = NULL;
925 }
927 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
928 /* Put the buffer into our internal cache for reuse if we can. */
929 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
930 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
931 I915_MADV_DONTNEED)) {
932 bo_gem->free_time = time;
934 bo_gem->name = NULL;
935 bo_gem->validate_index = -1;
937 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
938 } else {
939 drm_intel_gem_bo_free(bo);
940 }
941 }
943 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
944 time_t time)
945 {
946 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
948 assert(atomic_read(&bo_gem->refcount) > 0);
949 if (atomic_dec_and_test(&bo_gem->refcount))
950 drm_intel_gem_bo_unreference_final(bo, time);
951 }
953 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
954 {
955 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
957 assert(atomic_read(&bo_gem->refcount) > 0);
958 if (atomic_dec_and_test(&bo_gem->refcount)) {
959 drm_intel_bufmgr_gem *bufmgr_gem =
960 (drm_intel_bufmgr_gem *) bo->bufmgr;
961 struct timespec time;
963 clock_gettime(CLOCK_MONOTONIC, &time);
965 pthread_mutex_lock(&bufmgr_gem->lock);
966 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
967 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
968 pthread_mutex_unlock(&bufmgr_gem->lock);
969 }
970 }
972 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
973 {
974 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
975 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
976 struct drm_i915_gem_set_domain set_domain;
977 int ret;
979 pthread_mutex_lock(&bufmgr_gem->lock);
981 /* Allow recursive mapping. Mesa may recursively map buffers with
982 * nested display loops.
983 */
984 if (!bo_gem->mem_virtual) {
985 struct drm_i915_gem_mmap mmap_arg;
987 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
989 memset(&mmap_arg, 0, sizeof(mmap_arg));
990 mmap_arg.handle = bo_gem->gem_handle;
991 mmap_arg.offset = 0;
992 mmap_arg.size = bo->size;
993 ret = drmIoctl(bufmgr_gem->fd,
994 DRM_IOCTL_I915_GEM_MMAP,
995 &mmap_arg);
996 if (ret != 0) {
997 ret = -errno;
998 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
999 __FILE__, __LINE__, bo_gem->gem_handle,
1000 bo_gem->name, strerror(errno));
1001 pthread_mutex_unlock(&bufmgr_gem->lock);
1002 return ret;
1003 }
1004 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1005 }
1006 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1007 bo_gem->mem_virtual);
1008 bo->virtual = bo_gem->mem_virtual;
1010 set_domain.handle = bo_gem->gem_handle;
1011 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1012 if (write_enable)
1013 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1014 else
1015 set_domain.write_domain = 0;
1016 ret = drmIoctl(bufmgr_gem->fd,
1017 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1018 &set_domain);
1019 if (ret != 0) {
1020 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1021 __FILE__, __LINE__, bo_gem->gem_handle,
1022 strerror(errno));
1023 }
1025 pthread_mutex_unlock(&bufmgr_gem->lock);
1027 return 0;
1028 }
1030 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1031 {
1032 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1033 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1034 struct drm_i915_gem_set_domain set_domain;
1035 int ret;
1037 pthread_mutex_lock(&bufmgr_gem->lock);
1039 /* Get a mapping of the buffer if we haven't before. */
1040 if (bo_gem->gtt_virtual == NULL) {
1041 struct drm_i915_gem_mmap_gtt mmap_arg;
1043 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1044 bo_gem->name);
1046 memset(&mmap_arg, 0, sizeof(mmap_arg));
1047 mmap_arg.handle = bo_gem->gem_handle;
1049 /* Get the fake offset back... */
1050 ret = drmIoctl(bufmgr_gem->fd,
1051 DRM_IOCTL_I915_GEM_MMAP_GTT,
1052 &mmap_arg);
1053 if (ret != 0) {
1054 ret = -errno;
1055 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1056 __FILE__, __LINE__,
1057 bo_gem->gem_handle, bo_gem->name,
1058 strerror(errno));
1059 pthread_mutex_unlock(&bufmgr_gem->lock);
1060 return ret;
1061 }
1063 /* and mmap it */
1064 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1065 MAP_SHARED, bufmgr_gem->fd,
1066 mmap_arg.offset);
1067 if (bo_gem->gtt_virtual == MAP_FAILED) {
1068 bo_gem->gtt_virtual = NULL;
1069 ret = -errno;
1070 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1071 __FILE__, __LINE__,
1072 bo_gem->gem_handle, bo_gem->name,
1073 strerror(errno));
1074 pthread_mutex_unlock(&bufmgr_gem->lock);
1075 return ret;
1076 }
1077 }
1079 bo->virtual = bo_gem->gtt_virtual;
1081 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1082 bo_gem->gtt_virtual);
1084 /* Now move it to the GTT domain so that the CPU caches are flushed */
1085 set_domain.handle = bo_gem->gem_handle;
1086 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1087 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1088 ret = drmIoctl(bufmgr_gem->fd,
1089 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1090 &set_domain);
1091 if (ret != 0) {
1092 DBG("%s:%d: Error setting domain %d: %s\n",
1093 __FILE__, __LINE__, bo_gem->gem_handle,
1094 strerror(errno));
1095 }
1097 pthread_mutex_unlock(&bufmgr_gem->lock);
1099 return 0;
1100 }
1102 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1103 {
1104 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1105 int ret = 0;
1107 if (bo == NULL)
1108 return 0;
1110 pthread_mutex_lock(&bufmgr_gem->lock);
1111 bo->virtual = NULL;
1112 pthread_mutex_unlock(&bufmgr_gem->lock);
1114 return ret;
1115 }
1117 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1118 {
1119 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1120 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1121 struct drm_i915_gem_sw_finish sw_finish;
1122 int ret;
1124 if (bo == NULL)
1125 return 0;
1127 pthread_mutex_lock(&bufmgr_gem->lock);
1129 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1130 * results show up in a timely manner.
1131 */
1132 sw_finish.handle = bo_gem->gem_handle;
1133 ret = drmIoctl(bufmgr_gem->fd,
1134 DRM_IOCTL_I915_GEM_SW_FINISH,
1135 &sw_finish);
1136 ret = ret == -1 ? -errno : 0;
1138 bo->virtual = NULL;
1139 pthread_mutex_unlock(&bufmgr_gem->lock);
1141 return ret;
1142 }
1144 static int
1145 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1146 unsigned long size, const void *data)
1147 {
1148 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1149 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1150 struct drm_i915_gem_pwrite pwrite;
1151 int ret;
1153 memset(&pwrite, 0, sizeof(pwrite));
1154 pwrite.handle = bo_gem->gem_handle;
1155 pwrite.offset = offset;
1156 pwrite.size = size;
1157 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1158 ret = drmIoctl(bufmgr_gem->fd,
1159 DRM_IOCTL_I915_GEM_PWRITE,
1160 &pwrite);
1161 if (ret != 0) {
1162 ret = -errno;
1163 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1164 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1165 (int)size, strerror(errno));
1166 }
1168 return ret;
1169 }
1171 static int
1172 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1173 {
1174 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1175 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1176 int ret;
1178 get_pipe_from_crtc_id.crtc_id = crtc_id;
1179 ret = drmIoctl(bufmgr_gem->fd,
1180 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1181 &get_pipe_from_crtc_id);
1182 if (ret != 0) {
1183 /* We return -1 here to signal that we don't
1184 * know which pipe is associated with this crtc.
1185 * This lets the caller know that this information
1186 * isn't available; using the wrong pipe for
1187 * vblank waiting can cause the chipset to lock up
1188 */
1189 return -1;
1190 }
1192 return get_pipe_from_crtc_id.pipe;
1193 }
1195 static int
1196 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1197 unsigned long size, void *data)
1198 {
1199 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1200 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1201 struct drm_i915_gem_pread pread;
1202 int ret;
1204 memset(&pread, 0, sizeof(pread));
1205 pread.handle = bo_gem->gem_handle;
1206 pread.offset = offset;
1207 pread.size = size;
1208 pread.data_ptr = (uint64_t) (uintptr_t) data;
1209 ret = drmIoctl(bufmgr_gem->fd,
1210 DRM_IOCTL_I915_GEM_PREAD,
1211 &pread);
1212 if (ret != 0) {
1213 ret = -errno;
1214 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1215 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1216 (int)size, strerror(errno));
1217 }
1219 return ret;
1220 }
1222 /** Waits for all GPU rendering with the object to have completed. */
1223 static void
1224 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1225 {
1226 drm_intel_gem_bo_start_gtt_access(bo, 1);
1227 }
1229 /**
1230 * Sets the object to the GTT read and possibly write domain, used by the X
1231 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1232 *
1233 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1234 * can do tiled pixmaps this way.
1235 */
1236 void
1237 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1238 {
1239 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1240 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1241 struct drm_i915_gem_set_domain set_domain;
1242 int ret;
1244 set_domain.handle = bo_gem->gem_handle;
1245 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1246 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1247 ret = drmIoctl(bufmgr_gem->fd,
1248 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1249 &set_domain);
1250 if (ret != 0) {
1251 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1252 __FILE__, __LINE__, bo_gem->gem_handle,
1253 set_domain.read_domains, set_domain.write_domain,
1254 strerror(errno));
1255 }
1256 }
1258 static void
1259 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1260 {
1261 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1262 int i;
1264 free(bufmgr_gem->exec2_objects);
1265 free(bufmgr_gem->exec_objects);
1266 free(bufmgr_gem->exec_bos);
1268 pthread_mutex_destroy(&bufmgr_gem->lock);
1270 /* Free any cached buffer objects we were going to reuse */
1271 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1272 struct drm_intel_gem_bo_bucket *bucket =
1273 &bufmgr_gem->cache_bucket[i];
1274 drm_intel_bo_gem *bo_gem;
1276 while (!DRMLISTEMPTY(&bucket->head)) {
1277 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1278 bucket->head.next, head);
1279 DRMLISTDEL(&bo_gem->head);
1281 drm_intel_gem_bo_free(&bo_gem->bo);
1282 }
1283 }
1285 free(bufmgr);
1286 }
1288 /**
1289 * Adds the target buffer to the validation list and adds the relocation
1290 * to the reloc_buffer's relocation list.
1291 *
1292 * The relocation entry at the given offset must already contain the
1293 * precomputed relocation value, because the kernel will optimize out
1294 * the relocation entry write when the buffer hasn't moved from the
1295 * last known offset in target_bo.
1296 */
1297 static int
1298 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1299 drm_intel_bo *target_bo, uint32_t target_offset,
1300 uint32_t read_domains, uint32_t write_domain,
1301 int need_fence)
1302 {
1303 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1304 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1305 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1306 int fenced_command;
1308 if (bo_gem->has_error)
1309 return -ENOMEM;
1311 if (target_bo_gem->has_error) {
1312 bo_gem->has_error = 1;
1313 return -ENOMEM;
1314 }
1316 /* We never use HW fences for rendering on 965+ */
1317 if (bufmgr_gem->gen >= 4)
1318 need_fence = 0;
1320 fenced_command = need_fence;
1321 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1322 need_fence = 0;
1324 /* Create a new relocation list if needed */
1325 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1326 return -ENOMEM;
1328 /* Check overflow */
1329 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1331 /* Check args */
1332 assert(offset <= bo->size - 4);
1333 assert((write_domain & (write_domain - 1)) == 0);
1335 /* Make sure that we're not adding a reloc to something whose size has
1336 * already been accounted for.
1337 */
1338 assert(!bo_gem->used_as_reloc_target);
1339 if (target_bo_gem != bo_gem) {
1340 target_bo_gem->used_as_reloc_target = 1;
1341 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1342 }
1343 /* An object needing a fence is a tiled buffer, so it won't have
1344 * relocs to other buffers.
1345 */
1346 if (need_fence)
1347 target_bo_gem->reloc_tree_fences = 1;
1348 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1350 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1351 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1352 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1353 target_bo_gem->gem_handle;
1354 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1355 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1356 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1358 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1359 if (target_bo != bo)
1360 drm_intel_gem_bo_reference(target_bo);
1361 if (fenced_command)
1362 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1363 DRM_INTEL_RELOC_FENCE;
1364 else
1365 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1367 bo_gem->reloc_count++;
1369 return 0;
1370 }
1372 static int
1373 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1374 drm_intel_bo *target_bo, uint32_t target_offset,
1375 uint32_t read_domains, uint32_t write_domain)
1376 {
1377 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1379 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1380 read_domains, write_domain,
1381 !bufmgr_gem->fenced_relocs);
1382 }
1384 static int
1385 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1386 drm_intel_bo *target_bo,
1387 uint32_t target_offset,
1388 uint32_t read_domains, uint32_t write_domain)
1389 {
1390 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1391 read_domains, write_domain, 1);
1392 }
1394 /**
1395 * Walk the tree of relocations rooted at BO and accumulate the list of
1396 * validations to be performed and update the relocation buffers with
1397 * index values into the validation list.
1398 */
1399 static void
1400 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1401 {
1402 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1403 int i;
1405 if (bo_gem->relocs == NULL)
1406 return;
1408 for (i = 0; i < bo_gem->reloc_count; i++) {
1409 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1411 if (target_bo == bo)
1412 continue;
1414 /* Continue walking the tree depth-first. */
1415 drm_intel_gem_bo_process_reloc(target_bo);
1417 /* Add the target to the validate list */
1418 drm_intel_add_validate_buffer(target_bo);
1419 }
1420 }
1422 static void
1423 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1424 {
1425 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1426 int i;
1428 if (bo_gem->relocs == NULL)
1429 return;
1431 for (i = 0; i < bo_gem->reloc_count; i++) {
1432 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1433 int need_fence;
1435 if (target_bo == bo)
1436 continue;
1438 /* Continue walking the tree depth-first. */
1439 drm_intel_gem_bo_process_reloc2(target_bo);
1441 need_fence = (bo_gem->reloc_target_info[i].flags &
1442 DRM_INTEL_RELOC_FENCE);
1444 /* Add the target to the validate list */
1445 drm_intel_add_validate_buffer2(target_bo, need_fence);
1446 }
1447 }
1450 static void
1451 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1452 {
1453 int i;
1455 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1456 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1457 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1459 /* Update the buffer offset */
1460 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1461 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1462 bo_gem->gem_handle, bo_gem->name, bo->offset,
1463 (unsigned long long)bufmgr_gem->exec_objects[i].
1464 offset);
1465 bo->offset = bufmgr_gem->exec_objects[i].offset;
1466 }
1467 }
1468 }
1470 static void
1471 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1472 {
1473 int i;
1475 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1476 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1477 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1479 /* Update the buffer offset */
1480 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1481 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1482 bo_gem->gem_handle, bo_gem->name, bo->offset,
1483 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1484 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1485 }
1486 }
1487 }
1489 static int
1490 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1491 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1492 {
1493 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1494 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1495 struct drm_i915_gem_execbuffer execbuf;
1496 int ret, i;
1498 if (bo_gem->has_error)
1499 return -ENOMEM;
1501 pthread_mutex_lock(&bufmgr_gem->lock);
1502 /* Update indices and set up the validate list. */
1503 drm_intel_gem_bo_process_reloc(bo);
1505 /* Add the batch buffer to the validation list. There are no
1506 * relocations pointing to it.
1507 */
1508 drm_intel_add_validate_buffer(bo);
1510 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1511 execbuf.buffer_count = bufmgr_gem->exec_count;
1512 execbuf.batch_start_offset = 0;
1513 execbuf.batch_len = used;
1514 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1515 execbuf.num_cliprects = num_cliprects;
1516 execbuf.DR1 = 0;
1517 execbuf.DR4 = DR4;
1519 ret = drmIoctl(bufmgr_gem->fd,
1520 DRM_IOCTL_I915_GEM_EXECBUFFER,
1521 &execbuf);
1522 if (ret != 0) {
1523 ret = -errno;
1524 if (errno == ENOSPC) {
1525 DBG("Execbuffer fails to pin. "
1526 "Estimate: %u. Actual: %u. Available: %u\n",
1527 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1528 bufmgr_gem->
1529 exec_count),
1530 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1531 bufmgr_gem->
1532 exec_count),
1533 (unsigned int)bufmgr_gem->gtt_size);
1534 }
1535 }
1536 drm_intel_update_buffer_offsets(bufmgr_gem);
1538 if (bufmgr_gem->bufmgr.debug)
1539 drm_intel_gem_dump_validation_list(bufmgr_gem);
1541 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1542 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1543 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1545 /* Disconnect the buffer from the validate list */
1546 bo_gem->validate_index = -1;
1547 bufmgr_gem->exec_bos[i] = NULL;
1548 }
1549 bufmgr_gem->exec_count = 0;
1550 pthread_mutex_unlock(&bufmgr_gem->lock);
1552 return ret;
1553 }
1555 static int
1556 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1557 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1558 unsigned int flags)
1559 {
1560 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1561 struct drm_i915_gem_execbuffer2 execbuf;
1562 int ret, i;
1564 switch (flags & 0x7) {
1565 default:
1566 return -EINVAL;
1567 case I915_EXEC_BLT:
1568 if (!bufmgr_gem->has_blt)
1569 return -EINVAL;
1570 break;
1571 case I915_EXEC_BSD:
1572 if (!bufmgr_gem->has_bsd)
1573 return -EINVAL;
1574 break;
1575 case I915_EXEC_RENDER:
1576 case I915_EXEC_DEFAULT:
1577 break;
1578 }
1580 pthread_mutex_lock(&bufmgr_gem->lock);
1581 /* Update indices and set up the validate list. */
1582 drm_intel_gem_bo_process_reloc2(bo);
1584 /* Add the batch buffer to the validation list. There are no relocations
1585 * pointing to it.
1586 */
1587 drm_intel_add_validate_buffer2(bo, 0);
1589 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1590 execbuf.buffer_count = bufmgr_gem->exec_count;
1591 execbuf.batch_start_offset = 0;
1592 execbuf.batch_len = used;
1593 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1594 execbuf.num_cliprects = num_cliprects;
1595 execbuf.DR1 = 0;
1596 execbuf.DR4 = DR4;
1597 execbuf.flags = flags;
1598 execbuf.rsvd1 = 0;
1599 execbuf.rsvd2 = 0;
1601 ret = drmIoctl(bufmgr_gem->fd,
1602 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1603 &execbuf);
1604 if (ret != 0) {
1605 ret = -errno;
1606 if (ret == -ENOSPC) {
1607 DBG("Execbuffer fails to pin. "
1608 "Estimate: %u. Actual: %u. Available: %u\n",
1609 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1610 bufmgr_gem->exec_count),
1611 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1612 bufmgr_gem->exec_count),
1613 (unsigned int) bufmgr_gem->gtt_size);
1614 }
1615 }
1616 drm_intel_update_buffer_offsets2(bufmgr_gem);
1618 if (bufmgr_gem->bufmgr.debug)
1619 drm_intel_gem_dump_validation_list(bufmgr_gem);
1621 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1622 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1623 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1625 /* Disconnect the buffer from the validate list */
1626 bo_gem->validate_index = -1;
1627 bufmgr_gem->exec_bos[i] = NULL;
1628 }
1629 bufmgr_gem->exec_count = 0;
1630 pthread_mutex_unlock(&bufmgr_gem->lock);
1632 return ret;
1633 }
1635 static int
1636 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1637 drm_clip_rect_t *cliprects, int num_cliprects,
1638 int DR4)
1639 {
1640 return drm_intel_gem_bo_mrb_exec2(bo, used,
1641 cliprects, num_cliprects, DR4,
1642 I915_EXEC_RENDER);
1643 }
1645 static int
1646 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1647 {
1648 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1649 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1650 struct drm_i915_gem_pin pin;
1651 int ret;
1653 memset(&pin, 0, sizeof(pin));
1654 pin.handle = bo_gem->gem_handle;
1655 pin.alignment = alignment;
1657 ret = drmIoctl(bufmgr_gem->fd,
1658 DRM_IOCTL_I915_GEM_PIN,
1659 &pin);
1660 if (ret != 0)
1661 return -errno;
1663 bo->offset = pin.offset;
1664 return 0;
1665 }
1667 static int
1668 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1669 {
1670 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1671 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1672 struct drm_i915_gem_unpin unpin;
1673 int ret;
1675 memset(&unpin, 0, sizeof(unpin));
1676 unpin.handle = bo_gem->gem_handle;
1678 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1679 if (ret != 0)
1680 return -errno;
1682 return 0;
1683 }
1685 static int
1686 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1687 uint32_t tiling_mode,
1688 uint32_t stride)
1689 {
1690 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1691 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1692 struct drm_i915_gem_set_tiling set_tiling;
1693 int ret;
1695 if (bo_gem->global_name == 0 &&
1696 tiling_mode == bo_gem->tiling_mode &&
1697 stride == bo_gem->stride)
1698 return 0;
1700 memset(&set_tiling, 0, sizeof(set_tiling));
1701 do {
1702 /* set_tiling is slightly broken and overwrites the
1703 * input on the error path, so we have to open code
1704 * rmIoctl.
1705 */
1706 set_tiling.handle = bo_gem->gem_handle;
1707 set_tiling.tiling_mode = tiling_mode;
1708 set_tiling.stride = stride;
1710 ret = ioctl(bufmgr_gem->fd,
1711 DRM_IOCTL_I915_GEM_SET_TILING,
1712 &set_tiling);
1713 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1714 if (ret == -1)
1715 return -errno;
1717 bo_gem->tiling_mode = set_tiling.tiling_mode;
1718 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1719 bo_gem->stride = set_tiling.stride;
1720 return 0;
1721 }
1723 static int
1724 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1725 uint32_t stride)
1726 {
1727 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1728 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1729 int ret;
1731 /* Linear buffers have no stride. By ensuring that we only ever use
1732 * stride 0 with linear buffers, we simplify our code.
1733 */
1734 if (*tiling_mode == I915_TILING_NONE)
1735 stride = 0;
1737 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1738 if (ret == 0)
1739 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1741 *tiling_mode = bo_gem->tiling_mode;
1742 return ret;
1743 }
1745 static int
1746 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1747 uint32_t * swizzle_mode)
1748 {
1749 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1751 *tiling_mode = bo_gem->tiling_mode;
1752 *swizzle_mode = bo_gem->swizzle_mode;
1753 return 0;
1754 }
1756 static int
1757 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1758 {
1759 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1760 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1761 struct drm_gem_flink flink;
1762 int ret;
1764 if (!bo_gem->global_name) {
1765 memset(&flink, 0, sizeof(flink));
1766 flink.handle = bo_gem->gem_handle;
1768 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1769 if (ret != 0)
1770 return -errno;
1771 bo_gem->global_name = flink.name;
1772 bo_gem->reusable = 0;
1773 }
1775 *name = bo_gem->global_name;
1776 return 0;
1777 }
1779 /**
1780 * Enables unlimited caching of buffer objects for reuse.
1781 *
1782 * This is potentially very memory expensive, as the cache at each bucket
1783 * size is only bounded by how many buffers of that size we've managed to have
1784 * in flight at once.
1785 */
1786 void
1787 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1788 {
1789 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1791 bufmgr_gem->bo_reuse = 1;
1792 }
1794 /**
1795 * Enable use of fenced reloc type.
1796 *
1797 * New code should enable this to avoid unnecessary fence register
1798 * allocation. If this option is not enabled, all relocs will have fence
1799 * register allocated.
1800 */
1801 void
1802 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1803 {
1804 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1806 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1807 bufmgr_gem->fenced_relocs = 1;
1808 }
1810 /**
1811 * Return the additional aperture space required by the tree of buffer objects
1812 * rooted at bo.
1813 */
1814 static int
1815 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1816 {
1817 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1818 int i;
1819 int total = 0;
1821 if (bo == NULL || bo_gem->included_in_check_aperture)
1822 return 0;
1824 total += bo->size;
1825 bo_gem->included_in_check_aperture = 1;
1827 for (i = 0; i < bo_gem->reloc_count; i++)
1828 total +=
1829 drm_intel_gem_bo_get_aperture_space(bo_gem->
1830 reloc_target_info[i].bo);
1832 return total;
1833 }
1835 /**
1836 * Count the number of buffers in this list that need a fence reg
1837 *
1838 * If the count is greater than the number of available regs, we'll have
1839 * to ask the caller to resubmit a batch with fewer tiled buffers.
1840 *
1841 * This function over-counts if the same buffer is used multiple times.
1842 */
1843 static unsigned int
1844 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1845 {
1846 int i;
1847 unsigned int total = 0;
1849 for (i = 0; i < count; i++) {
1850 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1852 if (bo_gem == NULL)
1853 continue;
1855 total += bo_gem->reloc_tree_fences;
1856 }
1857 return total;
1858 }
1860 /**
1861 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1862 * for the next drm_intel_bufmgr_check_aperture_space() call.
1863 */
1864 static void
1865 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1866 {
1867 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1868 int i;
1870 if (bo == NULL || !bo_gem->included_in_check_aperture)
1871 return;
1873 bo_gem->included_in_check_aperture = 0;
1875 for (i = 0; i < bo_gem->reloc_count; i++)
1876 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1877 reloc_target_info[i].bo);
1878 }
1880 /**
1881 * Return a conservative estimate for the amount of aperture required
1882 * for a collection of buffers. This may double-count some buffers.
1883 */
1884 static unsigned int
1885 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1886 {
1887 int i;
1888 unsigned int total = 0;
1890 for (i = 0; i < count; i++) {
1891 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1892 if (bo_gem != NULL)
1893 total += bo_gem->reloc_tree_size;
1894 }
1895 return total;
1896 }
1898 /**
1899 * Return the amount of aperture needed for a collection of buffers.
1900 * This avoids double counting any buffers, at the cost of looking
1901 * at every buffer in the set.
1902 */
1903 static unsigned int
1904 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1905 {
1906 int i;
1907 unsigned int total = 0;
1909 for (i = 0; i < count; i++) {
1910 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1911 /* For the first buffer object in the array, we get an
1912 * accurate count back for its reloc_tree size (since nothing
1913 * had been flagged as being counted yet). We can save that
1914 * value out as a more conservative reloc_tree_size that
1915 * avoids double-counting target buffers. Since the first
1916 * buffer happens to usually be the batch buffer in our
1917 * callers, this can pull us back from doing the tree
1918 * walk on every new batch emit.
1919 */
1920 if (i == 0) {
1921 drm_intel_bo_gem *bo_gem =
1922 (drm_intel_bo_gem *) bo_array[i];
1923 bo_gem->reloc_tree_size = total;
1924 }
1925 }
1927 for (i = 0; i < count; i++)
1928 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1929 return total;
1930 }
1932 /**
1933 * Return -1 if the batchbuffer should be flushed before attempting to
1934 * emit rendering referencing the buffers pointed to by bo_array.
1935 *
1936 * This is required because if we try to emit a batchbuffer with relocations
1937 * to a tree of buffers that won't simultaneously fit in the aperture,
1938 * the rendering will return an error at a point where the software is not
1939 * prepared to recover from it.
1940 *
1941 * However, we also want to emit the batchbuffer significantly before we reach
1942 * the limit, as a series of batchbuffers each of which references buffers
1943 * covering almost all of the aperture means that at each emit we end up
1944 * waiting to evict a buffer from the last rendering, and we get synchronous
1945 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1946 * get better parallelism.
1947 */
1948 static int
1949 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1950 {
1951 drm_intel_bufmgr_gem *bufmgr_gem =
1952 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1953 unsigned int total = 0;
1954 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1955 int total_fences;
1957 /* Check for fence reg constraints if necessary */
1958 if (bufmgr_gem->available_fences) {
1959 total_fences = drm_intel_gem_total_fences(bo_array, count);
1960 if (total_fences > bufmgr_gem->available_fences)
1961 return -ENOSPC;
1962 }
1964 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1966 if (total > threshold)
1967 total = drm_intel_gem_compute_batch_space(bo_array, count);
1969 if (total > threshold) {
1970 DBG("check_space: overflowed available aperture, "
1971 "%dkb vs %dkb\n",
1972 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1973 return -ENOSPC;
1974 } else {
1975 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1976 (int)bufmgr_gem->gtt_size / 1024);
1977 return 0;
1978 }
1979 }
1981 /*
1982 * Disable buffer reuse for objects which are shared with the kernel
1983 * as scanout buffers
1984 */
1985 static int
1986 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1987 {
1988 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1990 bo_gem->reusable = 0;
1991 return 0;
1992 }
1994 static int
1995 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
1996 {
1997 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1999 return bo_gem->reusable;
2000 }
2002 static int
2003 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2004 {
2005 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2006 int i;
2008 for (i = 0; i < bo_gem->reloc_count; i++) {
2009 if (bo_gem->reloc_target_info[i].bo == target_bo)
2010 return 1;
2011 if (bo == bo_gem->reloc_target_info[i].bo)
2012 continue;
2013 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2014 target_bo))
2015 return 1;
2016 }
2018 return 0;
2019 }
2021 /** Return true if target_bo is referenced by bo's relocation tree. */
2022 static int
2023 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2024 {
2025 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2027 if (bo == NULL || target_bo == NULL)
2028 return 0;
2029 if (target_bo_gem->used_as_reloc_target)
2030 return _drm_intel_gem_bo_references(bo, target_bo);
2031 return 0;
2032 }
2034 static void
2035 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2036 {
2037 unsigned int i = bufmgr_gem->num_buckets;
2039 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2041 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2042 bufmgr_gem->cache_bucket[i].size = size;
2043 bufmgr_gem->num_buckets++;
2044 }
2046 static void
2047 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2048 {
2049 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2051 /* OK, so power of two buckets was too wasteful of memory.
2052 * Give 3 other sizes between each power of two, to hopefully
2053 * cover things accurately enough. (The alternative is
2054 * probably to just go for exact matching of sizes, and assume
2055 * that for things like composited window resize the tiled
2056 * width/height alignment and rounding of sizes to pages will
2057 * get us useful cache hit rates anyway)
2058 */
2059 add_bucket(bufmgr_gem, 4096);
2060 add_bucket(bufmgr_gem, 4096 * 2);
2061 add_bucket(bufmgr_gem, 4096 * 3);
2063 /* Initialize the linked lists for BO reuse cache. */
2064 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2065 add_bucket(bufmgr_gem, size);
2067 add_bucket(bufmgr_gem, size + size * 1 / 4);
2068 add_bucket(bufmgr_gem, size + size * 2 / 4);
2069 add_bucket(bufmgr_gem, size + size * 3 / 4);
2070 }
2071 }
2073 /**
2074 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2075 * and manage map buffer objections.
2076 *
2077 * \param fd File descriptor of the opened DRM device.
2078 */
2079 drm_intel_bufmgr *
2080 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2081 {
2082 drm_intel_bufmgr_gem *bufmgr_gem;
2083 struct drm_i915_gem_get_aperture aperture;
2084 drm_i915_getparam_t gp;
2085 int ret;
2086 int exec2 = 0;
2088 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2089 if (bufmgr_gem == NULL)
2090 return NULL;
2092 bufmgr_gem->fd = fd;
2094 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2095 free(bufmgr_gem);
2096 return NULL;
2097 }
2099 ret = drmIoctl(bufmgr_gem->fd,
2100 DRM_IOCTL_I915_GEM_GET_APERTURE,
2101 &aperture);
2103 if (ret == 0)
2104 bufmgr_gem->gtt_size = aperture.aper_available_size;
2105 else {
2106 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2107 strerror(errno));
2108 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2109 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2110 "May lead to reduced performance or incorrect "
2111 "rendering.\n",
2112 (int)bufmgr_gem->gtt_size / 1024);
2113 }
2115 gp.param = I915_PARAM_CHIPSET_ID;
2116 gp.value = &bufmgr_gem->pci_device;
2117 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2118 if (ret) {
2119 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2120 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2121 }
2123 if (IS_GEN2(bufmgr_gem))
2124 bufmgr_gem->gen = 2;
2125 else if (IS_GEN3(bufmgr_gem))
2126 bufmgr_gem->gen = 3;
2127 else if (IS_GEN4(bufmgr_gem))
2128 bufmgr_gem->gen = 4;
2129 else
2130 bufmgr_gem->gen = 6;
2132 gp.param = I915_PARAM_HAS_EXECBUF2;
2133 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2134 if (!ret)
2135 exec2 = 1;
2137 gp.param = I915_PARAM_HAS_BSD;
2138 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2139 bufmgr_gem->has_bsd = ret == 0;
2141 gp.param = I915_PARAM_HAS_BLT;
2142 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2143 bufmgr_gem->has_blt = ret == 0;
2145 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2146 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2147 bufmgr_gem->has_relaxed_fencing = ret == 0;
2149 if (bufmgr_gem->gen < 4) {
2150 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2151 gp.value = &bufmgr_gem->available_fences;
2152 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2153 if (ret) {
2154 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2155 errno);
2156 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2157 *gp.value);
2158 bufmgr_gem->available_fences = 0;
2159 } else {
2160 /* XXX The kernel reports the total number of fences,
2161 * including any that may be pinned.
2162 *
2163 * We presume that there will be at least one pinned
2164 * fence for the scanout buffer, but there may be more
2165 * than one scanout and the user may be manually
2166 * pinning buffers. Let's move to execbuffer2 and
2167 * thereby forget the insanity of using fences...
2168 */
2169 bufmgr_gem->available_fences -= 2;
2170 if (bufmgr_gem->available_fences < 0)
2171 bufmgr_gem->available_fences = 0;
2172 }
2173 }
2175 /* Let's go with one relocation per every 2 dwords (but round down a bit
2176 * since a power of two will mean an extra page allocation for the reloc
2177 * buffer).
2178 *
2179 * Every 4 was too few for the blender benchmark.
2180 */
2181 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2183 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2184 bufmgr_gem->bufmgr.bo_alloc_for_render =
2185 drm_intel_gem_bo_alloc_for_render;
2186 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2187 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2188 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2189 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2190 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2191 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2192 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2193 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2194 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2195 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2196 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2197 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2198 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2199 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2200 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2201 /* Use the new one if available */
2202 if (exec2) {
2203 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2204 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2205 } else
2206 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2207 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2208 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2209 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2210 bufmgr_gem->bufmgr.debug = 0;
2211 bufmgr_gem->bufmgr.check_aperture_space =
2212 drm_intel_gem_check_aperture_space;
2213 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2214 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2215 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2216 drm_intel_gem_get_pipe_from_crtc_id;
2217 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2219 init_cache_buckets(bufmgr_gem);
2221 return &bufmgr_gem->bufmgr;
2222 }