1 /**************************************************************************
2 *
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
26 * of the Software.
27 *
28 *
29 **************************************************************************/
30 /*
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
35 */
37 #ifdef HAVE_CONFIG_H
38 #include "config.h"
39 #endif
41 #include <xf86drm.h>
42 #include <xf86atomic.h>
43 #include <fcntl.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <string.h>
47 #include <unistd.h>
48 #include <assert.h>
49 #include <pthread.h>
50 #include <sys/ioctl.h>
51 #include <sys/mman.h>
52 #include <sys/stat.h>
53 #include <sys/types.h>
54 #include <stdbool.h>
56 #include "errno.h"
57 #include "libdrm_lists.h"
58 #include "intel_bufmgr.h"
59 #include "intel_bufmgr_priv.h"
60 #include "intel_chipset.h"
61 #include "string.h"
63 #include "i915_drm.h"
65 #define DBG(...) do { \
66 if (bufmgr_gem->bufmgr.debug) \
67 fprintf(stderr, __VA_ARGS__); \
68 } while (0)
70 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
72 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
74 struct drm_intel_gem_bo_bucket {
75 drmMMListHead head;
76 unsigned long size;
77 };
79 typedef struct _drm_intel_bufmgr_gem {
80 drm_intel_bufmgr bufmgr;
82 int fd;
84 int max_relocs;
86 pthread_mutex_t lock;
88 struct drm_i915_gem_exec_object *exec_objects;
89 struct drm_i915_gem_exec_object2 *exec2_objects;
90 drm_intel_bo **exec_bos;
91 int exec_size;
92 int exec_count;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[14 * 4];
96 int num_buckets;
97 time_t time;
99 drmMMListHead named;
101 uint64_t gtt_size;
102 int available_fences;
103 int pci_device;
104 int gen;
105 unsigned int has_bsd : 1;
106 unsigned int has_blt : 1;
107 unsigned int has_relaxed_fencing : 1;
108 unsigned int bo_reuse : 1;
109 bool fenced_relocs;
110 } drm_intel_bufmgr_gem;
112 #define DRM_INTEL_RELOC_FENCE (1<<0)
114 typedef struct _drm_intel_reloc_target_info {
115 drm_intel_bo *bo;
116 int flags;
117 } drm_intel_reloc_target;
119 struct _drm_intel_bo_gem {
120 drm_intel_bo bo;
122 atomic_t refcount;
123 uint32_t gem_handle;
124 const char *name;
126 /**
127 * Kenel-assigned global name for this object
128 */
129 unsigned int global_name;
130 drmMMListHead name_list;
132 /**
133 * Index of the buffer within the validation list while preparing a
134 * batchbuffer execution.
135 */
136 int validate_index;
138 /**
139 * Current tiling mode
140 */
141 uint32_t tiling_mode;
142 uint32_t swizzle_mode;
143 unsigned long stride;
145 time_t free_time;
147 /** Array passed to the DRM containing relocation information. */
148 struct drm_i915_gem_relocation_entry *relocs;
149 /**
150 * Array of info structs corresponding to relocs[i].target_handle etc
151 */
152 drm_intel_reloc_target *reloc_target_info;
153 /** Number of entries in relocs */
154 int reloc_count;
155 /** Mapped address for the buffer, saved across map/unmap cycles */
156 void *mem_virtual;
157 /** GTT virtual address for the buffer, saved across map/unmap cycles */
158 void *gtt_virtual;
160 /** BO cache list */
161 drmMMListHead head;
163 /**
164 * Boolean of whether this BO and its children have been included in
165 * the current drm_intel_bufmgr_check_aperture_space() total.
166 */
167 bool included_in_check_aperture;
169 /**
170 * Boolean of whether this buffer has been used as a relocation
171 * target and had its size accounted for, and thus can't have any
172 * further relocations added to it.
173 */
174 bool used_as_reloc_target;
176 /**
177 * Boolean of whether we have encountered an error whilst building the relocation tree.
178 */
179 bool has_error;
181 /**
182 * Boolean of whether this buffer can be re-used
183 */
184 bool reusable;
186 /**
187 * Size in bytes of this buffer and its relocation descendents.
188 *
189 * Used to avoid costly tree walking in
190 * drm_intel_bufmgr_check_aperture in the common case.
191 */
192 int reloc_tree_size;
194 /**
195 * Number of potential fence registers required by this buffer and its
196 * relocations.
197 */
198 int reloc_tree_fences;
199 };
201 static unsigned int
202 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
204 static unsigned int
205 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
207 static int
208 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
209 uint32_t * swizzle_mode);
211 static int
212 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
213 uint32_t tiling_mode,
214 uint32_t stride);
216 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
217 time_t time);
219 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
221 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
223 static unsigned long
224 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
225 uint32_t *tiling_mode)
226 {
227 unsigned long min_size, max_size;
228 unsigned long i;
230 if (*tiling_mode == I915_TILING_NONE)
231 return size;
233 /* 965+ just need multiples of page size for tiling */
234 if (bufmgr_gem->gen >= 4)
235 return ROUND_UP_TO(size, 4096);
237 /* Older chips need powers of two, of at least 512k or 1M */
238 if (bufmgr_gem->gen == 3) {
239 min_size = 1024*1024;
240 max_size = 128*1024*1024;
241 } else {
242 min_size = 512*1024;
243 max_size = 64*1024*1024;
244 }
246 if (size > max_size) {
247 *tiling_mode = I915_TILING_NONE;
248 return size;
249 }
251 /* Do we need to allocate every page for the fence? */
252 if (bufmgr_gem->has_relaxed_fencing)
253 return ROUND_UP_TO(size, 4096);
255 for (i = min_size; i < size; i <<= 1)
256 ;
258 return i;
259 }
261 /*
262 * Round a given pitch up to the minimum required for X tiling on a
263 * given chip. We use 512 as the minimum to allow for a later tiling
264 * change.
265 */
266 static unsigned long
267 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
268 unsigned long pitch, uint32_t *tiling_mode)
269 {
270 unsigned long tile_width;
271 unsigned long i;
273 /* If untiled, then just align it so that we can do rendering
274 * to it with the 3D engine.
275 */
276 if (*tiling_mode == I915_TILING_NONE)
277 return ALIGN(pitch, 64);
279 if (*tiling_mode == I915_TILING_X
280 || (IS_915(bufmgr_gem) && *tiling_mode == I915_TILING_Y))
281 tile_width = 512;
282 else
283 tile_width = 128;
285 /* 965 is flexible */
286 if (bufmgr_gem->gen >= 4)
287 return ROUND_UP_TO(pitch, tile_width);
289 /* The older hardware has a maximum pitch of 8192 with tiled
290 * surfaces, so fallback to untiled if it's too large.
291 */
292 if (pitch > 8192) {
293 *tiling_mode = I915_TILING_NONE;
294 return ALIGN(pitch, 64);
295 }
297 /* Pre-965 needs power of two tile width */
298 for (i = tile_width; i < pitch; i <<= 1)
299 ;
301 return i;
302 }
304 static struct drm_intel_gem_bo_bucket *
305 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
306 unsigned long size)
307 {
308 int i;
310 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
311 struct drm_intel_gem_bo_bucket *bucket =
312 &bufmgr_gem->cache_bucket[i];
313 if (bucket->size >= size) {
314 return bucket;
315 }
316 }
318 return NULL;
319 }
321 static void
322 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
323 {
324 int i, j;
326 for (i = 0; i < bufmgr_gem->exec_count; i++) {
327 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
328 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
330 if (bo_gem->relocs == NULL) {
331 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
332 bo_gem->name);
333 continue;
334 }
336 for (j = 0; j < bo_gem->reloc_count; j++) {
337 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
338 drm_intel_bo_gem *target_gem =
339 (drm_intel_bo_gem *) target_bo;
341 DBG("%2d: %d (%s)@0x%08llx -> "
342 "%d (%s)@0x%08lx + 0x%08x\n",
343 i,
344 bo_gem->gem_handle, bo_gem->name,
345 (unsigned long long)bo_gem->relocs[j].offset,
346 target_gem->gem_handle,
347 target_gem->name,
348 target_bo->offset,
349 bo_gem->relocs[j].delta);
350 }
351 }
352 }
354 static inline void
355 drm_intel_gem_bo_reference(drm_intel_bo *bo)
356 {
357 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
359 atomic_inc(&bo_gem->refcount);
360 }
362 /**
363 * Adds the given buffer to the list of buffers to be validated (moved into the
364 * appropriate memory type) with the next batch submission.
365 *
366 * If a buffer is validated multiple times in a batch submission, it ends up
367 * with the intersection of the memory type flags and the union of the
368 * access flags.
369 */
370 static void
371 drm_intel_add_validate_buffer(drm_intel_bo *bo)
372 {
373 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
374 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
375 int index;
377 if (bo_gem->validate_index != -1)
378 return;
380 /* Extend the array of validation entries as necessary. */
381 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
382 int new_size = bufmgr_gem->exec_size * 2;
384 if (new_size == 0)
385 new_size = 5;
387 bufmgr_gem->exec_objects =
388 realloc(bufmgr_gem->exec_objects,
389 sizeof(*bufmgr_gem->exec_objects) * new_size);
390 bufmgr_gem->exec_bos =
391 realloc(bufmgr_gem->exec_bos,
392 sizeof(*bufmgr_gem->exec_bos) * new_size);
393 bufmgr_gem->exec_size = new_size;
394 }
396 index = bufmgr_gem->exec_count;
397 bo_gem->validate_index = index;
398 /* Fill in array entry */
399 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
400 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
401 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
402 bufmgr_gem->exec_objects[index].alignment = 0;
403 bufmgr_gem->exec_objects[index].offset = 0;
404 bufmgr_gem->exec_bos[index] = bo;
405 bufmgr_gem->exec_count++;
406 }
408 static void
409 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
410 {
411 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
412 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
413 int index;
415 if (bo_gem->validate_index != -1) {
416 if (need_fence)
417 bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |=
418 EXEC_OBJECT_NEEDS_FENCE;
419 return;
420 }
422 /* Extend the array of validation entries as necessary. */
423 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
424 int new_size = bufmgr_gem->exec_size * 2;
426 if (new_size == 0)
427 new_size = 5;
429 bufmgr_gem->exec2_objects =
430 realloc(bufmgr_gem->exec2_objects,
431 sizeof(*bufmgr_gem->exec2_objects) * new_size);
432 bufmgr_gem->exec_bos =
433 realloc(bufmgr_gem->exec_bos,
434 sizeof(*bufmgr_gem->exec_bos) * new_size);
435 bufmgr_gem->exec_size = new_size;
436 }
438 index = bufmgr_gem->exec_count;
439 bo_gem->validate_index = index;
440 /* Fill in array entry */
441 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
442 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
443 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
444 bufmgr_gem->exec2_objects[index].alignment = 0;
445 bufmgr_gem->exec2_objects[index].offset = 0;
446 bufmgr_gem->exec_bos[index] = bo;
447 bufmgr_gem->exec2_objects[index].flags = 0;
448 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
449 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
450 if (need_fence) {
451 bufmgr_gem->exec2_objects[index].flags |=
452 EXEC_OBJECT_NEEDS_FENCE;
453 }
454 bufmgr_gem->exec_count++;
455 }
457 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
458 sizeof(uint32_t))
460 static void
461 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
462 drm_intel_bo_gem *bo_gem)
463 {
464 int size;
466 assert(!bo_gem->used_as_reloc_target);
468 /* The older chipsets are far-less flexible in terms of tiling,
469 * and require tiled buffer to be size aligned in the aperture.
470 * This means that in the worst possible case we will need a hole
471 * twice as large as the object in order for it to fit into the
472 * aperture. Optimal packing is for wimps.
473 */
474 size = bo_gem->bo.size;
475 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) {
476 int min_size;
478 if (bufmgr_gem->has_relaxed_fencing) {
479 if (bufmgr_gem->gen == 3)
480 min_size = 1024*1024;
481 else
482 min_size = 512*1024;
484 while (min_size < size)
485 min_size *= 2;
486 } else
487 min_size = size;
489 /* Account for worst-case alignment. */
490 size = 2 * min_size;
491 }
493 bo_gem->reloc_tree_size = size;
494 }
496 static int
497 drm_intel_setup_reloc_list(drm_intel_bo *bo)
498 {
499 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
500 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
501 unsigned int max_relocs = bufmgr_gem->max_relocs;
503 if (bo->size / 4 < max_relocs)
504 max_relocs = bo->size / 4;
506 bo_gem->relocs = malloc(max_relocs *
507 sizeof(struct drm_i915_gem_relocation_entry));
508 bo_gem->reloc_target_info = malloc(max_relocs *
509 sizeof(drm_intel_reloc_target));
510 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
511 bo_gem->has_error = true;
513 free (bo_gem->relocs);
514 bo_gem->relocs = NULL;
516 free (bo_gem->reloc_target_info);
517 bo_gem->reloc_target_info = NULL;
519 return 1;
520 }
522 return 0;
523 }
525 static int
526 drm_intel_gem_bo_busy(drm_intel_bo *bo)
527 {
528 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
529 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
530 struct drm_i915_gem_busy busy;
531 int ret;
533 memset(&busy, 0, sizeof(busy));
534 busy.handle = bo_gem->gem_handle;
536 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
538 return (ret == 0 && busy.busy);
539 }
541 static int
542 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
543 drm_intel_bo_gem *bo_gem, int state)
544 {
545 struct drm_i915_gem_madvise madv;
547 madv.handle = bo_gem->gem_handle;
548 madv.madv = state;
549 madv.retained = 1;
550 drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
552 return madv.retained;
553 }
555 static int
556 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
557 {
558 return drm_intel_gem_bo_madvise_internal
559 ((drm_intel_bufmgr_gem *) bo->bufmgr,
560 (drm_intel_bo_gem *) bo,
561 madv);
562 }
564 /* drop the oldest entries that have been purged by the kernel */
565 static void
566 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
567 struct drm_intel_gem_bo_bucket *bucket)
568 {
569 while (!DRMLISTEMPTY(&bucket->head)) {
570 drm_intel_bo_gem *bo_gem;
572 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
573 bucket->head.next, head);
574 if (drm_intel_gem_bo_madvise_internal
575 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
576 break;
578 DRMLISTDEL(&bo_gem->head);
579 drm_intel_gem_bo_free(&bo_gem->bo);
580 }
581 }
583 static drm_intel_bo *
584 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
585 const char *name,
586 unsigned long size,
587 unsigned long flags,
588 uint32_t tiling_mode,
589 unsigned long stride)
590 {
591 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
592 drm_intel_bo_gem *bo_gem;
593 unsigned int page_size = getpagesize();
594 int ret;
595 struct drm_intel_gem_bo_bucket *bucket;
596 bool alloc_from_cache;
597 unsigned long bo_size;
598 bool for_render = false;
600 if (flags & BO_ALLOC_FOR_RENDER)
601 for_render = true;
603 /* Round the allocated size up to a power of two number of pages. */
604 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
606 /* If we don't have caching at this size, don't actually round the
607 * allocation up.
608 */
609 if (bucket == NULL) {
610 bo_size = size;
611 if (bo_size < page_size)
612 bo_size = page_size;
613 } else {
614 bo_size = bucket->size;
615 }
617 pthread_mutex_lock(&bufmgr_gem->lock);
618 /* Get a buffer out of the cache if available */
619 retry:
620 alloc_from_cache = false;
621 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
622 if (for_render) {
623 /* Allocate new render-target BOs from the tail (MRU)
624 * of the list, as it will likely be hot in the GPU
625 * cache and in the aperture for us.
626 */
627 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
628 bucket->head.prev, head);
629 DRMLISTDEL(&bo_gem->head);
630 alloc_from_cache = true;
631 } else {
632 /* For non-render-target BOs (where we're probably
633 * going to map it first thing in order to fill it
634 * with data), check if the last BO in the cache is
635 * unbusy, and only reuse in that case. Otherwise,
636 * allocating a new buffer is probably faster than
637 * waiting for the GPU to finish.
638 */
639 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
640 bucket->head.next, head);
641 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
642 alloc_from_cache = true;
643 DRMLISTDEL(&bo_gem->head);
644 }
645 }
647 if (alloc_from_cache) {
648 if (!drm_intel_gem_bo_madvise_internal
649 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
650 drm_intel_gem_bo_free(&bo_gem->bo);
651 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
652 bucket);
653 goto retry;
654 }
656 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
657 tiling_mode,
658 stride)) {
659 drm_intel_gem_bo_free(&bo_gem->bo);
660 goto retry;
661 }
662 }
663 }
664 pthread_mutex_unlock(&bufmgr_gem->lock);
666 if (!alloc_from_cache) {
667 struct drm_i915_gem_create create;
669 bo_gem = calloc(1, sizeof(*bo_gem));
670 if (!bo_gem)
671 return NULL;
673 bo_gem->bo.size = bo_size;
674 memset(&create, 0, sizeof(create));
675 create.size = bo_size;
677 ret = drmIoctl(bufmgr_gem->fd,
678 DRM_IOCTL_I915_GEM_CREATE,
679 &create);
680 bo_gem->gem_handle = create.handle;
681 bo_gem->bo.handle = bo_gem->gem_handle;
682 if (ret != 0) {
683 free(bo_gem);
684 return NULL;
685 }
686 bo_gem->bo.bufmgr = bufmgr;
688 bo_gem->tiling_mode = I915_TILING_NONE;
689 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
690 bo_gem->stride = 0;
692 if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo,
693 tiling_mode,
694 stride)) {
695 drm_intel_gem_bo_free(&bo_gem->bo);
696 return NULL;
697 }
699 DRMINITLISTHEAD(&bo_gem->name_list);
700 }
702 bo_gem->name = name;
703 atomic_set(&bo_gem->refcount, 1);
704 bo_gem->validate_index = -1;
705 bo_gem->reloc_tree_fences = 0;
706 bo_gem->used_as_reloc_target = false;
707 bo_gem->has_error = false;
708 bo_gem->reusable = true;
710 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
712 DBG("bo_create: buf %d (%s) %ldb\n",
713 bo_gem->gem_handle, bo_gem->name, size);
715 return &bo_gem->bo;
716 }
718 static drm_intel_bo *
719 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
720 const char *name,
721 unsigned long size,
722 unsigned int alignment)
723 {
724 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
725 BO_ALLOC_FOR_RENDER,
726 I915_TILING_NONE, 0);
727 }
729 static drm_intel_bo *
730 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
731 const char *name,
732 unsigned long size,
733 unsigned int alignment)
734 {
735 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0,
736 I915_TILING_NONE, 0);
737 }
739 static drm_intel_bo *
740 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
741 int x, int y, int cpp, uint32_t *tiling_mode,
742 unsigned long *pitch, unsigned long flags)
743 {
744 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
745 unsigned long size, stride;
746 uint32_t tiling;
748 do {
749 unsigned long aligned_y, height_alignment;
751 tiling = *tiling_mode;
753 /* If we're tiled, our allocations are in 8 or 32-row blocks,
754 * so failure to align our height means that we won't allocate
755 * enough pages.
756 *
757 * If we're untiled, we still have to align to 2 rows high
758 * because the data port accesses 2x2 blocks even if the
759 * bottom row isn't to be rendered, so failure to align means
760 * we could walk off the end of the GTT and fault. This is
761 * documented on 965, and may be the case on older chipsets
762 * too so we try to be careful.
763 */
764 aligned_y = y;
765 height_alignment = 2;
767 if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
768 height_alignment = 16;
769 else if (tiling == I915_TILING_X
770 || (IS_915(bufmgr_gem) && tiling == I915_TILING_Y))
771 height_alignment = 8;
772 else if (tiling == I915_TILING_Y)
773 height_alignment = 32;
774 aligned_y = ALIGN(y, height_alignment);
776 stride = x * cpp;
777 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode);
778 size = stride * aligned_y;
779 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
780 } while (*tiling_mode != tiling);
781 *pitch = stride;
783 if (tiling == I915_TILING_NONE)
784 stride = 0;
786 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
787 tiling, stride);
788 }
790 /**
791 * Returns a drm_intel_bo wrapping the given buffer object handle.
792 *
793 * This can be used when one application needs to pass a buffer object
794 * to another.
795 */
796 drm_intel_bo *
797 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
798 const char *name,
799 unsigned int handle)
800 {
801 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
802 drm_intel_bo_gem *bo_gem;
803 int ret;
804 struct drm_gem_open open_arg;
805 struct drm_i915_gem_get_tiling get_tiling;
806 drmMMListHead *list;
808 /* At the moment most applications only have a few named bo.
809 * For instance, in a DRI client only the render buffers passed
810 * between X and the client are named. And since X returns the
811 * alternating names for the front/back buffer a linear search
812 * provides a sufficiently fast match.
813 */
814 for (list = bufmgr_gem->named.next;
815 list != &bufmgr_gem->named;
816 list = list->next) {
817 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list);
818 if (bo_gem->global_name == handle) {
819 drm_intel_gem_bo_reference(&bo_gem->bo);
820 return &bo_gem->bo;
821 }
822 }
824 bo_gem = calloc(1, sizeof(*bo_gem));
825 if (!bo_gem)
826 return NULL;
828 memset(&open_arg, 0, sizeof(open_arg));
829 open_arg.name = handle;
830 ret = drmIoctl(bufmgr_gem->fd,
831 DRM_IOCTL_GEM_OPEN,
832 &open_arg);
833 if (ret != 0) {
834 DBG("Couldn't reference %s handle 0x%08x: %s\n",
835 name, handle, strerror(errno));
836 free(bo_gem);
837 return NULL;
838 }
839 bo_gem->bo.size = open_arg.size;
840 bo_gem->bo.offset = 0;
841 bo_gem->bo.virtual = NULL;
842 bo_gem->bo.bufmgr = bufmgr;
843 bo_gem->name = name;
844 atomic_set(&bo_gem->refcount, 1);
845 bo_gem->validate_index = -1;
846 bo_gem->gem_handle = open_arg.handle;
847 bo_gem->bo.handle = open_arg.handle;
848 bo_gem->global_name = handle;
849 bo_gem->reusable = false;
851 memset(&get_tiling, 0, sizeof(get_tiling));
852 get_tiling.handle = bo_gem->gem_handle;
853 ret = drmIoctl(bufmgr_gem->fd,
854 DRM_IOCTL_I915_GEM_GET_TILING,
855 &get_tiling);
856 if (ret != 0) {
857 drm_intel_gem_bo_unreference(&bo_gem->bo);
858 return NULL;
859 }
860 bo_gem->tiling_mode = get_tiling.tiling_mode;
861 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
862 /* XXX stride is unknown */
863 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
865 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
866 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
868 return &bo_gem->bo;
869 }
871 static void
872 drm_intel_gem_bo_free(drm_intel_bo *bo)
873 {
874 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
875 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
876 struct drm_gem_close close;
877 int ret;
879 if (bo_gem->mem_virtual)
880 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
881 if (bo_gem->gtt_virtual)
882 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
884 /* Close this object */
885 memset(&close, 0, sizeof(close));
886 close.handle = bo_gem->gem_handle;
887 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
888 if (ret != 0) {
889 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
890 bo_gem->gem_handle, bo_gem->name, strerror(errno));
891 }
892 free(bo);
893 }
895 /** Frees all cached buffers significantly older than @time. */
896 static void
897 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
898 {
899 int i;
901 if (bufmgr_gem->time == time)
902 return;
904 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
905 struct drm_intel_gem_bo_bucket *bucket =
906 &bufmgr_gem->cache_bucket[i];
908 while (!DRMLISTEMPTY(&bucket->head)) {
909 drm_intel_bo_gem *bo_gem;
911 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
912 bucket->head.next, head);
913 if (time - bo_gem->free_time <= 1)
914 break;
916 DRMLISTDEL(&bo_gem->head);
918 drm_intel_gem_bo_free(&bo_gem->bo);
919 }
920 }
922 bufmgr_gem->time = time;
923 }
925 static void
926 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
927 {
928 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
929 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
930 struct drm_intel_gem_bo_bucket *bucket;
931 int i;
933 /* Unreference all the target buffers */
934 for (i = 0; i < bo_gem->reloc_count; i++) {
935 if (bo_gem->reloc_target_info[i].bo != bo) {
936 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
937 reloc_target_info[i].bo,
938 time);
939 }
940 }
941 bo_gem->reloc_count = 0;
942 bo_gem->used_as_reloc_target = false;
944 DBG("bo_unreference final: %d (%s)\n",
945 bo_gem->gem_handle, bo_gem->name);
947 /* release memory associated with this object */
948 if (bo_gem->reloc_target_info) {
949 free(bo_gem->reloc_target_info);
950 bo_gem->reloc_target_info = NULL;
951 }
952 if (bo_gem->relocs) {
953 free(bo_gem->relocs);
954 bo_gem->relocs = NULL;
955 }
957 DRMLISTDEL(&bo_gem->name_list);
959 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
960 /* Put the buffer into our internal cache for reuse if we can. */
961 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
962 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
963 I915_MADV_DONTNEED)) {
964 bo_gem->free_time = time;
966 bo_gem->name = NULL;
967 bo_gem->validate_index = -1;
969 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
970 } else {
971 drm_intel_gem_bo_free(bo);
972 }
973 }
975 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
976 time_t time)
977 {
978 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
980 assert(atomic_read(&bo_gem->refcount) > 0);
981 if (atomic_dec_and_test(&bo_gem->refcount))
982 drm_intel_gem_bo_unreference_final(bo, time);
983 }
985 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
986 {
987 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
989 assert(atomic_read(&bo_gem->refcount) > 0);
990 if (atomic_dec_and_test(&bo_gem->refcount)) {
991 drm_intel_bufmgr_gem *bufmgr_gem =
992 (drm_intel_bufmgr_gem *) bo->bufmgr;
993 struct timespec time;
995 clock_gettime(CLOCK_MONOTONIC, &time);
997 pthread_mutex_lock(&bufmgr_gem->lock);
998 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
999 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
1000 pthread_mutex_unlock(&bufmgr_gem->lock);
1001 }
1002 }
1004 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
1005 {
1006 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1007 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1008 struct drm_i915_gem_set_domain set_domain;
1009 int ret;
1011 pthread_mutex_lock(&bufmgr_gem->lock);
1013 if (!bo_gem->mem_virtual) {
1014 struct drm_i915_gem_mmap mmap_arg;
1016 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
1018 memset(&mmap_arg, 0, sizeof(mmap_arg));
1019 mmap_arg.handle = bo_gem->gem_handle;
1020 mmap_arg.offset = 0;
1021 mmap_arg.size = bo->size;
1022 ret = drmIoctl(bufmgr_gem->fd,
1023 DRM_IOCTL_I915_GEM_MMAP,
1024 &mmap_arg);
1025 if (ret != 0) {
1026 ret = -errno;
1027 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1028 __FILE__, __LINE__, bo_gem->gem_handle,
1029 bo_gem->name, strerror(errno));
1030 pthread_mutex_unlock(&bufmgr_gem->lock);
1031 return ret;
1032 }
1033 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
1034 }
1035 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1036 bo_gem->mem_virtual);
1037 bo->virtual = bo_gem->mem_virtual;
1039 set_domain.handle = bo_gem->gem_handle;
1040 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
1041 if (write_enable)
1042 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
1043 else
1044 set_domain.write_domain = 0;
1045 ret = drmIoctl(bufmgr_gem->fd,
1046 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1047 &set_domain);
1048 if (ret != 0) {
1049 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
1050 __FILE__, __LINE__, bo_gem->gem_handle,
1051 strerror(errno));
1052 }
1054 pthread_mutex_unlock(&bufmgr_gem->lock);
1056 return 0;
1057 }
1059 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
1060 {
1061 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1062 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1063 struct drm_i915_gem_set_domain set_domain;
1064 int ret;
1066 pthread_mutex_lock(&bufmgr_gem->lock);
1068 /* Get a mapping of the buffer if we haven't before. */
1069 if (bo_gem->gtt_virtual == NULL) {
1070 struct drm_i915_gem_mmap_gtt mmap_arg;
1072 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
1073 bo_gem->name);
1075 memset(&mmap_arg, 0, sizeof(mmap_arg));
1076 mmap_arg.handle = bo_gem->gem_handle;
1078 /* Get the fake offset back... */
1079 ret = drmIoctl(bufmgr_gem->fd,
1080 DRM_IOCTL_I915_GEM_MMAP_GTT,
1081 &mmap_arg);
1082 if (ret != 0) {
1083 ret = -errno;
1084 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1085 __FILE__, __LINE__,
1086 bo_gem->gem_handle, bo_gem->name,
1087 strerror(errno));
1088 pthread_mutex_unlock(&bufmgr_gem->lock);
1089 return ret;
1090 }
1092 /* and mmap it */
1093 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1094 MAP_SHARED, bufmgr_gem->fd,
1095 mmap_arg.offset);
1096 if (bo_gem->gtt_virtual == MAP_FAILED) {
1097 bo_gem->gtt_virtual = NULL;
1098 ret = -errno;
1099 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1100 __FILE__, __LINE__,
1101 bo_gem->gem_handle, bo_gem->name,
1102 strerror(errno));
1103 pthread_mutex_unlock(&bufmgr_gem->lock);
1104 return ret;
1105 }
1106 }
1108 bo->virtual = bo_gem->gtt_virtual;
1110 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1111 bo_gem->gtt_virtual);
1113 /* Now move it to the GTT domain so that the CPU caches are flushed */
1114 set_domain.handle = bo_gem->gem_handle;
1115 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1116 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1117 ret = drmIoctl(bufmgr_gem->fd,
1118 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1119 &set_domain);
1120 if (ret != 0) {
1121 DBG("%s:%d: Error setting domain %d: %s\n",
1122 __FILE__, __LINE__, bo_gem->gem_handle,
1123 strerror(errno));
1124 }
1126 pthread_mutex_unlock(&bufmgr_gem->lock);
1128 return 0;
1129 }
1131 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1132 {
1133 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1134 int ret = 0;
1136 if (bo == NULL)
1137 return 0;
1139 pthread_mutex_lock(&bufmgr_gem->lock);
1140 bo->virtual = NULL;
1141 pthread_mutex_unlock(&bufmgr_gem->lock);
1143 return ret;
1144 }
1146 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1147 {
1148 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1149 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1150 struct drm_i915_gem_sw_finish sw_finish;
1151 int ret;
1153 if (bo == NULL)
1154 return 0;
1156 pthread_mutex_lock(&bufmgr_gem->lock);
1158 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1159 * results show up in a timely manner.
1160 */
1161 sw_finish.handle = bo_gem->gem_handle;
1162 ret = drmIoctl(bufmgr_gem->fd,
1163 DRM_IOCTL_I915_GEM_SW_FINISH,
1164 &sw_finish);
1165 ret = ret == -1 ? -errno : 0;
1167 bo->virtual = NULL;
1168 pthread_mutex_unlock(&bufmgr_gem->lock);
1170 return ret;
1171 }
1173 static int
1174 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1175 unsigned long size, const void *data)
1176 {
1177 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1178 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1179 struct drm_i915_gem_pwrite pwrite;
1180 int ret;
1182 memset(&pwrite, 0, sizeof(pwrite));
1183 pwrite.handle = bo_gem->gem_handle;
1184 pwrite.offset = offset;
1185 pwrite.size = size;
1186 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1187 ret = drmIoctl(bufmgr_gem->fd,
1188 DRM_IOCTL_I915_GEM_PWRITE,
1189 &pwrite);
1190 if (ret != 0) {
1191 ret = -errno;
1192 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1193 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1194 (int)size, strerror(errno));
1195 }
1197 return ret;
1198 }
1200 static int
1201 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1202 {
1203 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1204 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1205 int ret;
1207 get_pipe_from_crtc_id.crtc_id = crtc_id;
1208 ret = drmIoctl(bufmgr_gem->fd,
1209 DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1210 &get_pipe_from_crtc_id);
1211 if (ret != 0) {
1212 /* We return -1 here to signal that we don't
1213 * know which pipe is associated with this crtc.
1214 * This lets the caller know that this information
1215 * isn't available; using the wrong pipe for
1216 * vblank waiting can cause the chipset to lock up
1217 */
1218 return -1;
1219 }
1221 return get_pipe_from_crtc_id.pipe;
1222 }
1224 static int
1225 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1226 unsigned long size, void *data)
1227 {
1228 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1229 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1230 struct drm_i915_gem_pread pread;
1231 int ret;
1233 memset(&pread, 0, sizeof(pread));
1234 pread.handle = bo_gem->gem_handle;
1235 pread.offset = offset;
1236 pread.size = size;
1237 pread.data_ptr = (uint64_t) (uintptr_t) data;
1238 ret = drmIoctl(bufmgr_gem->fd,
1239 DRM_IOCTL_I915_GEM_PREAD,
1240 &pread);
1241 if (ret != 0) {
1242 ret = -errno;
1243 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1244 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1245 (int)size, strerror(errno));
1246 }
1248 return ret;
1249 }
1251 /** Waits for all GPU rendering with the object to have completed. */
1252 static void
1253 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1254 {
1255 drm_intel_gem_bo_start_gtt_access(bo, 1);
1256 }
1258 /**
1259 * Sets the object to the GTT read and possibly write domain, used by the X
1260 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1261 *
1262 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1263 * can do tiled pixmaps this way.
1264 */
1265 void
1266 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1267 {
1268 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1269 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1270 struct drm_i915_gem_set_domain set_domain;
1271 int ret;
1273 set_domain.handle = bo_gem->gem_handle;
1274 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1275 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1276 ret = drmIoctl(bufmgr_gem->fd,
1277 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1278 &set_domain);
1279 if (ret != 0) {
1280 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1281 __FILE__, __LINE__, bo_gem->gem_handle,
1282 set_domain.read_domains, set_domain.write_domain,
1283 strerror(errno));
1284 }
1285 }
1287 static void
1288 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1289 {
1290 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1291 int i;
1293 free(bufmgr_gem->exec2_objects);
1294 free(bufmgr_gem->exec_objects);
1295 free(bufmgr_gem->exec_bos);
1297 pthread_mutex_destroy(&bufmgr_gem->lock);
1299 /* Free any cached buffer objects we were going to reuse */
1300 for (i = 0; i < bufmgr_gem->num_buckets; i++) {
1301 struct drm_intel_gem_bo_bucket *bucket =
1302 &bufmgr_gem->cache_bucket[i];
1303 drm_intel_bo_gem *bo_gem;
1305 while (!DRMLISTEMPTY(&bucket->head)) {
1306 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1307 bucket->head.next, head);
1308 DRMLISTDEL(&bo_gem->head);
1310 drm_intel_gem_bo_free(&bo_gem->bo);
1311 }
1312 }
1314 free(bufmgr);
1315 }
1317 /**
1318 * Adds the target buffer to the validation list and adds the relocation
1319 * to the reloc_buffer's relocation list.
1320 *
1321 * The relocation entry at the given offset must already contain the
1322 * precomputed relocation value, because the kernel will optimize out
1323 * the relocation entry write when the buffer hasn't moved from the
1324 * last known offset in target_bo.
1325 */
1326 static int
1327 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1328 drm_intel_bo *target_bo, uint32_t target_offset,
1329 uint32_t read_domains, uint32_t write_domain,
1330 bool need_fence)
1331 {
1332 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1333 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1334 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1335 bool fenced_command;
1337 if (bo_gem->has_error)
1338 return -ENOMEM;
1340 if (target_bo_gem->has_error) {
1341 bo_gem->has_error = true;
1342 return -ENOMEM;
1343 }
1345 /* We never use HW fences for rendering on 965+ */
1346 if (bufmgr_gem->gen >= 4)
1347 need_fence = false;
1349 fenced_command = need_fence;
1350 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1351 need_fence = false;
1353 /* Create a new relocation list if needed */
1354 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1355 return -ENOMEM;
1357 /* Check overflow */
1358 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1360 /* Check args */
1361 assert(offset <= bo->size - 4);
1362 assert((write_domain & (write_domain - 1)) == 0);
1364 /* Make sure that we're not adding a reloc to something whose size has
1365 * already been accounted for.
1366 */
1367 assert(!bo_gem->used_as_reloc_target);
1368 if (target_bo_gem != bo_gem) {
1369 target_bo_gem->used_as_reloc_target = true;
1370 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1371 }
1372 /* An object needing a fence is a tiled buffer, so it won't have
1373 * relocs to other buffers.
1374 */
1375 if (need_fence)
1376 target_bo_gem->reloc_tree_fences = 1;
1377 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1379 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1380 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1381 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1382 target_bo_gem->gem_handle;
1383 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1384 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1385 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1387 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1388 if (target_bo != bo)
1389 drm_intel_gem_bo_reference(target_bo);
1390 if (fenced_command)
1391 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1392 DRM_INTEL_RELOC_FENCE;
1393 else
1394 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1396 bo_gem->reloc_count++;
1398 return 0;
1399 }
1401 static int
1402 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1403 drm_intel_bo *target_bo, uint32_t target_offset,
1404 uint32_t read_domains, uint32_t write_domain)
1405 {
1406 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1408 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1409 read_domains, write_domain,
1410 !bufmgr_gem->fenced_relocs);
1411 }
1413 static int
1414 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1415 drm_intel_bo *target_bo,
1416 uint32_t target_offset,
1417 uint32_t read_domains, uint32_t write_domain)
1418 {
1419 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1420 read_domains, write_domain, true);
1421 }
1423 int
1424 drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo)
1425 {
1426 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1428 return bo_gem->reloc_count;
1429 }
1431 /**
1432 * Removes existing relocation entries in the BO after "start".
1433 *
1434 * This allows a user to avoid a two-step process for state setup with
1435 * counting up all the buffer objects and doing a
1436 * drm_intel_bufmgr_check_aperture_space() before emitting any of the
1437 * relocations for the state setup. Instead, save the state of the
1438 * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the
1439 * state, and then check if it still fits in the aperture.
1440 *
1441 * Any further drm_intel_bufmgr_check_aperture_space() queries
1442 * involving this buffer in the tree are undefined after this call.
1443 */
1444 void
1445 drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start)
1446 {
1447 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1448 int i;
1449 struct timespec time;
1451 clock_gettime(CLOCK_MONOTONIC, &time);
1453 assert(bo_gem->reloc_count >= start);
1454 /* Unreference the cleared target buffers */
1455 for (i = start; i < bo_gem->reloc_count; i++) {
1456 if (bo_gem->reloc_target_info[i].bo != bo) {
1457 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
1458 reloc_target_info[i].bo,
1459 time.tv_sec);
1460 }
1461 }
1462 bo_gem->reloc_count = start;
1463 }
1465 /**
1466 * Walk the tree of relocations rooted at BO and accumulate the list of
1467 * validations to be performed and update the relocation buffers with
1468 * index values into the validation list.
1469 */
1470 static void
1471 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1472 {
1473 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1474 int i;
1476 if (bo_gem->relocs == NULL)
1477 return;
1479 for (i = 0; i < bo_gem->reloc_count; i++) {
1480 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1482 if (target_bo == bo)
1483 continue;
1485 /* Continue walking the tree depth-first. */
1486 drm_intel_gem_bo_process_reloc(target_bo);
1488 /* Add the target to the validate list */
1489 drm_intel_add_validate_buffer(target_bo);
1490 }
1491 }
1493 static void
1494 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1495 {
1496 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1497 int i;
1499 if (bo_gem->relocs == NULL)
1500 return;
1502 for (i = 0; i < bo_gem->reloc_count; i++) {
1503 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1504 int need_fence;
1506 if (target_bo == bo)
1507 continue;
1509 /* Continue walking the tree depth-first. */
1510 drm_intel_gem_bo_process_reloc2(target_bo);
1512 need_fence = (bo_gem->reloc_target_info[i].flags &
1513 DRM_INTEL_RELOC_FENCE);
1515 /* Add the target to the validate list */
1516 drm_intel_add_validate_buffer2(target_bo, need_fence);
1517 }
1518 }
1521 static void
1522 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1523 {
1524 int i;
1526 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1527 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1528 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1530 /* Update the buffer offset */
1531 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1532 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1533 bo_gem->gem_handle, bo_gem->name, bo->offset,
1534 (unsigned long long)bufmgr_gem->exec_objects[i].
1535 offset);
1536 bo->offset = bufmgr_gem->exec_objects[i].offset;
1537 }
1538 }
1539 }
1541 static void
1542 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1543 {
1544 int i;
1546 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1547 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1548 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1550 /* Update the buffer offset */
1551 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1552 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1553 bo_gem->gem_handle, bo_gem->name, bo->offset,
1554 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1555 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1556 }
1557 }
1558 }
1560 static int
1561 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1562 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1563 {
1564 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1565 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1566 struct drm_i915_gem_execbuffer execbuf;
1567 int ret, i;
1569 if (bo_gem->has_error)
1570 return -ENOMEM;
1572 pthread_mutex_lock(&bufmgr_gem->lock);
1573 /* Update indices and set up the validate list. */
1574 drm_intel_gem_bo_process_reloc(bo);
1576 /* Add the batch buffer to the validation list. There are no
1577 * relocations pointing to it.
1578 */
1579 drm_intel_add_validate_buffer(bo);
1581 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1582 execbuf.buffer_count = bufmgr_gem->exec_count;
1583 execbuf.batch_start_offset = 0;
1584 execbuf.batch_len = used;
1585 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1586 execbuf.num_cliprects = num_cliprects;
1587 execbuf.DR1 = 0;
1588 execbuf.DR4 = DR4;
1590 ret = drmIoctl(bufmgr_gem->fd,
1591 DRM_IOCTL_I915_GEM_EXECBUFFER,
1592 &execbuf);
1593 if (ret != 0) {
1594 ret = -errno;
1595 if (errno == ENOSPC) {
1596 DBG("Execbuffer fails to pin. "
1597 "Estimate: %u. Actual: %u. Available: %u\n",
1598 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1599 bufmgr_gem->
1600 exec_count),
1601 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1602 bufmgr_gem->
1603 exec_count),
1604 (unsigned int)bufmgr_gem->gtt_size);
1605 }
1606 }
1607 drm_intel_update_buffer_offsets(bufmgr_gem);
1609 if (bufmgr_gem->bufmgr.debug)
1610 drm_intel_gem_dump_validation_list(bufmgr_gem);
1612 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1613 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1614 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1616 /* Disconnect the buffer from the validate list */
1617 bo_gem->validate_index = -1;
1618 bufmgr_gem->exec_bos[i] = NULL;
1619 }
1620 bufmgr_gem->exec_count = 0;
1621 pthread_mutex_unlock(&bufmgr_gem->lock);
1623 return ret;
1624 }
1626 static int
1627 drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used,
1628 drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
1629 unsigned int flags)
1630 {
1631 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1632 struct drm_i915_gem_execbuffer2 execbuf;
1633 int ret, i;
1635 switch (flags & 0x7) {
1636 default:
1637 return -EINVAL;
1638 case I915_EXEC_BLT:
1639 if (!bufmgr_gem->has_blt)
1640 return -EINVAL;
1641 break;
1642 case I915_EXEC_BSD:
1643 if (!bufmgr_gem->has_bsd)
1644 return -EINVAL;
1645 break;
1646 case I915_EXEC_RENDER:
1647 case I915_EXEC_DEFAULT:
1648 break;
1649 }
1651 pthread_mutex_lock(&bufmgr_gem->lock);
1652 /* Update indices and set up the validate list. */
1653 drm_intel_gem_bo_process_reloc2(bo);
1655 /* Add the batch buffer to the validation list. There are no relocations
1656 * pointing to it.
1657 */
1658 drm_intel_add_validate_buffer2(bo, 0);
1660 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1661 execbuf.buffer_count = bufmgr_gem->exec_count;
1662 execbuf.batch_start_offset = 0;
1663 execbuf.batch_len = used;
1664 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1665 execbuf.num_cliprects = num_cliprects;
1666 execbuf.DR1 = 0;
1667 execbuf.DR4 = DR4;
1668 execbuf.flags = flags;
1669 execbuf.rsvd1 = 0;
1670 execbuf.rsvd2 = 0;
1672 ret = drmIoctl(bufmgr_gem->fd,
1673 DRM_IOCTL_I915_GEM_EXECBUFFER2,
1674 &execbuf);
1675 if (ret != 0) {
1676 ret = -errno;
1677 if (ret == -ENOSPC) {
1678 DBG("Execbuffer fails to pin. "
1679 "Estimate: %u. Actual: %u. Available: %u\n",
1680 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1681 bufmgr_gem->exec_count),
1682 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1683 bufmgr_gem->exec_count),
1684 (unsigned int) bufmgr_gem->gtt_size);
1685 }
1686 }
1687 drm_intel_update_buffer_offsets2(bufmgr_gem);
1689 if (bufmgr_gem->bufmgr.debug)
1690 drm_intel_gem_dump_validation_list(bufmgr_gem);
1692 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1693 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1694 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1696 /* Disconnect the buffer from the validate list */
1697 bo_gem->validate_index = -1;
1698 bufmgr_gem->exec_bos[i] = NULL;
1699 }
1700 bufmgr_gem->exec_count = 0;
1701 pthread_mutex_unlock(&bufmgr_gem->lock);
1703 return ret;
1704 }
1706 static int
1707 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1708 drm_clip_rect_t *cliprects, int num_cliprects,
1709 int DR4)
1710 {
1711 return drm_intel_gem_bo_mrb_exec2(bo, used,
1712 cliprects, num_cliprects, DR4,
1713 I915_EXEC_RENDER);
1714 }
1716 static int
1717 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1718 {
1719 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1720 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1721 struct drm_i915_gem_pin pin;
1722 int ret;
1724 memset(&pin, 0, sizeof(pin));
1725 pin.handle = bo_gem->gem_handle;
1726 pin.alignment = alignment;
1728 ret = drmIoctl(bufmgr_gem->fd,
1729 DRM_IOCTL_I915_GEM_PIN,
1730 &pin);
1731 if (ret != 0)
1732 return -errno;
1734 bo->offset = pin.offset;
1735 return 0;
1736 }
1738 static int
1739 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1740 {
1741 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1742 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1743 struct drm_i915_gem_unpin unpin;
1744 int ret;
1746 memset(&unpin, 0, sizeof(unpin));
1747 unpin.handle = bo_gem->gem_handle;
1749 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1750 if (ret != 0)
1751 return -errno;
1753 return 0;
1754 }
1756 static int
1757 drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo,
1758 uint32_t tiling_mode,
1759 uint32_t stride)
1760 {
1761 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1762 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1763 struct drm_i915_gem_set_tiling set_tiling;
1764 int ret;
1766 if (bo_gem->global_name == 0 &&
1767 tiling_mode == bo_gem->tiling_mode &&
1768 stride == bo_gem->stride)
1769 return 0;
1771 memset(&set_tiling, 0, sizeof(set_tiling));
1772 do {
1773 /* set_tiling is slightly broken and overwrites the
1774 * input on the error path, so we have to open code
1775 * rmIoctl.
1776 */
1777 set_tiling.handle = bo_gem->gem_handle;
1778 set_tiling.tiling_mode = tiling_mode;
1779 set_tiling.stride = stride;
1781 ret = ioctl(bufmgr_gem->fd,
1782 DRM_IOCTL_I915_GEM_SET_TILING,
1783 &set_tiling);
1784 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1785 if (ret == -1)
1786 return -errno;
1788 bo_gem->tiling_mode = set_tiling.tiling_mode;
1789 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1790 bo_gem->stride = set_tiling.stride;
1791 return 0;
1792 }
1794 static int
1795 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1796 uint32_t stride)
1797 {
1798 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1799 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1800 int ret;
1802 /* Linear buffers have no stride. By ensuring that we only ever use
1803 * stride 0 with linear buffers, we simplify our code.
1804 */
1805 if (*tiling_mode == I915_TILING_NONE)
1806 stride = 0;
1808 ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride);
1809 if (ret == 0)
1810 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1812 *tiling_mode = bo_gem->tiling_mode;
1813 return ret;
1814 }
1816 static int
1817 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1818 uint32_t * swizzle_mode)
1819 {
1820 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1822 *tiling_mode = bo_gem->tiling_mode;
1823 *swizzle_mode = bo_gem->swizzle_mode;
1824 return 0;
1825 }
1827 static int
1828 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1829 {
1830 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1831 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1832 struct drm_gem_flink flink;
1833 int ret;
1835 if (!bo_gem->global_name) {
1836 memset(&flink, 0, sizeof(flink));
1837 flink.handle = bo_gem->gem_handle;
1839 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1840 if (ret != 0)
1841 return -errno;
1842 bo_gem->global_name = flink.name;
1843 bo_gem->reusable = false;
1845 DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named);
1846 }
1848 *name = bo_gem->global_name;
1849 return 0;
1850 }
1852 /**
1853 * Enables unlimited caching of buffer objects for reuse.
1854 *
1855 * This is potentially very memory expensive, as the cache at each bucket
1856 * size is only bounded by how many buffers of that size we've managed to have
1857 * in flight at once.
1858 */
1859 void
1860 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1861 {
1862 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1864 bufmgr_gem->bo_reuse = true;
1865 }
1867 /**
1868 * Enable use of fenced reloc type.
1869 *
1870 * New code should enable this to avoid unnecessary fence register
1871 * allocation. If this option is not enabled, all relocs will have fence
1872 * register allocated.
1873 */
1874 void
1875 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1876 {
1877 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1879 if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2)
1880 bufmgr_gem->fenced_relocs = true;
1881 }
1883 /**
1884 * Return the additional aperture space required by the tree of buffer objects
1885 * rooted at bo.
1886 */
1887 static int
1888 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1889 {
1890 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1891 int i;
1892 int total = 0;
1894 if (bo == NULL || bo_gem->included_in_check_aperture)
1895 return 0;
1897 total += bo->size;
1898 bo_gem->included_in_check_aperture = true;
1900 for (i = 0; i < bo_gem->reloc_count; i++)
1901 total +=
1902 drm_intel_gem_bo_get_aperture_space(bo_gem->
1903 reloc_target_info[i].bo);
1905 return total;
1906 }
1908 /**
1909 * Count the number of buffers in this list that need a fence reg
1910 *
1911 * If the count is greater than the number of available regs, we'll have
1912 * to ask the caller to resubmit a batch with fewer tiled buffers.
1913 *
1914 * This function over-counts if the same buffer is used multiple times.
1915 */
1916 static unsigned int
1917 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1918 {
1919 int i;
1920 unsigned int total = 0;
1922 for (i = 0; i < count; i++) {
1923 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1925 if (bo_gem == NULL)
1926 continue;
1928 total += bo_gem->reloc_tree_fences;
1929 }
1930 return total;
1931 }
1933 /**
1934 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1935 * for the next drm_intel_bufmgr_check_aperture_space() call.
1936 */
1937 static void
1938 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1939 {
1940 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1941 int i;
1943 if (bo == NULL || !bo_gem->included_in_check_aperture)
1944 return;
1946 bo_gem->included_in_check_aperture = false;
1948 for (i = 0; i < bo_gem->reloc_count; i++)
1949 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1950 reloc_target_info[i].bo);
1951 }
1953 /**
1954 * Return a conservative estimate for the amount of aperture required
1955 * for a collection of buffers. This may double-count some buffers.
1956 */
1957 static unsigned int
1958 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1959 {
1960 int i;
1961 unsigned int total = 0;
1963 for (i = 0; i < count; i++) {
1964 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1965 if (bo_gem != NULL)
1966 total += bo_gem->reloc_tree_size;
1967 }
1968 return total;
1969 }
1971 /**
1972 * Return the amount of aperture needed for a collection of buffers.
1973 * This avoids double counting any buffers, at the cost of looking
1974 * at every buffer in the set.
1975 */
1976 static unsigned int
1977 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1978 {
1979 int i;
1980 unsigned int total = 0;
1982 for (i = 0; i < count; i++) {
1983 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1984 /* For the first buffer object in the array, we get an
1985 * accurate count back for its reloc_tree size (since nothing
1986 * had been flagged as being counted yet). We can save that
1987 * value out as a more conservative reloc_tree_size that
1988 * avoids double-counting target buffers. Since the first
1989 * buffer happens to usually be the batch buffer in our
1990 * callers, this can pull us back from doing the tree
1991 * walk on every new batch emit.
1992 */
1993 if (i == 0) {
1994 drm_intel_bo_gem *bo_gem =
1995 (drm_intel_bo_gem *) bo_array[i];
1996 bo_gem->reloc_tree_size = total;
1997 }
1998 }
2000 for (i = 0; i < count; i++)
2001 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
2002 return total;
2003 }
2005 /**
2006 * Return -1 if the batchbuffer should be flushed before attempting to
2007 * emit rendering referencing the buffers pointed to by bo_array.
2008 *
2009 * This is required because if we try to emit a batchbuffer with relocations
2010 * to a tree of buffers that won't simultaneously fit in the aperture,
2011 * the rendering will return an error at a point where the software is not
2012 * prepared to recover from it.
2013 *
2014 * However, we also want to emit the batchbuffer significantly before we reach
2015 * the limit, as a series of batchbuffers each of which references buffers
2016 * covering almost all of the aperture means that at each emit we end up
2017 * waiting to evict a buffer from the last rendering, and we get synchronous
2018 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
2019 * get better parallelism.
2020 */
2021 static int
2022 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
2023 {
2024 drm_intel_bufmgr_gem *bufmgr_gem =
2025 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
2026 unsigned int total = 0;
2027 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
2028 int total_fences;
2030 /* Check for fence reg constraints if necessary */
2031 if (bufmgr_gem->available_fences) {
2032 total_fences = drm_intel_gem_total_fences(bo_array, count);
2033 if (total_fences > bufmgr_gem->available_fences)
2034 return -ENOSPC;
2035 }
2037 total = drm_intel_gem_estimate_batch_space(bo_array, count);
2039 if (total > threshold)
2040 total = drm_intel_gem_compute_batch_space(bo_array, count);
2042 if (total > threshold) {
2043 DBG("check_space: overflowed available aperture, "
2044 "%dkb vs %dkb\n",
2045 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
2046 return -ENOSPC;
2047 } else {
2048 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
2049 (int)bufmgr_gem->gtt_size / 1024);
2050 return 0;
2051 }
2052 }
2054 /*
2055 * Disable buffer reuse for objects which are shared with the kernel
2056 * as scanout buffers
2057 */
2058 static int
2059 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
2060 {
2061 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2063 bo_gem->reusable = false;
2064 return 0;
2065 }
2067 static int
2068 drm_intel_gem_bo_is_reusable(drm_intel_bo *bo)
2069 {
2070 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2072 return bo_gem->reusable;
2073 }
2075 static int
2076 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2077 {
2078 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
2079 int i;
2081 for (i = 0; i < bo_gem->reloc_count; i++) {
2082 if (bo_gem->reloc_target_info[i].bo == target_bo)
2083 return 1;
2084 if (bo == bo_gem->reloc_target_info[i].bo)
2085 continue;
2086 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
2087 target_bo))
2088 return 1;
2089 }
2091 return 0;
2092 }
2094 /** Return true if target_bo is referenced by bo's relocation tree. */
2095 static int
2096 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
2097 {
2098 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
2100 if (bo == NULL || target_bo == NULL)
2101 return 0;
2102 if (target_bo_gem->used_as_reloc_target)
2103 return _drm_intel_gem_bo_references(bo, target_bo);
2104 return 0;
2105 }
2107 static void
2108 add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size)
2109 {
2110 unsigned int i = bufmgr_gem->num_buckets;
2112 assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket));
2114 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2115 bufmgr_gem->cache_bucket[i].size = size;
2116 bufmgr_gem->num_buckets++;
2117 }
2119 static void
2120 init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem)
2121 {
2122 unsigned long size, cache_max_size = 64 * 1024 * 1024;
2124 /* OK, so power of two buckets was too wasteful of memory.
2125 * Give 3 other sizes between each power of two, to hopefully
2126 * cover things accurately enough. (The alternative is
2127 * probably to just go for exact matching of sizes, and assume
2128 * that for things like composited window resize the tiled
2129 * width/height alignment and rounding of sizes to pages will
2130 * get us useful cache hit rates anyway)
2131 */
2132 add_bucket(bufmgr_gem, 4096);
2133 add_bucket(bufmgr_gem, 4096 * 2);
2134 add_bucket(bufmgr_gem, 4096 * 3);
2136 /* Initialize the linked lists for BO reuse cache. */
2137 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
2138 add_bucket(bufmgr_gem, size);
2140 add_bucket(bufmgr_gem, size + size * 1 / 4);
2141 add_bucket(bufmgr_gem, size + size * 2 / 4);
2142 add_bucket(bufmgr_gem, size + size * 3 / 4);
2143 }
2144 }
2146 /**
2147 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
2148 * and manage map buffer objections.
2149 *
2150 * \param fd File descriptor of the opened DRM device.
2151 */
2152 drm_intel_bufmgr *
2153 drm_intel_bufmgr_gem_init(int fd, int batch_size)
2154 {
2155 drm_intel_bufmgr_gem *bufmgr_gem;
2156 struct drm_i915_gem_get_aperture aperture;
2157 drm_i915_getparam_t gp;
2158 int ret, tmp;
2159 bool exec2 = false;
2161 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
2162 if (bufmgr_gem == NULL)
2163 return NULL;
2165 bufmgr_gem->fd = fd;
2167 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
2168 free(bufmgr_gem);
2169 return NULL;
2170 }
2172 ret = drmIoctl(bufmgr_gem->fd,
2173 DRM_IOCTL_I915_GEM_GET_APERTURE,
2174 &aperture);
2176 if (ret == 0)
2177 bufmgr_gem->gtt_size = aperture.aper_available_size;
2178 else {
2179 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
2180 strerror(errno));
2181 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
2182 fprintf(stderr, "Assuming %dkB available aperture size.\n"
2183 "May lead to reduced performance or incorrect "
2184 "rendering.\n",
2185 (int)bufmgr_gem->gtt_size / 1024);
2186 }
2188 gp.param = I915_PARAM_CHIPSET_ID;
2189 gp.value = &bufmgr_gem->pci_device;
2190 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2191 if (ret) {
2192 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
2193 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
2194 }
2196 if (IS_GEN2(bufmgr_gem))
2197 bufmgr_gem->gen = 2;
2198 else if (IS_GEN3(bufmgr_gem))
2199 bufmgr_gem->gen = 3;
2200 else if (IS_GEN4(bufmgr_gem))
2201 bufmgr_gem->gen = 4;
2202 else
2203 bufmgr_gem->gen = 6;
2205 gp.value = &tmp;
2207 gp.param = I915_PARAM_HAS_EXECBUF2;
2208 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2209 if (!ret)
2210 exec2 = true;
2212 gp.param = I915_PARAM_HAS_BSD;
2213 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2214 bufmgr_gem->has_bsd = ret == 0;
2216 gp.param = I915_PARAM_HAS_BLT;
2217 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2218 bufmgr_gem->has_blt = ret == 0;
2220 gp.param = I915_PARAM_HAS_RELAXED_FENCING;
2221 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2222 bufmgr_gem->has_relaxed_fencing = ret == 0;
2224 if (bufmgr_gem->gen < 4) {
2225 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
2226 gp.value = &bufmgr_gem->available_fences;
2227 ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
2228 if (ret) {
2229 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2230 errno);
2231 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2232 *gp.value);
2233 bufmgr_gem->available_fences = 0;
2234 } else {
2235 /* XXX The kernel reports the total number of fences,
2236 * including any that may be pinned.
2237 *
2238 * We presume that there will be at least one pinned
2239 * fence for the scanout buffer, but there may be more
2240 * than one scanout and the user may be manually
2241 * pinning buffers. Let's move to execbuffer2 and
2242 * thereby forget the insanity of using fences...
2243 */
2244 bufmgr_gem->available_fences -= 2;
2245 if (bufmgr_gem->available_fences < 0)
2246 bufmgr_gem->available_fences = 0;
2247 }
2248 }
2250 /* Let's go with one relocation per every 2 dwords (but round down a bit
2251 * since a power of two will mean an extra page allocation for the reloc
2252 * buffer).
2253 *
2254 * Every 4 was too few for the blender benchmark.
2255 */
2256 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2258 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2259 bufmgr_gem->bufmgr.bo_alloc_for_render =
2260 drm_intel_gem_bo_alloc_for_render;
2261 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2262 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2263 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2264 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2265 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2266 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2267 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2268 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2269 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2270 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2271 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2272 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2273 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2274 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2275 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2276 /* Use the new one if available */
2277 if (exec2) {
2278 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2279 bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2;
2280 } else
2281 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2282 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2283 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2284 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2285 bufmgr_gem->bufmgr.debug = 0;
2286 bufmgr_gem->bufmgr.check_aperture_space =
2287 drm_intel_gem_check_aperture_space;
2288 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2289 bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable;
2290 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2291 drm_intel_gem_get_pipe_from_crtc_id;
2292 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2294 DRMINITLISTHEAD(&bufmgr_gem->named);
2295 init_cache_buckets(bufmgr_gem);
2297 return &bufmgr_gem->bufmgr;
2298 }