1 /**************************************************************************
2 *
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
26 * of the Software.
27 *
28 *
29 **************************************************************************/
30 /*
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
35 */
37 #ifdef HAVE_CONFIG_H
38 #include "config.h"
39 #endif
41 #include <xf86drm.h>
42 #include <fcntl.h>
43 #include <stdio.h>
44 #include <stdlib.h>
45 #include <string.h>
46 #include <unistd.h>
47 #include <assert.h>
48 #include <pthread.h>
49 #include <sys/ioctl.h>
50 #include <sys/mman.h>
51 #include <sys/stat.h>
52 #include <sys/types.h>
54 #include "errno.h"
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
60 #include "string.h"
62 #include "i915_drm.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
67 } while (0)
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
72 drmMMListHead head;
73 unsigned long size;
74 };
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
78 */
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
83 int fd;
85 int max_relocs;
87 pthread_mutex_t lock;
89 struct drm_i915_gem_exec_object *exec_objects;
90 drm_intel_bo **exec_bos;
91 int exec_size;
92 int exec_count;
94 /** Array of lists of cached gem objects of power-of-two sizes */
95 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
97 uint64_t gtt_size;
98 int available_fences;
99 int pci_device;
100 char bo_reuse;
101 } drm_intel_bufmgr_gem;
103 struct _drm_intel_bo_gem {
104 drm_intel_bo bo;
106 atomic_t refcount;
107 uint32_t gem_handle;
108 const char *name;
110 /**
111 * Kenel-assigned global name for this object
112 */
113 unsigned int global_name;
115 /**
116 * Index of the buffer within the validation list while preparing a
117 * batchbuffer execution.
118 */
119 int validate_index;
121 /**
122 * Current tiling mode
123 */
124 uint32_t tiling_mode;
125 uint32_t swizzle_mode;
127 time_t free_time;
129 /** Array passed to the DRM containing relocation information. */
130 struct drm_i915_gem_relocation_entry *relocs;
131 /** Array of bos corresponding to relocs[i].target_handle */
132 drm_intel_bo **reloc_target_bo;
133 /** Number of entries in relocs */
134 int reloc_count;
135 /** Mapped address for the buffer, saved across map/unmap cycles */
136 void *mem_virtual;
137 /** GTT virtual address for the buffer, saved across map/unmap cycles */
138 void *gtt_virtual;
140 /** BO cache list */
141 drmMMListHead head;
143 /**
144 * Boolean of whether this BO and its children have been included in
145 * the current drm_intel_bufmgr_check_aperture_space() total.
146 */
147 char included_in_check_aperture;
149 /**
150 * Boolean of whether this buffer has been used as a relocation
151 * target and had its size accounted for, and thus can't have any
152 * further relocations added to it.
153 */
154 char used_as_reloc_target;
156 /**
157 * Boolean of whether we have encountered an error whilst building the relocation tree.
158 */
159 char has_error;
161 /**
162 * Boolean of whether this buffer can be re-used
163 */
164 char reusable;
166 /**
167 * Size in bytes of this buffer and its relocation descendents.
168 *
169 * Used to avoid costly tree walking in
170 * drm_intel_bufmgr_check_aperture in the common case.
171 */
172 int reloc_tree_size;
174 /**
175 * Number of potential fence registers required by this buffer and its
176 * relocations.
177 */
178 int reloc_tree_fences;
179 };
181 static unsigned int
182 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
184 static unsigned int
185 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
187 static int
188 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
189 uint32_t * swizzle_mode);
191 static int
192 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
193 uint32_t stride);
195 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
196 time_t time);
198 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
200 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
202 static unsigned long
203 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
204 uint32_t *tiling_mode)
205 {
206 unsigned long min_size, max_size;
207 unsigned long i;
209 if (*tiling_mode == I915_TILING_NONE)
210 return size;
212 /* 965+ just need multiples of page size for tiling */
213 if (IS_I965G(bufmgr_gem))
214 return ROUND_UP_TO(size, 4096);
216 /* Older chips need powers of two, of at least 512k or 1M */
217 if (IS_I9XX(bufmgr_gem)) {
218 min_size = 1024*1024;
219 max_size = 128*1024*1024;
220 } else {
221 min_size = 512*1024;
222 max_size = 64*1024*1024;
223 }
225 if (size > max_size) {
226 *tiling_mode = I915_TILING_NONE;
227 return size;
228 }
230 for (i = min_size; i < size; i <<= 1)
231 ;
233 return i;
234 }
236 /*
237 * Round a given pitch up to the minimum required for X tiling on a
238 * given chip. We use 512 as the minimum to allow for a later tiling
239 * change.
240 */
241 static unsigned long
242 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
243 unsigned long pitch, uint32_t tiling_mode)
244 {
245 unsigned long tile_width = 512;
246 unsigned long i;
248 if (tiling_mode == I915_TILING_NONE)
249 return ROUND_UP_TO(pitch, tile_width);
251 /* 965 is flexible */
252 if (IS_I965G(bufmgr_gem))
253 return ROUND_UP_TO(pitch, tile_width);
255 /* Pre-965 needs power of two tile width */
256 for (i = tile_width; i < pitch; i <<= 1)
257 ;
259 return i;
260 }
262 static struct drm_intel_gem_bo_bucket *
263 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
264 unsigned long size)
265 {
266 int i;
268 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
269 struct drm_intel_gem_bo_bucket *bucket =
270 &bufmgr_gem->cache_bucket[i];
271 if (bucket->size >= size) {
272 return bucket;
273 }
274 }
276 return NULL;
277 }
279 static void
280 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
281 {
282 int i, j;
284 for (i = 0; i < bufmgr_gem->exec_count; i++) {
285 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
286 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
288 if (bo_gem->relocs == NULL) {
289 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
290 bo_gem->name);
291 continue;
292 }
294 for (j = 0; j < bo_gem->reloc_count; j++) {
295 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[j];
296 drm_intel_bo_gem *target_gem =
297 (drm_intel_bo_gem *) target_bo;
299 DBG("%2d: %d (%s)@0x%08llx -> "
300 "%d (%s)@0x%08lx + 0x%08x\n",
301 i,
302 bo_gem->gem_handle, bo_gem->name,
303 (unsigned long long)bo_gem->relocs[j].offset,
304 target_gem->gem_handle,
305 target_gem->name,
306 target_bo->offset,
307 bo_gem->relocs[j].delta);
308 }
309 }
310 }
312 static inline void
313 drm_intel_gem_bo_reference(drm_intel_bo *bo)
314 {
315 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
317 assert(atomic_read(&bo_gem->refcount) > 0);
318 atomic_inc(&bo_gem->refcount);
319 }
321 /**
322 * Adds the given buffer to the list of buffers to be validated (moved into the
323 * appropriate memory type) with the next batch submission.
324 *
325 * If a buffer is validated multiple times in a batch submission, it ends up
326 * with the intersection of the memory type flags and the union of the
327 * access flags.
328 */
329 static void
330 drm_intel_add_validate_buffer(drm_intel_bo *bo)
331 {
332 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
333 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
334 int index;
336 if (bo_gem->validate_index != -1)
337 return;
339 /* Extend the array of validation entries as necessary. */
340 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
341 int new_size = bufmgr_gem->exec_size * 2;
343 if (new_size == 0)
344 new_size = 5;
346 bufmgr_gem->exec_objects =
347 realloc(bufmgr_gem->exec_objects,
348 sizeof(*bufmgr_gem->exec_objects) * new_size);
349 bufmgr_gem->exec_bos =
350 realloc(bufmgr_gem->exec_bos,
351 sizeof(*bufmgr_gem->exec_bos) * new_size);
352 bufmgr_gem->exec_size = new_size;
353 }
355 index = bufmgr_gem->exec_count;
356 bo_gem->validate_index = index;
357 /* Fill in array entry */
358 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
359 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
360 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
361 bufmgr_gem->exec_objects[index].alignment = 0;
362 bufmgr_gem->exec_objects[index].offset = 0;
363 bufmgr_gem->exec_bos[index] = bo;
364 bufmgr_gem->exec_count++;
365 }
367 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
368 sizeof(uint32_t))
370 static void
371 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
372 drm_intel_bo_gem *bo_gem)
373 {
374 int size;
376 assert(!bo_gem->used_as_reloc_target);
378 /* The older chipsets are far-less flexible in terms of tiling,
379 * and require tiled buffer to be size aligned in the aperture.
380 * This means that in the worst possible case we will need a hole
381 * twice as large as the object in order for it to fit into the
382 * aperture. Optimal packing is for wimps.
383 */
384 size = bo_gem->bo.size;
385 if (!IS_I965G(bufmgr_gem) && bo_gem->tiling_mode != I915_TILING_NONE)
386 size *= 2;
388 bo_gem->reloc_tree_size = size;
389 }
391 static int
392 drm_intel_setup_reloc_list(drm_intel_bo *bo)
393 {
394 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
395 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
396 unsigned int max_relocs = bufmgr_gem->max_relocs;
398 if (bo->size / 4 < max_relocs)
399 max_relocs = bo->size / 4;
401 bo_gem->relocs = malloc(max_relocs *
402 sizeof(struct drm_i915_gem_relocation_entry));
403 bo_gem->reloc_target_bo = malloc(max_relocs * sizeof(drm_intel_bo *));
404 if (bo_gem->relocs == NULL || bo_gem->reloc_target_bo == NULL) {
405 bo_gem->has_error = 1;
407 free (bo_gem->relocs);
408 bo_gem->relocs = NULL;
410 free (bo_gem->reloc_target_bo);
411 bo_gem->reloc_target_bo = NULL;
413 return 1;
414 }
416 return 0;
417 }
419 static int
420 drm_intel_gem_bo_busy(drm_intel_bo *bo)
421 {
422 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
423 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
424 struct drm_i915_gem_busy busy;
425 int ret;
427 memset(&busy, 0, sizeof(busy));
428 busy.handle = bo_gem->gem_handle;
430 do {
431 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
432 } while (ret == -1 && errno == EINTR);
434 return (ret == 0 && busy.busy);
435 }
437 static int
438 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
439 drm_intel_bo_gem *bo_gem, int state)
440 {
441 struct drm_i915_gem_madvise madv;
443 madv.handle = bo_gem->gem_handle;
444 madv.madv = state;
445 madv.retained = 1;
446 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
448 return madv.retained;
449 }
451 static int
452 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
453 {
454 return drm_intel_gem_bo_madvise_internal
455 ((drm_intel_bufmgr_gem *) bo->bufmgr,
456 (drm_intel_bo_gem *) bo,
457 madv);
458 }
460 /* drop the oldest entries that have been purged by the kernel */
461 static void
462 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
463 struct drm_intel_gem_bo_bucket *bucket)
464 {
465 while (!DRMLISTEMPTY(&bucket->head)) {
466 drm_intel_bo_gem *bo_gem;
468 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
469 bucket->head.next, head);
470 if (drm_intel_gem_bo_madvise_internal
471 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
472 break;
474 DRMLISTDEL(&bo_gem->head);
475 drm_intel_gem_bo_free(&bo_gem->bo);
476 }
477 }
479 static drm_intel_bo *
480 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
481 const char *name,
482 unsigned long size,
483 unsigned long flags)
484 {
485 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
486 drm_intel_bo_gem *bo_gem;
487 unsigned int page_size = getpagesize();
488 int ret;
489 struct drm_intel_gem_bo_bucket *bucket;
490 int alloc_from_cache;
491 unsigned long bo_size;
492 int for_render = 0;
494 if (flags & BO_ALLOC_FOR_RENDER)
495 for_render = 1;
497 /* Round the allocated size up to a power of two number of pages. */
498 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
500 /* If we don't have caching at this size, don't actually round the
501 * allocation up.
502 */
503 if (bucket == NULL) {
504 bo_size = size;
505 if (bo_size < page_size)
506 bo_size = page_size;
507 } else {
508 bo_size = bucket->size;
509 }
511 pthread_mutex_lock(&bufmgr_gem->lock);
512 /* Get a buffer out of the cache if available */
513 retry:
514 alloc_from_cache = 0;
515 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
516 if (for_render) {
517 /* Allocate new render-target BOs from the tail (MRU)
518 * of the list, as it will likely be hot in the GPU
519 * cache and in the aperture for us.
520 */
521 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
522 bucket->head.prev, head);
523 DRMLISTDEL(&bo_gem->head);
524 alloc_from_cache = 1;
525 } else {
526 /* For non-render-target BOs (where we're probably
527 * going to map it first thing in order to fill it
528 * with data), check if the last BO in the cache is
529 * unbusy, and only reuse in that case. Otherwise,
530 * allocating a new buffer is probably faster than
531 * waiting for the GPU to finish.
532 */
533 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
534 bucket->head.next, head);
535 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
536 alloc_from_cache = 1;
537 DRMLISTDEL(&bo_gem->head);
538 }
539 }
541 if (alloc_from_cache) {
542 if (!drm_intel_gem_bo_madvise_internal
543 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
544 drm_intel_gem_bo_free(&bo_gem->bo);
545 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
546 bucket);
547 goto retry;
548 }
549 }
550 }
551 pthread_mutex_unlock(&bufmgr_gem->lock);
553 if (!alloc_from_cache) {
554 struct drm_i915_gem_create create;
556 bo_gem = calloc(1, sizeof(*bo_gem));
557 if (!bo_gem)
558 return NULL;
560 bo_gem->bo.size = bo_size;
561 memset(&create, 0, sizeof(create));
562 create.size = bo_size;
564 do {
565 ret = ioctl(bufmgr_gem->fd,
566 DRM_IOCTL_I915_GEM_CREATE,
567 &create);
568 } while (ret == -1 && errno == EINTR);
569 bo_gem->gem_handle = create.handle;
570 bo_gem->bo.handle = bo_gem->gem_handle;
571 if (ret != 0) {
572 free(bo_gem);
573 return NULL;
574 }
575 bo_gem->bo.bufmgr = bufmgr;
576 }
578 bo_gem->name = name;
579 atomic_set(&bo_gem->refcount, 1);
580 bo_gem->validate_index = -1;
581 bo_gem->reloc_tree_fences = 0;
582 bo_gem->used_as_reloc_target = 0;
583 bo_gem->has_error = 0;
584 bo_gem->tiling_mode = I915_TILING_NONE;
585 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
586 bo_gem->reusable = 1;
588 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
590 DBG("bo_create: buf %d (%s) %ldb\n",
591 bo_gem->gem_handle, bo_gem->name, size);
593 return &bo_gem->bo;
594 }
596 static drm_intel_bo *
597 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
598 const char *name,
599 unsigned long size,
600 unsigned int alignment)
601 {
602 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
603 BO_ALLOC_FOR_RENDER);
604 }
606 static drm_intel_bo *
607 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
608 const char *name,
609 unsigned long size,
610 unsigned int alignment)
611 {
612 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
613 }
615 static drm_intel_bo *
616 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
617 int x, int y, int cpp, uint32_t *tiling_mode,
618 unsigned long *pitch, unsigned long flags)
619 {
620 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
621 drm_intel_bo *bo;
622 unsigned long size, stride, aligned_y = y;
623 int ret;
625 if (*tiling_mode == I915_TILING_NONE)
626 aligned_y = ALIGN(y, 2);
627 else if (*tiling_mode == I915_TILING_X)
628 aligned_y = ALIGN(y, 8);
629 else if (*tiling_mode == I915_TILING_Y)
630 aligned_y = ALIGN(y, 32);
632 stride = x * cpp;
633 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
634 size = stride * aligned_y;
635 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
637 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
638 if (!bo)
639 return NULL;
641 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
642 if (ret != 0) {
643 drm_intel_gem_bo_unreference(bo);
644 return NULL;
645 }
647 *pitch = stride;
649 return bo;
650 }
652 /**
653 * Returns a drm_intel_bo wrapping the given buffer object handle.
654 *
655 * This can be used when one application needs to pass a buffer object
656 * to another.
657 */
658 drm_intel_bo *
659 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
660 const char *name,
661 unsigned int handle)
662 {
663 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
664 drm_intel_bo_gem *bo_gem;
665 int ret;
666 struct drm_gem_open open_arg;
667 struct drm_i915_gem_get_tiling get_tiling;
669 bo_gem = calloc(1, sizeof(*bo_gem));
670 if (!bo_gem)
671 return NULL;
673 memset(&open_arg, 0, sizeof(open_arg));
674 open_arg.name = handle;
675 do {
676 ret = ioctl(bufmgr_gem->fd,
677 DRM_IOCTL_GEM_OPEN,
678 &open_arg);
679 } while (ret == -1 && errno == EINTR);
680 if (ret != 0) {
681 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
682 name, handle, strerror(errno));
683 free(bo_gem);
684 return NULL;
685 }
686 bo_gem->bo.size = open_arg.size;
687 bo_gem->bo.offset = 0;
688 bo_gem->bo.virtual = NULL;
689 bo_gem->bo.bufmgr = bufmgr;
690 bo_gem->name = name;
691 atomic_set(&bo_gem->refcount, 1);
692 bo_gem->validate_index = -1;
693 bo_gem->gem_handle = open_arg.handle;
694 bo_gem->global_name = handle;
695 bo_gem->reusable = 0;
697 memset(&get_tiling, 0, sizeof(get_tiling));
698 get_tiling.handle = bo_gem->gem_handle;
699 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
700 if (ret != 0) {
701 drm_intel_gem_bo_unreference(&bo_gem->bo);
702 return NULL;
703 }
704 bo_gem->tiling_mode = get_tiling.tiling_mode;
705 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
706 if (bo_gem->tiling_mode == I915_TILING_NONE)
707 bo_gem->reloc_tree_fences = 0;
708 else
709 bo_gem->reloc_tree_fences = 1;
710 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
712 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
714 return &bo_gem->bo;
715 }
717 static void
718 drm_intel_gem_bo_free(drm_intel_bo *bo)
719 {
720 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
721 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
722 struct drm_gem_close close;
723 int ret;
725 if (bo_gem->mem_virtual)
726 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
727 if (bo_gem->gtt_virtual)
728 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
730 /* Close this object */
731 memset(&close, 0, sizeof(close));
732 close.handle = bo_gem->gem_handle;
733 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
734 if (ret != 0) {
735 fprintf(stderr,
736 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
737 bo_gem->gem_handle, bo_gem->name, strerror(errno));
738 }
739 free(bo);
740 }
742 /** Frees all cached buffers significantly older than @time. */
743 static void
744 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
745 {
746 int i;
748 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
749 struct drm_intel_gem_bo_bucket *bucket =
750 &bufmgr_gem->cache_bucket[i];
752 while (!DRMLISTEMPTY(&bucket->head)) {
753 drm_intel_bo_gem *bo_gem;
755 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
756 bucket->head.next, head);
757 if (time - bo_gem->free_time <= 1)
758 break;
760 DRMLISTDEL(&bo_gem->head);
762 drm_intel_gem_bo_free(&bo_gem->bo);
763 }
764 }
765 }
767 static void
768 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
769 {
770 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
771 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
772 struct drm_intel_gem_bo_bucket *bucket;
773 uint32_t tiling_mode;
774 int i;
776 /* Unreference all the target buffers */
777 for (i = 0; i < bo_gem->reloc_count; i++) {
778 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
779 reloc_target_bo[i],
780 time);
781 }
782 bo_gem->reloc_count = 0;
783 bo_gem->used_as_reloc_target = 0;
785 DBG("bo_unreference final: %d (%s)\n",
786 bo_gem->gem_handle, bo_gem->name);
788 /* release memory associated with this object */
789 if (bo_gem->reloc_target_bo) {
790 free(bo_gem->reloc_target_bo);
791 bo_gem->reloc_target_bo = NULL;
792 }
793 if (bo_gem->relocs) {
794 free(bo_gem->relocs);
795 bo_gem->relocs = NULL;
796 }
798 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
799 /* Put the buffer into our internal cache for reuse if we can. */
800 tiling_mode = I915_TILING_NONE;
801 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
802 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
803 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
804 I915_MADV_DONTNEED)) {
805 bo_gem->free_time = time;
807 bo_gem->name = NULL;
808 bo_gem->validate_index = -1;
810 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
812 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
813 } else {
814 drm_intel_gem_bo_free(bo);
815 }
816 }
818 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
819 time_t time)
820 {
821 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
823 assert(atomic_read(&bo_gem->refcount) > 0);
824 if (atomic_dec_and_test(&bo_gem->refcount))
825 drm_intel_gem_bo_unreference_final(bo, time);
826 }
828 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
829 {
830 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
832 assert(atomic_read(&bo_gem->refcount) > 0);
833 if (atomic_dec_and_test(&bo_gem->refcount)) {
834 drm_intel_bufmgr_gem *bufmgr_gem =
835 (drm_intel_bufmgr_gem *) bo->bufmgr;
836 struct timespec time;
838 clock_gettime(CLOCK_MONOTONIC, &time);
840 pthread_mutex_lock(&bufmgr_gem->lock);
841 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
842 pthread_mutex_unlock(&bufmgr_gem->lock);
843 }
844 }
846 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
847 {
848 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
849 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
850 struct drm_i915_gem_set_domain set_domain;
851 int ret;
853 pthread_mutex_lock(&bufmgr_gem->lock);
855 /* Allow recursive mapping. Mesa may recursively map buffers with
856 * nested display loops.
857 */
858 if (!bo_gem->mem_virtual) {
859 struct drm_i915_gem_mmap mmap_arg;
861 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
863 memset(&mmap_arg, 0, sizeof(mmap_arg));
864 mmap_arg.handle = bo_gem->gem_handle;
865 mmap_arg.offset = 0;
866 mmap_arg.size = bo->size;
867 do {
868 ret = ioctl(bufmgr_gem->fd,
869 DRM_IOCTL_I915_GEM_MMAP,
870 &mmap_arg);
871 } while (ret == -1 && errno == EINTR);
872 if (ret != 0) {
873 ret = -errno;
874 fprintf(stderr,
875 "%s:%d: Error mapping buffer %d (%s): %s .\n",
876 __FILE__, __LINE__, bo_gem->gem_handle,
877 bo_gem->name, strerror(errno));
878 pthread_mutex_unlock(&bufmgr_gem->lock);
879 return ret;
880 }
881 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
882 }
883 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
884 bo_gem->mem_virtual);
885 bo->virtual = bo_gem->mem_virtual;
887 set_domain.handle = bo_gem->gem_handle;
888 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
889 if (write_enable)
890 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
891 else
892 set_domain.write_domain = 0;
893 do {
894 ret = ioctl(bufmgr_gem->fd,
895 DRM_IOCTL_I915_GEM_SET_DOMAIN,
896 &set_domain);
897 } while (ret == -1 && errno == EINTR);
898 if (ret != 0) {
899 ret = -errno;
900 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
901 __FILE__, __LINE__, bo_gem->gem_handle,
902 strerror(errno));
903 pthread_mutex_unlock(&bufmgr_gem->lock);
904 return ret;
905 }
907 pthread_mutex_unlock(&bufmgr_gem->lock);
909 return 0;
910 }
912 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
913 {
914 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
915 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
916 struct drm_i915_gem_set_domain set_domain;
917 int ret;
919 pthread_mutex_lock(&bufmgr_gem->lock);
921 /* Get a mapping of the buffer if we haven't before. */
922 if (bo_gem->gtt_virtual == NULL) {
923 struct drm_i915_gem_mmap_gtt mmap_arg;
925 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
926 bo_gem->name);
928 memset(&mmap_arg, 0, sizeof(mmap_arg));
929 mmap_arg.handle = bo_gem->gem_handle;
931 /* Get the fake offset back... */
932 do {
933 ret = ioctl(bufmgr_gem->fd,
934 DRM_IOCTL_I915_GEM_MMAP_GTT,
935 &mmap_arg);
936 } while (ret == -1 && errno == EINTR);
937 if (ret != 0) {
938 ret = -errno;
939 fprintf(stderr,
940 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
941 __FILE__, __LINE__,
942 bo_gem->gem_handle, bo_gem->name,
943 strerror(errno));
944 pthread_mutex_unlock(&bufmgr_gem->lock);
945 return ret;
946 }
948 /* and mmap it */
949 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
950 MAP_SHARED, bufmgr_gem->fd,
951 mmap_arg.offset);
952 if (bo_gem->gtt_virtual == MAP_FAILED) {
953 ret = -errno;
954 fprintf(stderr,
955 "%s:%d: Error mapping buffer %d (%s): %s .\n",
956 __FILE__, __LINE__,
957 bo_gem->gem_handle, bo_gem->name,
958 strerror(errno));
959 pthread_mutex_unlock(&bufmgr_gem->lock);
960 return ret;
961 }
962 }
964 bo->virtual = bo_gem->gtt_virtual;
966 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
967 bo_gem->gtt_virtual);
969 /* Now move it to the GTT domain so that the CPU caches are flushed */
970 set_domain.handle = bo_gem->gem_handle;
971 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
972 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
973 do {
974 ret = ioctl(bufmgr_gem->fd,
975 DRM_IOCTL_I915_GEM_SET_DOMAIN,
976 &set_domain);
977 } while (ret == -1 && errno == EINTR);
979 if (ret != 0) {
980 ret = -errno;
981 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
982 __FILE__, __LINE__, bo_gem->gem_handle,
983 strerror(errno));
984 }
986 pthread_mutex_unlock(&bufmgr_gem->lock);
988 return ret;
989 }
991 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
992 {
993 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
994 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
995 int ret = 0;
997 if (bo == NULL)
998 return 0;
1000 assert(bo_gem->gtt_virtual != NULL);
1002 pthread_mutex_lock(&bufmgr_gem->lock);
1003 bo->virtual = NULL;
1004 pthread_mutex_unlock(&bufmgr_gem->lock);
1006 return ret;
1007 }
1009 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1010 {
1011 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1012 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1013 struct drm_i915_gem_sw_finish sw_finish;
1014 int ret;
1016 if (bo == NULL)
1017 return 0;
1019 assert(bo_gem->mem_virtual != NULL);
1021 pthread_mutex_lock(&bufmgr_gem->lock);
1023 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1024 * results show up in a timely manner.
1025 */
1026 sw_finish.handle = bo_gem->gem_handle;
1027 do {
1028 ret = ioctl(bufmgr_gem->fd,
1029 DRM_IOCTL_I915_GEM_SW_FINISH,
1030 &sw_finish);
1031 } while (ret == -1 && errno == EINTR);
1033 bo->virtual = NULL;
1034 pthread_mutex_unlock(&bufmgr_gem->lock);
1035 return 0;
1036 }
1038 static int
1039 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1040 unsigned long size, const void *data)
1041 {
1042 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1043 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1044 struct drm_i915_gem_pwrite pwrite;
1045 int ret;
1047 memset(&pwrite, 0, sizeof(pwrite));
1048 pwrite.handle = bo_gem->gem_handle;
1049 pwrite.offset = offset;
1050 pwrite.size = size;
1051 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1052 do {
1053 ret = ioctl(bufmgr_gem->fd,
1054 DRM_IOCTL_I915_GEM_PWRITE,
1055 &pwrite);
1056 } while (ret == -1 && errno == EINTR);
1057 if (ret != 0) {
1058 fprintf(stderr,
1059 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1060 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1061 (int)size, strerror(errno));
1062 }
1063 return 0;
1064 }
1066 static int
1067 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1068 {
1069 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1070 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1071 int ret;
1073 get_pipe_from_crtc_id.crtc_id = crtc_id;
1074 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1075 &get_pipe_from_crtc_id);
1076 if (ret != 0) {
1077 /* We return -1 here to signal that we don't
1078 * know which pipe is associated with this crtc.
1079 * This lets the caller know that this information
1080 * isn't available; using the wrong pipe for
1081 * vblank waiting can cause the chipset to lock up
1082 */
1083 return -1;
1084 }
1086 return get_pipe_from_crtc_id.pipe;
1087 }
1089 static int
1090 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1091 unsigned long size, void *data)
1092 {
1093 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1094 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1095 struct drm_i915_gem_pread pread;
1096 int ret;
1098 memset(&pread, 0, sizeof(pread));
1099 pread.handle = bo_gem->gem_handle;
1100 pread.offset = offset;
1101 pread.size = size;
1102 pread.data_ptr = (uint64_t) (uintptr_t) data;
1103 do {
1104 ret = ioctl(bufmgr_gem->fd,
1105 DRM_IOCTL_I915_GEM_PREAD,
1106 &pread);
1107 } while (ret == -1 && errno == EINTR);
1108 if (ret != 0) {
1109 ret = -errno;
1110 fprintf(stderr,
1111 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1112 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1113 (int)size, strerror(errno));
1114 }
1115 return ret;
1116 }
1118 /** Waits for all GPU rendering to the object to have completed. */
1119 static void
1120 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1121 {
1122 drm_intel_gem_bo_start_gtt_access(bo, 0);
1123 }
1125 /**
1126 * Sets the object to the GTT read and possibly write domain, used by the X
1127 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1128 *
1129 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1130 * can do tiled pixmaps this way.
1131 */
1132 void
1133 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1134 {
1135 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1136 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1137 struct drm_i915_gem_set_domain set_domain;
1138 int ret;
1140 set_domain.handle = bo_gem->gem_handle;
1141 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1142 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1143 do {
1144 ret = ioctl(bufmgr_gem->fd,
1145 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1146 &set_domain);
1147 } while (ret == -1 && errno == EINTR);
1148 if (ret != 0) {
1149 fprintf(stderr,
1150 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1151 __FILE__, __LINE__, bo_gem->gem_handle,
1152 set_domain.read_domains, set_domain.write_domain,
1153 strerror(errno));
1154 }
1155 }
1157 static void
1158 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1159 {
1160 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1161 int i;
1163 free(bufmgr_gem->exec_objects);
1164 free(bufmgr_gem->exec_bos);
1166 pthread_mutex_destroy(&bufmgr_gem->lock);
1168 /* Free any cached buffer objects we were going to reuse */
1169 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1170 struct drm_intel_gem_bo_bucket *bucket =
1171 &bufmgr_gem->cache_bucket[i];
1172 drm_intel_bo_gem *bo_gem;
1174 while (!DRMLISTEMPTY(&bucket->head)) {
1175 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1176 bucket->head.next, head);
1177 DRMLISTDEL(&bo_gem->head);
1179 drm_intel_gem_bo_free(&bo_gem->bo);
1180 }
1181 }
1183 free(bufmgr);
1184 }
1186 /**
1187 * Adds the target buffer to the validation list and adds the relocation
1188 * to the reloc_buffer's relocation list.
1189 *
1190 * The relocation entry at the given offset must already contain the
1191 * precomputed relocation value, because the kernel will optimize out
1192 * the relocation entry write when the buffer hasn't moved from the
1193 * last known offset in target_bo.
1194 */
1195 static int
1196 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1197 drm_intel_bo *target_bo, uint32_t target_offset,
1198 uint32_t read_domains, uint32_t write_domain)
1199 {
1200 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1201 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1202 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1204 if (bo_gem->has_error)
1205 return -ENOMEM;
1207 if (target_bo_gem->has_error) {
1208 bo_gem->has_error = 1;
1209 return -ENOMEM;
1210 }
1212 /* Create a new relocation list if needed */
1213 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1214 return -ENOMEM;
1216 /* Check overflow */
1217 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1219 /* Check args */
1220 assert(offset <= bo->size - 4);
1221 assert((write_domain & (write_domain - 1)) == 0);
1223 /* Make sure that we're not adding a reloc to something whose size has
1224 * already been accounted for.
1225 */
1226 assert(!bo_gem->used_as_reloc_target);
1227 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1228 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1230 /* Flag the target to disallow further relocations in it. */
1231 target_bo_gem->used_as_reloc_target = 1;
1233 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1234 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1235 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1236 target_bo_gem->gem_handle;
1237 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1238 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1239 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1241 bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
1242 drm_intel_gem_bo_reference(target_bo);
1244 bo_gem->reloc_count++;
1246 return 0;
1247 }
1249 /**
1250 * Walk the tree of relocations rooted at BO and accumulate the list of
1251 * validations to be performed and update the relocation buffers with
1252 * index values into the validation list.
1253 */
1254 static void
1255 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1256 {
1257 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1258 int i;
1260 if (bo_gem->relocs == NULL)
1261 return;
1263 for (i = 0; i < bo_gem->reloc_count; i++) {
1264 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[i];
1266 /* Continue walking the tree depth-first. */
1267 drm_intel_gem_bo_process_reloc(target_bo);
1269 /* Add the target to the validate list */
1270 drm_intel_add_validate_buffer(target_bo);
1271 }
1272 }
1274 static void
1275 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1276 {
1277 int i;
1279 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1280 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1281 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1283 /* Update the buffer offset */
1284 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1285 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1286 bo_gem->gem_handle, bo_gem->name, bo->offset,
1287 (unsigned long long)bufmgr_gem->exec_objects[i].
1288 offset);
1289 bo->offset = bufmgr_gem->exec_objects[i].offset;
1290 }
1291 }
1292 }
1294 static int
1295 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1296 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1297 {
1298 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1299 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1300 struct drm_i915_gem_execbuffer execbuf;
1301 int ret, i;
1303 if (bo_gem->has_error)
1304 return -ENOMEM;
1306 pthread_mutex_lock(&bufmgr_gem->lock);
1307 /* Update indices and set up the validate list. */
1308 drm_intel_gem_bo_process_reloc(bo);
1310 /* Add the batch buffer to the validation list. There are no
1311 * relocations pointing to it.
1312 */
1313 drm_intel_add_validate_buffer(bo);
1315 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1316 execbuf.buffer_count = bufmgr_gem->exec_count;
1317 execbuf.batch_start_offset = 0;
1318 execbuf.batch_len = used;
1319 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1320 execbuf.num_cliprects = num_cliprects;
1321 execbuf.DR1 = 0;
1322 execbuf.DR4 = DR4;
1324 do {
1325 ret = ioctl(bufmgr_gem->fd,
1326 DRM_IOCTL_I915_GEM_EXECBUFFER,
1327 &execbuf);
1328 } while (ret != 0 && errno == EINTR);
1330 if (ret != 0) {
1331 ret = -errno;
1332 if (errno == ENOSPC) {
1333 fprintf(stderr,
1334 "Execbuffer fails to pin. "
1335 "Estimate: %u. Actual: %u. Available: %u\n",
1336 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1337 bufmgr_gem->
1338 exec_count),
1339 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1340 bufmgr_gem->
1341 exec_count),
1342 (unsigned int)bufmgr_gem->gtt_size);
1343 }
1344 }
1345 drm_intel_update_buffer_offsets(bufmgr_gem);
1347 if (bufmgr_gem->bufmgr.debug)
1348 drm_intel_gem_dump_validation_list(bufmgr_gem);
1350 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1351 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1352 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1354 /* Disconnect the buffer from the validate list */
1355 bo_gem->validate_index = -1;
1356 bufmgr_gem->exec_bos[i] = NULL;
1357 }
1358 bufmgr_gem->exec_count = 0;
1359 pthread_mutex_unlock(&bufmgr_gem->lock);
1361 return ret;
1362 }
1364 static int
1365 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1366 {
1367 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1368 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1369 struct drm_i915_gem_pin pin;
1370 int ret;
1372 memset(&pin, 0, sizeof(pin));
1373 pin.handle = bo_gem->gem_handle;
1374 pin.alignment = alignment;
1376 do {
1377 ret = ioctl(bufmgr_gem->fd,
1378 DRM_IOCTL_I915_GEM_PIN,
1379 &pin);
1380 } while (ret == -1 && errno == EINTR);
1382 if (ret != 0)
1383 return -errno;
1385 bo->offset = pin.offset;
1386 return 0;
1387 }
1389 static int
1390 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1391 {
1392 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1393 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1394 struct drm_i915_gem_unpin unpin;
1395 int ret;
1397 memset(&unpin, 0, sizeof(unpin));
1398 unpin.handle = bo_gem->gem_handle;
1400 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1401 if (ret != 0)
1402 return -errno;
1404 return 0;
1405 }
1407 static int
1408 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1409 uint32_t stride)
1410 {
1411 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1412 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1413 struct drm_i915_gem_set_tiling set_tiling;
1414 int ret;
1416 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1417 return 0;
1419 /* If we're going from non-tiling to tiling, bump fence count */
1420 if (bo_gem->tiling_mode == I915_TILING_NONE)
1421 bo_gem->reloc_tree_fences++;
1423 memset(&set_tiling, 0, sizeof(set_tiling));
1424 set_tiling.handle = bo_gem->gem_handle;
1425 set_tiling.tiling_mode = *tiling_mode;
1426 set_tiling.stride = stride;
1428 do {
1429 ret = ioctl(bufmgr_gem->fd,
1430 DRM_IOCTL_I915_GEM_SET_TILING,
1431 &set_tiling);
1432 } while (ret == -1 && errno == EINTR);
1433 if (ret != 0) {
1434 *tiling_mode = bo_gem->tiling_mode;
1435 return -errno;
1436 }
1437 bo_gem->tiling_mode = set_tiling.tiling_mode;
1438 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1440 /* If we're going from tiling to non-tiling, drop fence count */
1441 if (bo_gem->tiling_mode == I915_TILING_NONE)
1442 bo_gem->reloc_tree_fences--;
1444 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1446 *tiling_mode = bo_gem->tiling_mode;
1447 return 0;
1448 }
1450 static int
1451 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1452 uint32_t * swizzle_mode)
1453 {
1454 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1456 *tiling_mode = bo_gem->tiling_mode;
1457 *swizzle_mode = bo_gem->swizzle_mode;
1458 return 0;
1459 }
1461 static int
1462 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1463 {
1464 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1465 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1466 struct drm_gem_flink flink;
1467 int ret;
1469 if (!bo_gem->global_name) {
1470 memset(&flink, 0, sizeof(flink));
1471 flink.handle = bo_gem->gem_handle;
1473 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1474 if (ret != 0)
1475 return -errno;
1476 bo_gem->global_name = flink.name;
1477 bo_gem->reusable = 0;
1478 }
1480 *name = bo_gem->global_name;
1481 return 0;
1482 }
1484 /**
1485 * Enables unlimited caching of buffer objects for reuse.
1486 *
1487 * This is potentially very memory expensive, as the cache at each bucket
1488 * size is only bounded by how many buffers of that size we've managed to have
1489 * in flight at once.
1490 */
1491 void
1492 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1493 {
1494 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1496 bufmgr_gem->bo_reuse = 1;
1497 }
1499 /**
1500 * Return the additional aperture space required by the tree of buffer objects
1501 * rooted at bo.
1502 */
1503 static int
1504 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1505 {
1506 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1507 int i;
1508 int total = 0;
1510 if (bo == NULL || bo_gem->included_in_check_aperture)
1511 return 0;
1513 total += bo->size;
1514 bo_gem->included_in_check_aperture = 1;
1516 for (i = 0; i < bo_gem->reloc_count; i++)
1517 total +=
1518 drm_intel_gem_bo_get_aperture_space(bo_gem->
1519 reloc_target_bo[i]);
1521 return total;
1522 }
1524 /**
1525 * Count the number of buffers in this list that need a fence reg
1526 *
1527 * If the count is greater than the number of available regs, we'll have
1528 * to ask the caller to resubmit a batch with fewer tiled buffers.
1529 *
1530 * This function over-counts if the same buffer is used multiple times.
1531 */
1532 static unsigned int
1533 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1534 {
1535 int i;
1536 unsigned int total = 0;
1538 for (i = 0; i < count; i++) {
1539 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1541 if (bo_gem == NULL)
1542 continue;
1544 total += bo_gem->reloc_tree_fences;
1545 }
1546 return total;
1547 }
1549 /**
1550 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1551 * for the next drm_intel_bufmgr_check_aperture_space() call.
1552 */
1553 static void
1554 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1555 {
1556 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1557 int i;
1559 if (bo == NULL || !bo_gem->included_in_check_aperture)
1560 return;
1562 bo_gem->included_in_check_aperture = 0;
1564 for (i = 0; i < bo_gem->reloc_count; i++)
1565 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1566 reloc_target_bo[i]);
1567 }
1569 /**
1570 * Return a conservative estimate for the amount of aperture required
1571 * for a collection of buffers. This may double-count some buffers.
1572 */
1573 static unsigned int
1574 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1575 {
1576 int i;
1577 unsigned int total = 0;
1579 for (i = 0; i < count; i++) {
1580 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1581 if (bo_gem != NULL)
1582 total += bo_gem->reloc_tree_size;
1583 }
1584 return total;
1585 }
1587 /**
1588 * Return the amount of aperture needed for a collection of buffers.
1589 * This avoids double counting any buffers, at the cost of looking
1590 * at every buffer in the set.
1591 */
1592 static unsigned int
1593 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1594 {
1595 int i;
1596 unsigned int total = 0;
1598 for (i = 0; i < count; i++) {
1599 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1600 /* For the first buffer object in the array, we get an
1601 * accurate count back for its reloc_tree size (since nothing
1602 * had been flagged as being counted yet). We can save that
1603 * value out as a more conservative reloc_tree_size that
1604 * avoids double-counting target buffers. Since the first
1605 * buffer happens to usually be the batch buffer in our
1606 * callers, this can pull us back from doing the tree
1607 * walk on every new batch emit.
1608 */
1609 if (i == 0) {
1610 drm_intel_bo_gem *bo_gem =
1611 (drm_intel_bo_gem *) bo_array[i];
1612 bo_gem->reloc_tree_size = total;
1613 }
1614 }
1616 for (i = 0; i < count; i++)
1617 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1618 return total;
1619 }
1621 /**
1622 * Return -1 if the batchbuffer should be flushed before attempting to
1623 * emit rendering referencing the buffers pointed to by bo_array.
1624 *
1625 * This is required because if we try to emit a batchbuffer with relocations
1626 * to a tree of buffers that won't simultaneously fit in the aperture,
1627 * the rendering will return an error at a point where the software is not
1628 * prepared to recover from it.
1629 *
1630 * However, we also want to emit the batchbuffer significantly before we reach
1631 * the limit, as a series of batchbuffers each of which references buffers
1632 * covering almost all of the aperture means that at each emit we end up
1633 * waiting to evict a buffer from the last rendering, and we get synchronous
1634 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1635 * get better parallelism.
1636 */
1637 static int
1638 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1639 {
1640 drm_intel_bufmgr_gem *bufmgr_gem =
1641 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1642 unsigned int total = 0;
1643 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1644 int total_fences;
1646 /* Check for fence reg constraints if necessary */
1647 if (bufmgr_gem->available_fences) {
1648 total_fences = drm_intel_gem_total_fences(bo_array, count);
1649 if (total_fences > bufmgr_gem->available_fences)
1650 return -ENOSPC;
1651 }
1653 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1655 if (total > threshold)
1656 total = drm_intel_gem_compute_batch_space(bo_array, count);
1658 if (total > threshold) {
1659 DBG("check_space: overflowed available aperture, "
1660 "%dkb vs %dkb\n",
1661 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1662 return -ENOSPC;
1663 } else {
1664 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1665 (int)bufmgr_gem->gtt_size / 1024);
1666 return 0;
1667 }
1668 }
1670 /*
1671 * Disable buffer reuse for objects which are shared with the kernel
1672 * as scanout buffers
1673 */
1674 static int
1675 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1676 {
1677 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1679 bo_gem->reusable = 0;
1680 return 0;
1681 }
1683 static int
1684 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1685 {
1686 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1687 int i;
1689 for (i = 0; i < bo_gem->reloc_count; i++) {
1690 if (bo_gem->reloc_target_bo[i] == target_bo)
1691 return 1;
1692 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_bo[i],
1693 target_bo))
1694 return 1;
1695 }
1697 return 0;
1698 }
1700 /** Return true if target_bo is referenced by bo's relocation tree. */
1701 static int
1702 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1703 {
1704 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1706 if (bo == NULL || target_bo == NULL)
1707 return 0;
1708 if (target_bo_gem->used_as_reloc_target)
1709 return _drm_intel_gem_bo_references(bo, target_bo);
1710 return 0;
1711 }
1713 /**
1714 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1715 * and manage map buffer objections.
1716 *
1717 * \param fd File descriptor of the opened DRM device.
1718 */
1719 drm_intel_bufmgr *
1720 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1721 {
1722 drm_intel_bufmgr_gem *bufmgr_gem;
1723 struct drm_i915_gem_get_aperture aperture;
1724 drm_i915_getparam_t gp;
1725 int ret, i;
1726 unsigned long size;
1728 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1729 bufmgr_gem->fd = fd;
1731 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1732 free(bufmgr_gem);
1733 return NULL;
1734 }
1736 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1738 if (ret == 0)
1739 bufmgr_gem->gtt_size = aperture.aper_available_size;
1740 else {
1741 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1742 strerror(errno));
1743 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1744 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1745 "May lead to reduced performance or incorrect "
1746 "rendering.\n",
1747 (int)bufmgr_gem->gtt_size / 1024);
1748 }
1750 gp.param = I915_PARAM_CHIPSET_ID;
1751 gp.value = &bufmgr_gem->pci_device;
1752 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1753 if (ret) {
1754 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1755 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1756 }
1758 if (!IS_I965G(bufmgr_gem)) {
1759 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1760 gp.value = &bufmgr_gem->available_fences;
1761 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1762 if (ret) {
1763 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
1764 errno);
1765 fprintf(stderr, "param: %d, val: %d\n", gp.param,
1766 *gp.value);
1767 bufmgr_gem->available_fences = 0;
1768 }
1769 }
1771 /* Let's go with one relocation per every 2 dwords (but round down a bit
1772 * since a power of two will mean an extra page allocation for the reloc
1773 * buffer).
1774 *
1775 * Every 4 was too few for the blender benchmark.
1776 */
1777 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
1779 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
1780 bufmgr_gem->bufmgr.bo_alloc_for_render =
1781 drm_intel_gem_bo_alloc_for_render;
1782 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
1783 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
1784 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
1785 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
1786 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
1787 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
1788 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
1789 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
1790 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
1791 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
1792 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
1793 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
1794 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
1795 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
1796 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
1797 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
1798 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
1799 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
1800 bufmgr_gem->bufmgr.debug = 0;
1801 bufmgr_gem->bufmgr.check_aperture_space =
1802 drm_intel_gem_check_aperture_space;
1803 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
1804 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
1805 drm_intel_gem_get_pipe_from_crtc_id;
1806 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
1808 /* Initialize the linked lists for BO reuse cache. */
1809 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
1810 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
1811 bufmgr_gem->cache_bucket[i].size = size;
1812 }
1814 return &bufmgr_gem->bufmgr;
1815 }