1 /**************************************************************************
2 *
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
26 * of the Software.
27 *
28 *
29 **************************************************************************/
30 /*
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
35 */
37 #ifdef HAVE_CONFIG_H
38 #include "config.h"
39 #endif
41 #include <xf86drm.h>
42 #include <fcntl.h>
43 #include <stdio.h>
44 #include <stdlib.h>
45 #include <string.h>
46 #include <unistd.h>
47 #include <assert.h>
48 #include <pthread.h>
49 #include <sys/ioctl.h>
50 #include <sys/mman.h>
51 #include <sys/stat.h>
52 #include <sys/types.h>
54 #include "errno.h"
55 #include "libdrm_lists.h"
56 #include "intel_atomic.h"
57 #include "intel_bufmgr.h"
58 #include "intel_bufmgr_priv.h"
59 #include "intel_chipset.h"
60 #include "string.h"
62 #include "i915_drm.h"
64 #define DBG(...) do { \
65 if (bufmgr_gem->bufmgr.debug) \
66 fprintf(stderr, __VA_ARGS__); \
67 } while (0)
69 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
71 struct drm_intel_gem_bo_bucket {
72 drmMMListHead head;
73 unsigned long size;
74 };
76 /* Only cache objects up to 64MB. Bigger than that, and the rounding of the
77 * size makes many operations fail that wouldn't otherwise.
78 */
79 #define DRM_INTEL_GEM_BO_BUCKETS 14
80 typedef struct _drm_intel_bufmgr_gem {
81 drm_intel_bufmgr bufmgr;
83 int fd;
85 int max_relocs;
87 pthread_mutex_t lock;
89 struct drm_i915_gem_exec_object *exec_objects;
90 struct drm_i915_gem_exec_object2 *exec2_objects;
91 drm_intel_bo **exec_bos;
92 int exec_size;
93 int exec_count;
95 /** Array of lists of cached gem objects of power-of-two sizes */
96 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
98 uint64_t gtt_size;
99 int available_fences;
100 int pci_device;
101 int gen;
102 char bo_reuse;
103 char fenced_relocs;
104 } drm_intel_bufmgr_gem;
106 #define DRM_INTEL_RELOC_FENCE (1<<0)
108 typedef struct _drm_intel_reloc_target_info {
109 drm_intel_bo *bo;
110 int flags;
111 } drm_intel_reloc_target;
113 struct _drm_intel_bo_gem {
114 drm_intel_bo bo;
116 atomic_t refcount;
117 uint32_t gem_handle;
118 const char *name;
120 /**
121 * Kenel-assigned global name for this object
122 */
123 unsigned int global_name;
125 /**
126 * Index of the buffer within the validation list while preparing a
127 * batchbuffer execution.
128 */
129 int validate_index;
131 /**
132 * Current tiling mode
133 */
134 uint32_t tiling_mode;
135 uint32_t swizzle_mode;
137 time_t free_time;
139 /** Array passed to the DRM containing relocation information. */
140 struct drm_i915_gem_relocation_entry *relocs;
141 /**
142 * Array of info structs corresponding to relocs[i].target_handle etc
143 */
144 drm_intel_reloc_target *reloc_target_info;
145 /** Number of entries in relocs */
146 int reloc_count;
147 /** Mapped address for the buffer, saved across map/unmap cycles */
148 void *mem_virtual;
149 /** GTT virtual address for the buffer, saved across map/unmap cycles */
150 void *gtt_virtual;
152 /** BO cache list */
153 drmMMListHead head;
155 /**
156 * Boolean of whether this BO and its children have been included in
157 * the current drm_intel_bufmgr_check_aperture_space() total.
158 */
159 char included_in_check_aperture;
161 /**
162 * Boolean of whether this buffer has been used as a relocation
163 * target and had its size accounted for, and thus can't have any
164 * further relocations added to it.
165 */
166 char used_as_reloc_target;
168 /**
169 * Boolean of whether we have encountered an error whilst building the relocation tree.
170 */
171 char has_error;
173 /**
174 * Boolean of whether this buffer can be re-used
175 */
176 char reusable;
178 /**
179 * Size in bytes of this buffer and its relocation descendents.
180 *
181 * Used to avoid costly tree walking in
182 * drm_intel_bufmgr_check_aperture in the common case.
183 */
184 int reloc_tree_size;
186 /**
187 * Number of potential fence registers required by this buffer and its
188 * relocations.
189 */
190 int reloc_tree_fences;
191 };
193 static unsigned int
194 drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count);
196 static unsigned int
197 drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count);
199 static int
200 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
201 uint32_t * swizzle_mode);
203 static int
204 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
205 uint32_t stride);
207 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
208 time_t time);
210 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo);
212 static void drm_intel_gem_bo_free(drm_intel_bo *bo);
214 static unsigned long
215 drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
216 uint32_t *tiling_mode)
217 {
218 unsigned long min_size, max_size;
219 unsigned long i;
221 if (*tiling_mode == I915_TILING_NONE)
222 return size;
224 /* 965+ just need multiples of page size for tiling */
225 if (bufmgr_gem->gen >= 4)
226 return ROUND_UP_TO(size, 4096);
228 /* Older chips need powers of two, of at least 512k or 1M */
229 if (bufmgr_gem->gen == 3) {
230 min_size = 1024*1024;
231 max_size = 128*1024*1024;
232 } else {
233 min_size = 512*1024;
234 max_size = 64*1024*1024;
235 }
237 if (size > max_size) {
238 *tiling_mode = I915_TILING_NONE;
239 return size;
240 }
242 for (i = min_size; i < size; i <<= 1)
243 ;
245 return i;
246 }
248 /*
249 * Round a given pitch up to the minimum required for X tiling on a
250 * given chip. We use 512 as the minimum to allow for a later tiling
251 * change.
252 */
253 static unsigned long
254 drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
255 unsigned long pitch, uint32_t tiling_mode)
256 {
257 unsigned long tile_width = 512;
258 unsigned long i;
260 if (tiling_mode == I915_TILING_NONE)
261 return ROUND_UP_TO(pitch, tile_width);
263 /* 965 is flexible */
264 if (bufmgr_gem->gen >= 4)
265 return ROUND_UP_TO(pitch, tile_width);
267 /* Pre-965 needs power of two tile width */
268 for (i = tile_width; i < pitch; i <<= 1)
269 ;
271 return i;
272 }
274 static struct drm_intel_gem_bo_bucket *
275 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
276 unsigned long size)
277 {
278 int i;
280 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
281 struct drm_intel_gem_bo_bucket *bucket =
282 &bufmgr_gem->cache_bucket[i];
283 if (bucket->size >= size) {
284 return bucket;
285 }
286 }
288 return NULL;
289 }
291 static void
292 drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
293 {
294 int i, j;
296 for (i = 0; i < bufmgr_gem->exec_count; i++) {
297 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
298 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
300 if (bo_gem->relocs == NULL) {
301 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
302 bo_gem->name);
303 continue;
304 }
306 for (j = 0; j < bo_gem->reloc_count; j++) {
307 drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo;
308 drm_intel_bo_gem *target_gem =
309 (drm_intel_bo_gem *) target_bo;
311 DBG("%2d: %d (%s)@0x%08llx -> "
312 "%d (%s)@0x%08lx + 0x%08x\n",
313 i,
314 bo_gem->gem_handle, bo_gem->name,
315 (unsigned long long)bo_gem->relocs[j].offset,
316 target_gem->gem_handle,
317 target_gem->name,
318 target_bo->offset,
319 bo_gem->relocs[j].delta);
320 }
321 }
322 }
324 static inline void
325 drm_intel_gem_bo_reference(drm_intel_bo *bo)
326 {
327 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
329 assert(atomic_read(&bo_gem->refcount) > 0);
330 atomic_inc(&bo_gem->refcount);
331 }
333 /**
334 * Adds the given buffer to the list of buffers to be validated (moved into the
335 * appropriate memory type) with the next batch submission.
336 *
337 * If a buffer is validated multiple times in a batch submission, it ends up
338 * with the intersection of the memory type flags and the union of the
339 * access flags.
340 */
341 static void
342 drm_intel_add_validate_buffer(drm_intel_bo *bo)
343 {
344 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
345 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
346 int index;
348 if (bo_gem->validate_index != -1)
349 return;
351 /* Extend the array of validation entries as necessary. */
352 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
353 int new_size = bufmgr_gem->exec_size * 2;
355 if (new_size == 0)
356 new_size = 5;
358 bufmgr_gem->exec_objects =
359 realloc(bufmgr_gem->exec_objects,
360 sizeof(*bufmgr_gem->exec_objects) * new_size);
361 bufmgr_gem->exec_bos =
362 realloc(bufmgr_gem->exec_bos,
363 sizeof(*bufmgr_gem->exec_bos) * new_size);
364 bufmgr_gem->exec_size = new_size;
365 }
367 index = bufmgr_gem->exec_count;
368 bo_gem->validate_index = index;
369 /* Fill in array entry */
370 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
371 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
372 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
373 bufmgr_gem->exec_objects[index].alignment = 0;
374 bufmgr_gem->exec_objects[index].offset = 0;
375 bufmgr_gem->exec_bos[index] = bo;
376 bufmgr_gem->exec_count++;
377 }
379 static void
380 drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence)
381 {
382 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
383 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
384 int index;
386 if (bo_gem->validate_index != -1)
387 return;
389 /* Extend the array of validation entries as necessary. */
390 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
391 int new_size = bufmgr_gem->exec_size * 2;
393 if (new_size == 0)
394 new_size = 5;
396 bufmgr_gem->exec2_objects =
397 realloc(bufmgr_gem->exec2_objects,
398 sizeof(*bufmgr_gem->exec2_objects) * new_size);
399 bufmgr_gem->exec_bos =
400 realloc(bufmgr_gem->exec_bos,
401 sizeof(*bufmgr_gem->exec_bos) * new_size);
402 bufmgr_gem->exec_size = new_size;
403 }
405 index = bufmgr_gem->exec_count;
406 bo_gem->validate_index = index;
407 /* Fill in array entry */
408 bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle;
409 bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count;
410 bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
411 bufmgr_gem->exec2_objects[index].alignment = 0;
412 bufmgr_gem->exec2_objects[index].offset = 0;
413 bufmgr_gem->exec_bos[index] = bo;
414 bufmgr_gem->exec2_objects[index].flags = 0;
415 bufmgr_gem->exec2_objects[index].rsvd1 = 0;
416 bufmgr_gem->exec2_objects[index].rsvd2 = 0;
417 if (need_fence) {
418 bufmgr_gem->exec2_objects[index].flags |=
419 EXEC_OBJECT_NEEDS_FENCE;
420 }
421 bufmgr_gem->exec_count++;
422 }
424 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
425 sizeof(uint32_t))
427 static void
428 drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem,
429 drm_intel_bo_gem *bo_gem)
430 {
431 int size;
433 assert(!bo_gem->used_as_reloc_target);
435 /* The older chipsets are far-less flexible in terms of tiling,
436 * and require tiled buffer to be size aligned in the aperture.
437 * This means that in the worst possible case we will need a hole
438 * twice as large as the object in order for it to fit into the
439 * aperture. Optimal packing is for wimps.
440 */
441 size = bo_gem->bo.size;
442 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE)
443 size *= 2;
445 bo_gem->reloc_tree_size = size;
446 }
448 static int
449 drm_intel_setup_reloc_list(drm_intel_bo *bo)
450 {
451 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
452 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
453 unsigned int max_relocs = bufmgr_gem->max_relocs;
455 if (bo->size / 4 < max_relocs)
456 max_relocs = bo->size / 4;
458 bo_gem->relocs = malloc(max_relocs *
459 sizeof(struct drm_i915_gem_relocation_entry));
460 bo_gem->reloc_target_info = malloc(max_relocs *
461 sizeof(drm_intel_reloc_target *));
462 if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
463 bo_gem->has_error = 1;
465 free (bo_gem->relocs);
466 bo_gem->relocs = NULL;
468 free (bo_gem->reloc_target_info);
469 bo_gem->reloc_target_info = NULL;
471 return 1;
472 }
474 return 0;
475 }
477 static int
478 drm_intel_gem_bo_busy(drm_intel_bo *bo)
479 {
480 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
481 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
482 struct drm_i915_gem_busy busy;
483 int ret;
485 memset(&busy, 0, sizeof(busy));
486 busy.handle = bo_gem->gem_handle;
488 do {
489 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
490 } while (ret == -1 && errno == EINTR);
492 return (ret == 0 && busy.busy);
493 }
495 static int
496 drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem,
497 drm_intel_bo_gem *bo_gem, int state)
498 {
499 struct drm_i915_gem_madvise madv;
501 madv.handle = bo_gem->gem_handle;
502 madv.madv = state;
503 madv.retained = 1;
504 ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
506 return madv.retained;
507 }
509 static int
510 drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv)
511 {
512 return drm_intel_gem_bo_madvise_internal
513 ((drm_intel_bufmgr_gem *) bo->bufmgr,
514 (drm_intel_bo_gem *) bo,
515 madv);
516 }
518 /* drop the oldest entries that have been purged by the kernel */
519 static void
520 drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem,
521 struct drm_intel_gem_bo_bucket *bucket)
522 {
523 while (!DRMLISTEMPTY(&bucket->head)) {
524 drm_intel_bo_gem *bo_gem;
526 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
527 bucket->head.next, head);
528 if (drm_intel_gem_bo_madvise_internal
529 (bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
530 break;
532 DRMLISTDEL(&bo_gem->head);
533 drm_intel_gem_bo_free(&bo_gem->bo);
534 }
535 }
537 static drm_intel_bo *
538 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr,
539 const char *name,
540 unsigned long size,
541 unsigned long flags)
542 {
543 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
544 drm_intel_bo_gem *bo_gem;
545 unsigned int page_size = getpagesize();
546 int ret;
547 struct drm_intel_gem_bo_bucket *bucket;
548 int alloc_from_cache;
549 unsigned long bo_size;
550 int for_render = 0;
552 if (flags & BO_ALLOC_FOR_RENDER)
553 for_render = 1;
555 /* Round the allocated size up to a power of two number of pages. */
556 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size);
558 /* If we don't have caching at this size, don't actually round the
559 * allocation up.
560 */
561 if (bucket == NULL) {
562 bo_size = size;
563 if (bo_size < page_size)
564 bo_size = page_size;
565 } else {
566 bo_size = bucket->size;
567 }
569 pthread_mutex_lock(&bufmgr_gem->lock);
570 /* Get a buffer out of the cache if available */
571 retry:
572 alloc_from_cache = 0;
573 if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) {
574 if (for_render) {
575 /* Allocate new render-target BOs from the tail (MRU)
576 * of the list, as it will likely be hot in the GPU
577 * cache and in the aperture for us.
578 */
579 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
580 bucket->head.prev, head);
581 DRMLISTDEL(&bo_gem->head);
582 alloc_from_cache = 1;
583 } else {
584 /* For non-render-target BOs (where we're probably
585 * going to map it first thing in order to fill it
586 * with data), check if the last BO in the cache is
587 * unbusy, and only reuse in that case. Otherwise,
588 * allocating a new buffer is probably faster than
589 * waiting for the GPU to finish.
590 */
591 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
592 bucket->head.next, head);
593 if (!drm_intel_gem_bo_busy(&bo_gem->bo)) {
594 alloc_from_cache = 1;
595 DRMLISTDEL(&bo_gem->head);
596 }
597 }
599 if (alloc_from_cache) {
600 if (!drm_intel_gem_bo_madvise_internal
601 (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) {
602 drm_intel_gem_bo_free(&bo_gem->bo);
603 drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem,
604 bucket);
605 goto retry;
606 }
607 }
608 }
609 pthread_mutex_unlock(&bufmgr_gem->lock);
611 if (!alloc_from_cache) {
612 struct drm_i915_gem_create create;
614 bo_gem = calloc(1, sizeof(*bo_gem));
615 if (!bo_gem)
616 return NULL;
618 bo_gem->bo.size = bo_size;
619 memset(&create, 0, sizeof(create));
620 create.size = bo_size;
622 do {
623 ret = ioctl(bufmgr_gem->fd,
624 DRM_IOCTL_I915_GEM_CREATE,
625 &create);
626 } while (ret == -1 && errno == EINTR);
627 bo_gem->gem_handle = create.handle;
628 bo_gem->bo.handle = bo_gem->gem_handle;
629 if (ret != 0) {
630 free(bo_gem);
631 return NULL;
632 }
633 bo_gem->bo.bufmgr = bufmgr;
634 }
636 bo_gem->name = name;
637 atomic_set(&bo_gem->refcount, 1);
638 bo_gem->validate_index = -1;
639 bo_gem->reloc_tree_fences = 0;
640 bo_gem->used_as_reloc_target = 0;
641 bo_gem->has_error = 0;
642 bo_gem->tiling_mode = I915_TILING_NONE;
643 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
644 bo_gem->reusable = 1;
646 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
648 DBG("bo_create: buf %d (%s) %ldb\n",
649 bo_gem->gem_handle, bo_gem->name, size);
651 return &bo_gem->bo;
652 }
654 static drm_intel_bo *
655 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
656 const char *name,
657 unsigned long size,
658 unsigned int alignment)
659 {
660 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size,
661 BO_ALLOC_FOR_RENDER);
662 }
664 static drm_intel_bo *
665 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr,
666 const char *name,
667 unsigned long size,
668 unsigned int alignment)
669 {
670 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0);
671 }
673 static drm_intel_bo *
674 drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
675 int x, int y, int cpp, uint32_t *tiling_mode,
676 unsigned long *pitch, unsigned long flags)
677 {
678 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
679 drm_intel_bo *bo;
680 unsigned long size, stride, aligned_y = y;
681 int ret;
683 /* If we're tiled, our allocations are in 8 or 32-row blocks,
684 * so failure to align our height means that we won't allocate
685 * enough pages.
686 *
687 * If we're untiled, we still have to align to 2 rows high
688 * because the data port accesses 2x2 blocks even if the
689 * bottom row isn't to be rendered, so failure to align means
690 * we could walk off the end of the GTT and fault. This is
691 * documented on 965, and may be the case on older chipsets
692 * too so we try to be careful.
693 */
694 if (*tiling_mode == I915_TILING_NONE)
695 aligned_y = ALIGN(y, 2);
696 else if (*tiling_mode == I915_TILING_X)
697 aligned_y = ALIGN(y, 8);
698 else if (*tiling_mode == I915_TILING_Y)
699 aligned_y = ALIGN(y, 32);
701 stride = x * cpp;
702 stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, *tiling_mode);
703 size = stride * aligned_y;
704 size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
706 bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags);
707 if (!bo)
708 return NULL;
710 ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride);
711 if (ret != 0) {
712 drm_intel_gem_bo_unreference(bo);
713 return NULL;
714 }
716 *pitch = stride;
718 return bo;
719 }
721 /**
722 * Returns a drm_intel_bo wrapping the given buffer object handle.
723 *
724 * This can be used when one application needs to pass a buffer object
725 * to another.
726 */
727 drm_intel_bo *
728 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
729 const char *name,
730 unsigned int handle)
731 {
732 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
733 drm_intel_bo_gem *bo_gem;
734 int ret;
735 struct drm_gem_open open_arg;
736 struct drm_i915_gem_get_tiling get_tiling;
738 bo_gem = calloc(1, sizeof(*bo_gem));
739 if (!bo_gem)
740 return NULL;
742 memset(&open_arg, 0, sizeof(open_arg));
743 open_arg.name = handle;
744 do {
745 ret = ioctl(bufmgr_gem->fd,
746 DRM_IOCTL_GEM_OPEN,
747 &open_arg);
748 } while (ret == -1 && errno == EINTR);
749 if (ret != 0) {
750 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
751 name, handle, strerror(errno));
752 free(bo_gem);
753 return NULL;
754 }
755 bo_gem->bo.size = open_arg.size;
756 bo_gem->bo.offset = 0;
757 bo_gem->bo.virtual = NULL;
758 bo_gem->bo.bufmgr = bufmgr;
759 bo_gem->name = name;
760 atomic_set(&bo_gem->refcount, 1);
761 bo_gem->validate_index = -1;
762 bo_gem->gem_handle = open_arg.handle;
763 bo_gem->global_name = handle;
764 bo_gem->reusable = 0;
766 memset(&get_tiling, 0, sizeof(get_tiling));
767 get_tiling.handle = bo_gem->gem_handle;
768 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
769 if (ret != 0) {
770 drm_intel_gem_bo_unreference(&bo_gem->bo);
771 return NULL;
772 }
773 bo_gem->tiling_mode = get_tiling.tiling_mode;
774 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
775 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
777 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
779 return &bo_gem->bo;
780 }
782 static void
783 drm_intel_gem_bo_free(drm_intel_bo *bo)
784 {
785 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
786 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
787 struct drm_gem_close close;
788 int ret;
790 if (bo_gem->mem_virtual)
791 munmap(bo_gem->mem_virtual, bo_gem->bo.size);
792 if (bo_gem->gtt_virtual)
793 munmap(bo_gem->gtt_virtual, bo_gem->bo.size);
795 /* Close this object */
796 memset(&close, 0, sizeof(close));
797 close.handle = bo_gem->gem_handle;
798 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
799 if (ret != 0) {
800 fprintf(stderr,
801 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
802 bo_gem->gem_handle, bo_gem->name, strerror(errno));
803 }
804 free(bo);
805 }
807 /** Frees all cached buffers significantly older than @time. */
808 static void
809 drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time)
810 {
811 int i;
813 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
814 struct drm_intel_gem_bo_bucket *bucket =
815 &bufmgr_gem->cache_bucket[i];
817 while (!DRMLISTEMPTY(&bucket->head)) {
818 drm_intel_bo_gem *bo_gem;
820 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
821 bucket->head.next, head);
822 if (time - bo_gem->free_time <= 1)
823 break;
825 DRMLISTDEL(&bo_gem->head);
827 drm_intel_gem_bo_free(&bo_gem->bo);
828 }
829 }
830 }
832 static void
833 drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
834 {
835 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
836 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
837 struct drm_intel_gem_bo_bucket *bucket;
838 uint32_t tiling_mode;
839 int i;
841 /* Unreference all the target buffers */
842 for (i = 0; i < bo_gem->reloc_count; i++) {
843 drm_intel_gem_bo_unreference_locked_timed(bo_gem->
844 reloc_target_info[i].bo,
845 time);
846 }
847 bo_gem->reloc_count = 0;
848 bo_gem->used_as_reloc_target = 0;
850 DBG("bo_unreference final: %d (%s)\n",
851 bo_gem->gem_handle, bo_gem->name);
853 /* release memory associated with this object */
854 if (bo_gem->reloc_target_info) {
855 free(bo_gem->reloc_target_info);
856 bo_gem->reloc_target_info = NULL;
857 }
858 if (bo_gem->relocs) {
859 free(bo_gem->relocs);
860 bo_gem->relocs = NULL;
861 }
863 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
864 /* Put the buffer into our internal cache for reuse if we can. */
865 tiling_mode = I915_TILING_NONE;
866 if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL &&
867 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 &&
868 drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem,
869 I915_MADV_DONTNEED)) {
870 bo_gem->free_time = time;
872 bo_gem->name = NULL;
873 bo_gem->validate_index = -1;
875 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
877 drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time);
878 } else {
879 drm_intel_gem_bo_free(bo);
880 }
881 }
883 static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo,
884 time_t time)
885 {
886 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
888 assert(atomic_read(&bo_gem->refcount) > 0);
889 if (atomic_dec_and_test(&bo_gem->refcount))
890 drm_intel_gem_bo_unreference_final(bo, time);
891 }
893 static void drm_intel_gem_bo_unreference(drm_intel_bo *bo)
894 {
895 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
897 assert(atomic_read(&bo_gem->refcount) > 0);
898 if (atomic_dec_and_test(&bo_gem->refcount)) {
899 drm_intel_bufmgr_gem *bufmgr_gem =
900 (drm_intel_bufmgr_gem *) bo->bufmgr;
901 struct timespec time;
903 clock_gettime(CLOCK_MONOTONIC, &time);
905 pthread_mutex_lock(&bufmgr_gem->lock);
906 drm_intel_gem_bo_unreference_final(bo, time.tv_sec);
907 pthread_mutex_unlock(&bufmgr_gem->lock);
908 }
909 }
911 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
912 {
913 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
914 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
915 struct drm_i915_gem_set_domain set_domain;
916 int ret;
918 pthread_mutex_lock(&bufmgr_gem->lock);
920 /* Allow recursive mapping. Mesa may recursively map buffers with
921 * nested display loops.
922 */
923 if (!bo_gem->mem_virtual) {
924 struct drm_i915_gem_mmap mmap_arg;
926 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
928 memset(&mmap_arg, 0, sizeof(mmap_arg));
929 mmap_arg.handle = bo_gem->gem_handle;
930 mmap_arg.offset = 0;
931 mmap_arg.size = bo->size;
932 do {
933 ret = ioctl(bufmgr_gem->fd,
934 DRM_IOCTL_I915_GEM_MMAP,
935 &mmap_arg);
936 } while (ret == -1 && errno == EINTR);
937 if (ret != 0) {
938 ret = -errno;
939 fprintf(stderr,
940 "%s:%d: Error mapping buffer %d (%s): %s .\n",
941 __FILE__, __LINE__, bo_gem->gem_handle,
942 bo_gem->name, strerror(errno));
943 pthread_mutex_unlock(&bufmgr_gem->lock);
944 return ret;
945 }
946 bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr;
947 }
948 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
949 bo_gem->mem_virtual);
950 bo->virtual = bo_gem->mem_virtual;
952 set_domain.handle = bo_gem->gem_handle;
953 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
954 if (write_enable)
955 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
956 else
957 set_domain.write_domain = 0;
958 do {
959 ret = ioctl(bufmgr_gem->fd,
960 DRM_IOCTL_I915_GEM_SET_DOMAIN,
961 &set_domain);
962 } while (ret == -1 && errno == EINTR);
963 if (ret != 0) {
964 ret = -errno;
965 fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n",
966 __FILE__, __LINE__, bo_gem->gem_handle,
967 strerror(errno));
968 pthread_mutex_unlock(&bufmgr_gem->lock);
969 return ret;
970 }
972 pthread_mutex_unlock(&bufmgr_gem->lock);
974 return 0;
975 }
977 int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
978 {
979 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
980 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
981 struct drm_i915_gem_set_domain set_domain;
982 int ret;
984 pthread_mutex_lock(&bufmgr_gem->lock);
986 /* Get a mapping of the buffer if we haven't before. */
987 if (bo_gem->gtt_virtual == NULL) {
988 struct drm_i915_gem_mmap_gtt mmap_arg;
990 DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle,
991 bo_gem->name);
993 memset(&mmap_arg, 0, sizeof(mmap_arg));
994 mmap_arg.handle = bo_gem->gem_handle;
996 /* Get the fake offset back... */
997 do {
998 ret = ioctl(bufmgr_gem->fd,
999 DRM_IOCTL_I915_GEM_MMAP_GTT,
1000 &mmap_arg);
1001 } while (ret == -1 && errno == EINTR);
1002 if (ret != 0) {
1003 ret = -errno;
1004 fprintf(stderr,
1005 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
1006 __FILE__, __LINE__,
1007 bo_gem->gem_handle, bo_gem->name,
1008 strerror(errno));
1009 pthread_mutex_unlock(&bufmgr_gem->lock);
1010 return ret;
1011 }
1013 /* and mmap it */
1014 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
1015 MAP_SHARED, bufmgr_gem->fd,
1016 mmap_arg.offset);
1017 if (bo_gem->gtt_virtual == MAP_FAILED) {
1018 bo_gem->gtt_virtual = NULL;
1019 ret = -errno;
1020 fprintf(stderr,
1021 "%s:%d: Error mapping buffer %d (%s): %s .\n",
1022 __FILE__, __LINE__,
1023 bo_gem->gem_handle, bo_gem->name,
1024 strerror(errno));
1025 pthread_mutex_unlock(&bufmgr_gem->lock);
1026 return ret;
1027 }
1028 }
1030 bo->virtual = bo_gem->gtt_virtual;
1032 DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
1033 bo_gem->gtt_virtual);
1035 /* Now move it to the GTT domain so that the CPU caches are flushed */
1036 set_domain.handle = bo_gem->gem_handle;
1037 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1038 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1039 do {
1040 ret = ioctl(bufmgr_gem->fd,
1041 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1042 &set_domain);
1043 } while (ret == -1 && errno == EINTR);
1045 if (ret != 0) {
1046 ret = -errno;
1047 fprintf(stderr, "%s:%d: Error setting domain %d: %s\n",
1048 __FILE__, __LINE__, bo_gem->gem_handle,
1049 strerror(errno));
1050 }
1052 pthread_mutex_unlock(&bufmgr_gem->lock);
1054 return ret;
1055 }
1057 int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
1058 {
1059 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1060 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1061 int ret = 0;
1063 if (bo == NULL)
1064 return 0;
1066 assert(bo_gem->gtt_virtual != NULL);
1068 pthread_mutex_lock(&bufmgr_gem->lock);
1069 bo->virtual = NULL;
1070 pthread_mutex_unlock(&bufmgr_gem->lock);
1072 return ret;
1073 }
1075 static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
1076 {
1077 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1078 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1079 struct drm_i915_gem_sw_finish sw_finish;
1080 int ret;
1082 if (bo == NULL)
1083 return 0;
1085 assert(bo_gem->mem_virtual != NULL);
1087 pthread_mutex_lock(&bufmgr_gem->lock);
1089 /* Cause a flush to happen if the buffer's pinned for scanout, so the
1090 * results show up in a timely manner.
1091 */
1092 sw_finish.handle = bo_gem->gem_handle;
1093 do {
1094 ret = ioctl(bufmgr_gem->fd,
1095 DRM_IOCTL_I915_GEM_SW_FINISH,
1096 &sw_finish);
1097 } while (ret == -1 && errno == EINTR);
1099 bo->virtual = NULL;
1100 pthread_mutex_unlock(&bufmgr_gem->lock);
1101 return 0;
1102 }
1104 static int
1105 drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset,
1106 unsigned long size, const void *data)
1107 {
1108 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1109 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1110 struct drm_i915_gem_pwrite pwrite;
1111 int ret;
1113 memset(&pwrite, 0, sizeof(pwrite));
1114 pwrite.handle = bo_gem->gem_handle;
1115 pwrite.offset = offset;
1116 pwrite.size = size;
1117 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
1118 do {
1119 ret = ioctl(bufmgr_gem->fd,
1120 DRM_IOCTL_I915_GEM_PWRITE,
1121 &pwrite);
1122 } while (ret == -1 && errno == EINTR);
1123 if (ret != 0) {
1124 fprintf(stderr,
1125 "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
1126 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1127 (int)size, strerror(errno));
1128 }
1129 return 0;
1130 }
1132 static int
1133 drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id)
1134 {
1135 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1136 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
1137 int ret;
1139 get_pipe_from_crtc_id.crtc_id = crtc_id;
1140 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
1141 &get_pipe_from_crtc_id);
1142 if (ret != 0) {
1143 /* We return -1 here to signal that we don't
1144 * know which pipe is associated with this crtc.
1145 * This lets the caller know that this information
1146 * isn't available; using the wrong pipe for
1147 * vblank waiting can cause the chipset to lock up
1148 */
1149 return -1;
1150 }
1152 return get_pipe_from_crtc_id.pipe;
1153 }
1155 static int
1156 drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
1157 unsigned long size, void *data)
1158 {
1159 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1160 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1161 struct drm_i915_gem_pread pread;
1162 int ret;
1164 memset(&pread, 0, sizeof(pread));
1165 pread.handle = bo_gem->gem_handle;
1166 pread.offset = offset;
1167 pread.size = size;
1168 pread.data_ptr = (uint64_t) (uintptr_t) data;
1169 do {
1170 ret = ioctl(bufmgr_gem->fd,
1171 DRM_IOCTL_I915_GEM_PREAD,
1172 &pread);
1173 } while (ret == -1 && errno == EINTR);
1174 if (ret != 0) {
1175 ret = -errno;
1176 fprintf(stderr,
1177 "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
1178 __FILE__, __LINE__, bo_gem->gem_handle, (int)offset,
1179 (int)size, strerror(errno));
1180 }
1181 return ret;
1182 }
1184 /** Waits for all GPU rendering to the object to have completed. */
1185 static void
1186 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
1187 {
1188 drm_intel_gem_bo_start_gtt_access(bo, 0);
1189 }
1191 /**
1192 * Sets the object to the GTT read and possibly write domain, used by the X
1193 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
1194 *
1195 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
1196 * can do tiled pixmaps this way.
1197 */
1198 void
1199 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
1200 {
1201 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1202 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1203 struct drm_i915_gem_set_domain set_domain;
1204 int ret;
1206 set_domain.handle = bo_gem->gem_handle;
1207 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1208 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
1209 do {
1210 ret = ioctl(bufmgr_gem->fd,
1211 DRM_IOCTL_I915_GEM_SET_DOMAIN,
1212 &set_domain);
1213 } while (ret == -1 && errno == EINTR);
1214 if (ret != 0) {
1215 fprintf(stderr,
1216 "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1217 __FILE__, __LINE__, bo_gem->gem_handle,
1218 set_domain.read_domains, set_domain.write_domain,
1219 strerror(errno));
1220 }
1221 }
1223 static void
1224 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
1225 {
1226 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1227 int i;
1229 free(bufmgr_gem->exec2_objects);
1230 free(bufmgr_gem->exec_objects);
1231 free(bufmgr_gem->exec_bos);
1233 pthread_mutex_destroy(&bufmgr_gem->lock);
1235 /* Free any cached buffer objects we were going to reuse */
1236 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1237 struct drm_intel_gem_bo_bucket *bucket =
1238 &bufmgr_gem->cache_bucket[i];
1239 drm_intel_bo_gem *bo_gem;
1241 while (!DRMLISTEMPTY(&bucket->head)) {
1242 bo_gem = DRMLISTENTRY(drm_intel_bo_gem,
1243 bucket->head.next, head);
1244 DRMLISTDEL(&bo_gem->head);
1246 drm_intel_gem_bo_free(&bo_gem->bo);
1247 }
1248 }
1250 free(bufmgr);
1251 }
1253 /**
1254 * Adds the target buffer to the validation list and adds the relocation
1255 * to the reloc_buffer's relocation list.
1256 *
1257 * The relocation entry at the given offset must already contain the
1258 * precomputed relocation value, because the kernel will optimize out
1259 * the relocation entry write when the buffer hasn't moved from the
1260 * last known offset in target_bo.
1261 */
1262 static int
1263 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1264 drm_intel_bo *target_bo, uint32_t target_offset,
1265 uint32_t read_domains, uint32_t write_domain,
1266 int need_fence)
1267 {
1268 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1269 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1270 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1272 if (bo_gem->has_error)
1273 return -ENOMEM;
1275 if (target_bo_gem->has_error) {
1276 bo_gem->has_error = 1;
1277 return -ENOMEM;
1278 }
1280 if (target_bo_gem->tiling_mode == I915_TILING_NONE)
1281 need_fence = 0;
1283 /* We never use HW fences for rendering on 965+ */
1284 if (bufmgr_gem->gen >= 4)
1285 need_fence = 0;
1287 /* Create a new relocation list if needed */
1288 if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo))
1289 return -ENOMEM;
1291 /* Check overflow */
1292 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
1294 /* Check args */
1295 assert(offset <= bo->size - 4);
1296 assert((write_domain & (write_domain - 1)) == 0);
1298 /* Make sure that we're not adding a reloc to something whose size has
1299 * already been accounted for.
1300 */
1301 assert(!bo_gem->used_as_reloc_target);
1302 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
1303 /* An object needing a fence is a tiled buffer, so it won't have
1304 * relocs to other buffers.
1305 */
1306 if (need_fence)
1307 target_bo_gem->reloc_tree_fences = 1;
1308 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
1310 /* Flag the target to disallow further relocations in it. */
1311 target_bo_gem->used_as_reloc_target = 1;
1313 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
1314 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
1315 bo_gem->relocs[bo_gem->reloc_count].target_handle =
1316 target_bo_gem->gem_handle;
1317 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
1318 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
1319 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
1321 bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
1322 drm_intel_gem_bo_reference(target_bo);
1323 if (need_fence)
1324 bo_gem->reloc_target_info[bo_gem->reloc_count].flags =
1325 DRM_INTEL_RELOC_FENCE;
1326 else
1327 bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0;
1329 bo_gem->reloc_count++;
1331 return 0;
1332 }
1334 static int
1335 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
1336 drm_intel_bo *target_bo, uint32_t target_offset,
1337 uint32_t read_domains, uint32_t write_domain)
1338 {
1339 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1341 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1342 read_domains, write_domain,
1343 !bufmgr_gem->fenced_relocs);
1344 }
1346 static int
1347 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
1348 drm_intel_bo *target_bo,
1349 uint32_t target_offset,
1350 uint32_t read_domains, uint32_t write_domain)
1351 {
1352 return do_bo_emit_reloc(bo, offset, target_bo, target_offset,
1353 read_domains, write_domain, 1);
1354 }
1356 /**
1357 * Walk the tree of relocations rooted at BO and accumulate the list of
1358 * validations to be performed and update the relocation buffers with
1359 * index values into the validation list.
1360 */
1361 static void
1362 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
1363 {
1364 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1365 int i;
1367 if (bo_gem->relocs == NULL)
1368 return;
1370 for (i = 0; i < bo_gem->reloc_count; i++) {
1371 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1373 /* Continue walking the tree depth-first. */
1374 drm_intel_gem_bo_process_reloc(target_bo);
1376 /* Add the target to the validate list */
1377 drm_intel_add_validate_buffer(target_bo);
1378 }
1379 }
1381 static void
1382 drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo)
1383 {
1384 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1385 int i;
1387 if (bo_gem->relocs == NULL)
1388 return;
1390 for (i = 0; i < bo_gem->reloc_count; i++) {
1391 drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo;
1392 int need_fence;
1394 /* Continue walking the tree depth-first. */
1395 drm_intel_gem_bo_process_reloc2(target_bo);
1397 need_fence = (bo_gem->reloc_target_info[i].flags &
1398 DRM_INTEL_RELOC_FENCE);
1400 /* Add the target to the validate list */
1401 drm_intel_add_validate_buffer2(target_bo, need_fence);
1402 }
1403 }
1406 static void
1407 drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem)
1408 {
1409 int i;
1411 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1412 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1413 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1415 /* Update the buffer offset */
1416 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1417 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1418 bo_gem->gem_handle, bo_gem->name, bo->offset,
1419 (unsigned long long)bufmgr_gem->exec_objects[i].
1420 offset);
1421 bo->offset = bufmgr_gem->exec_objects[i].offset;
1422 }
1423 }
1424 }
1426 static void
1427 drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem)
1428 {
1429 int i;
1431 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1432 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1433 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1435 /* Update the buffer offset */
1436 if (bufmgr_gem->exec2_objects[i].offset != bo->offset) {
1437 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1438 bo_gem->gem_handle, bo_gem->name, bo->offset,
1439 (unsigned long long)bufmgr_gem->exec2_objects[i].offset);
1440 bo->offset = bufmgr_gem->exec2_objects[i].offset;
1441 }
1442 }
1443 }
1445 static int
1446 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1447 drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
1448 {
1449 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1450 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1451 struct drm_i915_gem_execbuffer execbuf;
1452 int ret, i;
1454 if (bo_gem->has_error)
1455 return -ENOMEM;
1457 pthread_mutex_lock(&bufmgr_gem->lock);
1458 /* Update indices and set up the validate list. */
1459 drm_intel_gem_bo_process_reloc(bo);
1461 /* Add the batch buffer to the validation list. There are no
1462 * relocations pointing to it.
1463 */
1464 drm_intel_add_validate_buffer(bo);
1466 execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects;
1467 execbuf.buffer_count = bufmgr_gem->exec_count;
1468 execbuf.batch_start_offset = 0;
1469 execbuf.batch_len = used;
1470 execbuf.cliprects_ptr = (uintptr_t) cliprects;
1471 execbuf.num_cliprects = num_cliprects;
1472 execbuf.DR1 = 0;
1473 execbuf.DR4 = DR4;
1475 do {
1476 ret = ioctl(bufmgr_gem->fd,
1477 DRM_IOCTL_I915_GEM_EXECBUFFER,
1478 &execbuf);
1479 } while (ret != 0 && errno == EINTR);
1481 if (ret != 0) {
1482 ret = -errno;
1483 if (errno == ENOSPC) {
1484 fprintf(stderr,
1485 "Execbuffer fails to pin. "
1486 "Estimate: %u. Actual: %u. Available: %u\n",
1487 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1488 bufmgr_gem->
1489 exec_count),
1490 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1491 bufmgr_gem->
1492 exec_count),
1493 (unsigned int)bufmgr_gem->gtt_size);
1494 }
1495 }
1496 drm_intel_update_buffer_offsets(bufmgr_gem);
1498 if (bufmgr_gem->bufmgr.debug)
1499 drm_intel_gem_dump_validation_list(bufmgr_gem);
1501 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1502 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1503 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1505 /* Disconnect the buffer from the validate list */
1506 bo_gem->validate_index = -1;
1507 bufmgr_gem->exec_bos[i] = NULL;
1508 }
1509 bufmgr_gem->exec_count = 0;
1510 pthread_mutex_unlock(&bufmgr_gem->lock);
1512 return ret;
1513 }
1515 static int
1516 drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used,
1517 drm_clip_rect_t *cliprects, int num_cliprects,
1518 int DR4)
1519 {
1520 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1521 struct drm_i915_gem_execbuffer2 execbuf;
1522 int ret, i;
1524 pthread_mutex_lock(&bufmgr_gem->lock);
1525 /* Update indices and set up the validate list. */
1526 drm_intel_gem_bo_process_reloc2(bo);
1528 /* Add the batch buffer to the validation list. There are no relocations
1529 * pointing to it.
1530 */
1531 drm_intel_add_validate_buffer2(bo, 0);
1533 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects;
1534 execbuf.buffer_count = bufmgr_gem->exec_count;
1535 execbuf.batch_start_offset = 0;
1536 execbuf.batch_len = used;
1537 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1538 execbuf.num_cliprects = num_cliprects;
1539 execbuf.DR1 = 0;
1540 execbuf.DR4 = DR4;
1541 execbuf.flags = 0;
1542 execbuf.rsvd1 = 0;
1543 execbuf.rsvd2 = 0;
1545 do {
1546 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2,
1547 &execbuf);
1548 } while (ret != 0 && errno == EAGAIN);
1550 if (ret != 0 && errno == ENOMEM) {
1551 fprintf(stderr,
1552 "Execbuffer fails to pin. "
1553 "Estimate: %u. Actual: %u. Available: %u\n",
1554 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1555 bufmgr_gem->exec_count),
1556 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1557 bufmgr_gem->exec_count),
1558 (unsigned int) bufmgr_gem->gtt_size);
1559 }
1560 drm_intel_update_buffer_offsets2(bufmgr_gem);
1562 if (bufmgr_gem->bufmgr.debug)
1563 drm_intel_gem_dump_validation_list(bufmgr_gem);
1565 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1566 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1567 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1569 /* Disconnect the buffer from the validate list */
1570 bo_gem->validate_index = -1;
1571 bufmgr_gem->exec_bos[i] = NULL;
1572 }
1573 bufmgr_gem->exec_count = 0;
1574 pthread_mutex_unlock(&bufmgr_gem->lock);
1576 return 0;
1577 }
1579 static int
1580 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1581 {
1582 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1583 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1584 struct drm_i915_gem_pin pin;
1585 int ret;
1587 memset(&pin, 0, sizeof(pin));
1588 pin.handle = bo_gem->gem_handle;
1589 pin.alignment = alignment;
1591 do {
1592 ret = ioctl(bufmgr_gem->fd,
1593 DRM_IOCTL_I915_GEM_PIN,
1594 &pin);
1595 } while (ret == -1 && errno == EINTR);
1597 if (ret != 0)
1598 return -errno;
1600 bo->offset = pin.offset;
1601 return 0;
1602 }
1604 static int
1605 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1606 {
1607 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1608 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1609 struct drm_i915_gem_unpin unpin;
1610 int ret;
1612 memset(&unpin, 0, sizeof(unpin));
1613 unpin.handle = bo_gem->gem_handle;
1615 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1616 if (ret != 0)
1617 return -errno;
1619 return 0;
1620 }
1622 static int
1623 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1624 uint32_t stride)
1625 {
1626 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1627 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1628 struct drm_i915_gem_set_tiling set_tiling;
1629 int ret;
1631 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1632 return 0;
1634 memset(&set_tiling, 0, sizeof(set_tiling));
1635 set_tiling.handle = bo_gem->gem_handle;
1637 do {
1638 set_tiling.tiling_mode = *tiling_mode;
1639 set_tiling.stride = stride;
1641 ret = ioctl(bufmgr_gem->fd,
1642 DRM_IOCTL_I915_GEM_SET_TILING,
1643 &set_tiling);
1644 } while (ret == -1 && errno == EINTR);
1645 bo_gem->tiling_mode = set_tiling.tiling_mode;
1646 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1648 drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem);
1650 *tiling_mode = bo_gem->tiling_mode;
1651 return ret == 0 ? 0 : -errno;
1652 }
1654 static int
1655 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
1656 uint32_t * swizzle_mode)
1657 {
1658 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1660 *tiling_mode = bo_gem->tiling_mode;
1661 *swizzle_mode = bo_gem->swizzle_mode;
1662 return 0;
1663 }
1665 static int
1666 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name)
1667 {
1668 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
1669 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1670 struct drm_gem_flink flink;
1671 int ret;
1673 if (!bo_gem->global_name) {
1674 memset(&flink, 0, sizeof(flink));
1675 flink.handle = bo_gem->gem_handle;
1677 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1678 if (ret != 0)
1679 return -errno;
1680 bo_gem->global_name = flink.name;
1681 bo_gem->reusable = 0;
1682 }
1684 *name = bo_gem->global_name;
1685 return 0;
1686 }
1688 /**
1689 * Enables unlimited caching of buffer objects for reuse.
1690 *
1691 * This is potentially very memory expensive, as the cache at each bucket
1692 * size is only bounded by how many buffers of that size we've managed to have
1693 * in flight at once.
1694 */
1695 void
1696 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1697 {
1698 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
1700 bufmgr_gem->bo_reuse = 1;
1701 }
1703 /**
1704 * Enable use of fenced reloc type.
1705 *
1706 * New code should enable this to avoid unnecessary fence register
1707 * allocation. If this option is not enabled, all relocs will have fence
1708 * register allocated.
1709 */
1710 void
1711 drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
1712 {
1713 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1715 bufmgr_gem->fenced_relocs = 1;
1716 }
1718 /**
1719 * Return the additional aperture space required by the tree of buffer objects
1720 * rooted at bo.
1721 */
1722 static int
1723 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1724 {
1725 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1726 int i;
1727 int total = 0;
1729 if (bo == NULL || bo_gem->included_in_check_aperture)
1730 return 0;
1732 total += bo->size;
1733 bo_gem->included_in_check_aperture = 1;
1735 for (i = 0; i < bo_gem->reloc_count; i++)
1736 total +=
1737 drm_intel_gem_bo_get_aperture_space(bo_gem->
1738 reloc_target_info[i].bo);
1740 return total;
1741 }
1743 /**
1744 * Count the number of buffers in this list that need a fence reg
1745 *
1746 * If the count is greater than the number of available regs, we'll have
1747 * to ask the caller to resubmit a batch with fewer tiled buffers.
1748 *
1749 * This function over-counts if the same buffer is used multiple times.
1750 */
1751 static unsigned int
1752 drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count)
1753 {
1754 int i;
1755 unsigned int total = 0;
1757 for (i = 0; i < count; i++) {
1758 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1760 if (bo_gem == NULL)
1761 continue;
1763 total += bo_gem->reloc_tree_fences;
1764 }
1765 return total;
1766 }
1768 /**
1769 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1770 * for the next drm_intel_bufmgr_check_aperture_space() call.
1771 */
1772 static void
1773 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1774 {
1775 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1776 int i;
1778 if (bo == NULL || !bo_gem->included_in_check_aperture)
1779 return;
1781 bo_gem->included_in_check_aperture = 0;
1783 for (i = 0; i < bo_gem->reloc_count; i++)
1784 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->
1785 reloc_target_info[i].bo);
1786 }
1788 /**
1789 * Return a conservative estimate for the amount of aperture required
1790 * for a collection of buffers. This may double-count some buffers.
1791 */
1792 static unsigned int
1793 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1794 {
1795 int i;
1796 unsigned int total = 0;
1798 for (i = 0; i < count; i++) {
1799 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i];
1800 if (bo_gem != NULL)
1801 total += bo_gem->reloc_tree_size;
1802 }
1803 return total;
1804 }
1806 /**
1807 * Return the amount of aperture needed for a collection of buffers.
1808 * This avoids double counting any buffers, at the cost of looking
1809 * at every buffer in the set.
1810 */
1811 static unsigned int
1812 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1813 {
1814 int i;
1815 unsigned int total = 0;
1817 for (i = 0; i < count; i++) {
1818 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1819 /* For the first buffer object in the array, we get an
1820 * accurate count back for its reloc_tree size (since nothing
1821 * had been flagged as being counted yet). We can save that
1822 * value out as a more conservative reloc_tree_size that
1823 * avoids double-counting target buffers. Since the first
1824 * buffer happens to usually be the batch buffer in our
1825 * callers, this can pull us back from doing the tree
1826 * walk on every new batch emit.
1827 */
1828 if (i == 0) {
1829 drm_intel_bo_gem *bo_gem =
1830 (drm_intel_bo_gem *) bo_array[i];
1831 bo_gem->reloc_tree_size = total;
1832 }
1833 }
1835 for (i = 0; i < count; i++)
1836 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1837 return total;
1838 }
1840 /**
1841 * Return -1 if the batchbuffer should be flushed before attempting to
1842 * emit rendering referencing the buffers pointed to by bo_array.
1843 *
1844 * This is required because if we try to emit a batchbuffer with relocations
1845 * to a tree of buffers that won't simultaneously fit in the aperture,
1846 * the rendering will return an error at a point where the software is not
1847 * prepared to recover from it.
1848 *
1849 * However, we also want to emit the batchbuffer significantly before we reach
1850 * the limit, as a series of batchbuffers each of which references buffers
1851 * covering almost all of the aperture means that at each emit we end up
1852 * waiting to evict a buffer from the last rendering, and we get synchronous
1853 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1854 * get better parallelism.
1855 */
1856 static int
1857 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1858 {
1859 drm_intel_bufmgr_gem *bufmgr_gem =
1860 (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr;
1861 unsigned int total = 0;
1862 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1863 int total_fences;
1865 /* Check for fence reg constraints if necessary */
1866 if (bufmgr_gem->available_fences) {
1867 total_fences = drm_intel_gem_total_fences(bo_array, count);
1868 if (total_fences > bufmgr_gem->available_fences)
1869 return -ENOSPC;
1870 }
1872 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1874 if (total > threshold)
1875 total = drm_intel_gem_compute_batch_space(bo_array, count);
1877 if (total > threshold) {
1878 DBG("check_space: overflowed available aperture, "
1879 "%dkb vs %dkb\n",
1880 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1881 return -ENOSPC;
1882 } else {
1883 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024,
1884 (int)bufmgr_gem->gtt_size / 1024);
1885 return 0;
1886 }
1887 }
1889 /*
1890 * Disable buffer reuse for objects which are shared with the kernel
1891 * as scanout buffers
1892 */
1893 static int
1894 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1895 {
1896 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1898 bo_gem->reusable = 0;
1899 return 0;
1900 }
1902 static int
1903 _drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1904 {
1905 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
1906 int i;
1908 for (i = 0; i < bo_gem->reloc_count; i++) {
1909 if (bo_gem->reloc_target_info[i].bo == target_bo)
1910 return 1;
1911 if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo,
1912 target_bo))
1913 return 1;
1914 }
1916 return 0;
1917 }
1919 /** Return true if target_bo is referenced by bo's relocation tree. */
1920 static int
1921 drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
1922 {
1923 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo;
1925 if (bo == NULL || target_bo == NULL)
1926 return 0;
1927 if (target_bo_gem->used_as_reloc_target)
1928 return _drm_intel_gem_bo_references(bo, target_bo);
1929 return 0;
1930 }
1932 /**
1933 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1934 * and manage map buffer objections.
1935 *
1936 * \param fd File descriptor of the opened DRM device.
1937 */
1938 drm_intel_bufmgr *
1939 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1940 {
1941 drm_intel_bufmgr_gem *bufmgr_gem;
1942 struct drm_i915_gem_get_aperture aperture;
1943 drm_i915_getparam_t gp;
1944 int ret, i;
1945 unsigned long size;
1946 int exec2 = 0;
1948 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1949 if (bufmgr_gem == NULL)
1950 return NULL;
1952 bufmgr_gem->fd = fd;
1954 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1955 free(bufmgr_gem);
1956 return NULL;
1957 }
1959 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1961 if (ret == 0)
1962 bufmgr_gem->gtt_size = aperture.aper_available_size;
1963 else {
1964 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1965 strerror(errno));
1966 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1967 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1968 "May lead to reduced performance or incorrect "
1969 "rendering.\n",
1970 (int)bufmgr_gem->gtt_size / 1024);
1971 }
1973 gp.param = I915_PARAM_CHIPSET_ID;
1974 gp.value = &bufmgr_gem->pci_device;
1975 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1976 if (ret) {
1977 fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno);
1978 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1979 }
1981 if (IS_GEN2(bufmgr_gem))
1982 bufmgr_gem->gen = 2;
1983 else if (IS_GEN3(bufmgr_gem))
1984 bufmgr_gem->gen = 3;
1985 else if (IS_GEN4(bufmgr_gem))
1986 bufmgr_gem->gen = 4;
1987 else
1988 bufmgr_gem->gen = 6;
1990 gp.param = I915_PARAM_HAS_EXECBUF2;
1991 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1992 if (!ret)
1993 exec2 = 1;
1995 if (bufmgr_gem->gen < 4) {
1996 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1997 gp.value = &bufmgr_gem->available_fences;
1998 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1999 if (ret) {
2000 fprintf(stderr, "get fences failed: %d [%d]\n", ret,
2001 errno);
2002 fprintf(stderr, "param: %d, val: %d\n", gp.param,
2003 *gp.value);
2004 bufmgr_gem->available_fences = 0;
2005 } else {
2006 /* XXX The kernel reports the total number of fences,
2007 * including any that may be pinned.
2008 *
2009 * We presume that there will be at least one pinned
2010 * fence for the scanout buffer, but there may be more
2011 * than one scanout and the user may be manually
2012 * pinning buffers. Let's move to execbuffer2 and
2013 * thereby forget the insanity of using fences...
2014 */
2015 bufmgr_gem->available_fences -= 2;
2016 if (bufmgr_gem->available_fences < 0)
2017 bufmgr_gem->available_fences = 0;
2018 }
2019 }
2021 /* Let's go with one relocation per every 2 dwords (but round down a bit
2022 * since a power of two will mean an extra page allocation for the reloc
2023 * buffer).
2024 *
2025 * Every 4 was too few for the blender benchmark.
2026 */
2027 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
2029 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
2030 bufmgr_gem->bufmgr.bo_alloc_for_render =
2031 drm_intel_gem_bo_alloc_for_render;
2032 bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled;
2033 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
2034 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
2035 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
2036 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
2037 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
2038 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
2039 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
2040 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
2041 bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence;
2042 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
2043 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
2044 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
2045 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
2046 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
2047 /* Use the new one if available */
2048 if (exec2)
2049 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2;
2050 else
2051 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
2052 bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy;
2053 bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise;
2054 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
2055 bufmgr_gem->bufmgr.debug = 0;
2056 bufmgr_gem->bufmgr.check_aperture_space =
2057 drm_intel_gem_check_aperture_space;
2058 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
2059 bufmgr_gem->bufmgr.get_pipe_from_crtc_id =
2060 drm_intel_gem_get_pipe_from_crtc_id;
2061 bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references;
2063 /* Initialize the linked lists for BO reuse cache. */
2064 for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) {
2065 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
2066 bufmgr_gem->cache_bucket[i].size = size;
2067 }
2069 return &bufmgr_gem->bufmgr;
2070 }