intel/intel_chipset.h

   1 /*
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #ifndef _INTEL_CHIPSET_H
  29 #define _INTEL_CHIPSET_H
  30
  31 #define PCI_CHIP_ILD_G                  0x0042
  32 #define PCI_CHIP_ILM_G                  0x0046
  33
  34 #define PCI_CHIP_SANDYBRIDGE_GT1        0x0102 /* desktop */
  35 #define PCI_CHIP_SANDYBRIDGE_GT2        0x0112
  36 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS   0x0122
  37 #define PCI_CHIP_SANDYBRIDGE_M_GT1      0x0106 /* mobile */
  38 #define PCI_CHIP_SANDYBRIDGE_M_GT2      0x0116
  39 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
  40 #define PCI_CHIP_SANDYBRIDGE_S          0x010A /* server */
  41
  42 #define PCI_CHIP_IVYBRIDGE_GT1          0x0152 /* desktop */
  43 #define PCI_CHIP_IVYBRIDGE_GT2          0x0162
  44 #define PCI_CHIP_IVYBRIDGE_M_GT1        0x0156 /* mobile */
  45 #define PCI_CHIP_IVYBRIDGE_M_GT2        0x0166
  46 #define PCI_CHIP_IVYBRIDGE_S            0x015a /* server */
  47
  48 #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
  49 #define PCI_CHIP_HASWELL_GT2            0x0412
  50 #define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
  51 #define PCI_CHIP_HASWELL_M_GT2          0x0416
  52 #define PCI_CHIP_HASWELL_M_ULT_GT2      0x0A16 /* Mobile ULT */
  53
  54 #define IS_830(dev) (dev == 0x3577)
  55 #define IS_845(dev) (dev == 0x2562)
  56 #define IS_85X(dev) (dev == 0x3582)
  57 #define IS_865(dev) (dev == 0x2572)
  58
  59 #define IS_GEN2(dev) (IS_830(dev) ||                            \
  60                       IS_845(dev) ||                            \
  61                       IS_85X(dev) ||                            \
  62                       IS_865(dev))
  63
  64 #define IS_915G(dev) (dev == 0x2582 ||          \
  65                        dev == 0x258a)
  66 #define IS_915GM(dev) (dev == 0x2592)
  67 #define IS_945G(dev) (dev == 0x2772)
  68 #define IS_945GM(dev) (dev == 0x27A2 ||         \
  69                         dev == 0x27AE)
  70
  71 #define IS_915(dev) (IS_915G(dev) ||                            \
  72                      IS_915GM(dev))
  73
  74 #define IS_945(dev) (IS_945G(dev) ||                            \
  75                      IS_945GM(dev) ||                           \
  76                      IS_G33(dev) ||                             \
  77                      IS_PINEVIEW(dev))
  78
  79 #define IS_G33(dev)    (dev == 0x29C2 ||                \
  80                         dev == 0x29B2 ||                \
  81                         dev == 0x29D2)
  82
  83 #define IS_PINEVIEW(dev) (dev == 0xa001 ||      \
  84                           dev == 0xa011)
  85
  86 #define IS_GEN3(dev) (IS_915(dev) ||                            \
  87                       IS_945(dev) ||                            \
  88                       IS_G33(dev) ||                            \
  89                       IS_PINEVIEW(dev))
  90
  91 #define IS_I965GM(dev) (dev == 0x2A02)
  92
  93 #define IS_GEN4(dev) (dev == 0x2972 ||  \
  94                       dev == 0x2982 ||  \
  95                       dev == 0x2992 ||  \
  96                       dev == 0x29A2 ||  \
  97                       dev == 0x2A02 ||  \
  98                       dev == 0x2A12 ||  \
  99                       dev == 0x2A42 ||  \
 100                       dev == 0x2E02 ||  \
 101                       dev == 0x2E12 ||  \
 102                       dev == 0x2E22 ||  \
 103                       dev == 0x2E32 ||  \
 104                       dev == 0x2E42 ||  \
 105                       dev == 0x0042 ||  \
 106                       dev == 0x0046 ||  \
 107                       IS_I965GM(dev) || \
 108                       IS_G4X(dev))
 109
 110 #define IS_GM45(dev) (dev == 0x2A42)
 111
 112
 113 #define IS_GEN5(dev)    (dev == PCI_CHIP_ILD_G || \
 114                          dev == PCI_CHIP_ILM_G)
 115
 116 #define IS_GEN6(dev)    (dev == PCI_CHIP_SANDYBRIDGE_GT1 || \
 117                          dev == PCI_CHIP_SANDYBRIDGE_GT2 || \
 118                          dev == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
 119                          dev == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
 120                          dev == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
 121                          dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
 122                          dev == PCI_CHIP_SANDYBRIDGE_S)
 123
 124 #define IS_GEN7(devid)          (IS_IVYBRIDGE(devid) || \
 125                                  IS_HASWELL(devid))
 126
 127 #define IS_IVYBRIDGE(dev)       (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
 128                                  dev == PCI_CHIP_IVYBRIDGE_GT2 || \
 129                                  dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
 130                                  dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
 131                                  dev == PCI_CHIP_IVYBRIDGE_S)
 132
 133 #define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \
 134                                  devid == PCI_CHIP_HASWELL_M_GT1)
 135 #define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \
 136                                  devid == PCI_CHIP_HASWELL_M_GT2 || \
 137                                  devid == PCI_CHIP_HASWELL_M_ULT_GT2)
 138
 139 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
 140                                  IS_HSW_GT2(devid))
 141
 142 #define IS_G4X(dev) (dev == 0x2E02 || \
 143                      dev == 0x2E12 || \
 144                      dev == 0x2E22 || \
 145                      dev == 0x2E32 || \
 146                      dev == 0x2E42 || \
 147                      IS_GM45(dev))
 148
 149 #define IS_9XX(dev) (IS_GEN3(dev) ||                            \
 150                      IS_GEN4(dev) ||                            \
 151                      IS_GEN5(dev) ||                            \
 152                      IS_GEN6(dev) ||                            \
 153                      IS_GEN7(dev))
 154
 155 #endif /* _INTEL_CHIPSET_H */