45a219c3b182830419c3242a9475ebd015fad337
1 /*
2 * Copyright © 2008 Jérôme Glisse
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26 /*
27 * Authors:
28 * Aapo Tahkola <aet@rasterburn.org>
29 * Nicolai Haehnle <prefect_@gmx.net>
30 * Jérôme Glisse <glisse@freedesktop.org>
31 */
32 #include <assert.h>
33 #include <errno.h>
34 #include <stdlib.h>
35 #include <sys/mman.h>
36 #include <sys/ioctl.h>
37 #include "radeon_cs.h"
38 #include "radeon_cs_int.h"
39 #include "radeon_bo_int.h"
40 #include "radeon_cs_gem.h"
41 #include "radeon_bo_gem.h"
42 #include "drm.h"
43 #include "xf86drm.h"
44 #include "radeon_drm.h"
46 struct radeon_cs_manager_gem {
47 struct radeon_cs_manager base;
48 uint32_t device_id;
49 };
51 #pragma pack(1)
52 struct cs_reloc_gem {
53 uint32_t handle;
54 uint32_t read_domain;
55 uint32_t write_domain;
56 uint32_t flags;
57 };
59 #pragma pack()
60 #define RELOC_SIZE (sizeof(struct cs_reloc_gem) / sizeof(uint32_t))
62 struct cs_gem {
63 struct radeon_cs_int base;
64 struct drm_radeon_cs cs;
65 struct drm_radeon_cs_chunk chunks[2];
66 unsigned nrelocs;
67 uint32_t *relocs;
68 struct radeon_bo_int **relocs_bo;
69 };
71 static struct radeon_cs_int *cs_gem_create(struct radeon_cs_manager *csm,
72 uint32_t ndw)
73 {
74 struct cs_gem *csg;
76 /* max cmd buffer size is 64Kb */
77 if (ndw > (64 * 1024 / 4)) {
78 return NULL;
79 }
80 csg = (struct cs_gem*)calloc(1, sizeof(struct cs_gem));
81 if (csg == NULL) {
82 return NULL;
83 }
84 csg->base.csm = csm;
85 csg->base.ndw = 64 * 1024 / 4;
86 csg->base.packets = (uint32_t*)calloc(1, 64 * 1024);
87 if (csg->base.packets == NULL) {
88 free(csg);
89 return NULL;
90 }
91 csg->base.relocs_total_size = 0;
92 csg->base.crelocs = 0;
93 csg->nrelocs = 4096 / (4 * 4) ;
94 csg->relocs_bo = (struct radeon_bo_int**)calloc(1,
95 csg->nrelocs*sizeof(void*));
96 if (csg->relocs_bo == NULL) {
97 free(csg->base.packets);
98 free(csg);
99 return NULL;
100 }
101 csg->base.relocs = csg->relocs = (uint32_t*)calloc(1, 4096);
102 if (csg->relocs == NULL) {
103 free(csg->relocs_bo);
104 free(csg->base.packets);
105 free(csg);
106 return NULL;
107 }
108 csg->chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
109 csg->chunks[0].length_dw = 0;
110 csg->chunks[0].chunk_data = (uint64_t)(uintptr_t)csg->base.packets;
111 csg->chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
112 csg->chunks[1].length_dw = 0;
113 csg->chunks[1].chunk_data = (uint64_t)(uintptr_t)csg->relocs;
114 return (struct radeon_cs_int*)csg;
115 }
117 static int cs_gem_write_reloc(struct radeon_cs_int *cs,
118 struct radeon_bo *bo,
119 uint32_t read_domain,
120 uint32_t write_domain,
121 uint32_t flags)
122 {
123 struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
124 struct cs_gem *csg = (struct cs_gem*)cs;
125 struct cs_reloc_gem *reloc;
126 uint32_t idx;
127 unsigned i;
129 assert(boi->space_accounted);
131 /* check domains */
132 if ((read_domain && write_domain) || (!read_domain && !write_domain)) {
133 /* in one CS a bo can only be in read or write domain but not
134 * in read & write domain at the same sime
135 */
136 return -EINVAL;
137 }
138 if (read_domain == RADEON_GEM_DOMAIN_CPU) {
139 return -EINVAL;
140 }
141 if (write_domain == RADEON_GEM_DOMAIN_CPU) {
142 return -EINVAL;
143 }
144 /* check if bo is already referenced */
145 for(i = 0; i < cs->crelocs; i++) {
146 idx = i * RELOC_SIZE;
147 reloc = (struct cs_reloc_gem*)&csg->relocs[idx];
148 if (reloc->handle == bo->handle) {
149 /* Check domains must be in read or write. As we check already
150 * checked that in argument one of the read or write domain was
151 * set we only need to check that if previous reloc as the read
152 * domain set then the read_domain should also be set for this
153 * new relocation.
154 */
155 /* the DDX expects to read and write from same pixmap */
156 if (write_domain && (reloc->read_domain & write_domain)) {
157 reloc->read_domain = 0;
158 reloc->write_domain = write_domain;
159 } else if (read_domain & reloc->write_domain) {
160 reloc->read_domain = 0;
161 } else {
162 if (write_domain != reloc->write_domain)
163 return -EINVAL;
164 if (read_domain != reloc->read_domain)
165 return -EINVAL;
166 }
168 reloc->read_domain |= read_domain;
169 reloc->write_domain |= write_domain;
170 /* update flags */
171 reloc->flags |= (flags & reloc->flags);
172 /* write relocation packet */
173 radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000);
174 radeon_cs_write_dword((struct radeon_cs *)cs, idx);
175 return 0;
176 }
177 }
178 /* new relocation */
179 if (csg->base.crelocs >= csg->nrelocs) {
180 /* allocate more memory (TODO: should use a slab allocatore maybe) */
181 uint32_t *tmp, size;
182 size = ((csg->nrelocs + 1) * sizeof(struct radeon_bo*));
183 tmp = (uint32_t*)realloc(csg->relocs_bo, size);
184 if (tmp == NULL) {
185 return -ENOMEM;
186 }
187 csg->relocs_bo = (struct radeon_bo_int **)tmp;
188 size = ((csg->nrelocs + 1) * RELOC_SIZE * 4);
189 tmp = (uint32_t*)realloc(csg->relocs, size);
190 if (tmp == NULL) {
191 return -ENOMEM;
192 }
193 cs->relocs = csg->relocs = tmp;
194 csg->nrelocs += 1;
195 csg->chunks[1].chunk_data = (uint64_t)(uintptr_t)csg->relocs;
196 }
197 csg->relocs_bo[csg->base.crelocs] = boi;
198 idx = (csg->base.crelocs++) * RELOC_SIZE;
199 reloc = (struct cs_reloc_gem*)&csg->relocs[idx];
200 reloc->handle = bo->handle;
201 reloc->read_domain = read_domain;
202 reloc->write_domain = write_domain;
203 reloc->flags = flags;
204 csg->chunks[1].length_dw += RELOC_SIZE;
205 radeon_bo_ref(bo);
206 cs->relocs_total_size += boi->size;
207 radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000);
208 radeon_cs_write_dword((struct radeon_cs *)cs, idx);
209 return 0;
210 }
212 static int cs_gem_begin(struct radeon_cs_int *cs,
213 uint32_t ndw,
214 const char *file,
215 const char *func,
216 int line)
217 {
219 if (cs->section_ndw) {
220 fprintf(stderr, "CS already in a section(%s,%s,%d)\n",
221 cs->section_file, cs->section_func, cs->section_line);
222 fprintf(stderr, "CS can't start section(%s,%s,%d)\n",
223 file, func, line);
224 return -EPIPE;
225 }
226 cs->section_ndw = ndw;
227 cs->section_cdw = 0;
228 cs->section_file = file;
229 cs->section_func = func;
230 cs->section_line = line;
232 if (cs->cdw + ndw > cs->ndw) {
233 uint32_t tmp, *ptr;
235 /* round up the required size to a multiple of 1024 */
236 tmp = (cs->cdw + ndw + 0x3FF) & (~0x3FF);
237 ptr = (uint32_t*)realloc(cs->packets, 4 * tmp);
238 if (ptr == NULL) {
239 return -ENOMEM;
240 }
241 cs->packets = ptr;
242 cs->ndw = tmp;
243 }
244 return 0;
245 }
247 static int cs_gem_end(struct radeon_cs_int *cs,
248 const char *file,
249 const char *func,
250 int line)
252 {
253 if (!cs->section_ndw) {
254 fprintf(stderr, "CS no section to end at (%s,%s,%d)\n",
255 file, func, line);
256 return -EPIPE;
257 }
258 if (cs->section_ndw != cs->section_cdw) {
259 fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
260 cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw);
261 fprintf(stderr, "CS section end at (%s,%s,%d)\n",
262 file, func, line);
264 /* We must reset the section even when there is error. */
265 cs->section_ndw = 0;
266 return -EPIPE;
267 }
268 cs->section_ndw = 0;
269 return 0;
270 }
272 static int cs_gem_emit(struct radeon_cs_int *cs)
273 {
274 struct cs_gem *csg = (struct cs_gem*)cs;
275 uint64_t chunk_array[2];
276 unsigned i;
277 int r;
279 csg->chunks[0].length_dw = cs->cdw;
281 chunk_array[0] = (uint64_t)(uintptr_t)&csg->chunks[0];
282 chunk_array[1] = (uint64_t)(uintptr_t)&csg->chunks[1];
284 csg->cs.num_chunks = 2;
285 csg->cs.chunks = (uint64_t)(uintptr_t)chunk_array;
287 r = drmCommandWriteRead(cs->csm->fd, DRM_RADEON_CS,
288 &csg->cs, sizeof(struct drm_radeon_cs));
289 for (i = 0; i < csg->base.crelocs; i++) {
290 csg->relocs_bo[i]->space_accounted = 0;
291 radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
292 csg->relocs_bo[i] = NULL;
293 }
295 cs->csm->read_used = 0;
296 cs->csm->vram_write_used = 0;
297 cs->csm->gart_write_used = 0;
298 return r;
299 }
301 static int cs_gem_destroy(struct radeon_cs_int *cs)
302 {
303 struct cs_gem *csg = (struct cs_gem*)cs;
305 free(csg->relocs_bo);
306 free(cs->relocs);
307 free(cs->packets);
308 free(cs);
309 return 0;
310 }
312 static int cs_gem_erase(struct radeon_cs_int *cs)
313 {
314 struct cs_gem *csg = (struct cs_gem*)cs;
315 unsigned i;
317 if (csg->relocs_bo) {
318 for (i = 0; i < csg->base.crelocs; i++) {
319 if (csg->relocs_bo[i]) {
320 radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
321 csg->relocs_bo[i] = NULL;
322 }
323 }
324 }
325 cs->relocs_total_size = 0;
326 cs->cdw = 0;
327 cs->section_ndw = 0;
328 cs->crelocs = 0;
329 csg->chunks[0].length_dw = 0;
330 csg->chunks[1].length_dw = 0;
331 return 0;
332 }
334 static int cs_gem_need_flush(struct radeon_cs_int *cs)
335 {
336 return 0; //(cs->relocs_total_size > (32*1024*1024));
337 }
339 static void cs_gem_print(struct radeon_cs_int *cs, FILE *file)
340 {
341 struct radeon_cs_manager_gem *csm;
342 unsigned int i;
344 csm = (struct radeon_cs_manager_gem *)cs->csm;
345 fprintf(file, "VENDORID:DEVICEID 0x%04X:0x%04X\n", 0x1002, csm->device_id);
346 for (i = 0; i < cs->cdw; i++) {
347 fprintf(file, "0x%08X\n", cs->packets[i]);
348 }
349 }
351 static struct radeon_cs_funcs radeon_cs_gem_funcs = {
352 cs_gem_create,
353 cs_gem_write_reloc,
354 cs_gem_begin,
355 cs_gem_end,
356 cs_gem_emit,
357 cs_gem_destroy,
358 cs_gem_erase,
359 cs_gem_need_flush,
360 cs_gem_print,
361 };
363 static int radeon_get_device_id(int fd, uint32_t *device_id)
364 {
365 struct drm_radeon_info info;
366 int r;
368 *device_id = 0;
369 info.request = RADEON_INFO_DEVICE_ID;
370 info.value = device_id;
371 r = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info,
372 sizeof(struct drm_radeon_info));
373 return r;
374 }
376 struct radeon_cs_manager *radeon_cs_manager_gem_ctor(int fd)
377 {
378 struct radeon_cs_manager_gem *csm;
380 csm = calloc(1, sizeof(struct radeon_cs_manager_gem));
381 if (csm == NULL) {
382 return NULL;
383 }
384 csm->base.funcs = &radeon_cs_gem_funcs;
385 csm->base.fd = fd;
386 radeon_get_device_id(fd, &csm->device_id);
387 return &csm->base;
388 }
390 void radeon_cs_manager_gem_dtor(struct radeon_cs_manager *csm)
391 {
392 free(csm);
393 }