intel: enable relaxed fence allocation for i915

[glsdk/libdrm.git] / intel / intel_bufmgr_gem.c

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index c5847a8af422b0da303f8b102d9b85585ebdc1b9..37a3691c756ce7da420af71b485b14de7db06ee0 100644 (file)
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -99,9 +99,10 @@ typedef struct _drm_intel_bufmgr_gem {
        int available_fences;
        int pci_device;
        int gen;
-       char has_bsd;
-       char has_blt;
-       char bo_reuse;
+       unsigned int has_bsd : 1;
+       unsigned int has_blt : 1;
+       unsigned int has_relaxed_fencing : 1;
+       unsigned int bo_reuse : 1;
        char fenced_relocs;
 } drm_intel_bufmgr_gem;
 
@@ -243,6 +244,10 @@ drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size,
                return size;
        }
 
+       /* Do we need to allocate every page for the fence? */
+       if (bufmgr_gem->has_relaxed_fencing)
+               return ROUND_UP_TO(size, 4096);
+
        for (i = min_size; i < size; i <<= 1)
                ;
 
@@ -2128,6 +2133,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
        ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
        bufmgr_gem->has_blt = ret == 0;
 
+       gp.param = I915_PARAM_HAS_RELAXED_FENCING;
+       ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
+       bufmgr_gem->has_relaxed_fencing = ret == 0;
+
        if (bufmgr_gem->gen < 4) {
                gp.param = I915_PARAM_NUM_FENCES_AVAIL;
                gp.value = &bufmgr_gem->available_fences;