diff --git a/radeon/radeon_bo_gem.c b/radeon/radeon_bo_gem.c
index 9bf119a6444a1981a7048b4acc77917548ab640c..265f1777cea2cdd13a5ce5c50c590b4f65b4c184 100644 (file)
--- a/radeon/radeon_bo_gem.c
+++ b/radeon/radeon_bo_gem.c
-/*
+/*
* Copyright © 2008 Dave Airlie
* Copyright © 2008 Jérôme Glisse
* All Rights Reserved.
- *
+ *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* The above copyright notice and this permission notice (including the
#include <sys/mman.h>
#include <errno.h>
#include "xf86drm.h"
+#include "xf86atomic.h"
#include "drm.h"
#include "radeon_drm.h"
#include "radeon_bo.h"
#include "radeon_bo_int.h"
#include "radeon_bo_gem.h"
-
+#include <fcntl.h>
struct radeon_bo_gem {
struct radeon_bo_int base;
uint32_t name;
int map_count;
+ atomic_t reloc_in_cs;
void *priv_ptr;
};
bo->base.domains = domains;
bo->base.flags = flags;
bo->base.ptr = NULL;
+ atomic_set(&bo->reloc_in_cs, 0);
bo->map_count = 0;
if (handle) {
struct drm_gem_open open_arg;
return 0;
}
if (bo_gem->priv_ptr) {
- goto wait;
+ goto wait;
}
boi->ptr = NULL;
args.domain = 0;
ret = drmCommandWriteRead(boi->bom->fd, DRM_RADEON_GEM_BUSY,
- &args, sizeof(args));
+ &args, sizeof(args));
*domain = args.domain;
return ret;
}
static int bo_set_tiling(struct radeon_bo_int *boi, uint32_t tiling_flags,
- uint32_t pitch)
+ uint32_t pitch)
{
struct drm_radeon_gem_set_tiling args;
int r;
args.pitch = pitch;
r = drmCommandWriteRead(boi->bom->fd,
- DRM_RADEON_GEM_SET_TILING,
- &args,
- sizeof(args));
+ DRM_RADEON_GEM_SET_TILING,
+ &args,
+ sizeof(args));
return r;
}
static int bo_get_tiling(struct radeon_bo_int *boi, uint32_t *tiling_flags,
- uint32_t *pitch)
+ uint32_t *pitch)
{
- struct drm_radeon_gem_set_tiling args;
+ struct drm_radeon_gem_set_tiling args = {};
int r;
args.handle = boi->handle;
r = drmCommandWriteRead(boi->bom->fd,
- DRM_RADEON_GEM_GET_TILING,
- &args,
- sizeof(args));
+ DRM_RADEON_GEM_GET_TILING,
+ &args,
+ sizeof(args));
if (r)
- return r;
+ return r;
*tiling_flags = args.tiling_flags;
*pitch = args.pitch;
return bo_gem->name;
}
+void *radeon_gem_get_reloc_in_cs(struct radeon_bo *bo)
+{
+ struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
+ return &bo_gem->reloc_in_cs;
+}
+
int radeon_gem_get_kernel_name(struct radeon_bo *bo, uint32_t *name)
{
struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
flink.handle = bo->handle;
r = drmIoctl(boi->bom->fd, DRM_IOCTL_GEM_FLINK, &flink);
if (r) {
- return r;
+ return r;
}
*name = flink.name;
return 0;
@@ -340,3 +349,49 @@ int radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t
sizeof(args));
return r;
}
+
+int radeon_gem_prime_share_bo(struct radeon_bo *bo, int *handle)
+{
+ struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
+ int ret;
+
+ ret = drmPrimeHandleToFD(bo_gem->base.bom->fd, bo->handle, DRM_CLOEXEC, handle);
+ return ret;
+}
+
+struct radeon_bo *radeon_gem_bo_open_prime(struct radeon_bo_manager *bom,
+ int fd_handle,
+ uint32_t size)
+{
+ struct radeon_bo_gem *bo;
+ int r;
+ uint32_t handle;
+
+ bo = (struct radeon_bo_gem*)calloc(1, sizeof(struct radeon_bo_gem));
+ if (bo == NULL) {
+ return NULL;
+ }
+
+ bo->base.bom = bom;
+ bo->base.handle = 0;
+ bo->base.size = size;
+ bo->base.alignment = 0;
+ bo->base.domains = RADEON_GEM_DOMAIN_GTT;
+ bo->base.flags = 0;
+ bo->base.ptr = NULL;
+ atomic_set(&bo->reloc_in_cs, 0);
+ bo->map_count = 0;
+
+ r = drmPrimeFDToHandle(bom->fd, fd_handle, &handle);
+ if (r != 0) {
+ free(bo);
+ return NULL;
+ }
+
+ bo->base.handle = handle;
+ bo->name = handle;
+
+ radeon_bo_ref((struct radeon_bo *)bo);
+ return (struct radeon_bo *)bo;
+
+}