| author | Chris Wilson <chris@chris-wilson.co.uk> | |
| Thu, 9 Feb 2012 10:29:22 +0000 (10:29 +0000) | ||
| committer | Chris Wilson <chris@chris-wilson.co.uk> | |
| Wed, 15 Feb 2012 11:16:59 +0000 (11:16 +0000) | ||
| commit | 23eeb7e1e45417a5a84f826286dd982dba440cd3 | |
| tree | fa744258a4354cc23f45b32beb652fe863d1b238 | tree | snapshot (tar.xz tar.gz zip) |
| parent | 9b3ad51ae5fd9654df8ef75de845a519015150bb | commit | diff |
intel: Detect cache domain inconsistency with valgrind
Every access to either the GTT or CPU pointer is supposed to be
proceeded by a set_domain ioctl so that GEM is able to manage the cache
domains correctly and for the following access to be coherent. Of
course, some people explicitly want incoherent, non-blocking access
which is going to trigger warnings by this patch but are probably better
served by explicit suppression.
v2: Also mark the pointers as inaccessible following the explicit unmap
and implicit unmap upon return to the cache.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Every access to either the GTT or CPU pointer is supposed to be
proceeded by a set_domain ioctl so that GEM is able to manage the cache
domains correctly and for the following access to be coherent. Of
course, some people explicitly want incoherent, non-blocking access
which is going to trigger warnings by this patch but are probably better
served by explicit suppression.
v2: Also mark the pointers as inaccessible following the explicit unmap
and implicit unmap upon return to the cache.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| intel/intel_bufmgr_gem.c | diff | blob | history |