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raw | patch | inline | side by side (parent: e14aedc)
author | Marek Olšák <maraeo@gmail.com> | |
Tue, 7 Aug 2012 21:38:19 +0000 (23:38 +0200) | ||
committer | Marek Olšák <maraeo@gmail.com> | |
Thu, 9 Aug 2012 20:35:07 +0000 (22:35 +0200) |
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
radeon/radeon_surface.c | patch | blob | history |
index 499e994cff0e52219b50368f35810263624541a9..892dca6426717fe6e101fd4c876429ef7d75eb9a 100644 (file)
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
return 0;
}
- /* set tile split to row size, optimize latter for multi-sample surface
- * tile split >= 256 for render buffer surface. Also depth surface want
- * smaller value for optimal performances.
- */
- surf->tile_split = surf_man->hw_info.row_size;
- surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
+ /* Tweak TILE_SPLIT for performance here. */
+ if (surf->nsamples > 1) {
+ if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
+ switch (surf->nsamples) {
+ case 2:
+ surf->tile_split = 128;
+ break;
+ case 4:
+ surf->tile_split = 128;
+ break;
+ case 8:
+ surf->tile_split = 256;
+ break;
+ case 16: /* cayman only */
+ surf->tile_split = 512;
+ break;
+ default:
+ fprintf(stderr, "radeon: Wrong number of samples %i (%i)\n",
+ surf->nsamples, __LINE__);
+ return -EINVAL;
+ }
+ surf->stencil_tile_split = 64;
+ } else {
+ /* tile split must be >= 256 for colorbuffer surfaces */
+ surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
+ }
+ } else {
+ /* set tile split to row size */
+ surf->tile_split = surf_man->hw_info.row_size;
+ surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
+ }
/* bankw or bankh greater than 1 increase alignment requirement, not
* sure if it's worth using smaller bankw & bankh to stick with 2D