drm/i915: y tiling on i915G/i915GM is different
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 22 Sep 2011 20:20:53 +0000 (22:20 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 22 Sep 2011 20:20:53 +0000 (22:20 +0200)
Luckily the kernel has become extremely paranoid about such matters.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
intel/intel_bufmgr_gem.c

index 22617ec076ecc5e6af83e0af8e66ea8816225259..1baa0b3f9d91064c721a633930762c177ef97cf1 100644 (file)
@@ -275,7 +275,8 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem,
        if (*tiling_mode == I915_TILING_NONE)
                return ALIGN(pitch, 64);
 
-       if (*tiling_mode == I915_TILING_X)
+       if (*tiling_mode == I915_TILING_X
+                       || (IS_915(bufmgr_gem) && *tiling_mode == I915_TILING_Y))
                tile_width = 512;
        else
                tile_width = 128;
@@ -764,7 +765,8 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
 
                if (IS_GEN2(bufmgr_gem) && tiling != I915_TILING_NONE)
                        height_alignment = 16;
-               else if (tiling == I915_TILING_X)
+               else if (tiling == I915_TILING_X
+                       || (IS_915(bufmgr_gem) && tiling == I915_TILING_Y))
                        height_alignment = 8;
                else if (tiling == I915_TILING_Y)
                        height_alignment = 32;