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raw | patch | inline | side by side (parent: 1db22ff)
author | Chris Wilson <chris@chris-wilson.co.uk> | |
Mon, 21 Jun 2010 13:20:56 +0000 (14:20 +0100) | ||
committer | Chris Wilson <chris@chris-wilson.co.uk> | |
Mon, 21 Jun 2010 21:37:18 +0000 (22:37 +0100) |
When allocating a tiled buffer, if we remove the desired tiling mode due
to it being beyond hardware limits, also remove the stride. This ensures
that we only ever use stride 0 with I915_TILING_NONE.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
to it being beyond hardware limits, also remove the stride. This ensures
that we only ever use stride 0 with I915_TILING_NONE.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
intel/intel_bufmgr_gem.c | patch | blob | history |
index b4be1afe1a73ae3c607b4ffea9d34b1aa2483c03..19eea345ebab8db267822abd82829f4f984902f2 100644 (file)
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode);
} while (*tiling_mode != tiling);
+ if (*tiling_mode == I915_TILING_NONE)
+ stride = 0;
+
bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags,
*tiling_mode, stride);
if (!bo)