intel: Add some PCI IDs for Haswell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index e3a30fc7d5d08f11de1a9279a8e11aed027a73cf..435d01a365dbe165fd365d8c55191f9030f22b9b 100644 (file)
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -45,6 +45,12 @@
 #define PCI_CHIP_IVYBRIDGE_M_GT2       0x0166
 #define PCI_CHIP_IVYBRIDGE_S           0x015a /* server */
 
+#define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
+#define PCI_CHIP_HASWELL_GT2            0x0412
+#define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
+#define PCI_CHIP_HASWELL_M_GT2          0x0416
+#define PCI_CHIP_HASWELL_M_ULT_GT2      0x0A16 /* Mobile ULT */
+
 #define IS_830(dev) (dev == 0x3577)
 #define IS_845(dev) (dev == 0x2562)
 #define IS_85X(dev) (dev == 0x3582)
@@ -115,11 +121,23 @@
                         dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
                         dev == PCI_CHIP_SANDYBRIDGE_S)
 
-#define IS_GEN7(dev)   (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
-                        dev == PCI_CHIP_IVYBRIDGE_GT2 || \
-                        dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
-                        dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
-                        dev == PCI_CHIP_IVYBRIDGE_S)
+#define IS_GEN7(devid)          (IS_IVYBRIDGE(devid) || \
+                                 IS_HASWELL(devid))
+
+#define IS_IVYBRIDGE(dev)      (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
+                                dev == PCI_CHIP_IVYBRIDGE_GT2 || \
+                                dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
+                                dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
+                                dev == PCI_CHIP_IVYBRIDGE_S)
+
+#define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \
+                                 devid == PCI_CHIP_HASWELL_M_GT1)
+#define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \
+                                 devid == PCI_CHIP_HASWELL_M_GT2 || \
+                                 devid == PCI_CHIP_HASWELL_M_ULT_GT2)
+
+#define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
+                                 IS_HSW_GT2(devid))
 
 #define IS_G4X(dev) (dev == 0x2E02 || \
                      dev == 0x2E12 || \