intel: add more Haswell PCI IDs
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Mon, 6 Aug 2012 17:55:23 +0000 (14:55 -0300)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Wed, 8 Aug 2012 18:38:12 +0000 (15:38 -0300)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
intel/intel_chipset.h

index 9c1abc863f17073776f814b12d9c311e5b0a14ef..b73fa0f97367142b50b9decab919ecadc61c80db 100644 (file)
 
 #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
 #define PCI_CHIP_HASWELL_GT2            0x0412
+#define PCI_CHIP_HASWELL_GT2_PLUS       0x0422
 #define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
 #define PCI_CHIP_HASWELL_M_GT2          0x0416
-#define PCI_CHIP_HASWELL_M_ULT_GT2      0x0A16 /* Mobile ULT */
+#define PCI_CHIP_HASWELL_M_GT2_PLUS     0x0426
+#define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */
+#define PCI_CHIP_HASWELL_S_GT2          0x041A
+#define PCI_CHIP_HASWELL_S_GT2_PLUS     0x042A
+#define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */
+#define PCI_CHIP_HASWELL_SDV_GT2        0x0C12
+#define PCI_CHIP_HASWELL_SDV_GT2_PLUS   0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1      0x0C06 /* Mobile */
+#define PCI_CHIP_HASWELL_SDV_M_GT2      0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */
+#define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A
+#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */
+#define PCI_CHIP_HASWELL_ULT_GT2        0x0A12
+#define PCI_CHIP_HASWELL_ULT_GT2_PLUS   0x0A22
+#define PCI_CHIP_HASWELL_ULT_M_GT1      0x0A06 /* Mobile */
+#define PCI_CHIP_HASWELL_ULT_M_GT2      0x0A16
+#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */
+#define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A
+#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_CRW_GT1        0x0D12 /* Desktop */
+#define PCI_CHIP_HASWELL_CRW_GT2        0x0D22
+#define PCI_CHIP_HASWELL_CRW_GT2_PLUS   0x0D32
+#define PCI_CHIP_HASWELL_CRW_M_GT1      0x0D16 /* Mobile */
+#define PCI_CHIP_HASWELL_CRW_M_GT2      0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
+#define PCI_CHIP_HASWELL_CRW_S_GT1      0x0D1A /* Server */
+#define PCI_CHIP_HASWELL_CRW_S_GT2      0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
 
 #define IS_830(dev) (dev == 0x3577)
 #define IS_845(dev) (dev == 0x2562)
                                 dev == PCI_CHIP_IVYBRIDGE_S_GT2)
 
 #define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \
-                                 devid == PCI_CHIP_HASWELL_M_GT1)
+                                devid == PCI_CHIP_HASWELL_M_GT1 || \
+                                devid == PCI_CHIP_HASWELL_S_GT1 || \
+                                devid == PCI_CHIP_HASWELL_SDV_GT1 || \
+                                devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
+                                devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
+                                devid == PCI_CHIP_HASWELL_ULT_GT1 || \
+                                devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
+                                devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
+                                devid == PCI_CHIP_HASWELL_CRW_GT1 || \
+                                devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
+                                devid == PCI_CHIP_HASWELL_CRW_S_GT1)
 #define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \
                                  devid == PCI_CHIP_HASWELL_M_GT2 || \
-                                 devid == PCI_CHIP_HASWELL_M_ULT_GT2)
+                                devid == PCI_CHIP_HASWELL_S_GT2 || \
+                                devid == PCI_CHIP_HASWELL_SDV_GT2 || \
+                                devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
+                                devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
+                                devid == PCI_CHIP_HASWELL_ULT_GT2 || \
+                                devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
+                                devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
+                                devid == PCI_CHIP_HASWELL_CRW_GT2 || \
+                                devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
+                                devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
+                                devid == PCI_CHIP_HASWELL_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
+                                devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
 
 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
                                  IS_HSW_GT2(devid))